TW200937636A - Self-assembled sidewall spacer - Google Patents

Abstract

A semiconductor structure is provided that includes a spacer directly abutting a topographic edge of at least one patterned material layer. The spacer is a non-removable polymeric block component of a self assembled block copolymer. A method of forming such a semiconductor structure including the inventive spacer is also provided that utilizes self-assembled block copolymer technology.

Description

200937636 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a nanostructure (particularly a semiconductor structure) and a method of fabricating the same. In particular, the present invention relates to a nanostructure comprising at least one patterned region comprising at least one material and a topographical edge having a sidewall spacer comprising a polymeric block component of a self-assembling polymer And methods for making this structure using self-assembling polymer technology. Related Application This application is related to US No. 11/869171 (agent slot number FIS920070087US1; SSMP20946-1), this application is also applied at the same time as the application on the same day as the application; and related to US No. 11/869178 (Agency file number FIS920070087US2; SSMP 20946-2), this cross-reference application is filed at the same time as the same application. [Prior Art] Field effect transistors (FETs) are the basic architecture of today's integrated circuits. Such transistors can be formed in conventional bulk substrates (such as Shi Xi) or semiconductor-on-insulator (s〇I) substrates. Advanced FETs are fabricated by depositing gate electrodes on the gate dielectric and substrate. In general, the transistor process implements a lithography and etching process to define a conductive (e.g., 'polycrystalline slate') gate structure. The gate structure and substrate are then typically (but not necessarily always) thermally oxidized, and thereafter, by implanting the source 200937636 pole/no-pole extension. Sometimes, secrets/transmissions __ recordings are implanted, = a specific distance is established between the interpolar and implanted junctions. In some examples, ^, in the case of the |Lie n_FET device, implant the n~FET package (4) secret/dip pole extension without the source/secret wall. For the p_FET device, the source/record extension is typically implanted in the case of the inter-extension. Typically, after implantation of the source/no-pole extension, a spacer is formed that is thicker than the source/no-pole extension. Then, in the presence of Hou Congbi, he is obsessed with deep miscellaneous/secret. Execution of high-temperature bribery joint activation, followed by the general part of the miscellaneous / bungee and _ Wei. The formation of debris usually requires the deposition of refractory metal on the Si-containing substrate (refrae_ca (10) and then the thermal annealing of the material (4), the formation of the material into the deep source/drain region and the low-resistivity contact of the gate conductor. In the above, the thicker spacers provide a self-aligned offset between the gate electrode (i.e., polysilicon or any other conductive material) and the implant handle used to customize the semiconductor electrical properties of the FET. Integral circuits (1C) such as memory, logic, and other devices that are more integrated than existing feasible integrated circuits must find a way to further reduce the size of the FET. Reduce the size of the transistor to improve performance and tightness. Sexuality, but this reduction has some device degradation effects. By lowering the transistor linewidth, reducing the gate oxide thickness, and lowering the source/drain extension resistance, a new generation of high performance FET devices can be improved. The transistor line width reduces the distance between the source and the drain, which in turn makes the switching speed of the complementary MOS6 200937636 body (CMOS) circuit faster. The spacers used by the FET must also be reduced to provide a small device. However, methods including depositing dielectric materials (such as tantalum oxide or tantalum nitride) and anisotropic etching are used to form the spacer because the device continues It is less practical to shrink. The anisotropic etching step used in the formation of the spacers is also undesirable because it typically modifies, removes, and/or damages various materials within the FET field. Note that the above problems are not only related to FETs. In fact, there is a problem in the above-mentioned (4) gap formation and device shrinkage in any of the nanostructured towels which may include the spacers of the material or the stacking topography of the material in the adjacent structure. In view of the above, it is necessary to provide It is possible to use = and improve __ ' in various nanostructures to protect the edges or edges of the material or material present in the structure' and in particular to protect the new and improved spacers of the gate of the gate stack structure. Contents] To protect the gaps used in various nanostructures, the edge of the material or the stack of materials on which the rafters are stacked. The gap of the block component "" is the edge of the material. The spacer of the present invention may be 7 200937636 or it may be a permanent spacer that remains in the structure, which is removable in some applications. The present invention provides a nanostructure comprising a pattern comprising at least one material layer and having at least one region; and a topographical edge

A spacer directly adjacent to the edge of the surface, the spacer comprising a polymeric block component of the self-packaging block copolymer. In some embodiments of the invention, the self-assembling block copolymer employed in the present invention is selected from the group consisting of: polystyrene _ _ segment - polymethacrylic acid vinegar (PS-b- PMMA), polystyrene block-polyisoprene (PS-b-PI), polystyrene-rhodium-polybutadiene (pS-b-PBD), polystyrene block -Polyvinylpyridine (PS-b-PVP), polystyrene block-polyethylene oxide (PS-b-PEO), polystyrene-block-polyethylene (PS-b-PE), poly Styrene-b-polyorganosilicate (PS-b-POS), polystyrene-block-polyferrocene dimethyl decane (PS-b-PFS), polyethylene oxide-block- Polyisoprene (PEO-b-PI), polyethylene oxide-block-polybutadiene (PEO-b-PBD), polyethylene oxide block-polymethacrylate (PEO) -b-PMMA), polyethylene oxide-block-saturated polyethylene (PEO-b-PEE), polybutadiene-block-polyvinylpyridine (PBD-b-PVP), and polyisoprene Diene-block-polymethacrylate (PI-b-PMMA). In a particular embodiment of the invention, a nanostructure '200937636 is provided comprising: - a semiconductor substrate; a patterned material stack comprising at least one patterned gate electrode, the patterned gate electrode having a topographical edge And a spacer directly adjacent to the edge of the topography, the spacer comprising a polymeric block component of a self-assembling block copolymer. In addition to the above semiconductor structure, the present invention also provides a method of manufacturing the spacer of the present invention, which can be implemented in any process of nanostructure processing. The wall fabrication of the present invention is formed using a self-assembling block filament technique and, therefore, does not alter, damage and/or remove any material present in the surrounding field. Moreover, the method of the present invention does not utilize any anisotropic technique when fabricating the spacers. Generally, the method of the present invention comprises: providing - a layer comprising at least - a layer of material having at least one topographical edge, and a spacer forming a directly adjacent edge of the topography, the spacer comprising a self-assembly A proud segment of the copolymer of the proud segment. More specifically, the process of forming the spacers includes: coating a self-assembled (10) segment of the copolymer to a chemically-containing region comprising the at least one of the material layers, annealing to form a neat array of heterogeneous and non-returnable polymeric components, and The above removable polymeric ingredients are removed. 9 200937636 In another embodiment of the invention, the method comprises the steps of: providing a patterned material stack comprising at least one patterned idle electrode on a surface of a semiconductor substrate, the patterned gate electrode having a topographical edge; and a spacer formed directly adjacent to the edge of the topography, the spacer comprising a polymeric block component of a self-assembling block copolymer.

[Embodiment] The present invention is directed to a spacer for protecting a material or a stack of materials in a nanostructure, and a method of manufacturing the same, and will now be referred to the following description. Please note that the illustrations in this section are for general purpose purposes only and therefore the drawings are not proportional. In the following description, many specific details are proposed, such as specific structure,

The procedures and techniques are to provide a comprehensive understanding of the present invention. It can also be implemented, in the absence of deduction of details, the focus is not: in the example 'to avoid obscuring the structure or process steps well known to the invention. Another-: table 7" pieces (such as thin layers, regions or substrates) located in the middle of the door can be stored directly above other components or ~ yuan: when indicating that a component is "directly" on the other table There are no intermediate components in between. It should also be understood that when a component is referred to as "connected" or "coupled" to another component, the component is directly connected or coupled to the other component or may have intermediate components. Conversely, when a component is referred to as being "directly connected" or "directly coupled" to another component, it means that there is no intermediate component in between.极 ❹ Γ Γ Γ 代表 代表 代表 代表 代表 代表 极 极 极 极 极 极 极 极 极 极 极 极 极 极 极 极 极 极 极 极The U-wall of the present invention is shown and described in connection with a fET structure, but the invention is not limited to the FET applications described and illustrated herein. In fact, the wall of the present invention can be used in any nanostructure application towel to have a top edge that protects at least one of the layers of material from the wall. Other applications of the spacer of the present invention include, but are not limited to,: a spacer for protecting the edge of the topography of the capacitor structure, a topography edge for protecting the bipolar transistor structure, a spacer for protecting the edge of the electronic wire, and a MEMS protection The wall of the device is edged, the gap of the edge of the inductor is protected, the gap of the edge of the sensor is protected, and the gap of the edge of the optoelectronic device. Referring now to Fig. 1 Ε 1 Ε ' _ solution in the attachment _ solid surface of the present invention. The present invention begins with the initial construction of Figure 1A, which includes a stack of materials 12 comprising a gate dielectric and a gate electrode 16 on the surface of the semiconductor substrate 10. The semiconductor substrate 1 of the initial structure shown in FIG. 1A includes any semiconductor material including but not limited to Si, Ge, SiGe, SiC, SiGeC, QaAs, 200937636

GaN, InAs, InP and all other m/v or II/Vi compound semiconductors. The semiconductor substrate 10 may also comprise an organic semiconductor or a layered semiconductor such as Si/SiGe, an insulator (S1), an insulator (1) or a barrier on insulator (GOI). In some embodiments of the invention, it is preferred that the semiconductor substrate 10 be comprised of a Si-containing semiconductor material (i.e., a semiconductor material comprising germanium).半导体 The semiconductor substrate 10 can be doped, undoped, or contain doped and undoped regions therein. The semiconductor substrate 10 may comprise a single crystal orientation or it may comprise at least two coplanar surface regions having different crystal orientations (this substrate is referred to herein as a hybrid substrate). When a hybrid substrate is employed, the nFET is typically formed on the (100) crystalline surface, while the pFET is typically formed on the (110) crystalline plane. The mixed substrate y is formed by the techniques described in, for example, U.S. Patent Application Publication No. 2004/0256700 A1, No. 2005/0093104A1, and No. 2, No. 5, ship 629, A1. Reference. The first H-body substrate 10 may also include a first doped (n-type or P-type) region and region. For the sake of clarity, in the field of the present application, the two-door c-domain and the second doped region doped region two "t have a germanium conductivity and/or a doping concentration. These are ^^ are 彳" and The at least-isolated region is formed in the semiconductor substrate ig by using a conventional ion implantation process to form a pass-through region (not shown in Figure 12). The isolation region can be a trench isolation region or a field oxide isolation region. Ditch isolation areas can be formed using conventional trench isolation processes well known to those skilled in the art. For example, when forming a trench isolation region, lithography, etching, and filling the trench with a trench dielectric can be used. When the trench is filled, a liner is formed in the trench, and after the trench is filled, the dense can be performed. (^bnSiflcati〇n) steps, and can be planarized after the trench is filled. Field oxides can be formed by the so-called "local oxidation of the dream process." The idea is that the at least one isolation region provides isolation between adjacent gate regions, typically requiring isolation when adjacent gates have opposite conductivities (i.e., nFETs and pFETs). The adjacent gate regions may have the same conductivity (i.e., both are n-type or Ρ-type) or alternatively, they may have different electrical conductivities (i.e., one is n-type and the other is p-type). After processing the semiconductor substrate 10, an interface layer (not shown) is formed on the surface of the semiconductor substrate 10 as appropriate. The interface layer is formed using familiar techniques (including, for example, oxidation of oxidized money). When the two devices are Si-containing semiconductors, the interface layer may be composed of oxidized oxidized stone, oxynitride or cerium nitride oxide. When the substrate 10 is not a Si-containing semiconductor, it contains a semiconductor material, a semiconductor oxynitride or a nitride semiconductor. The thickness of the interface layer is usually given from about 〇·5 to about 2, and from about the door to the private treaty! Thin thickness is more common. However, the thickness may be different after processing at a higher temperature required for the manufacturing process of 曰, , and 吊. Next, a deposition process such as chemical vapor deposition (CVD), plasma-assisted CVD, physical vapor phase can be utilized on the surface of the interface layer (if present) or on the surface of the semiconductor structure 13 200937636 ιο (if there is no interface layer). Sedimentation (pvj)), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), vaporization, reactive antimony ore, chemical solution deposition, and other similar deposition processes to form gate dielectrics 14. In some embodiments of the invention, the gate dielectric 14 can be formed by a thermal growth process such as thermal oxidation or thermal nitridation, and the gate dielectric layer 14 can be formed using any combination of the above processes.闸 Gate dielectric 14 comprises any conventional dielectric material which may comprise an oxide, a nitride, an oxynitride or any combination thereof comprising multiple layers. In general (but not necessarily always), the gate dielectric 14 is an oxide of cerium, a nitrogen of cerium or an oxynitride of cerium. In other embodiments, the gate dielectric 14 is a high-k gate dielectric. The term "high-k gate dielectric" as used herein refers to a dielectric material having a dielectric constant greater than 4.0 (preferably greater than 7.0). Examples of such high-k gate dielectric materials include, but are not limited to, Ti02, 八12〇3, Ζ: ιΌ2, Hf〇2, Ta2〇5, La2〇3, mixed metal oxides (such as Maternal Oxidation® ()) / combinations thereof and multiple layers. The metal oxides and nitrides of the above metal oxides can also be used as the high-k gate dielectric material. The physical thickness of the gate dielectric 14 can vary, but the gate dielectric I4 typically has a thickness between about 0.5 and about 1 G, while a thickness between about 5 and about 3 nm is more common. · After forming the gate dielectric f 14 , the top of the dielectric f 14 is shaped 14

200937636 becomes the gate electrode 16. Specifically, a coating of a conductive material is formed on the gate dielectric 14 by a known deposition process such as physical vapor deposition, CVD or steaming. The conductive material used as the gate electrode 16 includes, but is not limited to, a Si-containing material such as a Si or SiGe alloy layer in a single crystal, polycrystalline or amorphous form. The electrically conductive material can also be a conductive metal, a conductive metal alloy, and/or a conductive metal nitride. Combinations of the above conductor materials are also contemplated herein. The gate electrode 16 is preferably made of a Si-containing material, and polycrystalline germanium (polySi) is preferred. In addition to the above-described conductive materials, the present invention also contemplates an example in which the gate electrode 16 70 is entirely sinusoidal or is a stack comprising a combination of dreaming and Si or SiGe. The telluride system is formed using a conventional passivation process well known to those skilled in the art to form a fully enthalpy gate which can be formed using conventional replacement gate processes; the details of which are not critical to the practice of the present invention. The cladding of the conductive gate material can be doped or undoped. In the case of doping, the deposition process may be performed in the formation of the cladding layer, or the doped Chen electrode may be formed by deposition, ionization and annealing. Ion implantation and annealing can be performed before or after the post-axis engraving step of patterning the material stack. Doping of the gate electrode 16 will change the work function of the formed gate conductor. 1 An illustrative example of a dopant ion from SFfT includes the periodic table of elements VA, 兀, (when forming a pMOSFET, a vertical thickness of the IIIA element 15 200937636 20 to about 180 nm can be used, and from about 40 nm to about 150 nm The thickness is relatively common. In some embodiments (not shown), a dielectric hard mask is formed on top of the gate electrode 16. If present, the dielectric hard mask is comprised of oxide, nitride or oxynitride, In particular, the oxide of tantalum or niobium is an excellent material for dielectric hard masks. Dielectric hard masks are used to protect the gate electrodes from FET fabrication without some other processing steps. The mask is formed by a conventional deposition process (such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition). Alternatively, a dielectric hard mask can be formed by a thermal process such as oxidation. After the initial structure shown in FIG. 1A, at least the gate electrode 16 of the material 12 is patterned by lithography and etch=''''''''''''''''''''' Example of the closed pole of the stack 4 12 Both the pole 16 and the gate dielectric 14 are patterned in this step. Note that although the invention is not limited to this number of patterns:: Dimorphization of adjacent patterned material stacks adjacent to the image - development exposure The resistance is removed from the structure at any time after the pattern is transferred to the material stack core 16 ❹ ❹ 200937636.

After patterning, a process can be used, such as a ashing resist. Sand Chenyuan Tea The above-mentioned money engraving step includes a dry process (ie, reactive ion money =:: bundle _, subsequent engraving and / or laser remuneration, chemical wet silk engraving process) or dry and wet side The combination of the "bovine-sounding" axis describes the above-described process when manufacturing the structure shown in Fig. 1B. The structure shown in Fig. 1B can be realized by the replacement process. = and is limited to the structure shown above for forming the circle 1B. Exposure =: two: for; ; shape f patterned material stacking 12. bare = 12 closed electrode and patterned open dielectric, but the person ^, the region only contains a single - material layer in the case Or the patterned area is equally useful when it contains more than two layers of material. Implantation ίί:: At this point: the ion-gap wall that is commonly known to those skilled in the art is generally extended to the region 21. Typically, there is no inter-sidewall map After the second electrode is inserted, after the step, it can be executed: the edge of the topography is 2〇). Here, the ion implantation process is performed in an ionic, selective annealing process to activate the implants during the ion implantation 17 200937636 process. In this: 2:::嶋 ion ion implant: after, ^ΐΖΤ,:;:ΤΤ^ 14^αν^, remove the closed-electrode dielectric to form the invention _ ❹ 垃 垃 f f-layer self-assembly The block copolymer is applied to the structure shown in Figure 1 ,, and ft forms a single-aligned pattern containing repeating structures. The height of the layer from and to the read copolymer has a thickness substantially the same as the thickness of the gate electrode 16. Therefore, the self-assembling segmented copolymer does not extend beyond the uppermost surface of the patterned material stack 12. At least the topography edge 20 of the patterned electrode 16 serves as a mandrel that maintains the block copolymer that needs to be patterned in this region. There are many different types of block copolymers that can be used to practice the invention. As long as the block copolymer contains two or more different polymeric block components that are immiscible with each other, the two or more different polymeric block components can be separated into different phases of two or more nanometer grades, thereby being suitable under suitable conditions A pattern of isolated nano-sized structural units is formed. In a preferred but not necessarily specific embodiment of the invention, the bulk copolymer is substantially comprised of the first and second polymeric block components A and B 18 200937636 which are immiscible. The stagnation copolymer may contain any number of polymeric oxime's arranged in any manner to form knives A and B. The inlaid copolymer can have a direct bond or a bond structure. Preferably, the block polymer is a linear diblock copolymer having the formula A-B. Further, the block copolymer may have any one of the following formulas:

A

A

B Α*Β·Α-Β A Β ❹ 特定 Specific examples of suitable block copolymers which can be used to form the structural unit of the present invention may include, but are not limited to, polystyrene-block-polymethacrylate (PS-b) -PMMA), polystyrene-block-polyisoprene (ps_b-pi), polystyrene block-polybutadiene (PS-b-PBD), polystyrene-block-poly Vinylpyridine (PS-b-PVP), polystyrene-block-polyethylene oxide (pS_b_PEO), polystyrene-segment-polyethylene (PS-b-PE), polystyrene_b- Polyorganophthalate (PS-b-POS), polystyrene-block-polyferrocene bismuth oxide (PS-b-PFS), polyethylene oxide-block-polyisoprene Alkene (pEO_b-PI), polyethylene oxide-dispersion-polybutadiene (ΡΕΟ-b-PBD), polyethylene oxide-segment·5^methyl acrylate acid (PEO-b) -PMMA), Poly Ethylene Ethylene - Saturated Polyethylene (PEO-b-PEE), Polybutadiene-Block-Polyethylene "Bipyridine (PBD-b-PVP), and Polyisoprene Diene-block_polydecyl acrylate (PI-b-PMMA). The specific structural unit formed from the block copolymer can be determined by the molecular weight ratio between the first and second polymeric block components A and B. For example, when the ratio of the molecular weight of the first 19 200937636 polymeric block component A to the molecular weight of the second polymeric block component B is greater than about 80:20, the block copolymer will be in a matrix consisting of the first polymeric segmental component A. In the middle, an array of neat spheres composed of the second polymeric block component b is formed. When the ratio of the molecular weight of the first polymeric block component A to the molecular weight of the second polymeric block component B is less than about 80:20 but greater than about 60:40, the block copolymer will consist of the first polymeric block component A. In the matrix, a neat cylindrical array consisting of the second polymeric block component B is formed. When the ratio of the molecular weight of the first polymeric block component A to the molecular weight of the second polymeric block component B is less than about 60:40 but greater than about 40:60, the block copolymer will form from the first and second polymeric blocks. An alternating sheet of ingredients A and B. Therefore, the molecular weight ratio between the first and second polymeric block components A and B can be adjusted in the block copolymer of the present invention to form a desired structural unit. In a preferred embodiment of the invention, the ratio of the molecular weight of the first polymeric block component A to the second polymeric block component B is from about 80:20 to about 60:40, resulting in the invention. The block copolymer will form a neat array of wires composed of the second polymeric block component b in a matrix composed of the first polymeric block component A. Preferably, the one of the components A and B is selectively movable relative to the other to form an isolated and neatly arranged structural single 7G consisting of unremoved components, or containing a removable component. A continuous structural layer of isolated or neatly arranged cavities or trenches. 20 200937636 j In Figure 1C, the non-removable block of the block copolymer is designated as reference numeral 22, and the trench established by the removable component of the segmented copolymer is designated as reference numeral 24. Note that while the current embodiment illustrates the formation of line/space patterning, the invention is not limited thereto. Due to the self-assembling block copolymer used in the process of the invention, each repeating unit has a width of about 5 Å (10) or less. Other types of patterns that can be patterned/formed include, for example, spheres, cylinders, or sheets. In a particularly preferred embodiment of the invention, the block copolymer used to form the self-assembly cycle pattern of the present invention is PS-PM-PMMA having a PS:PMMA molecular weight ratio of from about 80:20 to about 60:40. Typically, the term "X" indicates the mutual exclusion between different polymeric block components in the block copolymer, where X is the m〇ry_Huggins interaction parameter' and N is the degree of polymerization. The higher the degree, the higher the mutual repulsion between the different blocks in the block copolymer, and the more likely the phase Φ separation occurs. When λ Ν > 10 (hereinafter referred to as "strong separation limit"), phase separation is highly likely to occur between different blocks in the block copolymer. For the PS-b-PMMA diblock copolymer', X can be calculated to be about 0.028 + 3.9 / T, where T is the absolute temperature. Therefore, χ is at 473K (with 2〇() C) of about 0.0362. When the molecular weight (?η) of the PS-b-PMMA diblock copolymer is about 64 Kg/mo and the molecular weight ratio (PS:PMMA) is about 66:34, the degree of polymerization N is about 622.9, so about 200 ° C 22.5. 21 200937636 In this way, by adjusting one or more parameters, such as composition, total molecular weight, and annealing temperature, the mutual exclusion between different polymeric block components in the block copolymer of the present invention can be controlled to be differently embedded. The desired phase separation is performed between the segment components. Phase separation, in turn, can form a self-assembled periodic pattern (i.e., spherical, linear, cylindrical, or flake) containing a neat array of repeating structural units, as described above. In order to form a self-assembled periodic pattern, the copolymer is first dissolved in a suitable solvent system to form a block copolymer solution, and then the cross-section copolymer solvent is applied to the surface to form a thin block copolymer. The layer is then annealed to the thin block copolymer layer whereby phase separation is effected between the different polymeric block components contained in the block copolymer. The solvent system for dissolving the block copolymer and forming the block copolymer solution may comprise any suitable solvent 'which includes but is not limited to: methyl, monodecyl ether propylene glycol acetate (PGMEA), monoterpene Ether propylene glycol (PGME), and propylene glycol. Preferably, the block copolymer solution contains a block copolymer having a concentration of from about 0.1% to about 2% by weight based on the total weight of the solution. More preferably, the block copolymer solution contains a block copolymer having a concentration of from about 0.5% by weight to about 1.5% by weight. In a particularly preferred embodiment of the invention, the block copolymer solution comprises PS-b-PMMA dissolved in from about 5% to about 1.5% by weight of benzene or PGMEA. The block copolymer solution can be applied to the surface of the device structure using any suitable technique including, but not limited to, rotational molding, coating 22, 200937636 cloth, spray, ink coating, dip coating, and the like. Preferably, the block copolymer solution is rotationally formed on the surface of the device structure to form a thin layer of block copolymer thereon. After coating the thin block copolymer layer on the surface of the device, the entire device structure is annealed to effect microphase separation of the different block components contained in the block copolymer ' thereby forming a cycle with repeating structural units Sexual pattern.嵌段 Various methods can be utilized to anneal block copolymers using, but not limited to, thermal annealing (annealing in a vacuum or annealing in an inert atmosphere containing nitrogen or argon), ultraviolet annealing, thunder Shot annealing, solvent vapor assisted annealing (annealing at room temperature or annealing above room temperature), and supercritical fluid assisted annealing; these techniques will not be described in detail in order to avoid obscuring the focus of the present invention. In a particularly preferred embodiment of the invention, the thermal annealing step is performed, ® at a temperature above the glass transition temperature (Tg) of the block copolymer but below the decomposition or degradation temperature (Td) of the block copolymer. The block copolymer layer is annealed at a high annealing temperature. More preferably, at about 200. 〇300. The thermal annealing step is performed in the annealing temperature of (: the thermal annealing may last for less than about 1 hour to about 100 hours, and it is more common to be between about 1 hour and about 15 hours. In an alternative embodiment of the invention, utilized Ultraviolet (UV) treatment anneals the block copolymer layer.

After Fig. 1C 200937636 into eight = Γ, you can use the other f knife relative to the block copolymer to select the _, the recorded component - and the aprotic solvent: for example From the following item: Polar topography "The miscellaneous component of the filament material is read, leaving the "non-removable" component directly adjacent to the edge 20 of the topography as the spacer, reference numeral 22, representing the spacer of the present invention. Due to the self-assembled polymer technique used in the process of the present invention, the width W of the spacer 22 is measured from the bottom of the top of the semiconductor substrate 1G to > at 50 nm, and is wider at a width of about 1 〇 to about 4 〇 nm. common. At this point in the present invention, a block mask (not shown) may be formed on top of each patterned material stack 12' comprising spacers 22, and then the non-removable block copolymer is removed from the structure using conventional stripping processes. The composition 22 is provided to provide, for example, the structure shown in Figure 1D. Note that the use of a block mask is suitable for the particular embodiment described, while in other embodiments it may be unnecessary to use a block mask. Next, a conventional CMOS processing step is performed to provide the structure illustrated in Figure m. Specifically, the source/drain diffusion region 26 is formed in the surface of the semiconductor substrate 10 by conventional ion implantation. Visual 24 200937636 The case at this time the process of the invention performs a halo implant. Following the formation of the source/dot diffusion region 26, an annealing process can be used to activate the dopant implanted in the semiconductor substrate 10. Annealing may also be delayed and the annealing performed during the thermal conditions following the process of the present invention (e.g., during metal semiconductor alloy formation). Next, a metal semiconductor bismuth alloy layer 28 is formed on the source/drain diffusion region 26. The term "metal semiconductor alloy" as used herein refers to a reaction product formed by the thermal reaction of a metal with a semiconductor material. For example, the term "metal semiconductor alloy" can describe a metal; the metal is one of Ti, W, c, Ν, Pt, Pd, Er, Ir, and other rare earth or transition metal. It may also be a combination of two or more of these metals. Usually, the metal is one of Ti, W, C〇 and Ni. The term "metal semiconductor alloy" also describes a metal halide containing one of the above metals. The metal semiconductor alloy layer 28 is formed by first depositing (four) and semi-conductive material on the front of the structure of the county. The metal is usually one of Ti, W, Co, Ni, Pt and Pd, and is preferably one of Ti, W, Co and Ni. The metal may contain alloying additives such as ^, A, Si, SC, Ti, V, Cr, Mn, Fe, c, Ni, Cu, Ge, Y,

Zr, Nb, Mo, RU, Rh, Pd, ΐη, Sn, u, Hf, heart w, Re, Ir, I>t, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, H〇,

Tm, Yb, Lu and mixtures thereof. If present, the alloying additive is present in an amount up to about 50 atomic percent. The formation of metals is carried out by conventional methods, including, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, electrowinning, sputtering, chemical solution deposition, atomic layer deposition, physical vapor deposition, and others. Similar technology. The alloying additive may be formed simultaneously with the metal, or it may be added to the metal after metal deposition' or it may be co-deposited in other layers on top of the metal. The thickness of the deposited metal may vary depending on the junction thickness of the final thickness of the lithium Φ formed with respect to the upper boundary and the desired resistivity of the lower boundary. Typically, and for applications in FETs, the deposited metal has a thickness from about 5 to about 15 nm. Following the formation of the metal, an optional diffusion barrier such as TiN or TaN can be formed on top of the metal prior to annealing. The annealing is performed under the following conditions: the metal and the semiconductor are reacted together to form a metal semiconductor alloy layer, i.e., a metal telluride or a metal telluride. Annealing can be performed in a single step or a one-step annealing process can be used. Annealing is performed at a temperature of about 3 Torr or ❹ at a temperature of from about 400 to about 70 CTC. The optional diffusion barrier is removed after a single annealing process or after a first annealing of the two-step annealing, using conventional processes well known to those skilled in the art. Annealing can be performed in a constituent gas (He, Ar, or called). Annealing includes furnace annealing, rapid thermal annealing, peak annealing, microwave annealing, or laser annealing. Typically, annealing is a rapid thermal anneal' where the annealing time is typically less than about one minute. After the final annealing step, any unreacted metal is removed from the structure. 26

200937636 Note that the inter-pole 16 is formed by a Si-containing conductive material (i.e., polycrystalline stone =), and the metal semiconductor alloy layer 28 may be formed on the upper surface of the green electrode. In the concrete case where the dielectric hard material is present and remains in the structure during the formation of the metal semiconductor alloy layer, on the top of the gate electrode ,, no such metal-metal alloy layer is formed. A dielectric profile comprising oxides, nitrides, oxynitrides, or combinations thereof, is typically, but not always, formed on the structure. A dielectric profile can be used to introduce a device channel; as is well known in the art, the device channel + conductor substrate is under the _ conductor, which is laterally constrained laterally to the device source region and The lateral direction is limited to the device drain region on the other side. The dielectric liner 30 is formed using conventional depositions well known to those skilled in the art, and the thickness of the dielectric liner is typically from about 20 to about 1 〇〇 nm. Next, the interconnect dielectric material 32 is formed by deposition (usually by chemical vapor deposition, plasma enhanced chemical vapor deposition or spin coating), and σ is formed in the interconnect dielectric material 32 using lithography and surnames. . The interconnect dielectric material 包含 comprises any dielectric material having a dielectric constant of about 4. Torr or less relative to a vacuum. Some examples of suitable dielectrics that can be used to interconnect dielectric material 32 include, but are not limited to, Si 〇 2, silsesquioxanes, C-doped atoms containing other, c Ο and Η atoms. Oxide (ie, organic oxalate), thermoset poly(aryl ether), or multiple layers thereof. The term "polyaryl" as used in the specification means an aromatic moiety or a bond, such as an oxygen, sulfur, sulfone, sulfoxide, carbonyl or the like, bonded together by a bond, a fused ring, or an inert bond. Of 27 200937636 inert substituted aryl moiety. The openings are typically lined with a diffusion barrier material such as Ti, Ta, w, TaN, TiN or WN, and thereafter filled with a conductive material such as w, A, Cu or Al (:u alloy) (eg, by electroplating) openings The opening of the crucible extending to the source/drain diffusion region is referred to as a diffusion contact, and is indicated in the drawings by reference numeral 34. The contact 34 of the gate electrode 16 is also typically formed. As discussed above, the foregoing discussion represents the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the preferred embodiment of the present invention, the present invention is not limited to the FET applications described and illustrated herein, but the invention is not limited to the FET applications described and illustrated herein. The spacers can be used in any nanostructure application where the direct abutment is used to at least the topographical edges of the material layer. Other applications of the spacers of the present invention include, for example, the applications described above. ^ Referring now to Figures 2A-2B, Other structural examples of the invention. In particular, FIG. 2A shows a specific implementation such as: using lithography and etching and thereafter using the self-assembly techniques described above, in the formation of a material layer or material stack (reference numeral 5) a wide opening (having an aspect ratio of the trench height to the width of the trench greater than 1:3). In this figure t, the non-y removed component of the block copolymer is designated as reference numeral 22, and the adjacent material layer or material stack is to be The spacers at the edge of the topography (also including the non-removable components of the block copolymer) are designated 22. The material layer or stack of materials may comprise a semiconductor material, an insulating material, a conductive material, or any combination thereof. Figure 2B shows the actual 28 200937636

'The stack of adjacent layers of material or material will be stacked by the stagnation copolymer: the main one has a narrow opening: 1). In this pattern, the shape of the 丨 绿

Although the present invention has been described in detail with reference to the preferred embodiments of the present invention, it is to be understood that the invention may be modified without departing from the spirit and scope of the invention. The purpose is not limited to the illustrated and illustrated details and details, but should be based on the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1A-1E are schematic cross-sectional views depicting the basic processing steps used in accordance with the present invention. 2A-2B are cross-sectional views depicting two additional embodiments of the present invention in which a self-assembly technique is used to provide a spacer for a topographical edge of a material layer or stack of materials. [Main component symbol description] 10 semiconductor substrate 12 material stack 29 200937636 12' patterned material stack 14 gate dielectric 16 gate electrode 20 topography edge 21 source/drain extension region 22 block copolymer non-shiftable In addition to the component 22' spacer 24 is formed by the removable component of the block copolymer 26 source/drain diffusion region 28 metal semiconductor alloy layer 28' metal semiconductor alloy layer 30 dielectric liner 32 interconnect dielectric material 34 diffusion contact 34' contact 50 material layer or material stack

Claims (1)

200937636 X. Patent Application Range: 1. A semiconductor structure comprising: a patterned region comprising at least one material layer and having at least one topographical edge; and a spacer directly adjacent to the edge of the topography, the spacer comprising A polymeric block component of a self-assembling block copolymer. 2. The semiconductor structure of claim 1, wherein the self-assembling block copolymer package comprises: polystyrene-block-poly(meth)acrylate (PS-b-PMMA), polystyrene-block-poly Isoprene (PS-b-PI), polystyrene-block-polybutadiene (PS-b-PBD), polystyrene-block-polyvinylpyridine (PS-b-PVP), poly Styrene-block-polyethylene oxide (PS-b-PEO), polystyrene-block-polyethylene (PS-b-PE), polystyrene, polyorganoantimonate (PS-b- POS), polystyrene-block-polyferrocene dimethyl sulphur (PS-b-PFS), polyethylene oxide-block-polyisoprene (PE〇-b-PI) , polyethylene oxide-block-polybutadiene (PEO-b-PBD), polyethylene oxide-ruthenium-polymethyl acrylate (PEO-b-PMMA), polyepoxy Ethylene-post-stage-saturated polyethylene (PEO-b-PEE), polybutane-enephrasing-polyvinylpyridine (PBD-b-PVP), or polyisoprene-block-polymethacrylic acid Ester (PI-b-PMMA). 3. The semiconductor structure of claim 1 wherein the spacer has a width of less than 50 nm as measured at its bottommost portion. 31 to about 40 patterning ❹ 譬 200937636 4. The semiconductor structure of claim 3, wherein the width is from about 10 nm. I. The semiconductor structure of claim 1, wherein the lithography region is utilized. 6. The semiconductor structure of claim 1, wherein the patterned region comprises a half conductor material, a dielectric material, a conductive material, or any combination thereof. 7. A semiconductor structure as claimed in claim 1, wherein the closed domain comprises a patterned gate electrode of the effect transistor. Half of the structure, wherein the patterned electrode comprises a compound, a metal nitride or any multilayer thereof, such as a semiconductor structure, such that the patterned region additionally includes a site under the _ _ electrode _ Extreme dielectric.匕3 10. A semiconductor structure comprising: a semiconductor substrate; a patterned gate electrode comprising at least one patterned gate electrode having a topography edge; and a 间隙man' a spacer directly adjacent to the edge of the topography The spacer comprises a polymeric block component of a 32 200937636 self-assembling block copolymer. 11. The semiconductor structure of claim 10, wherein the self-assembling block copolymer comprises: polystyrene-block-polydecyl acrylate (PS-7-PMMA), polystyrene-block-polyisoprene Alkene (PS-b-PI), polystyrene-block-polybutylene dichloride (PS-b-PBD), polystyrene-block-polyethylene η-bite (ps-b-PVP), Polystyrene-block-polyethylene oxide (PS-b-PEO), polystyrene-block_polyethylene (PS-b-PE), polystyrene-b-polyorganic acid Salt® (PS-bp〇s), polystyrene-block-polyferrocene dimethyl decane (PS-b-PFS), polyethylene oxide-dispersion-polyisoprene (PE0_b_pi) , polyethylene oxide-block polybutadiene (PEO-b-PBD), polyepoxybutane, poly-mercapto acrylate (PEO-b-PMMA), polyepoxy -Section - Saturated Polyethylene (PEO-b-PEE), Polybutadiene-Block_Polycene (PBD-b-PVP), or Polyisoprene-Block-Polymethyl Acrylate (PI-b-PMMA). ® 12. The semiconductor structure of claim 1, wherein the spacer has a width of less than 50 nm measured at a lowermost portion thereof. 13. The semiconductor structure of claim 12, wherein the width is from about 1 〇 to about 4 〇 〇 14. The semiconductor structure of claim 1 wherein the patterned gate electrode comprises a Si-containing conductor 'a conductive metal , a conductive metal alloy, a metal 矽 33 ❹ ❷ 200937636 compound, - money compound or private multi-layer stack combination. 15. The semiconductor structure of claim 10, comprising an inter-electrode dielectric stack below the rounded gate electrode. 16. The semiconductor structure of claim 15 having a dielectric constant greater than 4.0 Dielectric material. ” 糸 具有 has a semiconductor clock of claim 10 and the top of the patterned material stack d the semiconductor substrate A, additionally comprising - in the semiconductor substrate dielectric material. The method of forming an interconnection structure in a semiconductor structure comprises: a package: at least a material layer and a spacer having a top edge having at least a topography edge, the spacer wall 3 being self-touched The method of claim 20, wherein the method of claim 20, wherein the providing the patterned region comprises a lithography patterning process. 22. The method of claim 20, wherein the self-assembling block The copolymer is selected from the group consisting of polystyrene-block_polydecyl acrylate (PS-b-PMMA), polystyrene-block-polyisoprene (PS_b_pi), polyfluorene Stupid ethylene block-polybutadiene (PS-b-PBD), polystyrene-enemy-polyethylene-bite (PS-b-PVP), polystyrene-block-poly epoxy Alkane (PS-b-PEO), polystyrene-block-polyethylene (PS_b_PE), polystyrene-7 polyorganosilicate (PS_b_P0S), polystyrene Ene-block_polyferrocene dimethyl decane (PS-b-PFS), polyethylene oxide-block-polyisoprene (PEO-b-PI), polyethylene oxide- mourning Segment-polybutadiene (pE〇_b_pBD), polyepoxypyrene-block-polymethacrylate (PE〇_b-PMMA), polycyclohexene-block-saturated polyethylene ( PEO-b-PEE), polybutadiene-drum segment-polyethylene pyridine (PBD-b-PVP), and polyisoprene-block-polydecyl acrylate (PI-b-PMMA). 23. The method of claim 20, wherein the forming the spacer comprises coating a self-assembling block copolymer in a region adjacent the patterned region, annealing to form one of the removable and non-removable polymeric components. The array, and the removal of the removable polymeric components. 24. The method of claim 23, wherein the coating comprises rotational molding, coating, 200937636 sprinkler irrigation, ink coating or dip coating. The method is a solution, wherein the coating is a method of rotationally forming a block copolymerization 2 = claim 23, wherein the annealing comprises thermal annealing, ultraviolet light retreating, laser agency, solution phase annealing, supercritical fluid fire 27. If requested The method of claim 26, wherein the annealing is performed by a thermal annealing at a temperature of from about 2 t to about 30 ° C. 28. The method of claim 20 wherein the spacer has a smaller one measured at a lowermost portion thereof 29. The method of claim 28, wherein the width is from about 1 〇 to about 4 〇 nm. 30. A method of forming a semiconductor structure, comprising: providing on a surface of a semiconductor substrate a patterned material stack comprising at least one patterned gate electrode, the patterned gate electrode having a topography edge; and a spacer directly adjacent the edge of the topography, the spacer comprising a self-assembling block copolymer a polymeric block component of the material. The method of claim 30, wherein the self-assembling block copolymer is selected from the group consisting of polystyrene-block-poly(meth)acrylate (PS-b-PMMA), poly Styrene-segment polyisoprene (ps-b-PI), polystyrene-block-polybutadiene (PS-b-PBD), polystyrene-block-polyvinylpyridine (PS- b-PVP), polystyrene-block-polyethylene oxide (PS-b-PEO), polystyrene-block-polyethylene (PS_b_PE), polystyrene-b-polyorganosilicate ( PS_b-POS), polystyrene-block-polyferrocene dioxime methyl decane (PS-b-pFS), polyethylene oxide-block-polyisoprene (PEO-b-PI) , polyethylene oxide-block_polybutadiene (pE〇_b pBD), polyethylene oxide-block-polydecyl acrylate (pE〇_b_PMMA), polyepoxy-embedding Segment-saturated polyethylene (PEO_b_PEE), polybutadiene, stagnation _ polyvinyl pyridine (PBD-b-PVP), and polyisoprene-block _ polydecyl acrylate (PI-b-PMMA) ). The method of claim 3, wherein the forming the spacer comprises coating a self-assembling block copolymer in an area adjacent to the patterned material stack, annealing to form removal and *removable polymer composition - tidy and remove the removable polymeric components. Coating 33.=:^. The coating comprises a rotational molding, 34. solution as claimed in claim 33. Method of the invention wherein the coating is rotationally shaped - block copolymerization 37 200937636 35. The method of claim 32, wherein the annealing comprises thermal annealing, ultraviolet annealing, laser annealing, solvent vapor assisted annealing or supercritical fluid assist Annealing 0. 36. The method of claim 35, wherein the annealing is performed on-to-be. Thermal annealing to a temperature of about 300 C. ❹ 37. The method of claim 30, wherein the towel has a width of less than 50 nm measured. What is the bottom part? 38. The method of claim 37, wherein the width is from about 30 to about 38 nm.