200935732 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種固定增益放大電路，特別是一種具 固定增益之電流切換邏輯（CML)電路。 【先前技術】 ❹ 第一圖顯示一種傳統轉導（transconductance )電 路1 〇 ’其具有源極退化（source degeneration)之組態。 此種電路10經常使用於電子系統中，用以線性放大輸入 5凡號至所需的輸出擺幅（swing )，以方便後級電路（例 如判斷電路）之操作^此電路1〇之小信號增益 (V0/(Vi+-Vi-))可以表示為 RL*gm/(l+(Rs/2)*gm/2)， ❹甘 其中RL為負載，gm為n型金屬氧化半導體（MOS)電 晶體Μ的轉導，RS為連接於兩個n型MOS電晶體Μ之 間的電阻。如果Ν型MOS電晶體Μ之轉導gm相當大時， 則上述的小信號增益可以近似為2*RL/Rs。然而，RL的 選擇受限於差動（differential)輸入Vi+、Vi-的速度；亦 即’若差動輸入Vi+、Vi_的速度較快，則RL之值就不能太 大。在RL不能太大的前提下，rs之值就必須很小，才能 200935732 得到一個夠大的增益。但是，Rs之值又不能太小，因為 Rs*gm之值要遠大於1才能使得增益可以近似為 RL/Rs。所以，只能藉由增力σ偏壓電流Ibias來讓gm值 變大；但是，這麼一來就會犧牲了輸出信號V。的直流位準 (或操作點）。 鑑於上述，因此亟需提出一種具固定小信號增益之電 ©路，用以解決傳統源極退化組態電路10之缺點。 【發明内容】 本發明目的之一在於提出一種具固定增益之電路，其可 以兼顧頻寬、功率及操作點的設計。 ❹ 本發明實施例包含一電流切換邏輯（CML)電路，及一 固定轉導（transconductance)電路，其提供偏壓給電 流切換邏輯電路，使其具有固定增益。根據其中一實施例， 固定轉導電路包含一電流鏡電路，藉由調整其電晶體彼此 間的寬長比（W/L)，使其具有固定轉導；以此固定轉導電 流鏡電路來偏壓電流切換邏輯電路，使其固定增益正比於 電流切換邏輯電路與固定轉導電路兩者之電阻比例。 200935732 【實施方式】 第二圖顯示本發明實施例之具固定增益的電流切換邏 輯（current mode logic，CML)電路2〇,其受到固定轉 導(transconductance )電路 30 之值厭,,_ 心偈壓。在本實施例中， 固定轉導電路30係為-電流鏡電路，然而本發明並不限 定於此，其他具有固定轉導之電路也可適用。 ❹ 電流切換邏輯電路20包含N型金屬氧化半導體 (MOS)電晶體Ml、M2，其閘極分別接收差動輸入Vi+、 Vi- ’而電晶體Ml、M2汲極之間則作為輸出v。。電晶體 Ml、M2没極與電源Vdd之間分別連接有負載電阻RL。 電晶體Ml、M2的源極連接在一起，其與地之間則連接有 一個電流源（current source)。在本實施例中，此電流 〇源包含一 N型MOS電晶體M3，其沒極連接至電晶體 Ml、M2的源極’其源極接地’其閘極則受到固定轉導電 路30之偏壓。 在本實施例中，固定轉導電路30包含有N型MOS 電晶體M4、M5，其閘極互相連接在一起。其中，電晶體 M4為二極體連接組態（diodeconnected)，亦即，其波 極與閘極互相連接；電晶體M5之寬（W)與長（L)比值 200935732 (K*(W/L)n)係為電晶體M4之寬長比（（W/L)n)的K倍， 其中Κ大於1，例如Κ等於4。電晶體Μ4之源極接地， 而電晶體Μ5之源極與地之間連接一電阻Rb。電晶體 M4、M5汲極與電源Vdd之間分別連接P型MOS電晶體 M6、M7，其中電晶體M7為二極體連接組態（diode connected )，亦即，其没極與閘極互相連接。200935732 IX. Description of the Invention: [Technical Field] The present invention relates to a fixed gain amplifying circuit, and more particularly to a current switching logic (CML) circuit having a fixed gain. [Prior Art] ❹ The first figure shows a conventional transconductance circuit 1 ’ ' having a configuration of source degeneration. Such a circuit 10 is often used in an electronic system to linearly amplify an input 5 to a desired output swing to facilitate operation of a subsequent stage circuit (eg, a decision circuit). The gain (V0/(Vi+-Vi-)) can be expressed as RL*gm/(l+(Rs/2)*gm/2), where RL is the load and gm is the n-type metal oxide semiconductor (MOS) transistor The transduction of Μ, RS is the resistance connected between two n-type MOS transistors. If the transduction gm of the MOS-type MOS transistor 相当 is relatively large, the small signal gain described above can be approximated as 2*RL/Rs. However, the choice of RL is limited by the speed of the differential inputs Vi+, Vi-; that is, if the differential inputs Vi+, Vi_ are faster, the value of RL cannot be too large. Under the premise that the RL cannot be too large, the value of rs must be small to get a large enough gain for 200935732. However, the value of Rs cannot be too small, because the value of Rs*gm is much larger than 1 to make the gain approximate RL/Rs. Therefore, the gm value can only be increased by increasing the bias σ bias current Ibias; however, the output signal V is sacrificed in this way. DC level (or operating point). In view of the above, it is therefore desirable to provide an electrical path with a fixed small signal gain to address the shortcomings of the conventional source degraded configuration circuit 10. SUMMARY OF THE INVENTION One object of the present invention is to provide a circuit with a fixed gain that allows for both bandwidth, power, and operating point design. ❹ Embodiments of the invention include a current switching logic (CML) circuit, and a fixed transconductance circuit that provides a bias voltage to the current switching logic circuit to have a fixed gain. According to one embodiment, the fixed transduction circuit comprises a current mirror circuit, which has a fixed transconductance by adjusting the width to length ratio (W/L) of the transistors to each other; thereby fixing the conductive flow mirror circuit The bias current switches the logic circuit such that its fixed gain is proportional to the resistance ratio of both the current switching logic circuit and the fixed transduction circuit. 200935732 [Embodiment] The second figure shows a current mode logic (CML) circuit 2 with a fixed gain according to an embodiment of the present invention, which is subjected to the value of the fixed transconductance circuit 30, _ 偈Pressure. In the present embodiment, the fixed transduction circuit 30 is a current mirror circuit, but the present invention is not limited thereto, and other circuits having fixed transduction are also applicable.电流 Current switching logic circuit 20 includes N-type metal oxide semiconductor (MOS) transistors M1, M2, the gates of which receive differential inputs Vi+, Vi-', respectively, and the drains of transistors M1, M2 serve as outputs v. . A load resistor RL is connected between the transistor M1 and M2 and the power supply Vdd. The sources of the transistors M1, M2 are connected together, and a current source is connected to the ground. In this embodiment, the current source includes an N-type MOS transistor M3, and its gate is connected to the source of the transistors M1 and M2, the source of which is grounded, and the gate thereof is biased by the fixed transducing circuit 30. Pressure. In the present embodiment, the fixed transduction circuit 30 includes N-type MOS transistors M4, M5 whose gates are connected to each other. Among them, the transistor M4 is diode-connected, that is, its wave and gate are connected to each other; the width (W) and the length (L) of the transistor M5 are 200935732 (K*(W/L) n) is K times the width to length ratio ((W/L)n) of the transistor M4, wherein Κ is greater than 1, for example, Κ is equal to 4. The source of the transistor Μ4 is grounded, and a resistor Rb is connected between the source of the transistor Μ5 and the ground. The P-type MOS transistors M6 and M7 are respectively connected between the drains of the transistors M4 and M5 and the power supply Vdd, wherein the transistor M7 is diode-connected, that is, the poles are connected to the gates. .
於固定轉導電路30中，流經電晶體M4之參考電流I 會鏡射（mirror )至電阻Rb，再進而提供偏壓給電流切換 邏輯電路20之電晶體M3。固定轉導電路30可以經調整 使其具有固定之轉導gm，以—固定轉導方式來偏壓電流切 換邏輯電路20，可使其if盏 固定。上述之參考電流I可 以表不為. 1= (1. 2 1 ❹In the fixed transducing circuit 30, the reference current I flowing through the transistor M4 is mirrored to the resistor Rb, which in turn provides a bias voltage to the transistor M3 of the current switching logic circuit 20. The fixed transducing circuit 30 can be adjusted to have a fixed transconductance gm that biases the current switching logic circuit 20 in a fixed transconductance mode to enable its if. The above reference current I can be expressed as. 1= (1. 2 1 ❹
μηε〇χ{ΨΙΠ)η Rbz ' VF 其中，/in為電子遷移率（mobility)，Cox為閘極至地的 電容值。 電流切換邏輯電路20之增益可以表示為： (1--j=)2 *RL〇cRL/Rb gm*RL=i2*MnCox(W/L)mΗηε〇χ{ΨΙΠ)η Rbz ' VF where /in is the electron mobility and Cox is the capacitance of the gate to the ground. The gain of the current switching logic circuit 20 can be expressed as: (1--j=)2 *RL〇cRL/Rb gm*RL=i2*MnCox(W/L)m
MnCox(W/L)n Rb2 4K 200935732 根據上式可得知，電流切換邏輯電路20之增益為一個 固定值，亦即，為電阻比例RL/Rb。藉此，電流切換邏輯 電路20之偏壓電流不需要大電流即可得到夠大的轉導， 因此可以節省電流（或功率）。再者，即使差動輸入Vi+、 Vi-的速度快，也不會影響RL的選取，因而可以兼顧到頻 寬。另外，也不會犧牲了輸出信號V。的直流位準（或操作 點）。 ❹ 在本實施例中，電流切換邏輯電路20與固定轉導電路 30係整合在一起；也就是說，兩者係以同一製程製造的。 因此，電流切換邏輯電路20之電阻RL與固定轉導電路 30之電阻Rb會具有相同的特性，使得電流切換邏輯電路 20之增益RL/Rb可以保持固定，不會受到製程變動的影 響。 〇 第三圖顯示本發明另一實施例之具固定增益的電流切 換邏輯（CML)電路40,其受到固定轉導電路50之偏壓。 本實施例類似於第二圖之實施例，主要差別在於將原N型 MOS電晶體置換為P型MOS電晶體，並將原P型MOS 電晶體置換為N型MOS電晶體。 200935732 電流切換邏輯電路40包含p型]viOS電晶體ΤΙ、Τ2， 其閘極分別接收差動輪入Vi+、Vi-，而電晶體ΤΙ、Τ2汲極 之間則作為輸出V。。電晶體T1、τ2汲極與地之間分別連 接有負載電阻RL。電晶體T1、Τ2的源極連接在一起，其 與電源Vdd之間則連接有一個電流源（current source)。在本實施例中，此電流源包含一 p型m〇s電 晶體T3，其汲極連接至電晶體τΐ、T2的源極；其源極連 ❹接至電源Vdd ;其閘極則受到固定轉導電路50之偏壓。 固定轉導電路50包含有P型MOS電晶體T4、T5,其 閘極互相連接在一起。其中，電晶體Τ5為二極體連接組 態（diode connected)，亦即，其沒極與閘極互相連接； 電晶體T5之寬（W)與長（L)比值（K*(W/L)P)係為電 晶體T4之寬長比（（W/L)p)的K倍，其中K大於1，例 ©如K等於4。電晶體T4之源極接至電源Vdd，而電晶體 T5之源極與電源vdd之間連接一電阻Rb。電晶體T4、 T5汲極與地之間分別連接n型MOS電晶體T6、T7，其 中電晶體T6為二極體連接組態（diode connected)，亦 即’其汲極與閘極互相連接。 200935732 固定轉導電路50之參考電流I與電流切換邏輯電路40 之增益類似於第二圖實施例，因此不再贅述。與第二圖實 施例之結果一樣，電流切換邏輯電路40之增益為一個固 定值，亦即，為電阻比例RL/Rb。藉此，電流切換邏輯電 路40之偏壓電流不需要大電流即可得到夠大的轉導，因 此可以節省電流（或功率）。再者，即使差動輸入Vi+、Vi-的速度快，也不會影響RL的選取，因而可以兼顧到頻寬。 ❹另外，也不會犧牲了輸出信號V。的直流位準（或操作點）。 在本實施例中，電流切換邏輯電路40與固定轉導電路 50係整合在一起；也就是說，兩者係以同一製程製造的。 因此，電流切換邏輯電路40之電阻RL與固定轉導電路 50之電阻Rb會具有相同的特性，使得電流切換邏輯電路 40之增益RL/Rb可以保持固定，不會受到製程變動的影 〇響。 以上所述僅為本發明之較佳實施例而已，並非用以限定 本發明之申請專利範圍；凡其它未脫離發明所揭示之精神 下所完成之等效改變或修飾，均應包含在下述之申請專利 範圍内。 【圖式簡單說明】 11 200935732 第一圖顯示一種具源極退化組態之傳統轉導電路。 第二圖顯示本發明實施例之具固定增益的電流切換邏輯電 路，其受到固定轉導電路之偏壓。 第三圖顯示本發明另一實施例之具固定增益的電流切換邏 輯電路，其受到固定轉導電路之偏壓。 【主要元件符號說明】MnCox(W/L)n Rb2 4K 200935732 According to the above equation, the gain of the current switching logic circuit 20 is a fixed value, that is, the resistance ratio RL/Rb. Thereby, the bias current of the current switching logic circuit 20 does not require a large current to obtain a large enough transconductance, thereby saving current (or power). Furthermore, even if the speeds of the differential inputs Vi+ and Vi- are fast, the selection of the RL is not affected, so that the bandwidth can be balanced. In addition, the output signal V is not sacrificed. DC level (or operating point). In the present embodiment, the current switching logic circuit 20 is integrated with the fixed transduction circuit 30; that is, both are manufactured in the same process. Therefore, the resistance RL of the current switching logic circuit 20 and the resistor Rb of the fixed transducing circuit 30 have the same characteristics, so that the gain RL/Rb of the current switching logic circuit 20 can be kept constant without being affected by the process variation. The third figure shows a fixed-gain current switching logic (CML) circuit 40 of another embodiment of the present invention that is biased by a fixed transduction circuit 50. This embodiment is similar to the embodiment of the second figure, and the main difference is that the original N-type MOS transistor is replaced with a P-type MOS transistor, and the original P-type MOS transistor is replaced with an N-type MOS transistor. 200935732 The current switching logic circuit 40 includes a p-type]viOS transistor ΤΙ, Τ2, the gates of which receive the differential wheel Vi+, Vi-, respectively, and the transistor ΤΙ, Τ 2 汲 between the poles as the output V. . A load resistor RL is connected between the drains of the transistors T1 and τ2 and the ground. The sources of the transistors T1 and Τ2 are connected together, and a current source is connected to the power source Vdd. In this embodiment, the current source includes a p-type m〇s transistor T3, the drain of which is connected to the source of the transistors τΐ, T2; the source is connected to the power supply Vdd; and the gate is fixed. The bias voltage of the transducing circuit 50. The fixed transduction circuit 50 includes P-type MOS transistors T4, T5 whose gates are connected to each other. Wherein, the transistor Τ5 is diode connected, that is, its pole is connected to the gate; the width (W) and length (L) ratio of the transistor T5 (K*(W/L) P) is K times the width to length ratio ((W/L)p) of the transistor T4, where K is greater than 1, for example, if K is equal to 4. The source of the transistor T4 is connected to the power source Vdd, and a resistor Rb is connected between the source of the transistor T5 and the power source vdd. The n-type MOS transistors T6 and T7 are respectively connected between the drains of the transistors T4 and T5 and the ground, and the transistors T6 are diode-connected, that is, the drains and the gates are connected to each other. The gain of the reference current I and the current switching logic circuit 40 of the fixed transduction circuit 50 is similar to that of the second embodiment, and therefore will not be described again. As with the results of the second embodiment, the gain of the current switching logic circuit 40 is a fixed value, i.e., the resistance ratio RL/Rb. Thereby, the bias current of the current switching logic circuit 40 does not require a large current to obtain a large transconductance, thereby saving current (or power). Furthermore, even if the speeds of the differential inputs Vi+ and Vi- are fast, the selection of the RL is not affected, and thus the bandwidth can be taken into consideration. In addition, the output signal V is not sacrificed. DC level (or operating point). In the present embodiment, the current switching logic circuit 40 is integrated with the fixed transduction circuit 50; that is, both are manufactured in the same process. Therefore, the resistor RL of the current switching logic circuit 40 and the resistor Rb of the fixed transducing circuit 50 have the same characteristics, so that the gain RL/Rb of the current switching logic circuit 40 can be kept constant without being affected by the variation of the process. The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application. [Simple description of the diagram] 11 200935732 The first figure shows a traditional transduction circuit with a source degraded configuration. The second figure shows a current switching logic circuit with a fixed gain in accordance with an embodiment of the present invention that is biased by a fixed transducing circuit. The third figure shows a current switching logic circuit with a fixed gain according to another embodiment of the present invention, which is biased by a fixed transducing circuit. [Main component symbol description]
10 20 30 40 50 Μ Rs RL ❹ 源極退化組態電路 電流切換邏輯電路 固定轉導電路 電流切換邏輯電路 固定轉導電路 ❹ 源極退化組癌電路之電晶體 源極退化組態電路之電阻 負載 M1-3電流切換邏輯電路之電晶體 M4-7固定轉導電路之電晶體 Rb 固定轉導電路之電阻 T卜3電流切換邏輯電路之電晶體 T4-7固定轉導電路之電晶體 1210 20 30 40 50 Μ Rs RL ❹ Source Degraded Configuration Circuit Current Switching Logic Circuit Fixed Transducer Circuit Current Switching Logic Circuit Fixed Transducer Circuit 电阻 Resistive Load of Transistor Source Degraded Configuration Circuit of Source Degraded Group Cancer Circuit M1-3 current switching logic circuit transistor M4-7 fixed transconductance circuit transistor Rb fixed transduction circuit resistance Tb3 current switching logic circuit transistor T4-7 fixed transduction circuit transistor 12