200935207 九、發明說明： 【發明所屬之技術領域】 本發明係有關-種參考電壓產生裝置，特別係一種可調整參考電壓 之準位係固定狀態的參考電壓產生敦置。 【先前技術】 不論是對於類比電路或數位電路設計而言，具有穩定的參考 電壓乃是相#重要的。惟，要保持參考電壓準位固定並不是—件 Ο ❹ 簡單的事，因為參考電卿料ι會㈣魏溫度、製造過程' 電源電壓準位等因素而偏移。 請參照第-圖，係習知一種參考電壓產生裝置示意圖。如圖 所示’習知的參考電壓產生敦置1〇係一種利用電晶體在弱反轉區 Ueak in—)工作的㈣轉考糕產生裝置，純括—電流產 生電路12與-主動負載電路14。且，電流產生電路η係用於產生 -電流1«，包括-電流鏡電路’其係由兩腦電晶體mi、脱所組成，電 晶體Ml與M2之閘極相互叙接且源極皆墟一供應電壓_，電晶體脱之 閘極斯及極並祕在-起，另—電流鏡（emTent mi·)電路，其係由 兩_S電晶體M3與M4所組成，電晶體M3與M4之閘極相絲接且電晶體 M3與M4又各職接電晶體犯㈣，且電晶體脱之閘極與祕麵接在一 起’以及兩個二極體電路，其分別具一臓電晶體奶與舶，電晶龍與 册之源姉接-供應電壓Vss且電晶體奶與分別與電晶體耶與_ 接’且電晶體脱之醜與閘極輕接，電晶細之汲極亦與閉極麵接在一 起。其中’電流產生電路12所產生的電流丨。可町列方程式⑴所表示， 5 (1) 200935207 可得知電流Ι〇幾乎與電源電壓準位無關：200935207 IX. Description of the Invention: [Technical Field] The present invention relates to a reference voltage generating device, and more particularly to a reference voltage generating state in which a fixed state of a reference voltage can be adjusted. [Prior Art] Whether for analog circuits or digital circuit designs, it is important to have a stable reference voltage. However, it is not a simple matter to keep the reference voltage level fixed, because the reference is offset by factors such as the temperature of the device, the temperature of the manufacturing process, and the voltage level of the power supply. Please refer to the first figure, which is a schematic diagram of a reference voltage generating device. As shown in the figure, the conventional reference voltage generation method is a (four) transfer cake generating device that operates using the transistor in the weak reversal zone Ueak in-), and the pure-current generating circuit 12 and the active load circuit are provided. 14. Moreover, the current generating circuit η is used to generate a current -1«, including a current mirror circuit, which is composed of two brain cells mi and detachment, and the gates of the transistors M1 and M2 are mutually connected and the source is the source. A supply voltage _, the transistor is off the gate and the pole is in the same way, the other is the current mirror (emTent mi·) circuit, which is composed of two _S transistors M3 and M4, the transistors M3 and M4 The gate is connected to the pole and the transistors M3 and M4 are connected to each other (4), and the gate of the transistor is disconnected from the gate and the two diode circuits are respectively provided with a transistor. Milk and the ship, the electric crystal dragon and the source of the book are connected - supply voltage Vss and the transistor milk is connected with the transistor and the _ _ and the transistor is ugly and the gate is lightly connected, and the crystal is fine Connected to the closed pole face. The current generated by the current generating circuit 12 is 丨. According to equation (1), the equation (1), 5 (1) 200935207 shows that the current Ι〇 is almost independent of the power supply voltage level:
~~2~~2
Fr 是熱當電壓（thermal voltage)，m Ο 是次臨限擺幅參數(sub-threshold swing parameter)，是使次臨限電流增 加十倍的閘極電壓增量。又，％與13分別為NM0S電晶體M3之閘極寬度與 閘極長度’ ％與Ζ4分別為NM0S電晶體M4之閘極寬度與閘極長度，％與心分 別為NM0S電晶體Μ5之閘極寬度與閘極長度，與ζ6分別為NM0S電晶體Μ6 之閘極寬度與閘極長度。 主動負載電路14則包括一 PM0S電晶體Μ9耦接電流產生電路12之電 晶體M2與Μ4於節點1以接收電流I。，NM0S電晶體Μ7、Μ10與MU，每一 電晶體之閘極耦接没極’且電晶體Μ7耦接Μ10及一供應電壓Vss，電晶體 Ml0與Ml 1則耦接電晶體M9於節點2，以及一 NM0S電晶體M8耦接電晶體Fr is the thermal voltage, and m Ο is the sub-threshold swing parameter, which is the gate voltage increment that increases the secondary current by ten times. Moreover, % and 13 are respectively the gate width and gate length '% and Ζ4 of the NM0S transistor M3 are the gate width and the gate length of the NM0S transistor M4, respectively, and the % and the center are the gates of the NM0S transistor Μ5, respectively. The width and gate length, and ζ6 are the gate width and gate length of the NM0S transistor Μ6, respectively. The active load circuit 14 includes a PMOS transistor 9 coupled to the transistors M2 and Μ4 of the current generating circuit 12 to receive the current I. , NM0S transistor Μ7, Μ10 and MU, the gate of each transistor is coupled to the pole ' and the transistor Μ7 is coupled to Μ10 and a supply voltage Vss, and the transistors M10 and Ml1 are coupled to the transistor M9 at node 2 And an NM0S transistor M8 coupled to the transistor
M7、M10與Mil。主動負載電路接收電流1«而在電晶體M8的汲級產生一參 考電壓Vref，參考電壓Vref並可以下列方程式（2)所表示：M7, M10 and Mil. The active load circuit receives the current 1« and generates a reference voltage Vref at the level of the transistor M8. The reference voltage Vref can be expressed by the following equation (2):
其中卜=//„(^%7，，&為臨界電壓，巧與‘分別為NM〇s (2) 電晶艘M7之閘極寬度與閘極長度，％與&分別為剛os電晶體M8之閘極寬 度與閘極長度，％與A分別為PM0S電晶體M9之閘極寬度與閘極長度，％。 6 200935207 與A。分別為NM0S電晶體M10之閘極寬度與閘極長度。 故，由方程式（2)可得知參考電壓準位和臨界電壓匕相關，且由於不同 的製程參數會產生不一樣的臨界電壓，所以參考電壓準位會隨製程參數變 ^ 動而有大幅度的偏移，如第二圖所示之溫度與參考電壓關係圖，其中八組 為在典型電晶體元件參數模型下的關係圖，8組為在較劣電晶體元件參數模 型下的關係圖’而C組為在較優電晶體元件參數模型下的關係圖。 有鑑於此，本發明係針對上述之困擾，提供一種創新的參考電 〇 壓產生裝置以克服上述缺失。 【發明内容】 本發明之一目的係在提供一種參考電壓產生裝置，其主要藉由一 改良的主動負載電路及配合一用於提供參考電壓控制準位的參考電壓準位 供應電路來降低參考電鮮位的偏移幅度，其巾主動貞載電路侧於輸出 一參考電壓，且主動負載電路會根據參考電壓準位供應電路所提供的參考 電壓控制準位來降低或是提高參考電壓準位，如此即可保持參考電壓之準 Q 位保持固定。 根據本發明所揭示的參考電壓產生裝置，係包括—電流產生電 路 主動負載電路耗接電流產生電路，以及一參考電壓準位供應電路搞 接主動負载電路。其中，電流產生電路係用於產生一電流，參考電壓準位 供應電路係用於提供至少一第一參考電壓控制準位與一第二參考電壓控制 準位，主動負載電路則從電流產生電路接收此電流且輸出一參考電壓，且 主動負載電路會依據參考電壓準位供應電路所提供的第一、第二參考電壓 控制準位，使所輸出的參考電壓之準位係保持在固定狀態。 7 200935207 且，主動負載電路包括至少一第一參考電壓控制電路與一相耦接第二 參考電壓控制電路，第一參考電壓控制電路係根據第一參考電壓控制準 位，增加從電流產生電路所汲取的電流，以降低參考電壓之準位， 第二爹 考電壓控制電路根據第二參考電壓控制準位，增加從電流產生電路所汲取 的電流，以提升參考電壓之準位。 本發明之目的或其他目的對於此技藝之通常知識者而言，閱讀以下實 施例之詳細内容後係顯而易知的。 先前的概述與接下來的詳細敘述都是範例，以便能進一步解釋本發明 之專利請求項。 【實施方式】 請參照第三圖，係根據本發明之一種參考電壓產生裝置的電 路示意圖。如圖所*，本發明之參考電壓裝置2〇 a包括一用於產 生電流1〇的電流產生電路22，一主動負載電路24減電流產生電略 22以接收電流h並輸出—參考電MVref，以及—參考電壓準位供應電略 26耦接主動負載電路24，且參考賴準健應電路26具有記憶元件，如 電子可抹除可程式化唯讀記憶體⑽P_)，以供晶圓經製造產出後，將參 考電壓控鮮位資繼存在記憶元件巾，因此參考電壓雜鶴電路％可 提供至少-第-參考電壓控制準位(sl...Sn)與—第二參考電壓控制準位 (Fl，"Fn)供主動負載電路24參考。 本發明的電流產生電路22與習知的電流產生電路12相同，即包括兩 電流鏡電路’其巾之—電流鏡電路具有兩她接的腦電晶額、船，另 -電流鏡電路具有兩她接的_s電晶體M3、M4，以及兩個二極趙電路， 8 200935207 其中一個二極體電路係由__N閘極輕接没極的顺〇s電晶體M5所構成，另 -一極體電路係由一閘極祕沒極的腿〇s電晶體M6所構成，且此兩二極 體電路之偏壓是在飽和區，而關於電流產生電路22之更詳細的救述内容請 直接參考電流產生電路，遂;j；再贅述。且，雜產生電路22&產生的電 流1〇是介於5nA到500nA的低電流，幾乎與電源電壓準位無關。 主動負載電路24包括一 PM0S電晶體M9，有兩相粞接的第一參考電壓 控制電路28與第二參考電壓控制電路3〇，以及兩相耦接的顺〇s電晶體M7 ^ 與NM0S電晶體M8。且’ pm〇S電晶體M9耦接電流產生電路22之PM0S電晶 體M2、NM0S電晶體M4於節點1以接收電流I。，第一參考電壓控制電路28 耦接電晶體M9於節點2,其中第一參考電壓控制電路28與第二參考電壓控 制電路30各皆包括複數二極體電路與複數NM〇s電晶體，且每一二極體電 路都是由一閘極耦接汲極的顺〇s電晶體所構成’另，顺〇s電晶體[之閘 極與没極耦接在一起’且汲極尚耦接第一參考電壓控制電路28於節點3， 源極則耦接一供應電壓VSS，NM0S電晶體M8之閘極則耦接電晶體M7之汲 Q 極於節點3，源極耦接一供應電壓Vss，汲極耦接第二參考定壓控制電路30。 因此，當電晶體M9將電流注入至第一參考電壓控制電路28與第二 參考電壓控制電路30，最後流經電晶體M8而於M8之汲極端輸出參考電壓 Vref。其中，第一參考電壓控制電路28會根據參考電壓準位供應電路26 所提供的第一參考電壓控制準位(Sl...Sn)，用來增加所汲取電流I。，以降 低參考電壓Vref之準位，所降低的幅度是即由參考電壓準位供應電路26 所控制’第二參考電壓控制電路30則是根據參考電壓準位供應電路26所 9 200935207 提供的第二參考電壓控制準位(Fl...Fn) ’用來增加所汲取的該電流I。，以 提升參考電壓Vref之準位，所提升的幅度是即由參考電壓準位供應電路π 所控制，故本發明就可藉由提升或降低參考電壓準位的方式，來修正參考 電壓之準位偏移量，使參考電壓Vref之準位保持固定。如第四圖所示之溫 度與參考電壓關係圖，其中A組為在典型電晶體元件參數模型下應有的關 係圖，B組為在較劣電晶體元件參數模型下經由參考電壓準位供應電路26 所提供的第一參考電壓控制準位(Sl...Sn)調整得到的關係圖，而C組為在 較優電晶體元件參數模型下經由參考電壓準位供應電路26所提供的第二參 考電壓控制準位(Fl"，Fn)調整得到的關係圖。 顯示利用本發明之參考電壓產生裝置，在製程參數變動的情形下， 參考電壓準位之偏移幅度已有明顯改善。 由此可知，本發明所揭示的參考電壓產生裝置利用調整參考電壓準 位的方式來降低參考電壓準位受製程參數的影響幅度，以盡可能讓參考電 壓準位保持固定。 〇 以上所述之實施例僅係為說明本發明之技術思想及特點，其目 的在使熟習此項技藝之人士能夠瞭解本發明之内容並據以實施， 當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精 神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍内。 【圖式簡單說明】 第一圖為習知之參考電壓產生裝置的電路示意圖。 第二圖為根據習知參考電壓產生裝置所產生的參考電壓與溫度的 關係圖。 200935207 第三圖為本發明之參考電壓產生裝置的電路示意圖。 第四圖為根據本發明參考電壓產生裝置所產生的參考電壓與溫度 的關係圖。 【主要元件符號說明】 ίο參考電壓產生裝置 12電流產生電路 14主動負載電路 20參考電壓產生裝置 22電流產生電路 24主動負載電路 ❹ 26參考電壓準位供應電路 28第一參考電壓控制電路 30第二參考電壓控制電路 11Where ==//„(^%7,,& is the threshold voltage, coincidence with 'NM〇s (2) gate width and gate length of M7, respectively, % and & respectively The gate width and gate length of transistor M8, % and A are the gate width and gate length of PM0S transistor M9, respectively. 6 200935207 and A. The gate width and gate of NM0S transistor M10 respectively Therefore, it can be known from equation (2) that the reference voltage level is related to the threshold voltage ,, and since different process parameters will produce different threshold voltages, the reference voltage level will change with the process parameters. Large offset, as shown in the second figure, the relationship between temperature and reference voltage. Eight of them are the relationship diagrams under the typical transistor component parameter model, and the eight groups are the relationship of the poorer transistor component parameter model. Fig. 4 and the group C is a relationship diagram under the parameter model of the superior transistor element. In view of the above, the present invention provides an innovative reference electric pressure generating device to overcome the above-mentioned drawbacks. One of the objects of the present invention is to provide a parameter The test voltage generating device mainly reduces the offset amplitude of the reference electric fresh bit by a modified active load circuit and a reference voltage level supply circuit for providing a reference voltage control level, and the active load circuit of the towel The output voltage is referenced to the reference voltage, and the active load circuit reduces or increases the reference voltage level according to the reference voltage control level provided by the reference voltage supply circuit, so that the reference Q bit of the reference voltage is kept constant. The reference voltage generating device according to the present invention includes a current generating circuit active load circuit consuming current generating circuit, and a reference voltage level supply circuit for engaging the active load circuit. The current generating circuit is configured to generate a The current, reference voltage level supply circuit is configured to provide at least a first reference voltage control level and a second reference voltage control level, and the active load circuit receives the current from the current generating circuit and outputs a reference voltage, and actively The load circuit will provide the first and second parameters provided by the reference voltage level supply circuit. The voltage control level keeps the level of the output reference voltage in a fixed state. 7 200935207 Moreover, the active load circuit includes at least one first reference voltage control circuit and one phase coupled to the second reference voltage control circuit, first The reference voltage control circuit controls the level according to the first reference voltage, increases the current drawn from the current generating circuit to lower the reference voltage level, and the second reference voltage control circuit controls the level according to the second reference voltage to increase the The current drawn by the current generating circuit is used to increase the level of the reference voltage. The object of the present invention or other objects will become apparent to those of ordinary skill in the art from reading the details of the following embodiments. The summary and the following detailed description are examples to further explain the patent claims of the present invention. [Embodiment] Please refer to the third figure, which is a circuit diagram of a reference voltage generating device according to the present invention. As shown in the figure, the reference voltage device 2A of the present invention includes a current generating circuit 22 for generating a current of 1 ,, and an active load circuit 24 reduces the current to generate a current 22 to receive the current h and output the reference MVref. And the reference voltage level supply circuit 26 is coupled to the active load circuit 24, and the reference reliance circuit 26 has a memory component, such as an electronic erasable programmable read only memory (10) P_), for the wafer to be fabricated. After the output, the reference voltage control bitstream is stored in the memory component towel, so the reference voltage hybrid crane circuit can provide at least a - reference voltage control level (sl...Sn) and - a second reference voltage control The bits (Fl, " Fn) are referenced by the active load circuit 24. The current generating circuit 22 of the present invention is the same as the conventional current generating circuit 12, that is, includes two current mirror circuits 'there is a towel-current mirror circuit having two brain power crystals, a ship, and another current mirror circuit having two She connected the _s transistor M3, M4, and two two-pole Zhao circuit, 8 200935207 One of the two-pole circuit is composed of __N gate lightly connected to the 〇 〇 transistor M5, another one The polar body circuit is composed of a gate 〇s transistor M6, and the bias voltage of the two diode circuits is in a saturation region, and a more detailed description of the current generating circuit 22 is provided. Direct reference to the current generating circuit, 遂; j; then repeat. Moreover, the current generated by the hybrid generating circuit 22 & 1 is a low current of between 5 nA and 500 nA, which is almost independent of the power supply voltage level. The active load circuit 24 includes a PMOS transistor M9, a first reference voltage control circuit 28 coupled to the two phases, a second reference voltage control circuit 3A, and a two-phase coupled s-s transistor M7^ and NM0S. Crystal M8. And the pm 〇S transistor M9 is coupled to the PMOS transistor M2 of the current generating circuit 22 and the NMOS transistor M4 at the node 1 to receive the current I. The first reference voltage control circuit 28 is coupled to the transistor M9 at the node 2, wherein the first reference voltage control circuit 28 and the second reference voltage control circuit 30 each include a complex diode circuit and a plurality of NM〇s transistors. And each diode circuit is composed of a smooth s-transistor with a gate coupled to the drain. In addition, the gate is connected to the gate and the drain is still coupled. The first reference voltage control circuit 28 is connected to the node 3, and the source is coupled to a supply voltage VSS. The gate of the NM0S transistor M8 is coupled to the 汲Q of the transistor M7 to the node 3, and the source is coupled to a supply voltage. Vss, the drain is coupled to the second reference constant voltage control circuit 30. Therefore, when the transistor M9 injects current into the first reference voltage control circuit 28 and the second reference voltage control circuit 30, it finally flows through the transistor M8 to output the reference voltage Vref at the 汲 extreme of M8. The first reference voltage control circuit 28 controls the level (S1 . . . Sn) according to the first reference voltage provided by the reference voltage level supply circuit 26 for increasing the drawn current I. To reduce the level of the reference voltage Vref, the reduced amplitude is controlled by the reference voltage level supply circuit 26. The second reference voltage control circuit 30 is based on the reference voltage level supply circuit 26 200935207 The two reference voltage control levels (Fl...Fn)' are used to increase the current I drawn. In order to increase the level of the reference voltage Vref, the magnitude of the boost is controlled by the reference voltage level supply circuit π, so the present invention can correct the reference voltage by increasing or decreasing the reference voltage level. The bit offset keeps the level of the reference voltage Vref fixed. As shown in the fourth figure, the relationship between temperature and reference voltage, where group A is the relationship diagram under the typical transistor component parameter model, and group B is the reference voltage level supply under the poor transistor component parameter model. The first reference voltage control level (S1...Sn) provided by the circuit 26 is adjusted to obtain a relationship diagram, and the C group is provided by the reference voltage level supply circuit 26 under the preferred transistor element parameter model. The relationship diagram obtained by adjusting the reference voltage control level (Fl ", Fn). The use of the reference voltage generating device of the present invention shows that the offset amplitude of the reference voltage level has been significantly improved in the case of variations in process parameters. Therefore, the reference voltage generating device disclosed in the present invention reduces the influence of the reference voltage level by the process voltage parameter by adjusting the reference voltage level to keep the reference voltage level as fixed as possible. The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and to implement the present invention. Equivalent changes or modifications made by the spirit of the present invention should still be included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a circuit diagram of a conventional reference voltage generating device. The second figure is a plot of reference voltage versus temperature generated by a conventional reference voltage generating device. 200935207 The third figure is a circuit diagram of the reference voltage generating device of the present invention. The fourth figure is a graph of the reference voltage and temperature generated by the reference voltage generating device according to the present invention. [Main component symbol description] ίο reference voltage generating device 12 current generating circuit 14 active load circuit 20 reference voltage generating device 22 current generating circuit 24 active load circuit ❹ 26 reference voltage level supply circuit 28 first reference voltage control circuit 30 second Reference voltage control circuit 11