TW200934851A - Circuit member connecting adhesive and semiconductor device - Google Patents

Circuit member connecting adhesive and semiconductor device

Info

Publication number
TW200934851A
TW200934851A TW097146663A TW97146663A TW200934851A TW 200934851 A TW200934851 A TW 200934851A TW 097146663 A TW097146663 A TW 097146663A TW 97146663 A TW97146663 A TW 97146663A TW 200934851 A TW200934851 A TW 200934851A
Authority
TW
Taiwan
Prior art keywords
adhesive
resin
wafer
circuit member
circuit
Prior art date
Application number
TW097146663A
Other languages
Chinese (zh)
Other versions
TWI419954B (en
Inventor
Akira Nagai
Yasunori Kawabata
Shigeki Katogi
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Publication of TW200934851A publication Critical patent/TW200934851A/en
Application granted granted Critical
Publication of TWI419954B publication Critical patent/TWI419954B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • CCHEMISTRY; METALLURGY
    • C09DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09JADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J11/00Features of adhesives not provided for in group C09J9/00, e.g. additives
    • C09J11/02Non-macromolecular additives
    • C09J11/04Non-macromolecular additives inorganic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/295Organic, e.g. plastic containing a filler
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • CCHEMISTRY; METALLURGY
    • C08ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08KUse of inorganic or non-macromolecular organic substances as compounding ingredients
    • C08K3/00Use of inorganic substances as compounding ingredients
    • C08K3/18Oxygen-containing compounds, e.g. metal carbonyls
    • C08K3/20Oxides; Hydroxides
    • C08K3/22Oxides; Hydroxides of metals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29399Coating material
    • H01L2224/294Coating material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81121Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81208Compression bonding applying unidirectional static pressure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83885Combinations of two or more hardening methods provided for in at least two different groups from H01L2224/83855 - H01L2224/8388, e.g. for hybrid thermoplastic-thermosetting adhesives
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01011Sodium [Na]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01012Magnesium [Mg]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01041Niobium [Nb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01045Rhodium [Rh]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01056Barium [Ba]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01077Iridium [Ir]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/0665Epoxy resin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788Glasses, e.g. amorphous oxides, nitrides or fluorides
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305Affixing by adhesive

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Organic Chemistry (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Provided is a circuit member connecting adhesive for connecting circuit boards facing each other. The circuit member connecting adhesive is composed of a resin composition containing a thermoplastic resin, a thermosetting resin and a curing agent, and metal hydroxide particles dispersed in the composition. The circuit member connecting adhesive has excellent reliability in connection between a semiconductor chip and a substrate, and improves recognition performance of an alignment mark to be used for alignment of a semiconductor chip with a substrate to a level sufficient for practical use.

Description

200934851 . 九、發明說明 【發明所屬之技術領域】 本發明係關於一種電路構件連接用黏著劑及使用該電 路構件連接用黏著劑之半導體裝置。 • 【先前技術】 . [背景技術] 0 作爲藉由面朝下接合方式而直接地構裝半導體晶片於 電路基板之方式係知道有在半導體晶片之電極部分形成焊 錫凸塊之電路基板藉由靜錫而進行連接之方式、或者是在 設置於半導體晶片之突起電極來塗佈導電性黏著劑而在電 路基板電極進行電連接之方法。在這些方式,在曝露於各 種環境下之狀態,根據連接之晶片和基板之熱膨脹係數差 之所造成之應力係發生於連接界面,因此,有所謂降低連 接可靠性之問題發生。 〇 因此,由於緩和連接界面之應力之目的,所以,檢討 以環氧樹脂等之底部塡充劑材來塡充晶片和基板之間隙之 方式。作爲底膜材之塡充方式係有在連接晶片和基板之後 * 而注入低黏度之液體狀樹脂之方式、以及在基板上放置底 - 部塡充劑材之後而搭載晶片之方式。作爲預先將底部塡充 劑材設置於基板後而搭載晶片之方法係有塗佈液體狀樹脂 之方法以及貼附薄膜狀樹脂之方法。 但是,在液體狀樹脂之塗佈,藉由分配器之所造成之 精密之塗佈量控制係爲困難,在近年來之晶片薄型化,由 -5- 200934851 於過多之塗佈而在接合時來滲出之樹脂係爬上晶片之側面 ,污染接合之工具,因此,必須洗淨工具,成爲量產時之 步驟變得繁雜之原因。 另一方面,在薄膜狀樹脂之狀態下,藉由控制薄膜之 厚度而使得樹脂量之最適當化變得容易,相反地,在薄膜 • 貼附於基板之際,必須進行稱爲臨時壓合步驟之薄膜貼附 . 步驟。在該狀態下,用以修正在構裝時之晶片和基板之位 Φ 置偏離而貼附於基板之薄膜係一般大於晶片尺寸,成爲高 密度化構裝之妨礙則爲其課題。爲了解決該課題,因此, 作爲供應尺寸相同於晶片尺寸之黏著劑之方法係提議在晶 片以個片化之前之晶圓狀態來供應黏著劑之後,藉由切割 等而進行晶片加工,同時,進行黏著劑之加工,得到附有 黏著劑之晶片之方法(參考專利文獻1、2 )。 專利文獻1 :日本專利第2833 1 1 1號公報 專利文獻2 :日本特開2006-49482號公報 ❹ 【發明內容】 [發明之揭示] * [發明所欲解決之課題] - 但是,向來提議之晶圓前置型之底部塡充方法(稱爲 在晶片進行個片化之前而在晶圓供應底部塡充劑之加工方 法。)係有下列之問題發生,在市場並無被一般化。 專利文獻1之方法係在晶圓貼附薄膜狀黏著劑之後, 藉由切割而進行個片化,得到附有黏著薄膜之晶片之方法 -6- 200934851 。在本方法,製作晶圓/黏著劑/間隔片之層積體’在切斷 這個後,剝離間隔片,得到附有黏著劑之晶片’但是’在 切斷層積體之際而有剝離黏著劑和間隔片之狀態發生’擔 心個片化之半導體晶片係飛散、流出。 專利文獻2係關於具有黏著材層和黏著劑層之晶圓加 • 工用帶之所關係到之方法,揭示:在晶圓貼附於晶圓加工 _ 用帶之後,進行切割及檢取,個片化之晶片以覆晶來連接 0 於基板之方法。一般在覆晶構裝,連接稱爲晶片電路面之 凸塊之端子和相對之基板側之端子,因此,藉由覆晶接合 器而對位及貼附晶片側之定位標記(對位標記)和基板側 之定位標記。但是,在晶片之電路面貼附黏著劑之狀態下 ,黏著劑係覆蓋電路面之定位標記,因此,必須透過黏著 劑而辨識定位標記。相對於此,在專利文獻2,並無提供 對於該問題之解決對策。 本發明之目的係提供一種半導體晶片及基板之連接可 〇 靠性呈良好同時能夠提高使用於半導體晶片和基板之對位 之定位標記之辨識性至實用上之充分水準爲止的電路構件 連接用黏著劑。本發明之目的係還提供一種使用該電路構 * 件連接用黏著劑的半導體裝置。 [用以解決課題之手段] 本發明係提供一種電路構件連接用黏著劑,係爲連接 相對向之電路基板用之電路構件連接用黏著劑,由含有熱 塑性樹脂、熱硬化性樹脂及硬化劑之樹脂組成物,與分散 200934851 於該組成物中之金屬氫氧化物粒子所構成。此外,在「相 對向之電路基板之連接」,含有電連接及/或電路基板之 固定。 本發明之電路構件連接用黏著劑係實現所謂半導體晶 片和基板間之良好之連接可靠性以及能夠辨識定位標記之 * 高度之光透過性之提到向來不可能同時成立之特性。 . 作爲連接可靠性係要求:對應於根據晶片和基板之熱 Φ 膨脹係數差之所產生之應力之高黏著化、用以對應於重熔 溫度之高耐熱性、用以對應於高溫環境化之低熱膨脹性、 用以對應於高溫高濕度環境下之低吸濕性等。爲了提高這 些特性,因此,認爲在能夠達成高耐熱性和高黏著性之環 氧樹脂,添加線膨脹係數小之二氧化矽塡充物,但是,在 此種系統,無法根據在二氧化矽塡充物和環氧樹脂之界面 之散亂等而得到透明性。 另一方面,認爲藉由添加透明玻璃粒子而確保透明性 〇 (例如曰本專利第340830 1號公報),但是,即使是在玻 璃粒子爲透明之狀態下,也有根據和分散玻璃粒子之樹脂 間之折射率差或界面之密合性不良等而損害透明性之狀況 • 發生,大多也根據玻璃粒子之脆弱性或熱膨脹係數差而無 - 法得到連接可靠性。 相對於此種狀況,在本發明之電路構件連接用黏著劑 ,可以藉由以熱塑性樹脂、熱硬化性樹脂及硬化劑來構成 基材,並且,在該基材添加及分散金屬氫氧化物粒子,而 同時成立良好之連接可靠性和高度之光透過性。 -8 - 200934851 本發明之電路構件連接用黏著劑係最好是未硬化時之 可見光平行透過率爲1 5〜1 0 0 % 。藉由可見光平行透過率成 爲該範圍內而使得在覆晶接合器之定位標記之辨識變得更 加地容易。 能夠縮小和樹脂間之折射率差,可以抑制在未硬化狀 • 態時之電路構件連接用黏著劑之光散亂至最低限度,金屬 - 氫氧化物粒子之折射率係最好是1.5〜1.7。 ❹ 就金屬氫氧化物粒子之粒徑而言,平均粒徑係最好是 成爲0·1μιη〜ΙΟμιη之範圍內。可以藉由金屬氫氧化物粒子 之平均粒徑成爲該範圍而提高其分散性或樹脂之流動性, 也可以期待樹脂之補強效果。 本發明之電路構件連接用黏著劑係最好是在180 °C下 加熱20秒後之差示掃描熱量測定中測得之反應率爲75% 以上。藉由在差示掃描熱量測定之反應率成爲前述之値而 得到穩定之低連接電阻,成爲良好之熱壓合樹脂。[Technical Field] The present invention relates to an adhesive for connecting a circuit member and a semiconductor device using the adhesive for connecting the circuit member. [Background Art] [Background Art] 0 As a method of directly mounting a semiconductor wafer on a circuit substrate by a face-down bonding method, it is known that a circuit substrate in which solder bumps are formed on an electrode portion of a semiconductor wafer is static A method in which tin is connected, or a method in which a conductive adhesive is applied to a bump electrode of a semiconductor wafer to be electrically connected to a circuit board electrode. In these modes, the stress caused by the difference in thermal expansion coefficient between the connected wafer and the substrate occurs at the connection interface in a state exposed to various environments, and therefore, there is a problem that the connection reliability is lowered. 〇 Therefore, since the purpose of stressing the connection interface is alleviated, the method of filling the gap between the wafer and the substrate by using the underlying medicinal material such as epoxy resin is reviewed. The charging method of the underlying film material is a method in which a liquid resin having a low viscosity is injected after the wafer and the substrate are bonded, and a wafer is mounted on the substrate after the bottom portion is placed on the substrate. A method of mounting a wafer after the bottom medicinal material is placed on a substrate in advance is a method of applying a liquid resin and a method of attaching a film-like resin. However, in the application of the liquid resin, the precise coating amount control by the dispenser is difficult, and in recent years, the wafer has been thinned, and the coating is excessively applied from -5 to 200934851 at the time of bonding. The resin that oozes out climbs up the side of the wafer and contaminates the bonding tool. Therefore, it is necessary to clean the tool, which becomes a cause of complicated procedures in mass production. On the other hand, in the state of the film-like resin, it is easy to optimize the amount of the resin by controlling the thickness of the film, and conversely, when the film is attached to the substrate, it is called temporary pressing. Step film attachment. Steps. In this state, it is a problem to correct the position of the wafer and the substrate at the time of the mounting, and the film attached to the substrate is generally larger than the wafer size, which is a hindrance to the high-density structure. In order to solve this problem, as a method of supplying an adhesive having the same size as the wafer size, it is proposed to perform wafer processing by dicing or the like after the wafer is supplied with the adhesive in a wafer state before dicing, and at the same time, A method of processing an adhesive to obtain a wafer with an adhesive (refer to Patent Documents 1 and 2). [Patent Document 1] Japanese Patent No. 2833 1 1 1 Patent Document 2: JP-A-2006-49482 ❹ [Disclosure of the Invention] [Problems to be Solved by the Invention] - However, it has been proposed The bottom-filling method of the wafer front type (referred to as the processing method of the ruthenium at the bottom of the wafer before the wafer is singulated) has the following problems, and is not generalized in the market. The method of Patent Document 1 is a method in which a wafer-like adhesive is attached to a wafer and then diced by dicing to obtain a wafer with an adhesive film -6-200934851. In the present method, a laminate of a wafer/adhesive/spacer is prepared. After the cutting is performed, the spacer is peeled off to obtain a wafer with an adhesive. However, there is a peeling adhesive at the time of cutting the laminate. And the state of the spacer occurs. 'The semiconductor chip that is worried about the chip is scattered and flows out. Patent Document 2 relates to a method relating to a wafer application tape having an adhesive layer and an adhesive layer, and discloses that after the wafer is attached to the wafer processing _ tape, cutting and picking are performed, The chip is wafer-bonded to connect 0 to the substrate. Generally, in a flip chip mounting, a terminal called a bump of a wafer circuit surface and a terminal opposite to a substrate side are connected, and therefore, a positioning mark (alignment mark) of the wafer side is aligned and attached by a flip chip bonder. And positioning marks on the substrate side. However, in the state where the adhesive is applied to the circuit surface of the wafer, the adhesive covers the alignment mark of the circuit surface, and therefore the positioning mark must be recognized by the adhesive. On the other hand, Patent Document 2 does not provide a solution to this problem. An object of the present invention is to provide a connection between a semiconductor wafer and a substrate, which is excellent in reliability, and which can improve the visibility of the alignment mark used for alignment of the semiconductor wafer and the substrate to a practically sufficient level. Agent. It is also an object of the present invention to provide a semiconductor device using the adhesive for connecting a circuit component. [Means for Solving the Problem] The present invention provides an adhesive for connecting a circuit member, which is an adhesive for connecting a circuit member for connecting a circuit board, and comprises a thermoplastic resin, a thermosetting resin, and a hardener. The resin composition is composed of metal hydroxide particles dispersed in the composition of 200934851. Further, the "connection of the opposite circuit boards" includes electrical connection and/or fixing of the circuit board. The adhesive for connecting circuit members of the present invention achieves the characteristics of good connection reliability between the so-called semiconductor wafer and the substrate, and the ability to recognize the light transmittance of the height of the positioning mark. As a connection reliability system, it is required to have a high adhesion due to a difference in thermal expansion coefficient between a wafer and a substrate, a high heat resistance corresponding to a remelting temperature, and an environment corresponding to high temperature. Low thermal expansion, used to correspond to low hygroscopicity in high temperature and high humidity environments. In order to improve these characteristics, it is considered that a cerium oxide filling having a small coefficient of linear expansion is added to an epoxy resin capable of achieving high heat resistance and high adhesion, but in such a system, it cannot be based on cerium oxide. The transparency of the interface between the entangled material and the epoxy resin is obtained. On the other hand, it is considered that the transparency is ensured by the addition of the transparent glass particles (for example, Japanese Patent No. 340830 1), but even in the state where the glass particles are transparent, there is a resin based on and dispersing the glass particles. The difference in refractive index or the poor adhesion of the interface, etc., which impairs the transparency. • Occasionally, the connection reliability is often obtained based on the fragility of the glass particles or the difference in thermal expansion coefficient. In this case, the adhesive for connecting the circuit member of the present invention can be composed of a thermoplastic resin, a thermosetting resin, and a curing agent, and the metal hydroxide particles can be added and dispersed on the substrate. At the same time, good connection reliability and high light transmittance are established. -8 - 200934851 The adhesive for connecting circuit members of the present invention preferably has a visible light parallel transmittance of 15 to 100% when it is not cured. The identification of the positioning marks on the flip chip bonder is made easier by the visible light parallel transmittance being within this range. The refractive index difference between the resin and the resin can be reduced, and the light of the adhesive for connecting the circuit members in the uncured state can be suppressed to a minimum, and the refractive index of the metal hydroxide particles is preferably 1.5 to 1.7. . ❹ In terms of the particle diameter of the metal hydroxide particles, the average particle diameter is preferably in the range of from 0.1 μm to ΙΟμηη. When the average particle diameter of the metal hydroxide particles is within this range, the dispersibility or the fluidity of the resin can be improved, and the reinforcing effect of the resin can be expected. Preferably, the adhesive for connecting the circuit member of the present invention has a reaction rate of 75% or more as measured in differential scanning calorimetry after heating at 180 ° C for 20 seconds. By setting the reaction rate in the differential scanning calorimetry to the above, a stable low connection resistance is obtained, and it becomes a good thermocompression resin.

Q 本發明之電路構件連接用黏著劑係最好是40°C〜l〇〇°C 之線膨脹係數爲7〇xl(T6/°C以下。在使用此種特性之電路 構件連接用黏著劑而連接半導體晶片和電路基板之時,抑 ' 制由於連接後之溫度變化或加熱吸濕之所造成之膨脹等, - 得到高度之連接可靠性。 此外,本發明係還提供一種具有藉由前述之電路構件 連接用黏著劑而接合之電路基板之半導體裝置。 [發明之效果] -9- 200934851 藉由本發明而提供一種半導體晶片及基板之連接可靠 性呈良好同時能夠提高使用於半導體晶片和基板之對位之 定位標記之辨識性至實用上之充分水準爲止的電路構件連 接用黏著劑。此外,提供一種使用該電路構件連接用黏著 劑的半導體裝置。 • 可以藉由使用本發明之電路構件連接用黏著劑,而成 . 爲能夠對應於窄間距化及窄間隙化之晶圓前置型之底部塡 Q 充技術,無切割時之污染發生,並且,可以在切割後,簡 便地得到附有黏著劑之半導體晶片,而且,能夠抑制因爲 對於晶圓之高度之密合化之所造成之切割時之剝離,抑制 在由於薄膜之高度之彈性化之所造成之切割後之鬚邊、毛 邊、破裂,在晶片構裝時,以低溫且短時間,來進行硬化 。此外,可以藉由使用本發明之電路構件連接用黏著劑之 晶圓前置型之底部塡充方法,而可同時成立因爲對於晶圓 之密合性和對於切割膠帶(Dicing tape)之密合性之最適 〇 當化之所造成之切割時之剝離之抑制以及在切割後之簡便 之剝離性,能夠抑制鬚邊、毛邊、破裂等之發生而實現用 以切割之未硬化時之薄膜之高度之彈性化,在晶片構裝時 * ,以低溫且短時間,來進行硬化。 【實施方式】 [發明之最佳實施形態] 就本發明之電路構件連接用黏著劑而進行說明。 本發明之電路構件連接用黏著劑係連接相對向之電路 -10- 200934851 基板用之電路構件連接用黏著劑。作爲相對向之電路基板 係並無特別限定之組合,但是’列舉例如(I)具有突出 之連接端子之半導體晶片以及(Π)形成有配線圖型之電 路基板。 在(I)具有突出之連接端子之半導體晶片中,半導 - 體晶片之突出之連接端子係可以是使用金線而形成之金螺 . 絲柱凸塊、藉由熱壓合或超音波倂用熱壓合機而固定金屬 0 球於半導體晶片之電極者、以及藉由電鍍或蒸鍍而形成者 。突出之連接端子係不需要藉由單一之金屬而構成,可以 包含金、銀、銅、鎳、銦、鈀、錫、鉍等之複數種金屬成 分,能夠成爲層積這些金屬層之形態。此外,具有突出之 連接端子之半導體晶片係可以是具有突出之連接端子之半 導體晶圓之狀態。爲了呈相對向地配置半導體晶片之突出 之連接端子和形成配線圖型之基板’因此’通常半導體晶 片係在相同於突出之連接端子之同一面,具有定位標記。 〇 在該狀態下,最好是在具有半導體晶片之突出之連接端子 之面,以貼附電路構件連接用黏著劑之狀態’使得覆晶接 合器,可以辨識透過電路構件連接用黏著劑來形成於晶片 ' 電路面之定位標記。 - (Π)形成有配線圖型之電路基板係亦可爲通常之電 路基板,並且,也可以是半導體晶片。在電路基板之狀態 下,配線圖型係除了能夠以蝕刻,來除去在環氧樹脂或具 有苯并三嗪骨格之樹脂含浸於玻纖布或不織布來形成之基 板、具有積層(butId-up)之基板或者是聚醯亞胺、玻璃 -11 - 200934851 、陶瓷等之絕緣基板表面之所形成之銅等之金屬層之不必 要部分而形成以外,也可以藉由電鍍而形成於絕緣基板之 表面,或者是也可以藉由蒸鍍等而形成。此外,配線圖型 係不需要藉由單一之金屬而形成,可以包含金、銀、銅、 鎳、銦、鈀、錫、鉍等之複數種金屬成分,能夠成爲層積 這些金屬層之形態。此外,在基板爲半導體晶片之狀態下 - ,配線圖型係通常藉由鋁而構成,但是,也可以在其表面 Ο ,形成金、銀、銅、鎳、銦、鈀、錫、鉍等之金屬層。 例如附有電路構件連接用黏著劑之半導體晶片係可以 藉由(1)在具有晶片化之前之突出之連接端子之半導體 晶圓所突出之連接端子面,藉由層壓等而貼附面積同等於 半導體晶圓之電路構件連接用黏著劑,(2)藉由切割而 將以在前述半導體晶圓之背面或前述電路構件連接用黏著 劑之上層積切割膠帶之步驟之所得到之層積體,來切斷成 爲個片,(3 )由切割膠帶來剝離附加個片化之電路構件 〇 連接用黏著劑之半導體晶片,而得到半導體晶片。在此使 用之切割膠帶係可以適用在基材帶上塗佈黏著材之市面販 賣之切割膠帶。作爲切割膠帶係大致分成爲感壓型和放射 ' 線反應型,但是,更加理想是藉由以UV照射之所造成之 - 硬化而減少黏著力且層積於黏著面之被黏著體之剝離變得 容易之放射線反應型切割膠帶。 本發明之電路構件連接用黏著劑係最好是能夠以貼附 在具有半導體晶片之突出之連接端子之面之狀態,辨識透 過電路構件連接用黏著劑來形成於晶片電路面之定位標記 -12- 200934851 。定位標記係可以藉由搭載於通常之覆晶接合器之晶片辨 識用之裝置而進行辨識。該辨識裝置係通常由具有鹵素燈 之齒素光源、光導管、照射裝置以及CCD相機而構成。 以C C D相機來放入之圖像係藉由圖像處理裝置而判斷和 預先登錄之對位用之圖像圖型之整合性,進行對位作用。 • 在本發明提到時之能夠辨識定位標記係指使用覆晶接合器 . 之晶片辨識用裝置而放入之定位標記之圖像和登錄之定位 0 標記之圖像之整合性變得良好,毫無問題地進行對位作業 。例如在使用 Athlete FA股份有限公司製之覆晶接合器 CB- 1 050之狀態下,在相反於貼附在具有電路構件連接用 黏著劑之突出之連接端子之面之層積體之連接端子面之相 反面,於覆晶接合器之吸附噴嘴,吸引層積體。然後,作 爲藉由裝置內之晶片辨識用裝置而攝影透過黏著劑層來形 成於半導體晶片表面之定位標記且得到和預先放入至圖像 處理裝置之半導體晶片之定位標記間之整合性而能夠辨識 〇 可以進行對位作業之黏著劑之電路構件連接用黏著劑係可 以判別成爲無法辨識不能夠對位之狀態之電路構件連接用 黏著劑。 ' 本發明之電路構件連接用黏著劑係最好是未硬化時之 - 可見光平行透過率爲15~100% 、更加理想是可見光平行透 過率爲 18〜100% 、甚至最好是可見光平行透過率爲 25~100% 。在可見光平行透過率小於15%之狀態下,有無 法進行在覆晶接合器之定位標記之辨識而變得不容易進行 對位作業之狀態發生。 -13- 200934851 可見光平行透過率係可以使用日本電色股份有限公司 製之濁度計NDH2000,藉由積分球式光電光度法而進行測 定。例如在以膜厚50μηι之帝人杜邦公司製之PET薄膜( Purex、全光線透過率90.45、混濁値4.47 )作爲基準物質 而進行校正後’在PET基材,塗佈25μιη厚度之電路連接 - 用黏著劑,測定這個。可以由測定之結果而求出濁度、全 . 光線透過率、擴散透過率及平行透過率。 0 此外,可見光平行透過率或可見光透過率係可以藉由 日立公司製之U-33 1 0形分光光度計而進行測定。例如能 夠在以膜厚50μηι之帝人杜邦公司製之PET薄膜(Purex 、555 nm之透過率86.03 % )作爲基準物質而進行基準線 修正測定後,在PET基材’塗佈25 μιη厚度之電路構件連 接用黏著劑,測定400nm~800nm之可見光區域之透過率 。在使用於覆晶接合器之鹵素光源和光導管之波長相對強 度,5 50nm〜600nm係最高之強度,因此,在本發明,可以 ❹ 具有555nm之透過率而進行透過率之比較。 在本發明之電路構件連接用黏著劑組合於切割膠帶之 狀態下,在電路構件連接用黏著劑對於UV照射後之切割 ' 膠帶之黏著力係最好是lON/m以下,並且,對於半導體晶 - 圓之黏著力係最好是7〇N/m以上。在對於UV照射後之切 割膠帶之黏著力爲l〇N/m以上之狀態下,在由切割膠帶來 剝離附有切割後之個片化之電路構件連接用黏著劑之半導 體晶片之作業,有發生晶片破壞或者是發生黏著劑層之變 形之狀態發生。另一方面,在對於半導體晶圓之黏著力爲 -14- 200934851 70N/m以下之狀態下,有因爲在切割時之刀片之旋轉切削 之所造成之撞擊和水壓之影響而有在晶片和黏著劑界面來 發生剝離之傾向。 電路構件連接用黏著劑和UV照射後之切割膠帶之黏 著力係可以正如以下而進行測定。也就是說,在藉由電路 構件連接用黏著劑設定於加熱溫度80°C之層壓機而在晶圓 . 進行層壓後,在以切割膠帶之黏著面作爲電路構件連接用 φ 黏著劑而在40°C進行層壓後,於切割膠帶側,以15mW來 進行3 00mJ程度之UV照射。在UV照射後之切割膠帶, 放入1 0mm幅寬之切口而準備拉引測定用之長方形。晶圓 按壓在台座,將成爲長方形之切割膠帶之某一端固定於拉 引測定機之拉引治具,進行90°剝離試驗,剝離電路構件 連接用黏著劑和UV照射後之切割膠帶。可以藉由該測定 而測定電路構件連接用黏著劑和UV照射後之切割膠帶之 黏著力。 G 電路構件連接用黏著劑和半導體晶圓之黏著力係在藉 由電路構件連接用黏著劑設定於加熱溫度80°C之層壓機而 在晶圓進行層壓後,在電路構件連接用黏著劑朝向黏著面 而貼附聚醯亞胺帶(Kopton Tape)(日東電工公司製、 - l〇mm幅寬、25μιη厚度)來充分地進行密合後,在聚醯亞 胺帶外形之電路構件連接用黏著劑,於1 0mm幅寬,放入 切口。由晶圓來剝離完成之電路構件連接用黏著劑和聚醯 亞胺帶之層積體之某一端,固定於拉引測定機之拉引治具 。晶圓按壓在台座,上拉長方形而進行90°剝離試驗,由 -15- 200934851 晶圓來剝離電路構件連接用黏著劑。可以藉由該測定而測 定電路構件連接用黏著劑和半導體晶圓之黏著力。It is preferable that the adhesive for connecting circuit members of the present invention has a linear expansion coefficient of 40 ° C to 10 ° C (T6 / ° C or less). The adhesive for connecting circuit members using such characteristics is used. When the semiconductor wafer and the circuit substrate are connected, the connection stability due to temperature change after connection or heat absorption and the like is obtained, and a high degree of connection reliability is obtained. Further, the present invention provides a The circuit device is connected to a semiconductor device of a circuit board bonded by an adhesive. [Effect of the Invention] -9- 200934851 The present invention provides a connection reliability of a semiconductor wafer and a substrate, and can be improved for use in a semiconductor wafer and a substrate. The identification of the alignment mark to the practically sufficient level of the adhesive for connecting the circuit member. Further, a semiconductor device using the adhesive for connecting the circuit member is provided. • The circuit member of the present invention can be used by using the circuit member of the present invention. Connected with an adhesive. It is a bottom 塡Q charging technology that can match the narrow pitch and narrow gap wafer front type. The contamination at the time of cutting occurs, and the semiconductor wafer with the adhesive can be easily obtained after the dicing, and the peeling at the time of cutting due to the adhesion of the height of the wafer can be suppressed, and the The edge of the film, the burrs, and the rupture caused by the elasticization of the height of the film are hardened at a low temperature for a short period of time during the wafer assembly. Further, the bonding can be performed by using the circuit member of the present invention. The bottom-filling method of the wafer front-end type can be simultaneously established because of the peeling of the wafer due to the adhesion of the wafer and the optimum adhesion to the Dicing tape. The suppression and the easy peelability after dicing can suppress the occurrence of the edge, the burrs, the cracks, and the like, and the elasticity of the film at the time of unclamping for cutting can be suppressed, and the film is mounted at a low temperature. [Embodiment] The preferred embodiment of the invention will be described with respect to the adhesive for connecting circuit members of the present invention. The connection adhesive is used to connect the adhesive to the circuit member for use in the circuit of the circuit of the present invention. The combination of the circuit board is not particularly limited. The semiconductor wafer and the circuit board on which the wiring pattern is formed. In (I) the semiconductor wafer having the protruding connection terminal, the protruding connection terminal of the semiconductor wafer may be gold formed using a gold wire. Screw. The stud bump, which is fixed by the thermocompression or ultrasonic wave kneading machine to fix the metal ball to the electrode of the semiconductor wafer, and formed by electroplating or vapor deposition. The protruding connection terminal is not It is required to be composed of a single metal, and may contain a plurality of metal components such as gold, silver, copper, nickel, indium, palladium, tin, or antimony, and may be in the form of laminating these metal layers. Further, the semiconductor wafer having the protruding connection terminals may be in the state of a semiconductor wafer having protruding connection terminals. In order to arrange the protruding connection terminals of the semiconductor wafer and the substrate forming the wiring pattern in the opposite direction, the semiconductor wafer is usually provided on the same surface as the protruding connection terminals, and has positioning marks. In this state, it is preferable that the surface of the connection terminal having the protruding of the semiconductor wafer is attached to the state in which the adhesive for connecting the circuit member is attached, so that the flip chip bonder can be formed by the adhesive for connecting the circuit member. Positioning mark on the chip's circuit surface. - (Π) The circuit board on which the wiring pattern is formed may be a normal circuit board, or may be a semiconductor wafer. In the state of the circuit board, the wiring pattern can be removed by etching, and the substrate formed by impregnating the epoxy resin or the resin having the benzotriazine skeleton with the fiberglass cloth or the non-woven fabric, has a build-up (butId-up). The substrate may be formed of an unnecessary portion of a metal layer such as copper formed on the surface of an insulating substrate such as polyimide, glass-11 - 200934851 or ceramic, or may be formed on the surface of the insulating substrate by electroplating. Alternatively, it may be formed by vapor deposition or the like. Further, the wiring pattern is not required to be formed by a single metal, and may include a plurality of metal components such as gold, silver, copper, nickel, indium, palladium, tin, or antimony, and may be in the form of laminating these metal layers. Further, in the state in which the substrate is a semiconductor wafer, the wiring pattern is usually formed of aluminum, but it may be formed on the surface thereof to form gold, silver, copper, nickel, indium, palladium, tin, antimony or the like. Metal layer. For example, a semiconductor wafer to which an adhesive for connecting a circuit member is attached can be attached by an area equal to (1) a connection terminal surface on which a semiconductor wafer having a protruding connection terminal before wafer formation protrudes, by lamination or the like (2) a laminate obtained by laminating a step of dicing tape on the back surface of the semiconductor wafer or the adhesive for connecting the circuit member by dicing The film is cut into pieces, and (3) the semiconductor wafer to which the additional circuit member and the bonding adhesive are attached is peeled off by a dicing tape to obtain a semiconductor wafer. The dicing tape used herein can be applied to a commercially available dicing tape for applying an adhesive to a substrate tape. The dicing tape is roughly classified into a pressure-sensitive type and a radiation-type reaction type. However, it is more preferable to reduce the adhesion by hardening by UV irradiation and to peel off the adherend which is laminated on the adhesive surface. A radiation-reactive cutting tape that is easy to use. It is preferable that the adhesive for connecting the circuit member of the present invention is capable of being attached to the surface of the connecting terminal having the protruding of the semiconductor wafer, and identifying the positioning mark -12 formed on the surface of the chip by the adhesive for connecting the member for transmitting the circuit member. - 200934851. The positioning mark can be identified by a device for wafer identification mounted on a conventional flip chip bonder. The identification device is typically constructed of a lenticular source having a halogen lamp, a light pipe, an illumination device, and a CCD camera. The image placed by the C C D camera is judged by the image processing device to be integrated with the image pattern for registration in advance registration. • The identifiable positioning mark at the time of the present invention means that the integration of the image of the positioning mark placed by the wafer discriminating device using the flip chip bonder and the image of the registered position 0 mark becomes good. The alignment work is carried out without problems. For example, in the state in which the flip chip bonder CB-1 050 manufactured by Athlete FA Co., Ltd. is used, the connection terminal surface of the laminate which is attached to the surface of the protruding connection terminal having the adhesive for connecting the circuit member is used. On the opposite side, the adsorption nozzle of the flip chip bonder attracts the laminate. Then, by using the wafer discriminating device in the device, the positioning mark formed on the surface of the semiconductor wafer through the adhesive layer is photographed and integrated with the positioning mark of the semiconductor wafer previously placed in the image processing device. The adhesive for connecting the circuit member for identifying the adhesive which can perform the alignment work can determine the adhesive for connecting the circuit member which is incapable of recognizing the state in which the alignment cannot be performed. The adhesive for connecting the circuit member of the present invention is preferably uncured - the visible light parallel transmittance is 15 to 100%, more preferably the visible light parallel transmittance is 18 to 100%, and even more preferably the visible light parallel transmittance. It is 25~100%. In the state where the parallel transmittance of visible light is less than 15%, whether or not the alignment mark of the flip chip bonder is recognized and the state of the alignment operation is not easily performed. -13- 200934851 Visible light parallel transmittance can be measured by integrating sphere photoelectric photometry using a turbidity meter NDH2000 manufactured by Nippon Denshoku Co., Ltd. For example, after the PET film (Purex, total light transmittance: 90.45, turbidity 値 4.47) manufactured by DuPont Co., Ltd. with a film thickness of 50 μm is used as a reference material, the circuit is bonded to a thickness of 25 μm on a PET substrate. Agent, measure this. The turbidity, the total light transmittance, the diffuse transmittance, and the parallel transmittance can be obtained from the results of the measurement. In addition, the visible light parallel transmittance or the visible light transmittance can be measured by a U-33 1 0 spectrophotometer manufactured by Hitachi. For example, a PET film (Purex, transmittance of 555 nm, 86.03%) having a film thickness of 50 μm can be used as a reference material for reference line correction measurement, and a circuit member having a thickness of 25 μm can be applied to the PET substrate. The adhesion is measured by connecting an adhesive to measure the transmittance in a visible light region of 400 nm to 800 nm. The relative intensity of the wavelength of the halogen light source and the light guide used in the flip chip bonder is as high as 5 50 nm to 600 nm. Therefore, in the present invention, the transmittance can be compared with a transmittance of 555 nm. In the state in which the adhesive for connecting the circuit member of the present invention is combined with the dicing tape, the adhesion of the adhesive for the circuit member to the UV after the irradiation is preferably 1 ON/m or less, and for the semiconductor crystal. - The adhesion of the circle is preferably 7〇N/m or more. In the state in which the adhesive force of the dicing tape after the UV irradiation is l〇N/m or more, the semiconductor wafer with the diced circuit member connecting adhesive is peeled off by the dicing tape, and A wafer breakage or a state in which deformation of the adhesive layer occurs occurs. On the other hand, in the state where the adhesion to the semiconductor wafer is -14-200934851 70 N/m or less, there is an influence on the impact and water pressure caused by the rotary cutting of the blade at the time of cutting. Adhesive interface to the tendency to peel off. The adhesion of the adhesive for connecting the circuit member and the dicing tape after UV irradiation can be measured as follows. In other words, after the laminate is laminated on the wafer by the adhesive for setting the circuit member to the heating temperature of 80 ° C, the adhesive surface of the dicing tape is used as the φ adhesive for the circuit member connection. After lamination at 40 ° C, UV irradiation of about 300 mJ was performed at 15 mW on the side of the dicing tape. The dicing tape after UV irradiation was placed in a slit of 10 mm width to prepare a rectangular shape for measurement. The wafer is pressed against the pedestal, and one end of the rectangular dicing tape is fixed to the pull jig of the drawing measuring machine, and the 90° peeling test is performed, and the adhesive for connecting the circuit member and the dicing tape after the UV irradiation are peeled off. The adhesion of the adhesive for connecting the circuit member and the dicing tape after the UV irradiation can be measured by the measurement. G. Adhesives for connecting the circuit member and the semiconductor wafer are laminated on the wafer by a laminator set at a heating temperature of 80 ° C by an adhesive for connecting the circuit members, and then bonded to the circuit member. After the agent is attached to the adhesive surface with a Kopton Tape (manufactured by Nitto Denko Corporation, - l〇mm width, 25 μm thickness) to fully adhere, the circuit member in the shape of the polyimide film The adhesive for attachment was placed at a width of 10 mm and placed in the slit. One end of the laminated body of the circuit member connecting adhesive and the polyimide tape which is peeled off by the wafer is fixed to the pull jig of the drawing measuring machine. The wafer was pressed against the pedestal, and the rectangular shape was pulled up to perform a 90° peeling test, and the adhesive for connecting the circuit member was peeled off by the -15-200934851 wafer. The adhesion of the adhesive for connecting the circuit member and the semiconductor wafer can be measured by the measurement.

電路構件連接用黏著劑係抑制在連接半導體晶片和電 路基板後之溫度變化或者是由於加熱吸濕之所造成之膨脹 等而達成高度之連接可靠性’因此,硬化後之40 °C〜1〇〇 °CThe adhesive for connecting the circuit members suppresses the temperature change after the connection of the semiconductor wafer and the circuit substrate or the expansion due to the heat absorption and the like, thereby achieving a high degree of connection reliability. Therefore, 40 ° C to 1 after hardening 〇°C

- 之線膨脹係數最好是7〇xl〇_6/°C以下、更加理想是60xl(T . 6广C以下、甚至最好是50xl(T6/t以下。在硬化後之線膨 φ 脹係數大於70xl(T6rC之狀態下,有因爲構裝後之溫度變 化或者是由於加熱吸濕之所造成之膨脹而無法保持在半導 體晶片之連接端子和電路基板之配線間之電連接之狀況發 生。 本發明之電路構件連接用黏著劑係含有包含熱塑性樹 脂、熱硬化性樹脂及硬化劑之樹脂組成物(在以下,有僅 稱爲「樹脂組成物」之狀態發生。)以及金屬氫氧化物粒 子,樹脂組成物係最好是可見光平行透過率爲1 5¾以上、 φ 更加理想是50%以上、甚至最好是80%以上。在可見光 平行透過率爲80%以上之狀態下,即使是高度地塡充金屬 氫氧化物粒子之狀態,也可以滿足既定之透過率,因此, 變得理想。在樹脂組成物之平行透過率低於1 5%之狀態下 - ,即使是不添加金屬氫氧化物粒子之狀態,也不容易辨識 在覆晶接合器之定位標記,有在對位作業來產生阻礙之狀 態發生。 正如以下之所詳細敘述的,作爲包含於樹組成物中之 熱硬化性樹脂係大多是採用使用作爲耐熱性樹脂之環氧樹 -16- 200934851 脂之狀態’在該狀態下,作爲硬化觸媒係適合採用咪唑化 合物或胺系硬化劑。此種硬化劑係知道在分子內含有氮原 子之化合物而進行高度之折射率化,因此,電路構件連接 用黏著劑係一般在未硬化狀態,折射率成爲1 .5以上。 此外,在本發明,於樹脂組成物中,含有熱塑性樹脂 - ’藉由熱塑性樹脂之含有而達到所謂電路構件連接用黏著 . 劑容易形成爲薄膜狀之效果。在該狀態下,最好是採用高 φ 分子量之熱塑性樹脂,作爲此種高分子量之熱塑性樹脂係 適合使用苯氧基樹脂或丙烯樹脂(丙烯共聚物等)等。在 採用此種熱塑性樹脂之狀態下,電路構件連接用黏著劑係 一般以未硬化狀態而使得折射率成爲1.7以下。於是,電 路構件連接用黏著劑係最好是以未硬化狀態而使得折射率 成爲1.5〜1.7,在該狀態下,1.6成爲中心値。 使用於本發明之金屬氫氧化物粒子係可以適合使用折 射率1 .5〜1 .7者。在折射率低於1.5之狀態下,和樹脂間 Q 之折射率差變大,因此,在粒子分散後之未硬化狀態之薄 膜,發生光散亂,無法得到充分之透過性。另一方面,也 在折射率大於1.7之狀態下,同樣地發生和樹脂組成物間 之折射率差,因此,不容易得到充分之透過性。此外,樹 , 脂之折射率係可以使用 Abbe折射率計,以鈉D射線( 5 8 9nm )作爲光源而進行測定。此外,塡充物之折射率係 可以藉由貝克(Becke)法而在顯微鏡下,進行測定。 使用於本發明之金屬氫氧化物粒子係最好是平均粒徑 爲Ο.ίμηι〜ΙΟμιη。在平均粒徑低於〇·1μιη之狀態下,粒子 -17- 200934851 之比表面積變大,表面能也變大,因此’粒子間之相互作 用變大,產生凝集體,有損害分散性之狀態發生。即使是 凝集體之分散良好,也由於比表面積變大而使得分散於樹 脂時之增黏舉動變大,損害成形性。另一方面’在平均粒 徑大於1 〇μιη之狀態下,相反於粒徑小之狀態’比表面積 - 變小,因此,樹脂之流動性變大,容易引起在成型時之空 , 隙產生。此外,就成爲粒子分散之一種目的之樹脂之補強 φ 效果而言,粒徑變大,因此,即使是以相同之添加量,來 分散粒子,也使得粒子數本身變少,補強效果變小。因此 ,分散性良好,作爲也可以期待補強效果之粒子係最好是 平均粒徑爲Ο.ίμηι〜ΙΟμιη。此外,作爲粒徑變大之狀態之 意外係由於晶片之凸塊和金屬氫氧化物粒子對於電路基板 之電極間之咬入之所造成之電特性之妨礙發生,也成爲不 適合於大粒徑粒子混入之理由。特別是在以低壓來進行構 裝之狀態或者是凸塊之材質成爲鎳等之硬質之狀態下,金 〇 屬氫氧化物粒子係並無埋入於端子而成爲直接接觸之凸塊 和基板電極之接觸之妨礙,或者即使是在添加導電粒子之 系統,也成爲導電粒子扁平之妨礙,有阻礙電連接之狀態 _ 發生。此外,在最大粒徑爲40μπι以上之狀態下,發生大 • 於晶片和基板之間隙之可能性,成爲由於構裝時之加壓而 傷害晶片之電路或基板之電路之原因。 此外’使用於本發明之金屬氫氧化物粒子係最好是比 重爲5以下、更加理想是比重爲2〜5、甚至最好是比重爲 2~3.2。在比重大於5之狀態下’在添加於黏著樹脂組成 -18- 200934851 物之清漆之狀況,由於比重差變大而成爲 沉降之原因,有不容易得到金屬氫氧化物 之電路構件連接用黏著劑之狀態發生。- The linear expansion coefficient is preferably 7〇xl〇_6/°C or less, more preferably 60xl (T. 6 wide C or less, or even preferably 50xl (T6/t or less. After expansion, the line expands and expands) When the coefficient is larger than 70xl (in the state of T6rC, there is a case where the temperature change after the mounting or the expansion due to heating and moisture absorption cannot be maintained in the electrical connection between the connection terminal of the semiconductor wafer and the wiring of the circuit board. The adhesive for connecting circuit members of the present invention contains a resin composition containing a thermoplastic resin, a thermosetting resin, and a curing agent (hereinafter, referred to simply as a "resin composition"), and metal hydroxide particles. Preferably, the resin composition has a visible light parallel transmittance of 1 53⁄4 or more, φ is more preferably 50% or more, and even more preferably 80% or more. In a state where the visible light parallel transmittance is 80% or more, even if it is highly The state in which the metal hydroxide particles are filled can satisfy the predetermined transmittance, and therefore, it is preferable. In the state where the parallel transmittance of the resin composition is less than 1 5% - even if metal hydrogen is not added The state of the oxide particles is not easily recognized in the state in which the positioning marks of the flip chip bond are formed, and the occurrence of hindrance in the alignment operation occurs. As described in detail below, the thermosetting property contained in the tree composition is as described in detail below. Most of the resin systems are in the state of using epoxy resin as a heat-resistant resin. In this state, an imidazole compound or an amine-based curing agent is suitably used as the curing catalyst. Since the compound containing a nitrogen atom contains a high refractive index, the adhesive for connecting the circuit member is generally in an uncured state, and the refractive index is 1.5 or more. Further, in the present invention, the resin composition contains The thermoplastic resin - 'adhesive for connecting the circuit member by the inclusion of the thermoplastic resin. The agent is easily formed into a film shape. In this state, it is preferable to use a thermoplastic resin having a high molecular weight as the high molecular weight. A thermoplastic resin is preferably a phenoxy resin, a propylene resin (such as a propylene copolymer), or the like. In the state of the grease, the adhesive for connecting the circuit member is generally in an uncured state so that the refractive index is 1.7 or less. Therefore, the adhesive for connecting the circuit member is preferably in an uncured state such that the refractive index becomes 1.5 to 1.7. In this state, 1.6 becomes a center. The metal hydroxide particles used in the present invention can be suitably used in a refractive index of 1.5 to 1. 7. In the state where the refractive index is less than 1.5, and between the resins Since the refractive index difference is large, the film which is not cured in the dispersed state of the particles is scattered, and sufficient permeability cannot be obtained. On the other hand, in the state where the refractive index is more than 1.7, the resin is similarly generated. Since the refractive index difference between the compositions is not easy to obtain sufficient permeability, the refractive index of the tree and the fat can be measured using an Abbe refractometer and sodium D-ray (589 μm) as a light source. Further, the refractive index of the entangled material can be measured under a microscope by the Becke method. The metal hydroxide particle system used in the present invention preferably has an average particle diameter of Ο.ίμηι~ΙΟμιη. In the state where the average particle diameter is less than 〇·1 μηη, the specific surface area of the particles -17-200934851 becomes large, and the surface energy also becomes large, so that the interaction between the particles becomes large, and aggregates are generated, which deteriorates the state of dispersibility. occur. Even if the aggregation of the aggregate is good, the specific surface area becomes large, so that the viscosity increase behavior when the resin is dispersed is increased, and the formability is impaired. On the other hand, in the state where the average particle diameter is larger than 1 〇μηη, the specific surface area - in the state where the particle diameter is small is small, so that the fluidity of the resin becomes large, and voids and voids at the time of molding are likely to occur. In addition, since the particle size is increased by the effect of the reinforcing φ which is a purpose of particle dispersion, even if the particles are dispersed in the same amount, the number of particles itself is reduced, and the reinforcing effect is small. Therefore, the dispersibility is good, and as a particle system which can also be expected to have a reinforcing effect, the average particle diameter is Ο.ίμηι~ΙΟμιη. Further, the accident of the state in which the particle diameter becomes large is unsuitable for the large-diameter particles due to the hindrance of the electrical characteristics of the bumps of the wafer and the metal hydroxide particles which are interposed between the electrodes of the circuit board. Reason for mixing. In particular, in a state in which it is mounted at a low pressure or in a state in which the material of the bump is hard such as nickel, the metal hydroxide particles are not embedded in the terminal and become direct contact bumps and substrate electrodes. The hindrance of the contact, or even in the system in which the conductive particles are added, becomes a hindrance to the flatness of the conductive particles, and the state in which the electrical connection is blocked occurs. Further, in the state where the maximum particle diameter is 40 μm or more, the possibility of a gap between the wafer and the substrate occurs, which is a cause of damage to the circuit of the circuit or the substrate of the wafer due to pressurization at the time of construction. Further, the metal hydroxide particles used in the present invention preferably have a specific gravity of 5 or less, more preferably a specific gravity of 2 to 5, and even more preferably a specific gravity of 2 to 3.2. In the case where the specific gravity is greater than 5, the varnish added to the adhesive resin composition -18-200934851 is a cause of sedimentation due to a large difference in specific gravity, and an adhesive for connecting a circuit member which does not easily obtain a metal hydroxide The state occurs.

此外,使用於本發明之金屬氫氧化物 射率爲1 . 5〜1 . 7同時和樹脂組成物(黏著 - 之折射率差爲±0.1以內、更加理想是折IK . 內。在折射率差超過±0.1時,因爲添加於 Φ 著樹脂組成物)而減少透過率,特別是在 有不容易以貼附在具有半導體晶片之突出 之狀態,辨識透過電路構件連接用黏著劑 路面之定位標記之狀態發生。 作爲此種金屬氫氧化物係如果是折射 均粒徑爲0.1 μ m〜1 0 μ m的話,則並無特別 習知之金屬氫氧化物,但是,由安定性和 來看的話,則更加理想是氫氧化鎂、氫氧 φ 、氫氧化鋁。金屬氫氧化物粒子之線膨脹 開始至7〇〇 °C以下之溫度範圍,成爲 更加理想是3x10_6/°C以下。在熱膨脹係 ' ,爲了降低電路構件連接用黏著劑之熱膨 多量之金屬氫氧化物粒子之必要產生。 在電路構件連接用黏著劑,相對於樹 量份而金屬氫氧化物粒子最好是20〜150 想是25〜100重量份、甚至最好是50-100 氫氧化物粒子少於20重量份之狀態下, 發生在清漆中之 粒子均勻地分散 粒子係最好是折 樹脂組成物)間 「率差爲±0.05以 樹脂組成物(黏 厚膜之狀態下, 之連接端子之面 來形成於晶片電 率 1.5〜1.7且平 限制,可以使用 得到之容易程度 化鈣、氫氧化鋇 係數最好是在由 7x 1 (T6/°C 以下、 數變大之狀態下 脹係數,有添加 月旨組成物1 〇 0重 重量份、更加理 重量份。在金屬 導致電路構件連 -19-Further, the metal hydroxide used in the present invention has an emissivity of 1.5 to 1. 7 and the resin composition (adhesion-refractive-index difference is within ±0.1, more preferably y. When it exceeds ±0.1, the transmittance is reduced by the addition of the Φ resin composition, and in particular, it is not easy to attach to the protruding state of the semiconductor wafer, and the positioning mark of the adhesive road surface for the transmission circuit member is recognized. The status takes place. When such a metal hydroxide is a refractive average particle diameter of 0.1 μm to 10 μm, there is no particularly known metal hydroxide. However, it is more desirable from the viewpoint of stability and stability. Magnesium hydroxide, hydrogen oxygen φ, aluminum hydroxide. The linear expansion of the metal hydroxide particles starts to a temperature range of 7 〇〇 ° C or less, and more preferably 3 x 10_6 / ° C or less. In the thermal expansion system, it is necessary to reduce the amount of hot metal hydroxide particles of the adhesive for connecting the circuit members. In the adhesive for connecting the circuit members, the metal hydroxide particles are preferably 20 to 150 with respect to the amount of the tree, and it is intended to be 25 to 100 parts by weight, even more preferably 50 to 100, and less than 20 parts by weight of the hydroxide particles. In the state where the particles in the varnish are uniformly dispersed, the particle system is preferably a resin composition having a rate difference of ±0.05 in a resin composition (in the state of a thick film, the surface of the connection terminal is formed on the wafer) The electric current is 1.5 to 1.7 and the flat limit can be used. It is easy to use calcium. The barium hydroxide coefficient is preferably composed of 7x 1 (T6/°C or less, the number is increased, and the expansion coefficient is added. 1 〇 0 parts by weight, more weight parts. In the metal leads to the circuit components -19-

200934851 接用黏著劑之線膨脹係數之增大以及彈性率之 ’有降低在壓合後之半導體晶片和基板之連g 態發生。另一方面,在練合量多於150重量仿 增加電路構件連接用黏著劑之熔融黏度,因 分地接合半導體之突出電極和基板之電路之狀 本發明之電路構件連接用黏著劑之樹脂組 樹脂組成物)係以(a )熱塑性樹脂、(b ) _ 及(c )硬化劑作爲成分。 作爲(a )熱塑性樹脂係列舉聚酯、聚胺 、聚乙烯醇縮丁醛、聚芳基化物、聚甲基甲基 丙烯酸橡膠、聚苯乙烯、苯氧基樹脂、NBR、 亞胺或矽酮變性樹脂(丙烯矽酮、環氧矽酮、 酮)等。此外’作爲(b )熱硬化性樹脂係有 雙馬來酸酐縮亞胺樹脂、三嗪樹脂、聚醯亞胺 胺樹脂、氰基丙烯酸酯樹脂、苯酚樹脂、不飽 '三聚氰胺樹脂、尿素樹脂、聚胺基甲酸乙醋 氰酸酯樹脂、呋喃樹脂、間苯二酚樹脂、二甲 并鳥糞胺樹脂、二烯丙基鄰苯二甲酸酯樹脂、 聚乙烯醇縮丁醛樹脂、矽氧烷變性環氧樹脂、 聚醯胺醯亞胺樹脂、丙烯酸酯樹脂,可以單獨 2種以上之混合物而使用這些。 即使是在前述之熱硬化性樹脂中,由耐熱 之觀點來看的話’則最好是環氧樹脂,特別是 之提升以及高Tg化(Tg ··玻璃轉移溫度)、 降低,因此 可靠性之狀 之狀態下, ,有無法充 態發生。 成物(黏著 硬化性樹脂 基甲酸乙酯 丙烯酸酯、 SBR、聚醯 聚醯亞胺矽 環氧樹脂、 樹脂、聚醯 和聚酯樹脂 樹脂、聚異 苯樹脂、苯 矽酮樹脂、 矽氧烷變性 或者是成爲 性、黏著性 希望透過性 低線膨脹係 -20- 200934851 數化,因此,最好是萘酚酚醛型固態環氧樹脂、含芴骨格 之液體狀環氧樹脂、或者是固態環氧樹脂。此外,作爲本 發明之(C )硬化劑(稱爲熱硬化性樹脂之硬化劑。)係 列舉苯酚系、咪唑系、醯肼系、硫代系、苯并噁嗪系、三 氟化硼-胺錯合物、鎏鹽、胺醯亞胺、聚胺鹽、二氰二醯 - 胺、有機過氧化物系之硬化劑。此外,爲了延長這些硬化 . 劑之可見時間,因此,能夠以聚胺基甲酸乙酯系、聚酯系 Q 之高分子物質等,來進行被覆及微膠囊化。 此外,爲了增大黏著強度,因此,可以含有偶合劑, 爲了補助薄膜成形性,因此,可以含有聚酯、聚胺基甲酸 乙酯、聚乙烯醇縮丁醛、聚芳基化物、聚甲基甲基丙烯酸 酯、丙烯酸橡膠、聚苯乙烯、苯氧基樹脂、NBR、SBR、 聚醯亞胺或矽酮變性樹脂(丙烯矽酮、環氧矽酮、聚醯亞 胺矽酮)等之熱塑性樹脂,此外,由於金屬氫氧化物粒子 之表面改質之目的,因此,也可以含有矽酮油、聚矽氧烷 〇 、矽酮寡聚物、偶合劑。 本發明之電路構件連接用黏著劑係也能夠添加以有機 高分子化合物所被覆之粒徑3~5μηι之導電粒子及/或金屬 • 之導電粒子而成爲異方導電黏著劑。作爲在以有機高分子 - 化合物所被覆之前之導電粒子係Au、Ag、Ni、Cu、銲錫 等之金屬粒子或碳等,爲了得到充分之適用期,因此,表 層係即使是在遷移金屬中,也比起Ni、Cu等而還最好是 Au、Ag或白金族之貴金屬類,更加理想是Au。此外,能 夠以Au等之貴金屬類,來被覆Ni、Cu等之金屬表面。此 -21 - 200934851 外,在使用於非導電性之玻璃、陶瓷、塑膠等藉由被覆等 來形成前述導通層(由導通材料來形成之層)而最外層成 爲貴金屬類來作爲導電粒子之狀態或者是使用熱熔融金屬 粒子來作爲導電粒子之狀態下,導電粒子係具有因爲加熱 加壓之所造成之變形性,因此,吸收電極之高度偏差,在 連接時,增加和電極之接觸面積,提高連接可靠性,所以 ,變得理想。爲了得到良好之連接電阻,因此,貴金屬類 之被覆層之厚度係最好是100埃(A)以上。但是,在被 覆時之所產生之貴金屬類層之缺損或者是在導電粒子之混 合分散時之所產生之貴金屬類層之缺損等係因爲成爲原因 之所引起之氧化還原作用而產生游離自由基之時,引起保 存性之降低,所以,在Ni、Cu等之金屬上設置貴金屬類 之層之狀態下,被覆層之厚度係最好是300埃(A)以上 。接著,在變得過度厚之時,這些效果係飽和,因此,希 望最大是ίμιη,但是,這個係無法限制被覆層之厚度。 通常以有機高分子化合物,來被覆這些導電粒子之表 面。有機高分子化合物係在成爲水溶性時,被覆作業性變 得良好,因此,變得理想。作爲水溶性高分子係列舉褐藻 酸、果膠酸、羧基甲基纖維素、瓊脂、卡德蘭膠(Curdlan) 和聚三葡萄糖(pullulan)等之多糖類;聚天冬氨酸、聚谷氨 酸、聚賴氨酸、聚蘋果酸、聚甲基丙烯酸、聚甲基丙烯酸 銨鹽、聚甲基丙烯酸鈉鹽、聚醯胺酸、聚順丁烯二酸、聚 衣康酸、聚富馬酸、聚(P-苯乙烯羧酸)、聚丙烯酸、聚 丙烯醯胺、聚丙烯酸甲酯、聚丙烯酸乙酯、聚丙烯酸銨鹽 -22- 200934851 、聚丙烯酸鈉鹽、聚醯胺酸、聚醯胺酸銨鹽、聚醯胺酸鈉 鹽及聚乙醛酸等之聚羧酸、聚羧酸酯及其鹽、聚乙烯醇、 聚乙烯基吡咯烷酮及聚丙烯醇等之乙烯基系單體。這些係 可以使用單一之化合物,也可以倂用2種以上之化合物。 被覆層之厚度係最好是ΐμηι以下,排除該被覆層而使得導 ' 電粒子將連接端子和連接端子予以電連接,因此,在加熱 - 、加壓時,必須排除接觸到連接端子之部分之被覆層。通 Φ 常導電性粒子係以相對於樹脂組成物(黏著劑樹脂)成分 100體積份而成爲0.1〜3 0體積份之範圍,由於用途,來分 別使用。爲了防止由於過剩之導電性粒子之所造成之鄰接 電路之短路等,因此,更加理想是〇. 1 ~ 1 〇體積份。 本發明係提供一種具有藉由以上說明之電路構件連接 用黏著劑之所接合之電路基板之半導體裝置。此外’電路 基板係最好是藉由電路構件連接用黏著劑之硬化而進行接 合。作爲具有藉由本發明之電路構件連接用黏著劑之所接 Ο 合之電路基板之半導體裝置之例子係列舉半導體記憶體、 半導體記憶體用之密封樹脂封裝體、邏輯控制器用之密封 樹脂封裝體等。 實施例 在以下,根據實施例及比較例而還更加具體地說明本 發明,但是,本發明係完全不限定於以下之實施例。 (實施例1 ) -23- 200934851 作爲3次元交聯性樹脂係環氧樹脂EP- 1 03 2-Η 60 (曰 本環氧樹脂股份有限公司製、製品名稱)20重量份、環氧 樹脂YL98 0 (日本環氧樹脂股份有限公司製、製品名稱) 15重量份、苯氧基樹脂YP50S (東都化成股份有限公司、 製品名稱)25重量份,作爲微膠囊型硬化劑係 HX-* 3 941 HP (旭化成股份有限公司製、製品名稱)40重量份 以及砂院偶合劑SH6040 ( Dow Corning Toray砂酮公司製 Q 、製品名稱)1重量份,溶解於甲苯和乙酸乙酯之混合溶 媒中,得到黏著樹脂組成物(樹脂組成物)之清漆。在使 用滾筒塗佈器而塗佈該清漆之一部分於間隔片薄膜(PET 薄膜)上之後,藉由在70°C之烤箱,乾燥1 〇分鐘而在間 隔片之上,得到厚度25 μηι之黏著劑樹脂組成物之膜。 將該膜設置在Abbe折射率計(鈉D射線)之試料台 ,剝離間隔片,在這個滴下1滴之匹配油,載置折射率 1.74之試驗片,測定折射率。結果,黏著劑樹脂組成物之 ❹ 折射率係1.60 ( 25°C )。另一方面,在計量清漆後,在這 個,加入平均粒徑〇.49μιη之氫氧化鎂MH-30 (岩谷化學 工業股份有限公司製、製品名稱)59重量份,進行攪拌而 ' 分散於清漆中。在間隔片薄膜(PET薄膜)上使用滾筒塗 - 佈器而塗佈該清漆之後,藉由在70°C之烤箱,乾燥1〇分 鐘,而在間隔片之上,得到厚度2 5 μπι之透過性確認用薄 膜。藉由UV-VIS分光光度計而測定得到之透過性確認用 薄膜之555 nm之透過率係65% 。接著,在另外計量開始 之清漆後,在這個加入平均粒徑〇·49μιη之氫氧化鎂59重 -24- 200934851 量份,進行攪拌而分散於清漆中。在間隔片薄膜(PET薄 膜)上使用滾筒塗佈器而塗佈該清漆之後,藉由在7(TC之 烤箱,乾燥10分鐘,而在間隔片之上,得到厚度50μιη之 電路構件連接用黏著劑。 (實施例2) 除了加入平均粒徑1.3μιη之氫氧化鋁BF013(日本輕 金屬股份有限公司製、製品名稱)60.5重量份來取代實施 例1之氫氧化鎂粒子以外,其餘係相同於實施例1而得到 電路構件連接用黏著劑。 (比較例1 ) 除了加入平均粒徑〇.5μηι之二氧化矽粒子SE205 0 C Admatechs公司製、製品名稱)55.25重量份來取代實施 例1之氫氧化鎂粒子以外,其餘係相同於實施例1 $ # ^ Q 電路連接用黏著劑。 (比較例2) 除了加入平均粒徑〇·3μΐη之二氧化矽粒子F-21 ( fg森 股份有限公司製、製品名稱)5 5.2 5重量份來取代實施例 1之氫氧化鎂粒子以外,其餘係相同於實施例1而得到電 路連接用黏著劑。 -25- 200934851200934851 The increase in the coefficient of linear expansion of the adhesive and the decrease in the elastic modulus occur in the continuous state of the semiconductor wafer and the substrate after the pressing. On the other hand, in the case where the amount of the bonding is more than 150, the melt viscosity of the adhesive for connecting the circuit member is increased, and the resin of the bonding member for the circuit member of the present invention is bonded to the circuit of the protruding electrode of the semiconductor and the substrate. The resin composition is composed of (a) a thermoplastic resin, (b) _ and (c) a curing agent. As (a) thermoplastic resin series, polyester, polyamine, polyvinyl butyral, polyarylate, polymethylmethacrylic rubber, polystyrene, phenoxy resin, NBR, imine or fluorenone Denatured resin (acrylone, epoxy ketone, ketone), and the like. Further, 'as (b) a thermosetting resin is a bis-maleic anhydride imide resin, a triazine resin, a polyamidamine resin, a cyanoacrylate resin, a phenol resin, an unsaturated 'melamine resin, a urea resin, Ethyl urethane resin, furan resin, resorcinol resin, dimethyl guanamine resin, diallyl phthalate resin, polyvinyl butyral resin, oxime The alkene-denatured epoxy resin, the polyamidoximine resin, and the acrylate resin may be used alone or in combination of two or more. Even in the above-mentioned thermosetting resin, it is preferable that it is an epoxy resin from the viewpoint of heat resistance, in particular, it is improved, and high Tg (Tg··glass transition temperature) is lowered, so reliability is high. In the state of the shape, there is a failure to occur. Products (adhesively curable resin urethane acrylate, SBR, poly phthalimide oxime epoxy resin, resin, polyfluorene and polyester resin resin, polyisocene resin, benzophenone resin, decane oxide) Denaturation is a desirable, adhesive, permeable, low-linear expansion system -20- 200934851. Therefore, it is best to use a naphthol phenolic solid epoxy resin, a liquid epoxy resin containing a sacral lattice, or a solid ring. Further, the (C) curing agent (referred to as a curing agent for a thermosetting resin) of the present invention is a phenol-based, imidazole-based, anthraquinone-based, thio-, benzoxazine-based, or trifluorobenzene series. a boron-amine complex, an onium salt, an amine imide, a polyamine salt, a dicyanodiamide-amine, an organic peroxide-based hardener. Further, in order to extend the visible time of these hardening agents, Coating and microencapsulation can be carried out by using a polyurethane material or a polymer material of polyester Q. Further, in order to increase the adhesive strength, a coupling agent may be contained, and in order to compensate for film formability, Can contain poly , polyurethane, polyvinyl butyral, polyarylate, polymethyl methacrylate, acrylic rubber, polystyrene, phenoxy resin, NBR, SBR, polyimine or hydrazine a thermoplastic resin such as a ketone-denatured resin (acrylone, oxime oxime, or oxime oxime), and, in addition, for the purpose of surface modification of the metal hydroxide particles, may also contain an oxime oil or a poly矽 〇 〇 〇 矽 矽 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 电路 电路 电路 电路 电路 电路 电路 电路 电路The particles are an isotropic conductive adhesive, and the conductive particles are Au, Ag, Ni, Cu, metal particles such as solder, or the like before being coated with the organic polymer compound, in order to obtain a sufficient application period. The surface layer is preferably a noble metal of Au, Ag or a platinum group, and is more preferably a noble metal such as Ni, Cu or the like, even if it is in a transition metal. Further, it is possible to coat Ni with a noble metal such as Au. Gold of Cu, etc. In addition, the conductive layer (the layer formed of a conductive material) is formed by coating or the like on a non-conductive glass, ceramic, plastic, or the like, and the outermost layer is a noble metal as a conductive particle. In the state in which the hot molten metal particles are used as the conductive particles, the conductive particles have deformability due to heating and pressurization, and therefore, the height deviation of the absorption electrode increases the contact area with the electrode at the time of connection. In order to obtain a good connection resistance, it is preferable that the thickness of the coating layer of the noble metal is 100 angstroms (A) or more. However, the noble metal generated at the time of coating is preferable. The defect of the layer or the defect of the noble metal layer generated when the conductive particles are mixed and dispersed is caused by the redox reaction caused by the cause of the free radical, and the storage property is lowered. In the state in which a layer of a noble metal is provided on a metal such as Ni or Cu, the thickness of the coating layer is preferably 300 Å or more (A) or more. . Then, when it becomes excessively thick, these effects are saturated, and therefore, it is desirable that the maximum is ίμιη, but this system cannot limit the thickness of the coating layer. The surface of these conductive particles is usually coated with an organic polymer compound. When the organic polymer compound is water-soluble, the coating workability is improved, which is preferable. As a water-soluble polymer series, polysaccharides such as alginic acid, pectic acid, carboxymethyl cellulose, agar, Curdlan and pullulan; polyaspartic acid and polyglutamine Acid, polylysine, polymalic acid, polymethacrylic acid, polymethylammonium methacrylate, polymethyl methacrylate, polylysine, polymaleic acid, polyitaconic acid, polyfama Acid, poly(P-styrene carboxylic acid), polyacrylic acid, polypropylene decylamine, polymethyl acrylate, polyethyl acrylate, polyacrylic acid ammonium salt-22- 200934851, polyacrylic acid sodium salt, polylysine, poly Polyvinyl carboxylic acid, polycarboxylate, polyglycolic acid, polycarboxylate, polycarboxylate, and the like, polyvinyl alcohol, polyvinylpyrrolidone, and vinyl alcohol . These compounds may be used alone or in combination of two or more. The thickness of the coating layer is preferably ΐμηι or less, and the coating layer is excluded such that the conductive particles electrically connect the connection terminal and the connection terminal. Therefore, when heating and pressurizing, it is necessary to exclude the portion contacting the connection terminal. Covered layer. The Φ constant conductive particles are in a range of 0.1 to 30 parts by volume based on 100 parts by volume of the resin composition (adhesive resin) component, and are used depending on the application. In order to prevent a short circuit of an adjacent circuit due to excess conductive particles, it is more preferably 1 to 1 〇 by volume. The present invention provides a semiconductor device having a circuit board bonded by an adhesive for connecting circuit members described above. Further, the circuit board is preferably joined by hardening of the adhesive for connecting the circuit members. Examples of the semiconductor device including the circuit board to which the circuit member for connection of the circuit member of the present invention is bonded are a semiconductor resin, a sealing resin package for a semiconductor memory, a sealing resin package for a logic controller, and the like. . EXAMPLES Hereinafter, the present invention will be more specifically described based on examples and comparative examples, but the present invention is not limited to the examples below. (Example 1) -23- 200934851 As a 3-dimensional crosslinkable resin epoxy resin EP- 1 03 2-Η 60 (manufactured by Sakamoto Epoxy Co., Ltd., product name) 20 parts by weight, epoxy resin YL98 0 (Nippon Epoxy Resin Co., Ltd. product name) 15 parts by weight, phenoxy resin YP50S (Dongdu Chemical Co., Ltd., product name) 25 parts by weight, as a microcapsule type hardener HX-* 3 941 HP 40 parts by weight of Asahi Kasei Co., Ltd., and 1 part by weight of sand compound coupling agent SH6040 (Q, product name, manufactured by Dow Corning Toray Co., Ltd.), dissolved in a mixed solvent of toluene and ethyl acetate, and adhered. A varnish of a resin composition (resin composition). After coating one of the varnishes on the spacer film (PET film) using a roll coater, it is dried on a spacer at 70 ° C for 1 〇 minutes to obtain a thickness of 25 μηι. A film of a resin composition. The film was placed on a sample stand of an Abbe refractometer (sodium D-ray), and the spacer was peeled off. One drop of the matching oil was dropped thereon, and a test piece having a refractive index of 1.74 was placed thereon to measure the refractive index. As a result, the 折射率 refractive index of the adhesive resin composition was 1.60 (25 ° C). On the other hand, after the varnish was measured, 59 parts by weight of magnesium hydroxide MH-30 (manufactured by Iwatani Chemical Industry Co., Ltd.) having an average particle diameter of 49.49 μm was added thereto, and the mixture was stirred and dispersed in the varnish. . After coating the varnish on a spacer film (PET film) using a roll coater, it was dried in an oven at 70 ° C for 1 minute, and over the spacer, a thickness of 2 5 μm was obtained. Film for confirmation. The transmittance at 555 nm of the film for transparency confirmation measured by a UV-VIS spectrophotometer was 65%. Next, after the start of the varnish was additionally measured, the amount of the hydroxide having an average particle diameter of 〇·49 μm was added in an amount of 59 to -24 to 200934851, and the mixture was stirred and dispersed in the varnish. After coating the varnish on a spacer film (PET film) using a roll coater, the substrate member was bonded at a thickness of 50 μm by drying in a 7 (TC oven for 10 minutes on the spacer sheet). (Example 2) Except that 60.5 parts by weight of aluminum hydroxide BF013 (manufactured by Nippon Light Metal Co., Ltd., product name) having an average particle diameter of 1.3 μm was added instead of the magnesium hydroxide particles of Example 1, the same procedure was carried out. An adhesive for connecting a circuit member was obtained in Example 1. (Comparative Example 1) In place of the oxidized hydroxide of Example 1, except that cerium oxide particles SE205 0 C Admatechs Co., Ltd., product name: 55.25 parts by weight of an average particle diameter of 〇.5 μηι was added. The remainder of the magnesium particles were the same as in Example 1 $ #^ Q for the connection of the adhesive. (Comparative Example 2) In place of the magnesium hydroxide particles of Example 1, except that 55.2 parts by weight of cerium oxide particles F-21 (product name, manufactured by Fgsen Co., Ltd.) having an average particle diameter of 〇·3 μΐη was added. The adhesive for circuit connection was obtained in the same manner as in Example 1. -25- 200934851

材料名稱 實施例1 實施例2 EP1032H60 20 20 YL980 15 15 YP50S 25 25 HX-3 94 1 HP 40 40 SH6040 1 1 氫氧化鎂(平均粒徑 0,49um) 59 - 氫氧化鋁(平均粒徑 1 .3 um) - 60.5 表中之配合單位係重量份 [表2] 材料名稱 比較例1 比較例2 EP1032H60 20 20 YL980 15 15 YP50S 25 25 HX-3941HP 40 40 SH6040 1 1 二氧化矽SE2050(平均粒徑0.5um) 55.25 _ 二氧化矽F-21(平均粒徑0_3um) - 55.25 表中之配合單位係重量份 (半導體裝置之製作、特性確認) 分別製作藉由在實施例1〜2以及比較例1〜2所得到之 電路連接用黏著劑來連接之半導體裝置,實施特性之確認 -26- 200934851 (半導體晶圓/電路構件連接用黏著劑/切割膠帶層積體) 在加熱JCM公司製之附模組膠膜(Die Attach Film)安 裝器之吸附台座至8 0 °C後’在吸附台座上,使得凸塊側朝 向上方而搭載形成鍍金凸塊之厚度15〇μιη、直徑6英吋之 半導體晶圓。將實施例1 ~2以及比較例1〜2所記載之電路 - 構件連接用黏著劑,切斷成爲每個間隔片200mmx200mm . ,使得絕緣性黏著劑層側,朝向於半導體晶圓之凸塊側, 0 不捲入空氣地由半導體晶圓之端開始,藉由附模組(DieMaterial Name Example 1 Example 2 EP1032H60 20 20 YL980 15 15 YP50S 25 25 HX-3 94 1 HP 40 40 SH6040 1 1 Magnesium hydroxide (average particle size 0,49 um) 59 - Aluminum hydroxide (average particle size 1 . 3 um) - 60.5 The unit of the unit weight in the table [Table 2] Material name comparison example 1 Comparative example 2 EP1032H60 20 20 YL980 15 15 YP50S 25 25 HX-3941HP 40 40 SH6040 1 1 Cerium oxide SE2050 (average particle size 0.5 um) 55.25 _ cerium oxide F-21 (average particle diameter 0_3 um) - 55.25 The weight of the compounding unit in the table (production of semiconductor device, characteristic confirmation) was produced by using Examples 1 to 2 and Comparative Example 1, respectively. (2) The semiconductor device to which the circuit is connected by an adhesive is connected, and the performance is confirmed. -26- 200934851 (Adhesive for semiconductor wafer/circuit member connection/cut tape laminate) After the adsorption pedestal of the Die Attach Film mounter reaches 80 °C, 'on the adsorption pedestal, the bump side is oriented upward and the thickness of the gold-plated bump is 15 〇μηη, and the semiconductor crystal of 6 inches in diameter is mounted. circle. The circuit-member bonding adhesives described in Examples 1 to 2 and Comparative Examples 1 and 2 were cut into 200 mm x 200 mm for each spacer so that the insulating adhesive layer side faced the bump side of the semiconductor wafer. , 0 is not involved in the air from the end of the semiconductor wafer, with the module (Die

Attach)安裝器之貼附滾筒而進行擠壓及層壓。在層壓後, 沿著晶圓之外形而切斷黏著劑之溢出部分。在切斷後,剝 離間隔片。接著,使得貼附黏著劑之面朝向下方而將剝離 間隔片後之晶圓和電路構件連接用黏著劑之層積體,來搭 載於台座溫度設定爲25°C之附模組膠膜(Die Attach Film) 安裝器之吸附台座,並且,12英吋晶圓用之切割框架,設 置於晶圓之外圍。使得UV硬化型切割膠帶UC-334EP-110 φ (古川電工公司製、製品名稱)之黏著面,朝向於半導體 晶圓側,不捲入空氣地由切割框架之端開始,藉由附模組 (Die Attach)安裝器之貼附滾筒而進行擠壓及層壓。在層 - 壓後’於切割框架之外圍及內圍之中間附近,將切割膠帶 - 予以切斷,得到固定於切割框架之電路構件連接用黏著劑 /半導體晶圓/切割膠帶層積體。 (切割) 將固定於切割框架之電路構件連接用黏著劑/半導體 -27- 200934851 晶圓/切割膠帶層積體,搭載於DISCO股份有限公司製之 全自動切割鋸DFD636 1。透過黏著劑而進行標線之對位。 藉由單片切割,以lOmmx 10mm之間隔,來切斷至切割膠 帶內爲止。在切斷後,進行洗淨,在以吹附空氣而飛散水 分之後,由切割膠帶側開始,進行UV照射。然後,由切 ' 割膠帶側開始,突起於半導體晶圓側,得到電路構件連接 . 用黏著劑形成於凸塊側之lOmmx 10mm之半導體晶片。 ❹ (壓合) 以附有電路構件連接用黏著劑之半導體晶片之黏著劑 面朝向於晶片碟之底面之狀態,來收納於晶片碟,這個設 置於Panasonic公司製之覆晶接合器FCB3之晶片碟收納 場所。接著,將Au/Ni電鍍之Cu電路印刷基板,設置於 基板搭載台座。由電路構件連接用黏著劑側開始,辨識形 成於半導體晶片電路面之鋁製定位標記,在進行和基板之 〇 對位後,以200°c、10秒鐘、1.86MPa之條件,來進行加 熱加壓,得到半導體裝置。在得到之半導體裝置之176個 凸塊連結菊鏈(daisy chain )之連接電阻係8.6 ◦,確認 ' 成爲良好之連接狀態。此外,在半導體裝置放置於30°C、 - 相對濕度60%之槽內192小時之後,進行3次之IR重熔 處理(最大265 °C ),結果,並無發生晶片之剝離或導通 不良。此外,將IR重熔後之半導體裝置,放置於高溫高 濕度試驗機(85 °C /85¾ RH ) 200小時,確認在放置後之 連接電阻,並無發生導通不良。此外,將IR重熔後之半 -28- 200934851 導體裝置,放置於溫度循環試驗機(-55 °C 30分鐘、室溫 5分鐘、125 °C 30分鐘)內,進行在槽內之連接電阻測定 ,確認並無發生在經過200次循環後之導通不良。 就在實施例1 ~2以及比較例1〜2所得到之電路構件連 接用黏著劑而言,藉由下列之測定而進行特性之確認。 . (線膨脹係數之測定) φ 將在實施例及比較例所得到之電路構件連接用黏著劑 ,每間隔片地放置在設定爲1 80 °c之烤箱3小時,進行加 熱硬化處理。由間隔片開始剝離加熱硬化後之薄膜,切斷 成爲30mmx2mm之大小。使用精工(SEIKO )儀器公司製 之TMA/SS61 00 (製品名稱),在設定夾頭間爲20mm之 後,以測定溫度範圍20°C〜300°C、升溫速度5°C /min、相 對於剖面積而成爲0.5 MPa壓力之荷重條件’藉由拉引試 驗模式而進行熱機械分析,求出線膨脹係數。 〇 (反應率之測定) 在鋁製測定容器來計量藉由實施例及比較例所得到之 - 電路構件連接用黏著劑2~1 Omg之後,藉由 PerkinElmer 公司製之差示掃描熱量測定裝置 DSC ( Differential Scaning Calorimeter) Pylisl (製品名稱),以 20 °C /min 之升溫速度至30~300°C爲止,而進行發熱量之測定’以這 個作爲初期發熱量。接著,藉由熱壓合裝置之加熱頭夾住 於間隔片之熱電偶而進行溫度之確認’設定在20秒鐘後 -29- 200934851 ,達到180 °C之溫度。藉由該加熱頭之設定而加熱夾住於 間隔片之電路構件連接用黏著劑20秒鐘’得到施行同等 於熱壓合時之加熱處理之狀態之薄膜。計量加熱處理後之 薄膜2~10mg而放入至鋁製測定容器,藉由DSC,以20°C /min之升溫速度至30-300 °C爲止,而進行發熱量之測定 • ,以這個作爲加熱後之發熱量。由得到之發熱量,藉由下 . 列之公式而算出反應率(% )。 ❹ 公式=(初期發熱量-加熱後之發熱量)/(初期發熱量)X〗〇〇 作爲電路構件連接用黏著劑之特性係在每個實施例及 比較例之平行透過率、硬化後之線膨脹係數、可否辨識在 覆晶接合器之定位標記、反應率、甚至壓合後之連接電阻 値以及可靠性試驗後之連接電阻値,顯示於表3。 〇 [表3] 項目 實施例1 實施例2 比較例1 比較例2 平行透過率(%) 63 64 2 2 線膨脹係數(4〇-i〇(rc)(xi〇-Vc) 43 46 50 48 晶片定位標記之辨識 可能 可能 不可能 不可能 反應率(%) 78 78 75 76 壓合後之連接電阻(Ω) 8.3 8.3 導通不良 導通不良 高溫高濕度試驗200小時後之連接電阻(Ω) 8.5 8.6 - - 溫度循環試驗200次循環後之連接電阻(Ω) 8.5 8.5 - - 正如實施例所顯示的,添加折射率1.5 7〜1.60之金屬 -30- 200934851 氫氧化物粒子之電路構件連接用黏著劑係可以確認:1)平 行透過率爲3 0%以上,因此,可以使用覆晶接合器之辨識 系統,透過黏著劑而辨識晶片電路面之定位標記;2)硬化 後之線膨脹係數減低至70x 1 (T6/°C以下,在連接可靠性試 驗,並無發生導通不良;3)以熱壓合時之加熱條件,來達 - 到75¾以上之反應率,因此,顯示穩定之低連接電阻,即 . 使是以玻璃基板作爲對象之異方導電性黏著劑,並且,或 0 者是以玻璃環氧基板作爲對象之接觸型熱壓合樹脂,也變 得良好。另一方面,在比較例1、2,由於添加折射率 1 .46之二氧化矽而使得和樹脂組成物之折射率差變大,發 生光散亂,平行透過率變小。在該狀態下,無法進行在覆 晶接合器之定位標記之辨識作業,無法進行對位,因此, 無法確保半導體裝置之初期導通。 [產業上之可利用性] Q 本發明之電路構件連接用黏著劑係可以使用作爲能夠 對應於窄間距化及窄間隙化之前置型底部塡充工法。附黏 著劑之半導體晶片係無切割時之污染發生並且可以在切割 - 後,藉著由切割膠帶簡便地剝離而得到。此外,本發明之 - 電路構件連接用黏著劑係可以利用成爲能夠同時成立:實 現附黏著劑晶片和電路基板之高精度之對位之透明性以及 由於低熱膨脹係數化之所造成之高度連接可靠性之迅速硬 化性之晶圓貼附對應用之黏著劑。 -31 -Attach) The applicator is attached to the roller for extrusion and lamination. After lamination, the overflow portion of the adhesive is cut along the outer shape of the wafer. After cutting, the spacer is peeled off. Next, the laminate on which the adhesive is attached is directed downward, and the laminate of the spacer and the adhesive for connecting the circuit member after the spacer is peeled off is mounted on the module film having a pedestal temperature of 25 ° C (Die Attach Film) The suction pedestal of the mounter and the 12-inch wafer cutting frame is placed on the periphery of the wafer. The adhesion surface of the UV-curable dicing tape UC-334EP-110 φ (manufactured by Furukawa Electric Co., Ltd.) is oriented toward the side of the semiconductor wafer, starting from the end of the cutting frame without being caught in the air, by attaching a module ( Die Attach) The applicator is attached to the roller for extrusion and lamination. The dicing tape was cut in the vicinity of the periphery of the dicing frame and the inner periphery of the dicing frame after the layer-pressing, and the circuit member connecting adhesive/semiconductor wafer/cutting tape laminate fixed to the dicing frame was obtained. (Cut) Adhesive/semiconductor for connecting circuit components to be fixed to the cutting frame -27- 200934851 The wafer/cut tape laminate is mounted on the fully automatic cutting saw DFD636 1 manufactured by DISCO. The alignment of the markings is carried out by means of an adhesive. By cutting a single piece, it is cut at a distance of 10 mm x 10 mm until it is cut into the tape. After the cutting, the washing was performed, and after the water was dispersed by blowing air, the UV irradiation was performed from the side of the dicing tape. Then, starting from the cut-cut tape side, the semiconductor member was attached to the semiconductor wafer side to obtain a circuit member connection. The semiconductor wafer of 10 mm x 10 mm formed on the bump side was formed with an adhesive. ❹ (Pressing) The surface of the wafer of the semiconductor wafer with the adhesive for connecting the circuit member is placed on the bottom surface of the wafer, and is placed on the wafer. This wafer is mounted on the flip chip bonder FCB3 manufactured by Panasonic. Dish storage place. Next, an Au/Ni-plated Cu circuit printed substrate was placed on the substrate mounting pedestal. Starting from the adhesive side of the circuit member connection, the aluminum positioning mark formed on the circuit surface of the semiconductor wafer is recognized, and after being aligned with the substrate, the heating is performed at 200 ° C, 10 seconds, and 1.86 MPa. Pressurization to obtain a semiconductor device. In the obtained 176 bumps of the obtained semiconductor device, the connection resistance of the daisy chain was 8.6 ◦, and it was confirmed that 'the connection state was good. Further, after the semiconductor device was placed in a bath at 30 ° C and a relative humidity of 60% for 192 hours, three times of IR remelting treatment (maximum 265 ° C) was performed, and as a result, no wafer peeling or conduction failure occurred. Further, the semiconductor device after IR remelting was placed in a high-temperature and high-humidity tester (85 °C / 853⁄4 RH) for 200 hours, and the connection resistance after standing was confirmed, and conduction failure did not occur. In addition, the half--28-200934851 conductor device after IR remelting was placed in a temperature cycle tester (-55 °C for 30 minutes, room temperature for 5 minutes, and 125 °C for 30 minutes) to perform connection resistance in the tank. The measurement confirmed that the conduction failure did not occur after 200 cycles. The adhesives for connecting the circuit members obtained in Examples 1 to 2 and Comparative Examples 1 and 2 were confirmed by the following measurements. (Measurement of coefficient of linear expansion) φ The adhesive for connecting the circuit members obtained in the examples and the comparative examples was placed in an oven set to 180 ° C for 3 hours, and subjected to heat curing treatment. The heat-hardened film was peeled off from the spacer and cut into a size of 30 mm x 2 mm. Using TMA/SS61 00 (product name) manufactured by Seiko Instruments Co., Ltd., after setting the chuck to 20 mm, the temperature range is 20 ° C to 300 ° C, and the temperature rise rate is 5 ° C / min. The load condition of the pressure of 0.5 MPa by the area was subjected to thermomechanical analysis by the pull test mode, and the coefficient of linear expansion was obtained. 〇 (Measurement of Reaction Rate) After measuring 2 to 10 mg of the adhesive for connecting circuit members obtained in the examples and the comparative examples in an aluminum measuring container, a differential scanning calorimeter DSC manufactured by PerkinElmer Co., Ltd. (Differential Scaning Calorimeter) Pylisl (product name), measured at a temperature rise rate of 20 °C /min to 30~300 °C, is used as the initial calorific value. Next, the temperature was confirmed by the thermocouple of the thermocompression device sandwiching the thermocouple of the spacer, and the temperature was set to 190-200934851 after 20 seconds to reach a temperature of 180 °C. By the setting of the heating head, the adhesive for connecting the circuit member sandwiched between the spacers is heated for 20 seconds to obtain a film which is in the same state as the heat treatment at the time of thermocompression bonding. 2 to 10 mg of the film after the heat treatment is placed in an aluminum measuring container, and the calorific value is measured by DSC at a temperature rising rate of 20 ° C /min to 30-300 ° C. The amount of heat generated after heating. From the obtained calorific value, the reaction rate (%) was calculated by the following formula.公式 Formula = (initial calorific value - calorific value after heating) / (initial calorific value) X 〇〇 The characteristics of the adhesive for connecting the circuit members are the parallel transmittance and hardening of each of the examples and the comparative examples. The coefficient of linear expansion, the identification of the positioning marks on the flip chip bonder, the reaction rate, and even the connection resistance after pressing, and the connection resistance after the reliability test are shown in Table 3. 〇[Table 3] Item Example 1 Example 2 Comparative Example 1 Comparative Example 2 Parallel transmittance (%) 63 64 2 2 Linear expansion coefficient (4〇-i〇(rc)(xi〇-Vc) 43 46 50 48 Identification of wafer positioning marks may not be possible. Responsive rate (%) 78 78 75 76 Connection resistance after pressing (Ω) 8.3 8.3 Poor conduction failure Poor high temperature and high humidity test connection resistance after 200 hours (Ω) 8.5 8.6 - - Temperature cycling test After 200 cycles of connection resistance (Ω) 8.5 8.5 - - As shown in the examples, a metal with a refractive index of 1.5 7 to 1.60 is added. - 30, 1983, pp. It can be confirmed that: 1) the parallel transmittance is more than 30%. Therefore, the identification system of the flip chip bonder can be used to identify the positioning mark of the circuit surface of the wafer through the adhesive; 2) the coefficient of linear expansion after hardening is reduced to 70x. 1 (T6/°C or less, in the connection reliability test, no conduction failure occurs; 3) The heating rate at the time of thermal compression is up to a reaction rate of 753⁄4 or more, thus showing a stable low connection resistance, That is, the glass substrate is targeted The contact-type thermocompression resin which is a glass epoxy substrate is also excellent in the case of the heterogeneous conductive adhesive. On the other hand, in Comparative Examples 1 and 2, since the refractive index difference of the resin composition was increased by adding cerium oxide having a refractive index of 1.46, light was scattered and the parallel transmittance was small. In this state, the identification of the positioning marks on the flip-chip bond cannot be performed, and the alignment cannot be performed. Therefore, the initial conduction of the semiconductor device cannot be ensured. [Industrial Applicability] Q The adhesive for connecting circuit members of the present invention can be used as a bottom-filling method capable of meeting a narrow pitch and a narrow gap. The semiconductor wafer with the adhesive is produced without contamination at the time of cutting and can be obtained by simply peeling off the dicing tape after cutting. Further, the adhesive for connecting circuit members of the present invention can be used at the same time to achieve high-precision alignment transparency of the adhesive-attached wafer and the circuit substrate, and reliable connection due to low thermal expansion coefficient. The fast-hardening wafer is attached to the adhesive for the application. -31 -

Claims (1)

200934851 十、申請專利範園 1· 一種電路構件連接用黏著劑,係爲連接相對向之 電路基板用之電路構件連接用黏著劑,其特徵爲,由含有 熱塑性樹脂、熱硬化性樹脂及硬化劑之樹脂組成物,與分 散於該組成物中之金屬氫氧化物粒子所構成。 ' 2 ·如申請專利範圍第1項記載之電路構件連接用黏 • 著劑’其中未硬化時之可見光平行透過率爲15〜100%。 〇 3 ·如申請專利範圍第1項或第2項記載之電路構件 連接用黏著劑’其中該金屬氫氧化物粒子之折射率爲1.5〜 1.7° 4·如申請專利範圍第1項〜第3項中任一項記載之電 路構件連接用黏著劑,其中該金屬氫氧化物粒子之平均粒 徑爲 0.1μιη~10μΓη。 5 _如申請專利範圍第1項〜第4項中任一項記載之電 路構件連接用黏著劑’其中依據在1 8 0。(:下加熱2 0秒後之 G 差示掃描熱量測定中測得之反應率爲75%以上。 6 ·如申請專利範圍第1項〜第5項中任一項記載之電 路構件連接用黏著劑’其中4 0 °C〜100。(:之線膨脹係數爲 ' 70xl(T6/°C 以下。 - 7. 一種半導體裝置’其特徵爲’具有使用如申請專 利範圍第1項〜第6項中任一項記載之電路構件連接用黏 著劑所連接之電路基板。 -32- 200934851 七、指定代表圖 (一) 、本案指定代表圖為:無 (二) 、本代表圖之元件代表符號簡單說明:無200934851 X. Patent application 1 1. An adhesive for connecting circuit members, which is an adhesive for connecting circuit members for connecting circuit boards, which is characterized by comprising a thermoplastic resin, a thermosetting resin, and a hardener. The resin composition is composed of metal hydroxide particles dispersed in the composition. '2. The visible light parallel transmittance of the adhesive for connecting circuit members according to the first aspect of the invention is 15 to 100%. 〇3. The adhesive for connecting circuit members according to the first or second aspect of the patent application, wherein the metal hydroxide particles have a refractive index of 1.5 to 1.7°. 4, as claimed in the first to third claims. The adhesive for connecting circuit members according to any one of the preceding claims, wherein the metal hydroxide particles have an average particle diameter of from 0.1 μm to 10 μm. 5 _ The adhesive for connecting a circuit member according to any one of the first to fourth aspects of the patent application is as follows. (: The reaction rate measured in the G differential scanning calorimetry after heating for 20 seconds is 75% or more. 6) The bonding of the circuit member according to any one of the first to fifth aspects of the patent application range Agent 'where 40 ° C ~ 100. (: The coefficient of linear expansion is '70xl (T6 / ° C or less. - 7. A semiconductor device 'characterized as 'has been used as claimed in the first to sixth items A circuit board to which an adhesive for connecting circuit members is connected as described in any one of the above. -32- 200934851 VII. Designated representative diagram (1) The representative representative figure of the present case is: none (2), the representative symbol of the representative figure is simple Description: None 八、本案若有化學式時,請揭示最能顯示發明特徵的化學 式:無8. If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention: none -4--4-
TW097146663A 2007-11-29 2008-12-01 Adhesive for circuit component connection and semiconductor device TWI419954B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007308668 2007-11-29

Publications (2)

Publication Number Publication Date
TW200934851A true TW200934851A (en) 2009-08-16
TWI419954B TWI419954B (en) 2013-12-21

Family

ID=40678672

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097146663A TWI419954B (en) 2007-11-29 2008-12-01 Adhesive for circuit component connection and semiconductor device

Country Status (5)

Country Link
JP (1) JP5088376B2 (en)
KR (1) KR101302933B1 (en)
CN (2) CN101835866B (en)
TW (1) TWI419954B (en)
WO (1) WO2009069783A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5372665B2 (en) * 2009-08-31 2013-12-18 株式会社日立メディアエレクトロニクス Photo-curing adhesive, optical pickup device and manufacturing method thereof
JP5445187B2 (en) * 2010-02-05 2014-03-19 日立化成株式会社 Circuit member connecting adhesive and semiconductor device using the same
JP5415334B2 (en) * 2010-03-26 2014-02-12 ナミックス株式会社 Pre-feed type liquid semiconductor encapsulating resin composition
JP6043939B2 (en) * 2012-08-24 2016-12-14 ボンドテック株式会社 Method and apparatus for positioning an object on a substrate
JP6157890B2 (en) * 2013-03-26 2017-07-05 日東電工株式会社 Underfill material, sealing sheet, and method for manufacturing semiconductor device
JP2014203971A (en) * 2013-04-04 2014-10-27 日東電工株式会社 Underfill film, sealing sheet, method for manufacturing semiconductor device, and semiconductor device
JP2014074181A (en) * 2013-12-25 2014-04-24 Hitachi Chemical Co Ltd Manufacturing method of semiconductor device and semiconductor device manufactured thereby
CN104312471A (en) * 2014-11-10 2015-01-28 深圳市飞世尔实业有限公司 Anisotropic conductive film containing benzoxazine and preparation method of anisotropic conductive film

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117572A (en) * 1983-11-28 1985-06-25 日立化成工業株式会社 Method of connecting circuit
JP2698528B2 (en) * 1993-03-26 1998-01-19 日本碍子株式会社 Electrical insulator used for non-ceramic insulator housing
TW392179B (en) * 1996-02-08 2000-06-01 Asahi Chemical Ind Anisotropic conductive composition
JP2002371263A (en) 2001-06-14 2002-12-26 Nitto Denko Corp Adhesive composition for multilayer flexible printed circuit board and multilayer flexible printed circuit board obtained by using the same
KR20030001231A (en) * 2001-06-25 2003-01-06 텔레포스 주식회사 Anisotropic conductive adhesives having enhanced viscosity, bonding methods using the same and integrated cirduit pakages
JP2003073641A (en) * 2001-08-31 2003-03-12 Hitachi Chem Co Ltd Flame-retardant adhesive film, wiring board for mounting semiconductor, semiconductor and method for manufacturing the semiconductor device
JP2003206452A (en) * 2002-01-10 2003-07-22 Toray Ind Inc Adhesive composition for semiconductor device, adhesive sheet for semiconductor device using the same, substrates for connecting semiconductors and semiconductor device
JP4240460B2 (en) * 2003-03-06 2009-03-18 ソニーケミカル&インフォメーションデバイス株式会社 Adhesive, adhesive manufacturing method, and electrical apparatus
JP2006199778A (en) * 2005-01-19 2006-08-03 Hitachi Chem Co Ltd Adhesive composition, adhesive for use in circuit connection, method for connecting circuits using the same, and connected body
JP4993880B2 (en) * 2005-07-06 2012-08-08 旭化成イーマテリアルズ株式会社 Anisotropic conductive adhesive sheet and finely connected structure
JP2007091959A (en) * 2005-09-30 2007-04-12 Sumitomo Electric Ind Ltd Anisotropically conductive adhesive
CN101578698B (en) * 2007-01-10 2011-04-20 日立化成工业株式会社 Adhesive for connection of circuit member and semiconductor device using the same

Also Published As

Publication number Publication date
JPWO2009069783A1 (en) 2011-04-21
KR20100074312A (en) 2010-07-01
JP5088376B2 (en) 2012-12-05
WO2009069783A1 (en) 2009-06-04
TWI419954B (en) 2013-12-21
KR101302933B1 (en) 2013-09-06
CN101835866B (en) 2013-01-02
CN101835866A (en) 2010-09-15
CN102977809A (en) 2013-03-20

Similar Documents

Publication Publication Date Title
JP5487619B2 (en) Circuit member connecting adhesive and semiconductor device using the same
JP5573970B2 (en) Manufacturing method of semiconductor device
JP5557526B2 (en) Circuit member connecting adhesive and semiconductor device
TW200934851A (en) Circuit member connecting adhesive and semiconductor device
JP5224111B2 (en) Adhesive film for semiconductor wafer processing
JP2011080033A (en) Adhesive composition, adhesive sheet, and method of manufacturing semiconductor device
JP2011140617A (en) Adhesive composition for forming underfill, adhesive sheet for forming underfill, and method for manufacturing semiconductor device
JP2011006658A (en) Adhesive composition, adhesive sheet for connection of circuit member, and process for manufacture of semiconductor device
TWI425066B (en) Preparation method of adhesive composition, circuit board for connecting circuit member, and manufacturing method of semiconductor device
JP5263158B2 (en) Circuit member connecting adhesive and semiconductor device
TWI509043B (en) Adhesive composition, method for manufacturing connection of circuit member and semiconductor device
JP2010287835A (en) Method of manufacturing semiconductor circuit member
JP6222267B2 (en) Semiconductor device manufacturing method and semiconductor device manufactured using the same
JP5445187B2 (en) Circuit member connecting adhesive and semiconductor device using the same
JP2014074181A (en) Manufacturing method of semiconductor device and semiconductor device manufactured thereby

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees