TW200933925A - Packaging base and application and manufacturing method thereof - Google Patents

Packaging base and application and manufacturing method thereof Download PDF

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Publication number
TW200933925A
TW200933925A TW097103174A TW97103174A TW200933925A TW 200933925 A TW200933925 A TW 200933925A TW 097103174 A TW097103174 A TW 097103174A TW 97103174 A TW97103174 A TW 97103174A TW 200933925 A TW200933925 A TW 200933925A
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TW
Taiwan
Prior art keywords
dielectric layer
light
emitting diode
package
package base
Prior art date
Application number
TW097103174A
Other languages
Chinese (zh)
Inventor
Chung-Yuan Liu
Original Assignee
Chung-Yuan Liu
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chung-Yuan Liu filed Critical Chung-Yuan Liu
Priority to TW097103174A priority Critical patent/TW200933925A/en
Publication of TW200933925A publication Critical patent/TW200933925A/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

A packaging base, an application and a manufacturing method thereof are disclosed. The manufacturing method of the packaging base comprises: providing a metal plate; forming a dielectric layer on the surface of the metal plate; forming two electrode circuits on the dielectric layer; processing the metal plate to form a base body for receiving at least one light emitting diode (LED) chip. The packaging base is applicable to an LED packaging structure and an LED packaging module.

Description

200933925 九、發明說明: 【發明所屬之技術領域】 本發明是有關於一種封裝基座及其應用與製造方法, 且特別是有關於發光二極體之封裝基座及其應用與製造方 法。 【先前技術】 發光二極體(Light Emitting Diode ; LED)具有工作電壓 © 低,耗電量小,發光效率高,反應時間短,光色純,結構 牢固,抗衝擊,耐振動,性能穩定可靠,重量輕,體積小 及成本低等特點。隨著技術的進步,LED可展現的亮度等 級越來越高,其應用領域也越來越廣泛,例如:大面積圖 文顯示全彩屏,狀態指示、標誌照明、信號顯示、液晶顯 示器的背光源或車内照明。 習知的LED係以金屬導電支架(Lead Frame)配合塑料 射出成形方式製作出封裝基座。導電支架係用以電性連接 0 LED晶片之電極。封裝基座係以射出成形方式形成,藉以 使封裝材料包覆及固定住導電支架。封裝基座内形成一凹 口區域用以放置LED晶片。在LED晶片置入封裝基座内 後,接著,填入一透明封裝材料(例如環氧樹脂)於封裝基座 内,因而形成LED封裝結構。 然而,習知LED封裝結構中,由於一般封裝基座之材 料為塑膠,其並非為良好的熱導體,因而散熱效果不佳, 而需額外加設散熱片、散熱塊、散熱基板或散熱鰭片等散 熱單元來提散熱效果,導致整體成本增加。 200933925 【發明内容】 因此本發明之一方面係在於提供一種封裝基座及其應 用與製造方法,藉以一體成型金屬封裝基座,因而大幅地 提升散熱效果。 本發明之又一方面係在於提供一種封裝基座及其應用 與製造方法,藉以簡化封裝基座之製造方法,因而確保製 良率,提升生產效率。 © 根據本發明之實施例,本發明之封裝基座至少包含有 座體、介電層及二電極線路。座體具有至少一凹陷部,用 以容置至少一發光二極體晶片,其中座體係以金屬材料所 製成。介電層形成於座體之表面上,電極線路形成於介電 層上,用以電性連接於發光二極體晶片。 又,根據本發明之實施例,本發明之封裝基座的製造 方法至少包含:提供金屬基板;形成介電層於金屬基板的 表面上;形成電極線路於介電層上;以及藉由一體成型之 〇 方式來加工金屬基板,以形成座體,其中座體具有至少一 凹陷部,用以容置至少一發光二極體晶片。 又,根據本發明之實施例,上述封裝基座可應用於發 光二極體之封裝結構和封裝模組中。 又,根據本發明之實施例,上述封裝基座的製造方法 可應用於發光二極體之封裝結構和封裝模組的製造方法 中 〇 因此,本發明之發光二極體封裝結構和封裝模組的封 裝基座係以金屬材料來製成,因而大幅地提升散熱效果, 200933925 且具有易於加工、製程簡易及可大量製造之功效。再者, 金屬封裝基座可適用谭接方式來結合於印刷電路板 (Printed circuit board ; PCB)或散熱單元上。 【實施方式】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂’本說明書將特舉出一系列實施例來加以說 明。但值得注意的是’此些實施例只是用以說明本發明之 © 實施方式,而非用以限定本發明。 請參照第1圖和第2圖,第1圖係繪示依照本發明之 第一實施例之發光二極體封裝結構的剖面示意圖,第2圖 係繪示依照本發明之第一實施例之發光二極體封裝結構的 俯視示意圖。本實施例之封裝基座可應用於發光二極體之 封裝結構或封裝模組中,其中本實施例之發光二極體封裝 結構100至少包含有封裝基座n〇、發光二極體晶片12〇 及封膠體130。封裝基座110係一艎成型之方式來製成,用 〇 以谷置發光二極體晶片120,封膠體130係用以包覆並密封 住發光二極體晶片12〇。 如第1圖和第2圖所示,本實施例之封裝基座11〇至 少包含有座體111、介電層112及二電極線路113。座體lu 係以金屬材料所製成,例如:銅、金、銀、鐵、鋁或其合 金材料,因而具有良好導熱性,且較佳為具有高剛性和易 加工特性之的金屬材料,例如:銅或鋁。座體lu具有凹 陷部114和反射面115’凹陷部114例如係呈圓杯形凹陷結 構,用以容置發光二極體晶片12〇,並使發光二極體晶片 200933925 12〇的發光可由凹陷部U4的開口來射出。反射面ι15係一 體成型於凹陷部114的内周面,以反射發光二極體晶片12〇 的側向光。 如第1圖和第2圖所示’本實施例之封裝基座11〇的 介電層m係形成於座體⑴之表面上,較佳係以有機或 靡高介電常數材料來形成’例如:陶竟、樹脂材料、 有機玻璃纖維、氮化梦、氧化鋁、二氧化矽、聚亞酿胺 (P〇lyimide; PI)、高分子材料、切的氧化物、氮化物、金 © 屬氧化物或其上述材料之任意組合,藉以形成座體U1和 發光一極體晶片120之間的電性絕緣。介電層112之厚度 係實質介於5/zm和100 /zm之間,以確保介電層H2的電 性絕緣效果,且介電層112之厚度較佳係介於5以m和5〇 /im之間,以降低介電層112的熱阻抗,避免影響金屬座 體111的散熱效果。其中介電層112可利用沉積或塗佈 (Coating)的方式來形成,其形成方式例如:物理氣相沉積 技術(Physical Vapor Deposition ; PVD)、化學氣相沉積技術 〇 (Chemical Vapor Deposition ; CVD)、蒸鍍(Evaporation Deposition)、離子鍍(Ion Plating)、原子層沉積法(Atomic Layer Deposition.; ALD)、滅鍵(Sputtering Deposition)、印 刷塗佈(Printing)、滾輪塗佈(Roller Coating)、旋轉塗佈(spin coating)或喷塗(Spray Coating)。 值得注意的是,本實施例之介電層112可形成為預設 之顏色,較佳係屬淺色系,例如白色,以提升封裝基座110 之反射面115的光反射效果。再者,反射面115亦可塗佈 一高反射率材料,例如:Al、Ag、Cr、Mo、Ti、Pt、Pd、 200933925200933925 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a package base, an application and a method of fabricating the same, and more particularly to a package base for a light-emitting diode and a method of its application and manufacture. [Prior Art] Light Emitting Diode (LED) has low operating voltage ©, low power consumption, high luminous efficiency, short reaction time, pure light color, firm structure, impact resistance, vibration resistance, stable and reliable performance. Light weight, small size and low cost. With the advancement of technology, LEDs can display higher and higher brightness levels, and their application fields are more and more extensive, such as: large-area graphic display full color screen, status indication, logo illumination, signal display, backlight of liquid crystal display Or interior lighting. Conventional LEDs are fabricated with a metal conductive bracket (Lead Frame) in combination with plastic injection molding to form a package base. The conductive support is used to electrically connect the electrodes of the 0 LED chip. The package base is formed by injection molding, whereby the package material is wrapped and fixed to the conductive support. A recessed region is formed in the package base for placing the LED wafer. After the LED chip is placed in the package base, a transparent encapsulating material (e.g., epoxy) is then filled into the package base, thereby forming an LED package structure. However, in the conventional LED package structure, since the material of the general package base is plastic, it is not a good heat conductor, so the heat dissipation effect is not good, and an additional heat sink, heat sink block, heat dissipation substrate or heat sink fin is required. The heat dissipation unit is used to improve the heat dissipation effect, resulting in an increase in overall cost. SUMMARY OF THE INVENTION Accordingly, it is an aspect of the present invention to provide a package base, an application and a method of manufacturing the same, thereby integrally forming a metal package base, thereby greatly improving the heat dissipation effect. Still another aspect of the present invention is to provide a package base and an application and manufacturing method thereof, thereby simplifying the manufacturing method of the package base, thereby ensuring a yield and improving production efficiency. © In accordance with an embodiment of the present invention, a package base of the present invention includes at least a body, a dielectric layer, and a two-electrode line. The base has at least one recess for receiving at least one of the light-emitting diode wafers, wherein the seat system is made of a metal material. The dielectric layer is formed on the surface of the body, and the electrode lines are formed on the dielectric layer for electrically connecting to the LED substrate. Moreover, according to an embodiment of the present invention, a method of fabricating a package pedestal according to the present invention includes at least: providing a metal substrate; forming a dielectric layer on a surface of the metal substrate; forming an electrode line on the dielectric layer; and integrally molding The metal substrate is processed to form a base body, wherein the base body has at least one recessed portion for accommodating at least one light emitting diode wafer. Moreover, according to an embodiment of the invention, the package base can be applied to a package structure and a package module of a light-emitting diode. Moreover, according to the embodiment of the present invention, the manufacturing method of the package base can be applied to the package structure of the light emitting diode and the manufacturing method of the package module. Therefore, the light emitting diode package structure and the package module of the present invention The package base is made of a metal material, which greatly enhances the heat dissipation effect. It is easy to process, easy to process and can be mass-produced in 200933925. Furthermore, the metal package base can be used in a tandem manner to be bonded to a printed circuit board (PCB) or a heat sink unit. The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; However, it is to be understood that the embodiments are merely illustrative of the embodiments of the invention and are not intended to limit the invention. Referring to FIG. 1 and FIG. 2, FIG. 1 is a cross-sectional view showing a light emitting diode package structure according to a first embodiment of the present invention, and FIG. 2 is a first embodiment of the present invention. A schematic top view of a light emitting diode package structure. The packaged pedestal of the present embodiment can be applied to a package structure or a package module of a light-emitting diode. The light-emitting diode package structure 100 of the embodiment includes at least a package pedestal n 〇 and a light-emitting diode chip 12 . 〇 and sealant 130. The package pedestal 110 is formed by a method of forming a luminescent diode chip 120 for covering and sealing the LED chip 12A. As shown in Figs. 1 and 2, the package base 11 of the present embodiment includes at least a body 111, a dielectric layer 112, and a two-electrode line 113. The seat body is made of a metal material such as copper, gold, silver, iron, aluminum or an alloy thereof, and thus has good thermal conductivity, and is preferably a metal material having high rigidity and easy processing characteristics, for example, : Copper or aluminum. The recess lu has a recessed portion 114 and a reflective surface 115'. The recessed portion 114 is, for example, a cup-shaped recessed structure for accommodating the light-emitting diode wafer 12〇, and the light-emitting diode wafer 200933925 12〇 can be illuminated by the recess. The opening of the portion U4 is emitted. The reflecting surface ι15 is integrally formed on the inner peripheral surface of the depressed portion 114 to reflect the lateral light of the light-emitting diode wafer 12A. As shown in FIGS. 1 and 2, the dielectric layer m of the package base 11 of the present embodiment is formed on the surface of the base (1), preferably formed of an organic or germanium high dielectric constant material. For example: Tao Jing, resin materials, plexiglass, nitriding dreams, alumina, cerium oxide, polyphosphorus (P〇lyimide; PI), polymer materials, cut oxides, nitrides, gold © The oxide or any combination thereof is used to form electrical insulation between the body U1 and the light-emitting body wafer 120. The thickness of the dielectric layer 112 is substantially between 5/zm and 100/zm to ensure the electrical insulation effect of the dielectric layer H2, and the thickness of the dielectric layer 112 is preferably between 5 and 5 〇. Between /im, the thermal impedance of the dielectric layer 112 is lowered to avoid affecting the heat dissipation effect of the metal base 111. The dielectric layer 112 can be formed by deposition or coating in a manner such as: Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD). Evaporation Deposition, Ion Plating, Atomic Layer Deposition. (ALD), Sputtering Deposition, Printing, Roller Coating, Spin coating or spray coating. It should be noted that the dielectric layer 112 of the present embodiment may be formed in a predetermined color, preferably in a light color, such as white, to enhance the light reflection effect of the reflective surface 115 of the package base 110. Furthermore, the reflective surface 115 can also be coated with a high reflectivity material such as: Al, Ag, Cr, Mo, Ti, Pt, Pd, 200933925

Au、Ti〇2、Si〇2、AINd或上述材料之任意組合,藉以提升 反射面115的表面反射率》 如第1圖和第2圖所示,電極線路113係形成於介電 層112上,用以電性連接於發光二極體晶片120之電極, 並作為外部電性連接的路徑。電極線路113之材料較佳為 金屬材料’例如:銀、金、鉑、鈀、鎳、鎢、銅、鎮、氧 化鎘、錫、氧化錫、氧化銦錫(ITO)、鉬、銥、铑或其合金, 其形成方法例如為戳印(Stamping)、網印(Screen Printing)、 ❹ 點膠(Syringe Dispensing)、滾輪塗佈(Roller Coating)、物理 氣相沉積技術(Physical Vapor Deposition ; PVD)或半導體顯 影製程技術(Photolithography)。 在本實施例中,發光二極體晶片120可藉由晶粒黏著 劑來黏著於凹陷部114的底部’而電極線路113延伸形成 至凹陷部114的底部,並藉由銲線116(例如:金線、銀線、 銅線或鋁線)來電性連接發光二極體晶片120。然不限於 此,發光二極體晶片120亦可藉由共晶焊接或表面黏著 Q (SMD)的方式來電性連接於電極線路113。 如第1圖所示,本實施例之封膠體130的材質例如為: 環氧樹脂、PMMA、聚碳酸酯(Polycarbonate)或矽膠’用以 包覆並密封發光二極體晶片12〇和銲線116。 請參照第3A圖至第3E圖,其繪示依照本發明之第一 實施例之封裝基座的製程剖面圖。當製造本實施例之發光 二極體封裝結構100時’首先’提供封裝基座110。在本實 施例中,當製造封裝基座時’首先,提供一金屬基板 101,接著,形成介電層112於金屬基板101的表面上,接 200933925 著,形成電極線路113於介電層112上,在本實施例中, 可預先利用沉積或塗佈方式來形成一導電層1〇2(例如為銅 箔)於介電層112上,再利用半導體顯影製程技術來圖案化 (蝕刻)導電層102,而形成電極線路113。接著,藉由一館 成型之方式來加工金屬基板101,以形成座體111,並一體 形成凹陷部114和反射面115’其中座體ill例如係利用沖 壓、裁切、精密鑄造、鑄造、機械加工、壓鵠或锻造等一 體成型方式來形成,因而製成封裝基座110»然後,設置發 〇 光二極鳢晶片120於封裝基座110之凹陷部114的底部, 並使發光二極體晶片120與電極線路113形成電性連接。 接著,形成一封膠體130於封裝基座11〇上,以包覆並密 封發光二極體晶片120,因而形成發光二極體封裝結構1〇〇&lt;&gt; 因此,由於本實施例之發光二極體封裝結構10〇之封 裝基座110係以金屬材料所製成,故可具有良好的導熱效 果,且具有較大之散熱面積(可藉由整逋封裝基座11()來散 熱),因而可大幅地提升散熱效果,且金屬封裝基座11〇可 ❹ 適用於以焊接方式來結合於印刷電路板(Printed circuit board ; PCB)或散熱單元(散熱片、散熱塊、散熱基板或散 熱鰭片)上。再者,由於本實施例之封裝基座11〇可利用一 體成型之方式來形成,因而具有容易加工、製程簡易及可 大量製造之功效。 請參照第4A圖至第4D圖,其繪示依照本發明之第二 實施例之封裝基座的製程剖面囷。以下僅就本實施例與第 一實施例之相異處進行說明,關於相似處在此不再贅述。 相較於第一實施例’當製造第二實施例之發光二極體封裝 200933925 結構100的封裝基座110a時,金屬基板101可預先藉由一 體成型之方式來形成座體111,接著,再形成介電層112於 座體111(金屬基板101)的表面上,接著,形成電極線路 113(例如為銀膠)於介電層112上,因而形成第二實施例之 封裝基座ll〇a。 請參照第5圖,其繪示依照本發明之第三實施例之發 光二極體封裝模組的剖面示意圖。以下僅就本實施例與第 一實施例之相異處進行說明,關於相似處在此不再贅述。 © 相較於第一實施例,第三實施例之封裝基座110b可同時設 有複數個發光二極體晶片120b,因而形成一發光二極體封 裝模組100b。此時,封裝基座110b之座體111b具有複數 個凹陷部114b和複數個電極線路113b,以容置此些發光二 極體晶片120b。此些電極線路113b可個別連接於此些發光 二極體晶片120b;或者,此些電極線路113b之間可形成串 聯或並聯。 當製造本實施例之發光二極體封裝模組100b時,首 Q 先,提供封裝基座ll〇b。在本實施例中,當製造封裝基座 110時,首先,提供一金屬基板101,接著,形成介電層112 於金屬基板101的表面上,接著,形成電極線路113b於介 電層112上,接著,藉由一體成型之方式來加工金屬基板 101,以形成座體111b,因而製成封裝基座110b。值得注 意的是,金屬基板101亦可預先形成座體111b,再形成介 電層112和電極線路113b。且金屬座體111b可加工成任意 形狀,因而方便進行組裝和配置。然後,設置發光二極體 晶片120b於封裝基座ll〇b之凹陷部114b的底部,並使發 11 200933925 光二極鳢晶片120b與電極線路inb形成電性連接》接著, 分別形成封膠體130b於封裝基座11〇上,因而形成發光二 極體封裝模組l〇〇b。 由上述本發明的實施例可知,本發明之發光二極體封 裝結構和封裝模組的封裝基座可藉由金屬材料來一體成 型,因而可大幅地提升散熱效果,且易於加工,具有製程 簡易及可大量製造之功效。 雖然本發明已以實施例揭露如上,然其並非用以限定 本發明,任何熟習此技藝者’在不脫離本發明之精神和範 圍内,當可作各種之更動與潤飾,因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂,所附圖式之詳細說明如下: 第1圖係繪示依照本發明之第一實施例之發光二極體 封裝結構的剖面示意圖。 第2圖係續·示依照本發明之第一實施例之發光二極體 封裝結構的俯視示意囷。 第3A圖至第3E圓係繪示依照本發明之第一實施例之 封裝基座的製程剖面囷。 第4A圖至第4D囷係繪示依照本發明之第二實施例之 封裝基座的製程剖面圖。 第5圖係繪示依照本發明之第三實施例之發光二極體 封裝模組的剖面示意圖。 12 200933925 【主要元件符號說明】 102 :導電層 101 :金屬基板 1〇〇 :發光二極體封裝結構 100b:發光二極體封裝模組 111、111b :座體 113、113b :電極線路 115 :反射面 110、110a、ll〇b :封裝基座 112 :介電層 114、114b :凹陷部Au, Ti〇2, Si〇2, AINd, or any combination of the above materials, thereby enhancing the surface reflectance of the reflective surface 115. As shown in FIGS. 1 and 2, the electrode line 113 is formed on the dielectric layer 112. The electrode is electrically connected to the electrode of the LED chip 120 and serves as a path for external electrical connection. The material of the electrode line 113 is preferably a metal material 'for example: silver, gold, platinum, palladium, nickel, tungsten, copper, town, cadmium oxide, tin, tin oxide, indium tin oxide (ITO), molybdenum, niobium, tantalum or The alloy is formed by, for example, Stamping, Screen Printing, Syringe Dispensing, Roller Coating, Physical Vapor Deposition (PVD) or Semiconductor development process technology (Photolithography). In the present embodiment, the LED wafer 120 can be adhered to the bottom portion of the recess portion 114 by a die attaching agent, and the electrode line 113 is extended to the bottom of the recess portion 114 by the bonding wire 116 (for example: The gold wire, the silver wire, the copper wire or the aluminum wire) is electrically connected to the light emitting diode chip 120. However, the light-emitting diode chip 120 may be electrically connected to the electrode line 113 by eutectic soldering or surface adhesion Q (SMD). As shown in FIG. 1 , the material of the encapsulant 130 of the present embodiment is, for example, epoxy resin, PMMA, polycarbonate or silicone rubber for coating and sealing the LED wafer 12 and the bonding wire. 116. Referring to Figures 3A through 3E, there are shown process cross-sectional views of a package pedestal in accordance with a first embodiment of the present invention. The package base 110 is 'first' provided when the light emitting diode package structure 100 of the present embodiment is fabricated. In the present embodiment, when the package base is manufactured, 'first, a metal substrate 101 is provided, and then a dielectric layer 112 is formed on the surface of the metal substrate 101, and is connected to 200933925 to form an electrode line 113 on the dielectric layer 112. In this embodiment, a conductive layer 1 2 (for example, a copper foil) may be formed on the dielectric layer 112 by deposition or coating, and the conductive layer may be patterned (etched) by a semiconductor developing process technology. 102, and the electrode line 113 is formed. Next, the metal substrate 101 is processed by a molding process to form the seat body 111, and the recessed portion 114 and the reflecting surface 115' are integrally formed. The seat body ill is, for example, stamped, cut, precision cast, cast, mechanical. Formed by integral molding such as processing, pressing or forging, thereby forming the package base 110», then, the hair-emitting diode wafer 120 is disposed at the bottom of the recess 114 of the package base 110, and the light-emitting diode wafer is formed. 120 is electrically connected to the electrode line 113. Next, a colloid 130 is formed on the package base 11 to cover and seal the LED wafer 120, thereby forming a light emitting diode package structure. < </ RTI> Therefore, the illuminating light of the embodiment The package base 110 of the diode package structure is made of a metal material, so that it has good heat conduction effect and has a large heat dissipation area (which can be dissipated by the entire package base 11 ()) Therefore, the heat dissipation effect can be greatly improved, and the metal package base 11 can be used for soldering to a printed circuit board (PCB) or a heat dissipation unit (heat sink, heat sink, heat sink, or heat sink). Fin). Furthermore, since the package base 11 of the present embodiment can be formed by integral molding, it has the advantages of easy processing, simple process, and mass production. Referring to Figures 4A through 4D, there is shown a process section 封装 of a package pedestal in accordance with a second embodiment of the present invention. In the following, only the differences between the embodiment and the first embodiment will be described, and the similarities will not be described herein. Compared with the first embodiment, when the package base 110a of the light-emitting diode package 200933925 structure 100 of the second embodiment is manufactured, the metal substrate 101 can be formed into a body 111 in advance by integral molding, and then, A dielectric layer 112 is formed on the surface of the body 111 (metal substrate 101), and then an electrode line 113 (for example, silver paste) is formed on the dielectric layer 112, thereby forming the package base 11a of the second embodiment. . Referring to FIG. 5, a cross-sectional view of a light emitting diode package module according to a third embodiment of the present invention is shown. In the following, only the differences between the embodiment and the first embodiment will be described, and the similarities will not be described herein. The package base 110b of the third embodiment can be provided with a plurality of light-emitting diode chips 120b at the same time, thereby forming a light-emitting diode package module 100b. At this time, the base 111b of the package base 110b has a plurality of recessed portions 114b and a plurality of electrode lines 113b for accommodating the light-emitting diode wafers 120b. The electrode lines 113b may be individually connected to the light emitting diode chips 120b; or, the electrode lines 113b may be formed in series or in parallel. When the light emitting diode package module 100b of the present embodiment is manufactured, the first Q first provides the package base 11b. In the present embodiment, when the package base 110 is manufactured, first, a metal substrate 101 is provided, then a dielectric layer 112 is formed on the surface of the metal substrate 101, and then an electrode line 113b is formed on the dielectric layer 112. Next, the metal substrate 101 is processed by integral molding to form the seat body 111b, thereby forming the package base 110b. It is to be noted that the metal substrate 101 may be formed in advance with the body 111b, and the dielectric layer 112 and the electrode line 113b may be formed. Moreover, the metal seat body 111b can be processed into any shape, thereby facilitating assembly and configuration. Then, the LED body 120b is disposed on the bottom of the recess portion 114b of the package base 11b, and electrically connects the electrode 11200933925 photodiode wafer 120b to the electrode line inb. Then, the encapsulant 130b is formed respectively. The package base 11 is mounted thereon, thereby forming a light emitting diode package module 10b. According to the embodiment of the present invention, the package structure of the LED package structure and the package module of the present invention can be integrally formed by a metal material, thereby greatly improving the heat dissipation effect, and is easy to process, and has a simple process. And the effect of mass production. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the skilled in the art can make various modifications and retouchings without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; A schematic cross-sectional view of a light emitting diode package structure. Fig. 2 is a plan view showing the outline of a light emitting diode package according to a first embodiment of the present invention. 3A to 3E are diagrams showing a process profile of the package base in accordance with the first embodiment of the present invention. 4A to 4D are cross-sectional views showing the process of the package base in accordance with the second embodiment of the present invention. Figure 5 is a cross-sectional view showing a light emitting diode package module in accordance with a third embodiment of the present invention. 12 200933925 [Description of main component symbols] 102: Conductive layer 101: Metal substrate 1〇〇: Light-emitting diode package structure 100b: Light-emitting diode package module 111, 111b: Seat 113, 113b: Electrode line 115: Reflection Faces 110, 110a, 11〇b: package base 112: dielectric layers 114, 114b: recesses

116 :銲線 120、120b :發光二極體晶片 130 :封膠體 〇 13116: bonding wire 120, 120b: light emitting diode chip 130: sealing body 〇 13

Claims (1)

200933925 十、申請專利範園: 1. 一種封裝基座,至少包含: 一座體,具有至少一凹陷部,用以容置至少一發光二 極體晶片,其中該座體係以金屬材料所製成; 一介電層’形成於該座體之表面上;以及 二電極線路,形成於該介電層上,用以電性連接於該 發光二極體晶片。 ® 2·如申請專利範圍第1項所述之封裝基座,其中該座 體之材料係選自由銅、金、銀、鐵、鋁及其合金所組成之 一族群。 3. 如申請專利範圍第1項所述之封裝基座,更至少包 含: 一反射面’形成於該凹陷部的内周面,用以反射該發 光二極體晶片之側向光。 4. 如申請專利範圍第1項所述之封裝基座,其中該介 電層以有機高介電常數材料來形成。 5·如申請專利範圍第1項所述之封裝基座,其中該介 電層以無機高介電常數材料來形成。 6.如申請專利範圍第1項所述之封裝基座,其中該介 200933925 電層之材料係選自由陶瓷、樹脂材料、有機玻璃纖維、氮 化矽、氧化鋁、二氧化矽、聚亞醯胺(p〇lyimide; ρι)、高分 子材料、含矽的氧化物、氮化物及金屬氧化物所組成之一 族群。 7. 如申請專利範圍第!項所述之封裝基座,其中該介 電層之厚度係實質介於5em和l〇〇#m之間。 8. 如申請專利範園第7項所述之封裝基座,其中該介 電層之厚度係實質介於5/zm和50从m之間。 9. 如申請專利範圍第丨項所述之封裝基座,其中該電 極線路之材料係選自由銀、金、鉑、鈀、鎳、鎢、銅、鎘、 氧化鎘、錫、氧化錫、氧化銦錫(IT〇)、鉬、銥、铑及其合 金所組成之一族群》 10. —種封裝基座的製造方法,至少包含: 提供一金屬基板; 形成一介電層於該金屬基板的表面上; 形成二電極線路於該介電層上;以及 藉由一體成型之方式來加工該金屬基板,以形成一座 體’其中該座體具有至少一凹陷部,用以容置至少一發光 一極體晶片》 11.如申請專利範圍第10項所述之封裝基座的製造方 15 200933925 法,其中該形成該介電層之步驟係利用沉積或塗佈(Coating) 的方式來形成。 12.如申請專利範圍第11項所述之封裝基座的製造方 法,其中該介電層之形成方式係選自由物理氣相沉積技術 (Physical Vapor Deposition ; PVD)、化學氣相沉積技術 (Chemical Vapor Deposition ; CVD)、蒸鍍(Evaporation Deposition)、離子鑛(Ion Plating)、原子層沉積法(Atomic ❹ Layer Deposition ; ALD)、減鍵(Sputtering Deposition)、印 刷塗佈(Printing)、滾輪塗佈(Roller Coating)、旋轉塗佈(spin coating)及喷塗(Spray Coating)所組成之一族群。 13.如申請專利範圍第10項所述之封裝基座的製造方 法,其中該電極線路之形成方式係選自由戳印(Stamping)、 網印(Screen Printing)、點膠(Syringe Dispensing)、滾輪塗 佈(Roller Coating)、物理氣相沉積技術(Physicar Vapor Deposition; PVD)及半導體顯影製程技術(Photolithography) 所組成之一族群。 14·如申請專利範圍第10項所述之封裝基座的製造方 法,其中該座體之形成方式係選自由沖壓、裁切、精密鑄 造、鑄造、機械加工、壓鑄及鍛造所組成之一族群。 15.如申請專利範圍第1〇項所述之封裝基座的製造方 法,其中該藉由一體成型之方式來加工該金屬基板的步驟 16 200933925 係進行在該形成該些電極線路步驟之後。 16. 如申請專利範圍第10項所述之封裝基座的製造方 法’其中該藉由一體成型之方式來加工該金屬基板的少驟 係進行在該形成該介電層步驟之前0 17. 如申請專利範圍第1〇項所述之封裝基座的製造方 法’其中該形成該些電極線路的步驟至少包含: 形成一導電層於該介電層上;以及 圖案化該導電層,以形成該些電極線路。 18. —種發光二極體之封裝結構,至少包含: 一封裝基座,至少包含: 一座體,具有一凹陷部,其中該座體係以金屬材 料所製成; 一介電層,形成於該座艎之表面上;以及 二電極線路,形成於該介電層上; 一發光二極體晶片’容置於該凹陷部内’並與該些電 極線路形成電性連接;以及 一封膠艘’包覆並密封該發光二極體晶片。 19. 如申請專利範圍第18項所述之發光二極體的封裝 結構,其中該座體之材料係選自由銅、金、銀、鐵、鋁及 其合金所組成之一族群。 17 200933925 20. 如申請專利範圍第18項所述之發光二極體的封装 結構,其中該封裝基座更至少包含: 一反射面,形成於該凹陷部的内周面,用以反射該發 光二極體晶片之侧向光。 21. 如申請專利範圍第18項所述之發光二極鱧的封裝 結構,其中該介電層以有機高介電常數材料來形成。 22. 如申請專利範圍第18項所述之發光二極體的封裝 結構,其中該介電層以無機高介電常數材料來形成。 23. 如申請專利範圍第18項所述之發光二極體的封裝 結構,其中該介電層之材料係選自由陶瓷、樹脂材料、有 機玻璃纖維、氮化矽、氧化鋁、二氧化矽、聚亞醯胺 (Polyimide; PI)、高分子材料、含矽的氧化物、氮化物及金 屬氧化物所組成之一族群。 24. 如申請專利範圍第18項所述之發光二極體的封裝 結構,其中該介電層之厚度係實質介於5#m和l〇〇#m2 間。 25. 如申請專利範圍第24項所述之發光二極體的封裝 結構’其中該介電層之厚度係實質介於5〇em之 間。 18 200933925 26. 如申請專利範圍第18項所述之發光二極體的封裝 結構,其中該電極線路之材料係選自由銀、金、鉑、鈀、 鎳、鶴、銅、録、氧化锡、錫、氧化錫、氧化銦錫(ITO)、 翻、銀、姥及其合金所組成之一族群。 27. 如申請專利範圍第18項所述之發光二極體的封裝 結構,其中該些電極線路係藉由二銲線來分別電性連接於 該發光二極體晶片。 ❹ ❹ 28. 如申請專利範圍第18項所述之發光二極體的封裝 結構,其中該封膠體的材質為環氧樹脂、PMMA、聚碳酸 醋(Polycarbonate)或石夕膠。 29. —種發光二極體之封裝結構的製造方法,至少包 含: 提供一封裝基座,其中該提供該封裝基座的步驟至少 包含: 提供一金屬基板; 形成一介電層於該金屬基板的表面上; 形成二電極線路於該介電層上;以及 藉由一體成型之方式來加工該金屬基板,以形成 一座體,其中該座體具有一凹陷部; 設置一發光二極體晶片於該封裝基座的該凹陷部内, 並與該些電極線路形成電性連接;以及 形成一封膠體於該封裝基座上,用以包覆並密封該發 19 200933925 光二極體晶片。 30. 如申請專利範圍第29項所述之封裝結構的製造方 法,其中該形成該介電層之步驟係利用沉積或塗佈(Coating) 的方式來形成。 31. 如申請專利範圍第29項所述之封裝結構的製造方 法,其中該介電層之形成方式係選自由物理氣相沉積技術 0 (Physical Vapor Deposition ; PVD)、化學氣相沉積技術 (Chemical Vapor Deposition ; CVD)、蒸鍵(Evaporation Deposition)、離子锻(Ion Plating)、原子層沉積法(Atomic Layer Deposition ; ALD)、減鑛(Sputtering Deposition)、印 刷塗佈(Printing)、滾輪塗佈(Roller Coating)、旋轉塗佈(spin coating)及喷塗(Spray Coating)所組成之一族群。 32. 如申請專利範圍第29項所述之封裝結構的製造方 法,其中該電極線路之形成方式係選自由戳印(Stamping)、 網印(Screen Printing)、點膠(Syringe Dispensing)、滾輪塗 佈(Roller Coating)、物理氣相沉積技術(Physical Vapor Deposition ; PVD)及半導體顯影製程技術(Photolithography) 所組成之一族群。 33. 如申請專利範圍第29項所述之封裝結構的製造方 法,其中該座體之形成方式係選自由沖壓、裁切、精密鑄 造、鑄造、機械加工、壓鑄及鍛造所組成之一族群。 20 200933925 34. 如_請專利範園第29項所述之封裝結構的製造方 法、其中該藉由一體成型之方式來加工該金屬基板的步驟 係進行在該形成該些電極線路步驟之後。 35. 如申請專利範圍第29項所述之封裝結構的製造方 法’其中該藉由-體成狀方式來加工該金屬絲的步驟 係進行在該形成該介電層步驟之前。 36. 如申請專利範圍第29項所述之封裝結構的製造方 法’其中該形成該些電極線路的步驟至少包含: 形成一導電層於該介電層上;以及 圖案化該導電層,以形成該些電極線路。 37. —種發光二極趙封裝模組,至少包含·· 一封裝基座,至少包含: 〇 一座體,具有複數個凹陷部,其令該座體係以金 屬材料所製成; 一介電層,形成於該座體之表面上;以及 複數個電極線路,形成於該介電層上; 複數個發光二極髏晶片,分別容置於該些凹陷部内, 並與該些電極線路形成電性連接;以及 複數個封膠體,包覆並密封該些發光二極體晶片。 38. —種發光二極體封裝模組至少包含: 21 200933925 提供一封裝基座,其中該提供該封裝基座的步驟至少 包含: 提供一金屬基板; 形成一介電層於該金屬基板的表面上; 形成複數個電極線路於該介電層上;以及 藉由一體成型之方式來加工該金屬基板,以形成 一座體,其中該座體具有複數個凹陷部; 分別設置複數個發光二極體晶片於該封裝基座的該些 ❹ 凹陷部内,並與該些電極線路形成電性連接;以及 形成複數個封膠體於該封裝基座上,用以包覆並密封 該發光二極體晶片》200933925 X. Patent application: 1. A package base comprising at least: a body having at least one recess for receiving at least one LED chip, wherein the system is made of a metal material; A dielectric layer is formed on the surface of the body; and a two-electrode line is formed on the dielectric layer for electrically connecting to the LED chip. The package base of claim 1, wherein the material of the seat is selected from the group consisting of copper, gold, silver, iron, aluminum, and alloys thereof. 3. The package base of claim 1, further comprising: a reflective surface formed on an inner peripheral surface of the recess for reflecting lateral light of the light-emitting diode chip. 4. The package base of claim 1, wherein the dielectric layer is formed of an organic high dielectric constant material. 5. The package base of claim 1, wherein the dielectric layer is formed of an inorganic high dielectric constant material. 6. The package base according to claim 1, wherein the material of the 200933925 electrical layer is selected from the group consisting of ceramics, resin materials, plexiglass fibers, tantalum nitride, aluminum oxide, cerium oxide, polythene. A group of amines (p〇lyimide; ρι), polymer materials, cerium-containing oxides, nitrides, and metal oxides. 7. If you apply for a patent scope! The package base of the item, wherein the thickness of the dielectric layer is substantially between 5em and 10m. 8. The package base of claim 7, wherein the thickness of the dielectric layer is substantially between 5/zm and 50. 9. The package base of claim 2, wherein the material of the electrode line is selected from the group consisting of silver, gold, platinum, palladium, nickel, tungsten, copper, cadmium, cadmium oxide, tin, tin oxide, oxidation. A group consisting of indium tin (IT〇), molybdenum, niobium, tantalum and alloys thereof. 10. A method for manufacturing a package base, comprising at least: providing a metal substrate; forming a dielectric layer on the metal substrate Forming a two-electrode line on the dielectric layer; and processing the metal substrate by integral molding to form a body, wherein the body has at least one recess for accommodating at least one light-emitting The method of manufacturing a package base according to claim 10, wherein the step of forming the dielectric layer is formed by deposition or coating. 12. The method of manufacturing a package pedestal according to claim 11, wherein the dielectric layer is formed by a physical vapor deposition (PVD) or a chemical vapor deposition technique (Chemical). Vapor Deposition; CVD), evaporation deposition, Ion Plating, Atomic ❹ Layer Deposition (ALD), Sputtering Deposition, Printing, Roller Coating (Roller Coating), spin coating and spray coating. 13. The method of manufacturing a package base according to claim 10, wherein the electrode line is formed by stamping, screen printing, Syringe Dispensing, and a roller. A group consisting of Roller Coating, Physical Vapor Deposition (PVD) and Photolithography. The method of manufacturing a package base according to claim 10, wherein the seat body is formed by a group consisting of stamping, cutting, precision casting, casting, machining, die casting, and forging. . 15. The method of manufacturing a package base according to claim 1, wherein the step of processing the metal substrate by integral molding is performed after the step of forming the electrode lines. 16. The method of manufacturing a package base according to claim 10, wherein the process of processing the metal substrate by integral molding is performed before the step of forming the dielectric layer. The method for manufacturing a package base according to the first aspect of the invention, wherein the forming the electrode lines comprises at least: forming a conductive layer on the dielectric layer; and patterning the conductive layer to form the Some electrode lines. 18. The package structure of a light-emitting diode, comprising at least: a package base comprising at least: a body having a recess, wherein the base system is made of a metal material; a dielectric layer formed on the And a two-electrode line formed on the dielectric layer; a light-emitting diode chip 'accepted in the recess' and electrically connected to the electrode lines; and a plastic boat The light emitting diode wafer is coated and sealed. 19. The package structure of a light-emitting diode according to claim 18, wherein the material of the body is selected from the group consisting of copper, gold, silver, iron, aluminum and alloys thereof. The package structure of the light-emitting diode according to claim 18, wherein the package base further comprises: a reflective surface formed on an inner peripheral surface of the recess for reflecting the light Lateral light from a diode wafer. 21. The package structure of a light-emitting diode according to claim 18, wherein the dielectric layer is formed of an organic high dielectric constant material. 22. The package structure of a light-emitting diode according to claim 18, wherein the dielectric layer is formed of an inorganic high dielectric constant material. 23. The package structure of the light-emitting diode according to claim 18, wherein the material of the dielectric layer is selected from the group consisting of ceramics, resin materials, plexiglass fibers, tantalum nitride, aluminum oxide, cerium oxide, A group consisting of polyimide (PI), polymer materials, cerium-containing oxides, nitrides, and metal oxides. 24. The package structure of a light-emitting diode according to claim 18, wherein the thickness of the dielectric layer is substantially between 5#m and l〇〇#m2. 25. The package structure of the light-emitting diode according to claim 24, wherein the thickness of the dielectric layer is substantially between 5 〇em. The package structure of the light-emitting diode according to claim 18, wherein the material of the electrode line is selected from the group consisting of silver, gold, platinum, palladium, nickel, crane, copper, nickel, tin oxide, A group of tin, tin oxide, indium tin oxide (ITO), tumbling, silver, antimony and alloys thereof. 27. The package structure of the light-emitting diode of claim 18, wherein the electrode lines are electrically connected to the light-emitting diode chip by two bonding wires, respectively.封装 ❹ 28. The package structure of the light-emitting diode according to claim 18, wherein the sealant is made of epoxy resin, PMMA, polycarbonate or terracotta. 29. The method of fabricating a package structure of a light emitting diode, comprising: providing a package base, wherein the step of providing the package base comprises at least: providing a metal substrate; forming a dielectric layer on the metal substrate Forming a two-electrode line on the dielectric layer; and processing the metal substrate by integral molding to form a body, wherein the body has a recess; and providing a light-emitting diode chip The recessed portion of the package base is electrically connected to the electrode lines; and a glue is formed on the package base to cover and seal the hair 19 200933925 photodiode wafer. 30. The method of fabricating a package structure according to claim 29, wherein the step of forming the dielectric layer is formed by deposition or coating. The method of manufacturing a package structure according to claim 29, wherein the dielectric layer is formed by a physical vapor deposition technique (PVD) or a chemical vapor deposition technique (Chemical Vapor Deposition; PVD). Vapor Deposition; CVD), evaporation deposition, Ion Plating, Atomic Layer Deposition (ALD), Sputtering Deposition, Printing, Roller Coating ( Roller Coating), spin coating and spray coating. 32. The method of manufacturing a package structure according to claim 29, wherein the electrode line is formed by stamping, screen printing, Syringe Dispensing, roller coating. A group consisting of Roller Coating, Physical Vapor Deposition (PVD) and Photolithography. 33. The method of fabricating a package structure according to claim 29, wherein the body is formed in a group selected from the group consisting of stamping, cutting, precision casting, casting, machining, die casting, and forging. 20 200933925 34. The method of manufacturing a package structure as described in claim 29, wherein the step of processing the metal substrate by integral molding is performed after the step of forming the electrode lines. 35. A method of fabricating a package structure as described in claim 29, wherein the step of processing the wire by the body-forming method is performed prior to the step of forming the dielectric layer. 36. The method of fabricating a package structure according to claim 29, wherein the step of forming the electrode lines comprises at least: forming a conductive layer on the dielectric layer; and patterning the conductive layer to form The electrode lines. 37. A light-emitting diode package module comprising at least one package base, comprising at least: a body having a plurality of recesses, the base system being made of a metal material; a layer formed on the surface of the body; and a plurality of electrode lines formed on the dielectric layer; a plurality of light-emitting diode chips respectively received in the recesses and electrically formed with the electrode lines And a plurality of encapsulants for coating and sealing the LED chips. 38. A light emitting diode package module comprising: 21 200933925 providing a package base, wherein the step of providing the package base comprises at least: providing a metal substrate; forming a dielectric layer on a surface of the metal substrate Forming a plurality of electrode lines on the dielectric layer; and processing the metal substrate by integral molding to form a body, wherein the body has a plurality of depressed portions; respectively, a plurality of light emitting diodes are respectively disposed Was in the recessed portion of the package base and electrically connected to the electrode lines; and forming a plurality of sealants on the package base for covering and sealing the light emitting diode chip
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI397990B (en) * 2010-05-04 2013-06-01 Lite On Electronics Guangzhou Led module and led lamp

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI397990B (en) * 2010-05-04 2013-06-01 Lite On Electronics Guangzhou Led module and led lamp

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