16 25790twf.doc/n 200933888 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體電路晶片。 【先前技術】 ♦κ 向雙擴散金氧半導體(laterally double-diffused metal oxide semiconductor ’ LDM0S)是半導體製程中廣為使用的 ❹一種電源元件。ldmos可提供較高的崩潰電壓(Vbd)，並 且在插作時可具有低的接通電阻(〇n_resistance，尺。^)，因 此’常用作為電源管理IC(power management 1C)中的高壓 元件。互補式金氧半導體-橫向擴散金氧半導體_雙載子元 件製程(CMOS-DMOS-Bipolar，CDMOS process)以及 HV LDMOS類比製程’即是電源管理汇普遍採用的製程平台。 隨著電子產品高度類比化和輕薄短小的趨勢，對於電 壓的精準度、穩定度與電池續航力的要求不斷提高，電源 管理IC(power management 1C)的角色因而與日倶增。通 © 常’電源管理1C中需要各種額定電壓不同的高壓元件。然 而，在典型的半導體廠中，單一的LDMOS製程僅能提供 單一種額定電壓的高壓元件，即每一種額定電壓的高壓元 件必須以一 1C來為之。故，若典型的電源管理IC需要使 用不同額定電壓之元件，則必須有不同的1C來滿足需求， 因此尺寸較大且成本較高。 另一方面，LDMOS還可用作開關元件與類比元件。 然而’通常’開關元件僅需在瞬間產生足夠的電流即可達 6 200933888 16 25790twf.doc/n 到開啟的目的。而類t卜元4 以避免造成誤判。由‘ 長時間具有穩定的電壓 不相同，因此，在兀:與類比元件的特性需求並 關兀件或類比元件的特性需求來製作，而益法同 滿足開關元件與類比元件兩者之特性的ldm〇s。、I作出 綜上所述’受顺__ ❹ 需求或單-種額定電壓== 會靖㈣晶片面積， 【發明内容】 本發明提供-種積體電路晶片，可 電壓之元件(她age rating device)。 /、有額疋 本發明提供一種積體電路晶片，可同時具有開關 LDMOS元件以及類比LDM〇s元件。 、，開關 ❹ 本發明提供-種積體電路晶片，其包括多個具有不同 額定電㈣LDM〇S元件，錄具有第—導電型之基底 上，各LDMOS元件的組成構件相同且分別包括二閉極導 電層，分別位於上述基底的二第一主動區上。具有第二導 電型之共用汲極接觸區，位於第二主動主區中，第二主動 主區位於上述多個第-主動區之間。此外，還包括一隔離 結構，分隔上述第二主動主區與上述多個第一主動區。各 第一主動區與上述第二主動區之間的隔離結構在沿著各閘 極導電層下方之通道的通道長度方向上的長度為A，且位 7 200933888 16 25790twf.doc/n 於各第 诵、首具之各閘極導電層在沿著上述通道之上述16 25790 twf.doc/n 200933888 IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit chip. [Prior Art] ♦ A laterally double-diffused metal oxide semiconductor (LDM0S) is a power supply element widely used in semiconductor processes. The ldmos provides a high breakdown voltage (Vbd) and can have a low on-resistance (〇n_resistance, ft.^) when plugged in, so it is commonly used as a high voltage component in power management 1C. Complementary MOS-transverse-diffused MOS semiconductors (CMOS-DMOS-Bipolar, CDMOS process) and HV LDMOS analog process are the commonly used process platforms for power management. With the trend toward high analogization and lightness and thinness of electronic products, the requirements for voltage accuracy, stability and battery life continue to increase, and the role of power management ICs is increasing. Passing © Of the 'Power Management 1C' requires high voltage components with different rated voltages. However, in a typical semiconductor factory, a single LDMOS process can only provide a single high-voltage component of rated voltage, that is, a high-voltage component of each rated voltage must be a 1C. Therefore, if a typical power management IC needs to use components with different rated voltages, different 1Cs must be used to meet the demand, so the size is large and the cost is high. On the other hand, LDMOS can also be used as a switching element and an analog element. However, the 'normal' switching element only needs to generate enough current in an instant to reach the purpose of opening the 2009 33888 16 25790twf.doc/n. And class t element 4 to avoid causing misjudgment. The voltages that are stable over a long period of time are not the same, and therefore, they are made with the characteristic requirements of the analog components and the characteristic requirements of the components or analog components, and the benefits are the same as those of the switching components and the analog components. Ldm〇s. I, in summary, the 'received __ ❹ demand or single-type rated voltage == Huijing (four) wafer area, [invention] The present invention provides an integrated circuit chip, voltage components (herage rating Device). The present invention provides an integrated circuit chip which can have both a switching LDMOS device and an analog LDM 〇 s device. The present invention provides an integrated circuit chip comprising a plurality of different rated (four) LDM(R) S elements on a substrate having a first conductivity type, each of the LDMOS elements having the same constituent members and respectively including two closed ends Conductive layers are respectively located on the two first active regions of the substrate. A common drain contact region having a second conductivity type is located in the second active main region, and the second active main region is located between the plurality of first active regions. In addition, an isolation structure is further included to partition the second active main area and the plurality of first active areas. The length of the isolation structure between each of the first active region and the second active region in the channel length direction of the channel below each gate conductive layer is A, and the bit is 7 200933888 16 25790twf.doc/n诵, the first of each of the gate conductive layers is along the above-mentioned channel
通道長度方向上的長度為L，各LD]Vir^ - μ 值。 LUMOS几件具有不同A7L 依照本發明實施例所述，上述之積 元件還包括具有第二導電型之深井區 ί個第第二導電型之二源極接觸區，分別位於上述 ❹ ❹ 八別t °具有第二導電型之二淡摻雜源極區， 刀別位於上述多個第—絲區中，與 電性連接。呈有第一導雷剞夕_ 1 Μ 、夕似彝極接觸& -主I體區’位於上述多個第 極述源極接觸區與上述多個淡摻雜源 。具有—第二導電型之二漂移區，分別環繞於各 區與上述第二主祕之_上義離結構的下方 周圍，與上述汲極接觸區電性連接。二閘極介電層， 位於各閘極導電層與各第—主動區之I此外，各閑極導 電層之一部份與部分各基體區電容耦合，各定義出上述通 道區，且分別延伸至上述隔離結構上彼此電性連接。 依照本發明實施例所述，上述之積體電路晶片中，上 述多個LDMOS元件均為LDNMOS元件，第一導電型為p 型；第二導電型為N型。 ” 依照本發明實施例所述，上述之積體電路晶片中，上 述多個LDMOS元件均為LDPMOS元件，第一導電型為^^ 型；第二導電型為p型。 依照本發明實施例所述’上述之積體電路晶片中，上 述多個LDMOS元件中至少其一是LDNMOS元件，上述 8 16 25790twf.doc/n 200933888 ;第二導電型為N 是LDPM0S元件， 丨；第二導電型為p LDNMOS元件中之第一導電型為p型； 型。上述多個LDM0S元件中至少另—是 LDPMOS元件中之第一導電型為N型； 型。 依照本發明實施例所述 CMOS元件。 依照本發明實施例所述 包括雙載子元件。 上述之積體電路晶片更包括 上述之積體電路晶片中，更 依照本發明實施例所述，上述之積體電路晶片中，上 述多個A/L值的範圍在（u至2之間，但視不同的製程世 代及元件的額定電壓，A/L值可不限於此。 依照本發明實施例所述，上述之積體電 述隔離結構為場隔離結構或淺溝渠隔離結構。 本發明提出一種積體電路晶片，其包括開關LDM〇s 元件以及類比LDMOS元件，位於具有第一導電型之基底 上。開關LDMOS元件以及類比LDMOS元件二者的組成 ❹構件相同且分別包括二閘極導電層，分別位於上述基底的 二第一主動區上。具有第二導電型之共用汲極接觸區，位 於第二主動主區中，第二主動主區位於上述多個第一主動 區之間。此外’還包括一隔離結構，分隔上述第二主動主 區與上述多個第一主動區。各第一主動區與上述第二主動 區之間的上述隔離結構在沿著各閘極導電層下方之通道的 通道長度方向上的長度為A，且位於各第一主動區上之各 閘極導電層在沿著上述通道之上述通道長度方向上的長度 16 25790twf.doc/n 200933888The length in the length direction of the channel is L, and each LD]Vir^ - μ value. According to an embodiment of the present invention, the above-mentioned integrated component further includes a second well contact region having a second conductivity type, and a second source contact region of the second conductivity type, respectively located at the above-mentioned ❹ 八 八The second lightly doped source region of the second conductivity type is located in the plurality of first filament regions and electrically connected. The first lead _ 1 Μ , the 彝 彝 彝 contact & - the main I body region ′ is located in the plurality of first pole source contact regions and the plurality of lightly doped sources. The two drift regions having a second conductivity type are respectively connected around the respective regions and the lower portion of the second main structure, and are electrically connected to the drain contact regions. The second gate dielectric layer is located at each gate conductive layer and each of the first active regions. Further, one of the idler conductive layers is capacitively coupled with a portion of each of the base regions, and each of the channel regions is defined and extended respectively. Electrically connected to each other to the above isolation structure. According to the embodiment of the invention, in the above integrated circuit chip, the plurality of LDMOS elements are LDNMOS elements, the first conductivity type is p type, and the second conductivity type is N type. According to an embodiment of the invention, in the integrated circuit chip, the plurality of LDMOS devices are all LDPMOS devices, the first conductivity type is a ^^ type, and the second conductivity type is a p-type. In the above-mentioned integrated circuit chip, at least one of the plurality of LDMOS elements is an LDNMOS element, the above-mentioned 8 16 25790 twf.doc/n 200933888; the second conductivity type is N is an LDPM0S element, and the second conductivity type is The first conductivity type of the p LDNMOS device is a p-type; a type of at least one of the plurality of LDMOS components is an N-type of the first conductivity type of the LD PMOS device; a CMOS device according to an embodiment of the invention. The embodiment of the present invention includes a dual-carrier component. The integrated circuit chip further includes the above-described integrated circuit chip, and according to the embodiment of the present invention, the plurality of A/s in the integrated circuit chip. The range of L values is between (u and 2), but the A/L value may not be limited thereto according to the different process generations and the rated voltage of the components. According to the embodiment of the present invention, the above-mentioned integrated electrical isolation structure is field Isolation structure or shallow groove Channel isolation structure. The present invention provides an integrated circuit wafer including a switch LDM 〇 s element and an analog LDMOS device on a substrate having a first conductivity type. The components of the switch LDMOS device and the analog LDMOS device are the same and Each of the two gate conductive layers is respectively disposed on the two first active regions of the substrate. The common drain contact region of the second conductivity type is located in the second active main region, and the second active main region is located in the plurality of An active region further includes an isolation structure separating the second active main region from the plurality of first active regions. The isolation structure between each of the first active regions and the second active region is along The length of the channel under each gate conductive layer is A in the length direction of the channel, and the length of each gate conductive layer on each of the first active regions in the length direction of the channel along the channel is 16 25790 twf.doc/ n 200933888
為L，開關LDMOS元件以及類比LDM〇s元件具有不 A/L 值。 J 依照本發明實施例所述，上述之積體電路晶片中，上 述開關LDMOS元件之A/L值小於上述類比應〇 之A/L值。 仵 依照本發明實施例所述，上述之積體電路晶片中 述開關LDMOS元件之a/l值的範圍在〇 33至丨12。 〇 依照本發明實施例所述，上述之積體電路晶片十，上 述類比LDMOS元件之上述A/L值的範圍在〇.54至U3。 依照本發明實施例所述，上述之積體電路晶片中，上 述開關LDMOS元件以及上述類比LDM〇s元件均為 LD>iMOS元件’均為⑽麵元件，第一導電型為卩型、: 第二導電型為N型。 依照本發明實施例所述，上述之積體電路晶片中，上 述開關LDMOS元件以及上述類比LDM〇s元件均為 LDPMOS元件，第一導電型為n型；第二導電型為p型。 〇 依照本發明實施例所述，上述之積體電路晶片中，上 述開關LDMOS元件以及上述類比LDMOS元件其一是 LDNMOS元件且另一是LDPMOS元件。LDNMOS元件中 之第一導電型為P型；第二導電型為N型。LDPMOS元件 中之第一導電型為N型；第二導電型為p型。 依照本發明實施例所述，上述之積體電路晶片更包括 CMOS元件。 依照本發明實施例所述’上述之積體電路晶片更包括 16 25790twf.doc/n 200933888 雙載子元件。 依照本發明實施例所述，上述之積體電路晶片中，上 述隔離結構為場隔離結構或淺溝渠隔離結構。 本發明可以透過源極接觸區與汲汲接觸區之間之隔 離結構在沿著通道長度方向上的長度A以及位於主動區上 之閘極導電層在沿著通道長度方向上的長度[的改變，而 在晶片上同時形成不同額定電壓之元件(v〇ltage mting 〇 device)。 本發明可以利用單-的製程，透過光罩圖案的改變， 而在同一晶片上形成具有不同額定電壓2LDM〇s元件， 口此其不僅製程簡單，而且可以避免晶片面積不必要的 浪費’滿足客戶多方面之需求。 本發明可以利用單一的製程，透過光罩圖案的改變， 而在同-晶片上形成具有特性需求不同之開關ldm〇s元 件以及類比LDMOS元件。 ❹ ^^為讓本發明之上述和其他目的、特徵和優點能更明顯 董下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 、11 【實施方式】 圖^疋依照本發明實施例所繪示之一種積體電路晶 件：^圖。圖2是繪示圖1之積體電路晶片之部分構 «月同時參照圖！與圖2，本發明之積體電路晶片包含 11 16 25790twf.doc/n 200933888 多個ldmos元件。這些ldmos元件均為ldnmos元 件’或均為LDPMOS元件，或其中數個是LDNM〇s元件 而其他為LDPMOS元件。為方便說明，僅以兩個ldm〇S 元件1〇、20且其二者均為LDNM0S元件來說明之。然而， 本發明並不以此為限。 在本實施例中，LDNMOS元件1〇以及ldnm〇s元 件20均是位於P型基底100或是p型井區上，在此以p ❹ 型基底綱來說明之。LDNMOS元件1〇以及LDNM〇s 元件20分別包括兩個閘極結構128、兩個N型源極接觸區 110、兩個N型淡摻雜源極區H2、一個N型共汲極接觸 區116以及兩個N型漂移區118，位於p型基底1〇〇中的 N型深井區1〇2中。更具體地說，LDNM〇s元件1〇以及 LDNMOS元件20在深井區102中的構件是在隔離結構1〇4 所定義出的兩個第一主動區106以及一個第二主動區ι〇8 中’其中第二主動區1〇8位於兩個第一主動區1〇6之間。 各閘極結構128包括閘極導電層120以及閘介電層 ❹122。各閘極介電層位於隔離結構刚所定義的第一主動區 106中。各閘極導電層12〇覆蓋在各閘極介電層上。在: ^施例中’各閘極導電層12〇還覆蓋在第一主動區1〇6盥 第二主動區108之間的隔離結構刚上。此外，各間極/導 電層120的末端還藉由延伸至隔離結構刚上的延 120a彼此電性連接。 σ| 兩個Ν型源極接觸區u〇，分別位於第一主動區_ 中。為了避免熱載子效應，各閘極結構128之一側，分別 12 16 25790twf.doc/n 200933888 還有/X摻雜N型;炎摻雜源極區112，其分別與各N型源 極接觸區not性連接。各N型源極接觸㊣11〇以及各n 型淡摻雜源極區112被1>型基體區114所環繞。p型基體 區1H有一部份與閘極導電層12〇電容輕合，構 130。 N型共用汲極接觸區116，則是位於第二主動主區 卜兩個N型漂移區118’齡騎繞於各第—主動區1〇6 ❹與第-主動區108之間的隔離結構1〇4的下方周圍，並與 N型汲極接觸區116電性連接。 八 此外，在各P型基體區114中還可分別包括一 p型接 線區(pick-up regi〇n)l24。在N型深井區1〇2外的基底1〇〇 中還可再包括P型護環(guard ring)i26。 在本實施例中，LDNMOS元件1〇以及LDNM〇s元 件20的組成構件相同，但，其中部分構件的大小略有差 異’以使其達到不同的特性需求。更具體地說，LDNM〇s 元件10以及LDNMOS元件20中，各第一主動區與 第一主動區108之間的隔離結構1〇4在沿著通道區13〇之 通道長度方向上的長度分別為A1與A2 ;而各閘極導電層 120位於第一主動區106上之閘極導電層12〇在沿著通道 區130之通道長度方向X上的長度分別為u與L2。在本 實施例中，LDMOS元件10之A1/L1值不等於LDMOS元 件20之A2/L2值，使得LDNM〇s元件1〇以及LDNM〇s 元件20具有不同的特性。若欲得到A/L較大的For L, the switching LDMOS component and the analog LDM 〇 s component have a non-A/L value. According to an embodiment of the invention, in the above integrated circuit chip, the A/L value of the above-mentioned switching LDMOS device is smaller than the A/L value of the analogy. According to an embodiment of the invention, the a/l value of the switching LDMOS device in the integrated circuit chip described above ranges from 〇33 to 丨12. According to the embodiment of the present invention, the above-mentioned A/L value of the analog LDMOS device is in the range of 5454 to U3. According to the embodiment of the present invention, in the above integrated circuit chip, the switch LDMOS device and the analog LDM 〇 s device are both LD> iMOS devices are both (10) surface elements, and the first conductivity type is 卩 type,: The two conductivity type is N type. According to the embodiment of the invention, in the above integrated circuit chip, the above-mentioned switching LDMOS device and the analog LDM 〇 s device are both LD PMOS devices, the first conductivity type is n-type, and the second conductivity type is p-type. According to the embodiment of the invention, in the above integrated circuit chip, the above-mentioned switching LDMOS device and the analog LDMOS device are both an LDNMOS device and the other is an LDPMOS device. The first conductivity type in the LDNMOS device is a P type; the second conductivity type is an N type. The first conductivity type in the LDPMOS device is N-type; the second conductivity type is p-type. According to an embodiment of the invention, the integrated circuit chip further includes a CMOS component. The above-mentioned integrated circuit chip further includes a 16 25790 twf.doc/n 200933888 double carrier element according to an embodiment of the present invention. According to the embodiment of the invention, in the integrated circuit chip, the isolation structure is a field isolation structure or a shallow trench isolation structure. The present invention can pass the length A along the length of the channel and the length of the gate conductive layer on the active region along the length of the channel through the isolation structure between the source contact region and the germanium contact region. On the wafer, components of different rated voltages (v〇ltage mting 〇 device) are simultaneously formed. The invention can utilize a single-process, through the change of the mask pattern, to form 2LDM〇s components with different rated voltages on the same wafer, which not only has a simple process, but also avoids unnecessary waste of the wafer area. A variety of needs. The present invention can form a switch ldm s component having different characteristic requirements and an analog LDMOS device on the same wafer by a single process through the change of the reticle pattern. The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] FIG. 1 is an integrated circuit crystal according to an embodiment of the present invention: FIG. FIG. 2 is a partial view of the integrated circuit of the integrated circuit of FIG. As with Figure 2, the integrated circuit chip of the present invention comprises 11 16 25790 twf.doc/n 200933888 multiple ldmos components. These ldmos components are either ldnmos components' or both LDPMOS components, or several of them are LDNM〇s components and others are LDPMOS components. For convenience of explanation, only two ldm〇S elements 1〇, 20 and both of them are LDNM0S elements. However, the invention is not limited thereto. In the present embodiment, both the LDNMOS device 1 and the ldnm〇s device 20 are located on the P-type substrate 100 or the p-type well region, and are described herein as a p ❹ type substrate. The LDNMOS device 1A and the LDNM〇s device 20 respectively include two gate structures 128, two N-type source contact regions 110, two N-type lightly doped source regions H2, and an N-type common drain contact region 116. And two N-type drift regions 118 located in the N-type deep well region 1〇2 in the p-type substrate 1〇〇. More specifically, the components of the LDNM〇s element 1〇 and the LDNMOS element 20 in the deep well region 102 are in the two first active regions 106 and one second active region ι8 defined by the isolation structure 1〇4. 'The second active area 1〇8 is located between the two first active areas 1〇6. Each gate structure 128 includes a gate conductive layer 120 and a gate dielectric layer 122. Each of the gate dielectric layers is located in the first active region 106 as defined by the isolation structure. Each of the gate conductive layers 12 is covered on each of the gate dielectric layers. In the embodiment, each of the gate conductive layers 12 〇 also covers the isolation structure between the first active region 1 〇 6 盥 the second active region 108. In addition, the ends of the respective interpole/conductive layers 120 are electrically connected to each other by a length 120a extending to the isolation structure. σ| Two Ν-type source contact areas u〇 are located in the first active area _. In order to avoid the hot carrier effect, one side of each gate structure 128, 12 16 25790 twf.doc/n 200933888 and /X doped N type; inflammatory doped source region 112, respectively, and each N-type source Contact area not connected. Each of the N-type source contacts is positive 11 〇 and each of the n-type lightly doped source regions 112 is surrounded by the 1> type substrate region 114. A portion of the p-type body region 1H is lightly coupled to the gate conductive layer 12 and has a structure 130. The N-type shared drain contact region 116 is an isolation structure between the two active-type main regions, the two N-type drift regions 118', and between the first active regions, the first active region, and the first active region 108. Around the lower side of 1〇4, and electrically connected to the N-type drain contact area 116. Further, a p-type re-spinning region l24 may be included in each of the P-type base regions 114. A P-type guard ring i26 may be further included in the substrate 1〇〇 outside the N-type deep well area. In the present embodiment, the constituent members of the LDNMOS element 1A and the LDNM〇s element 20 are the same, but some of the members are slightly different in size to meet different characteristic requirements. More specifically, in the LDNM〇s element 10 and the LDNMOS element 20, the lengths of the isolation structures 1〇4 between the first active region and the first active region 108 in the channel length direction along the channel region 13〇 are respectively A1 and A2; and the gate conductive layer 12 of each gate conductive layer 120 on the first active region 106 has lengths u and L2 in the channel length direction X along the channel region 130, respectively. In the present embodiment, the A1/L1 value of the LDMOS element 10 is not equal to the A2/L2 value of the LDMOS element 20, so that the LDNM 〇 s element 1 〇 and the LDNM 〇 s element 20 have different characteristics. If you want to get a larger A/L
LDMOS 元件，僅需改變光罩的圖案，增加第一主動區1〇6與第二 13 16 25790twf.doc/n 200933888 之社隱結構⑽的長度A，或是縮小閑極 / sl2G的長度L’抑或是前述兩者同時改變。若欲得 較小的LDMOS元件’僅需僅需改變光罩的圖案， 、ι，、弟-主動區106與第二主動區1()8之間之隔離結構 的長度A ’或是增加閘極導電層12〇的長度L，抑或 是前述兩者同時改變。 在一實施例中，LDNMOS元件1〇以及LDNM〇s元 ❹LDMOS components, only need to change the pattern of the reticle, increase the length A of the first active area 1 〇 6 and the second 13 16 25790 twf.doc/n 200933888 social hidden structure (10), or reduce the length of the idle pole / sl2G L' Or both of them change at the same time. If you want a smaller LDMOS device, you only need to change the pattern of the reticle, ι, the length of the isolation structure between the active-active region 106 and the second active region 1 () 8 or increase the gate. The length L of the pole conductive layer 12A, or both, changes simultaneously. In an embodiment, the LDNMOS device 1〇 and the LDNM〇s element are
件20為具有不同較龍的元件，例如是㈣管理積體電 路晶片中的兩個額定電壓不同的高壓元件。LDNM〇s元件 10以及LDNMOS元件20之源極端可耐高壓，僅需在閘極 導電層120施加微小的電壓即可耐高壓，因此，i閘極介 電層122所需的厚度僅需100埃至2〇〇埃左右。ldnm〇s 元件10以及LDNMOS元件20的a/l值在αι至2之間， 但視不同的製程世代及元件的額定電壓，A/L值可不限於 此。當LDNMOS元件10的A1/L1值小於LDNMOS元件 20的A2/L2值時，LDNMOS元件1〇的崩潰電壓較低，也 就是其額定的電壓較低；LDNMOS元件2的崩潰電壓較 高，也就是其額定的電壓較大。 本發明除了可以應用在額定電壓的元件上之外，還可 應用在其他的領域中，例如是同時應用在具有不同電流特 性需求之開關元件以及類比元件上。在一實施例中， LDNMOS元件10以及LDNMOS元件20分別為開關元件 以及類比元件。通常，開關元件僅需在開啟的瞬間產生足 夠的電流即可達到開啟的目的，其所需的飽和電流較小， 16 25790twf.doc/n 200933888 因此，LDNMOS元件10的Al/Ll值較小’其範圍例如是 在0.33至1.12。而類比元件則必須長時間具有穩定的電壓 以避免造成誤判，也就是，其必須具有足夠大且穩定的飽 和電流，電流-電壓曲線中具有平坦的飽和區，因此， LDNMOS元件20的A2/L2值較大，其範圍例如是在〇·54 至 1.13。The component 20 is an element having different dragons, for example, (iv) managing two high voltage components having different rated voltages in the integrated circuit chip. The source terminals of the LDNM〇s device 10 and the LDNMOS device 20 are resistant to high voltage, and only a small voltage is applied to the gate conductive layer 120 to withstand high voltage. Therefore, the thickness of the i gate dielectric layer 122 is only 100 angstroms. It is about 2 〇〇. The a/l values of the ldnm〇s element 10 and the LDNMOS element 20 are between αι and 2, but the A/L value may not be limited to this depending on the process generation and the rated voltage of the components. When the A1/L1 value of the LDNMOS device 10 is smaller than the A2/L2 value of the LDNMOS device 20, the breakdown voltage of the LDNMOS device 1 is lower, that is, the rated voltage thereof is lower; the breakdown voltage of the LDNMOS device 2 is higher, that is, Its rated voltage is large. In addition to being applicable to components of rated voltage, the present invention can be applied to other fields, for example, simultaneously applied to switching elements and analog components having different current characteristics. In one embodiment, LDNMOS device 10 and LD NMOS device 20 are switching elements and analog elements, respectively. Generally, the switching element only needs to generate enough current at the moment of turning on to achieve the purpose of turning on, and the required saturation current is small, 16 25790 twf.doc/n 200933888 Therefore, the Al/Ll value of the LDNMOS element 10 is small' The range is, for example, from 0.33 to 1.12. The analog component must have a stable voltage for a long time to avoid misjudgment, that is, it must have a sufficiently large and stable saturation current, and a flat saturation region in the current-voltage curve. Therefore, the A2/L2 of the LDNMOS device 20 The value is large, and its range is, for example, 〇·54 to 1.13.
❹ 在一實施例中，在0‘35微米18伏特之LDNMOS製 程中’積體電路晶片上之開關LDMOS元件的源極接觸區 與汲極接觸區之間之隔離結構的長度Α為0.6微米；多晶 矽閘極在主動區上的長度L為1.8微米，A/L = 〇.333 ; P 型基體區與多晶矽閘極重疊的長度（通道長度）為〇·5微 米，其電流與電壓的關係曲線如圖4Α所示。積體電路晶 片上之類比LDMOS元件的源極接觸區與汲極接觸區之間 之隔離結構的長度Α為1.2微米；多晶矽閘極在主動區上 的長度L為2.2微米，a/L = 〇.545 ; P型基體區與多晶矽 閘極重疊的長度(通道長度)為〇 5微米，其電流與電壓的關 係曲線如圖4B所示。其結果顯示開關LDM〇s元 潰電壓為29.8伏特；電阻⑽咖)為咖歐·平 月 元件㈣潰電壓為38.3伏特；電阻(她如) ^姆/平方難，^其飽和電流曲線非常平坦。 ，另一實施例中，在〇,35微米3〇伏特之咖峨 中，顏電路晶#上之開關LDMQS元件 =沒極接親之間之隔離結構的長度微接= 晶石夕閉極在主動區上的長度微米，级 15 16 25790twf.doc/n 200933888 型基體區與乡晶㈣極4疊的長度(通道長度）為〇5微 米，其電流與電壓的關係曲線如圖5A所示。積體電路晶 片上之類比LDMOS兀件的源極接觸區與汲極接觸區 之隔離結構的長度A為1.8微米；多晶糊極在主動區上 的長度L為2.2微米’ A/L^.8l8 ; p型基體區與多 閘極重疊的長度(通道長度)為〇.5微米，其電流與電壓的關 係曲線如圖5B獅。其結果_開關LDMqs元件的崩 潰電壓為37.7伏特；電阻為37.7歐姆/平方爱米。類比 LDMOS耕的崩潰電壓為則伏特；電阻為62 9歐姆/ 平方釐米，且其飽和電流曲線非常平坦。 列中，在〇.35微米40伏特之LD_〇s it:: 晶片上之開關LDM0S元件的源極接觸 區與錄闕區之間之隔離結構的長度A為18微米^ 晶石夕閘極在主魅上的長度L為丨6微米尬=ι i25 ; p Ϊ基晶矽閘極重疊的長度(通道長度)為0.5微 片上的關係曲線如圖6八所示。積體電路晶 元，極接觸區與卿觸區之間 ==為2.5微米；多晶娜在主動區上 門極ί&微米’A/L==1.135;p型基體區與多晶石夕 通道長度)為0.5微米，其電流與電壓的關 圖6B所示。其結果顯示開關LDM〇s元件的崩 =壓為49.7伏特；電阻為6〇2歐姆 元件，潰電壓為如伏特； 7 = 千方爱未，且其飽和電流曲線非常平坦。 姆/ 16 25790twf.doc/n 200933888 以上是以LDNMOS元件來說明元件10、20，在實際 應用時元件10、20也可以均是LDPMOS元件。若上述的 LDNMOS元件中的P型表示第一導電型；n型表示第二導 電型，則在LDPMOS元件中，第一導電型則為N型；第 二導電型則為P型。❹ In one embodiment, the length 隔离 of the isolation structure between the source contact region and the drain contact region of the switching LDMOS device on the integrated circuit wafer in the 0'35 micron 18 volt LDNMOS process is 0.6 micrometers; The length L of the polysilicon gate on the active region is 1.8 μm, A/L = 〇.333; the length of the P-type base region overlaps with the polysilicon gate (channel length) is 〇·5 μm, and its current versus voltage curve As shown in Figure 4Α. The length of the isolation structure between the source contact region and the drain contact region of the analog LDMOS device on the integrated circuit wafer is 1.2 μm; the length L of the polysilicon gate on the active region is 2.2 μm, a/L = 〇 .545 ; The length of the P-type base region overlaps with the polysilicon gate (channel length) is 〇5 μm, and the current-voltage curve is shown in Fig. 4B. The result shows that the switch LDM 〇s element collapse voltage is 29.8 volts; the resistance (10) coffee) is the coffee European flat moon component (four), the voltage is 38.3 volts; the resistance (she is) ^ m / square difficult, ^ its saturation current curve is very flat . In another embodiment, in the 〇, 35 micron 3 volt volt curry, the switch LDMQS component on the 颜电路晶# = the length of the isolation structure between the immersed contacts = microstrip 晶The length of the active area is micron, and the length of the base layer of the 15 16 25790 twf.doc/n 200933888 type and the base (4) pole (channel length) is 〇 5 μm, and the current-voltage relationship curve is shown in FIG. 5A. The length A of the isolation structure of the source contact region and the drain contact region of the analog LDMOS device on the integrated circuit wafer is 1.8 μm; the length L of the polycrystalline paste on the active region is 2.2 μm 'A/L^. 8l8; The length of the p-type base region and the multi-gate overlap (channel length) is 〇.5 μm, and the relationship between current and voltage is shown in Fig. 5B. As a result, the breakdown voltage of the switch LDMqs element was 37.7 volts; the resistance was 37.7 ohms/square meter. Analogy LDMOS has a breakdown voltage of volts; the resistance is 62 9 ohms/cm 2 and its saturation current curve is very flat. In the column, the length of the isolation structure between the source contact region and the recording region of the LD_〇s it::35 μm 40 volt LDM0S device is 18 μm ^ Spar The length L on the main charm is 丨6 μm ι=ι i25; the length of the p Ϊ-based crystal gate overlap (channel length) is 0.5 microchip as shown in Fig. 6-8. Integral circuit crystal cell, between the polar contact region and the clear contact region == 2.5 μm; polycrystalline Na is in the active region upper gate ί & micron 'A / L = = 1.135; p-type matrix region and polycrystalline litter channel The length is 0.5 microns and the current and voltage are shown in Figure 6B. The result shows that the switch LDM 〇 s component has a collapse voltage of 49.7 volts; the resistance is 6 〇 2 ohm components, the breakdown voltage is as volts; 7 = thousand squares love, and its saturation current curve is very flat. M / 16 25790twf.doc/n 200933888 The above descriptions of components 10 and 20 are LDNMOS components. In practical applications, components 10 and 20 may also be LDPMOS components. If the P type in the above LDNMOS device indicates the first conductivity type, and the n type indicates the second conductivity type, in the LDPMOS device, the first conductivity type is N type, and the second conductivity type is P type.
同樣地，元件10、20也可以分別是LDNMOS元件以 及LDPMOS元件。若上述的LDNMOS元件中的P型表示 第一導電型；N型表示第二導電型，則在LDPMOS元件 中，第一導電型則為N型；第二導電型則為p型。 此外，請參考圖3,在實際應用時，積體電路晶片3〇〇 除了具有多個不同的LDMOS元件302之外，還可以包括 其他的元件，例如是CMOS元件3〇4或是雙載子元件3〇6。 本發明可以利用單一的製程，透過光罩圖案的改變， 而在同-W上形成具有不同雜之LDMGS元件，因 ^，其不僅製程簡單，而且可以避免晶片面積不必要的浪 費二Ϊ足客戶多方面之需求。此外，本發明也可以利用單 -曰過光罩圖案的改變及增加光罩層數，而在同 具有触需林狄關LDMGS元件以及 類比LDMOS元件。 杯ΓίΓΓ財㈣聽如上，然娃_以限定 當視後附之申請專利範圍所本發明之保護範圍 16 25790twf.doc/n 200933888 【圖式簡單說明】 圖1是依照本發明實施例所繪示之一種積體電路晶片 的剖面示意圖。 圖2是繪示圖丨之積體電路晶片之部分構件的上視 圖。 圖3是依照本發明另一實施例所繪示之—種積體電路 晶片的剖面示意圖。 圖4 A與圖4B分別是依照本發明一實施例所繪示之開 關LDMOS元件以及類比LDM〇s元件之電流與電壓的關 係曲線。 圖5A與圖5B分別是依照本發明另一實施例所繪示之 開關LDMOS元件以及類比LDMOS元件之電流與電壓的 關係曲線。 圖6A與圖6B分別是依照本發明又一實施例所繪示之 開關LDMOS元件以及類比LDM〇s元件之電流與電壓的 關係曲線。 【主要元件符號說明】 10、20 :橫向雙擴散金氧半導體(LDMOS) 100 :第一導電型基底 102 ·第一導電型深井區 104 :隔離結構 106 .第一主動區 108 .第一主動區 18 200933888 16 25790twf.doc/n 110 :第二導電型源極接觸區 112 :第二導電型淡摻雜源極區 114 :第一導電型基體區 116 :第二導電型汲極接觸區 118 :第二導電型漂移區 120 :閘極導電層 120a :導電層之延伸部 122:閘介電層 Ό 124:第一導電型接線區 126 :第一導電型護環區 128 :閘極結構 130 :通道區 300 : 1C晶片 302 :多個LDMOS元件 304 : CMOS 元件 306 :雙載子元件 Ο X:通道長度方向 L、A :長度Similarly, elements 10, 20 can also be LDNMOS elements and LD PMOS elements, respectively. If the P type in the above LDNMOS device indicates the first conductivity type, and the N type indicates the second conductivity type, in the LDPMOS device, the first conductivity type is N type, and the second conductivity type is p type. In addition, referring to FIG. 3, in practical applications, the integrated circuit chip 3 may include other components in addition to the plurality of different LDMOS elements 302, such as CMOS components 3〇4 or dual carriers. Element 3〇6. The invention can utilize a single process, through the change of the mask pattern, to form different kinds of LDMGS components on the same-W, because it is not only simple in process, but also can avoid unnecessary waste of the wafer area. A variety of needs. In addition, the present invention can also utilize the change of the single-pass mask pattern and the number of mask layers, while having the touch-sensitive Lin Diguan LDMGS component and the analog LDMOS component. Cup Γ ΓΓ ΓΓ ( 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 16 16 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 A schematic cross-sectional view of an integrated circuit chip. Fig. 2 is a top plan view showing a part of the components of the integrated circuit chip of Fig. 2. 3 is a cross-sectional view showing an integrated circuit chip in accordance with another embodiment of the present invention. 4A and 4B are diagrams showing current and voltage curves of a switching LDMOS device and an analog LDM 〇 s device, respectively, according to an embodiment of the invention. 5A and 5B are graphs showing current versus voltage of a switched LDMOS device and an analog LDMOS device, respectively, according to another embodiment of the invention. 6A and FIG. 6B are respectively a graph showing current versus voltage of a switching LDMOS device and an analog LDM 〇 s device according to still another embodiment of the present invention. [Major component symbol description] 10, 20: lateral double-diffused metal oxide semiconductor (LDMOS) 100: first conductive type substrate 102. First conductive type deep well region 104: isolation structure 106. First active region 108. First active region 18 200933888 16 25790twf.doc/n 110: second conductivity type source contact region 112: second conductivity type lightly doped source region 114: first conductivity type substrate region 116: second conductivity type drain contact region 118: The second conductive type drift region 120: the gate conductive layer 120a: the conductive layer extension portion 122: the gate dielectric layer Ό 124: the first conductive type wiring region 126: the first conductive type guard ring region 128: the gate structure 130: Channel region 300: 1C wafer 302: a plurality of LDMOS elements 304: CMOS element 306: double carrier element Ο X: channel length direction L, A: length