TW200931460A - Anode-stacked mechanism of multi-layered chip-type solid-state electrolytic capacitor - Google Patents

Anode-stacked mechanism of multi-layered chip-type solid-state electrolytic capacitor Download PDF

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TW200931460A
TW200931460A TW97100260A TW97100260A TW200931460A TW 200931460 A TW200931460 A TW 200931460A TW 97100260 A TW97100260 A TW 97100260A TW 97100260 A TW97100260 A TW 97100260A TW 200931460 A TW200931460 A TW 200931460A
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Taiwan
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anode
type solid
solid electrolytic
electrolytic capacitor
wafer
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TW97100260A
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Chinese (zh)
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ji-hao Qiu
ming-zong Chen
ming-cheng Li
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Apaq Technology Co Ltd
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Priority to TW97100260A priority Critical patent/TW200931460A/en
Publication of TW200931460A publication Critical patent/TW200931460A/en

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Abstract

An anode-stacked mechanism of multi-layered chip-type solid-state electrolytic capacitor is disclosed, in which plural chip-type solid-state electrolytic capacitors form a lamination-type solid-state electrolytic capacitor, the anode ends of the adjacent chip-type solid-state electrolytic capacitors are separated and connected by a conductor, so that the anode end of each chip type electrolytic capacitor is disposed inside the lamination-type solid-state electrolytic capacitor almost horizontally.

Description

200931460 九、發明說明: 【發明所屬之技術領域】 本發明是有關一種晶片型固態電解 是有關一種組成疊層式固態電解電容曰為,特別 態電解電容器,該晶片型固態電M t之晶片型固 以幾乎水平的方式設於疊層式 極碥是 者。 增式固態電解電容器之中 〇 【先前技術】 習見之固態電解電容器,如第1 態電解電容器100 ,包括有陽 田 不,〇固 οηι 括有%極部101和陰極部 ‘ 201,陰極部201的中央*炙·^人 叼r天為多孔性鋁金屬箔202,多 -孔性銘金屬肖202的外部依序為氧化紹介電層 203、導電高分層綱、碳膠層2()5、銀膠層施;陽 極部101與陰極部201之間以-絕緣層102隔離。 近年來’為了因應現有電子產品高容量需求的 趨勢,疊層式固態電解電容器乃被發展出來。該疊 層式固態電解電容器,如第2、3圖所示,係美國 6,421,227 B2案所揭露的疊層式固態電解電容器, 该璺層式固態電解電容器i係以多數個固態電解電 容器11、12、13相互堆疊所組成,如圖所示,當多 數個固電解電谷器11、12、13相互堆疊在一起時, 各固態電解電容器11、12、13之陰極部14是藉由 銀導電膠15彼此連接,最底層的陰極部14並以銀 5 200931460 導電膠連結至導線架18。各固態電解電容器U、12、 13的陽極部16末端則利用電阻焊接或雷射 方式焊接至導線架17。 辱 當相互疊層之多數個固態電解電容器u、i2、 13的陽極部16共同焊接至導線架17時每個陽極 部與導線架17焊接時會呈現f曲及變形的現象 (如第4圖所示)。200931460 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer-type solid-state electrolysis relating to a stacked solid-state electrolytic capacitor, a special-state electrolytic capacitor, and a wafer-type solid-state electric Mt wafer type The solid-state is the most compact method. Among the types of solid-state electrolytic capacitors, the solid-state electrolytic capacitors, such as the first-state electrolytic capacitors 100, include the yangtian, the tamping οηι including the % pole portion 101 and the cathode portion 201, and the cathode portion 201. The central *炙·^人叼r days is a porous aluminum metal foil 202, and the external order of the multi-porous Ming metal Shao 202 is oxide dielectric layer 203, conductive high layer, carbon glue layer 2 () 5, silver glue Layer application; the anode portion 101 and the cathode portion 201 are separated by an insulating layer 102. In recent years, in order to cope with the trend of high capacity demand of existing electronic products, laminated solid electrolytic capacitors have been developed. The stacked solid-state electrolytic capacitor, as shown in Figs. 2 and 3, is a stacked solid electrolytic capacitor disclosed in U.S. Patent No. 6,421,227 B2, which is a plurality of solid electrolytic capacitors 11 and 12 And 13 are stacked on each other, as shown in the figure, when a plurality of solid electrolytic electric grids 11, 12, 13 are stacked on each other, the cathode portions 14 of the solid electrolytic capacitors 11, 12, 13 are made of silver conductive adhesive 15 is connected to each other, and the bottommost cathode portion 14 is joined to the lead frame 18 by a silver 5 200931460 conductive paste. The ends of the anode portions 16 of the solid electrolytic capacitors U, 12, and 13 are welded to the lead frame 17 by electric resistance welding or laser welding. When the anode portions 16 of the plurality of solid electrolytic capacitors u, i2, 13 stacked on each other are collectively welded to the lead frame 17, each anode portion is bent and deformed when soldered to the lead frame 17 (Fig. 4). Shown).

為了減少陽極部16的變形量,雖然可如第3圖 所示地將多數個固態電解電容器分成上疊層 解電容11G及下疊層固態電解電容12();但是,陽極 部16為結合至導線架17所作之變形或弯曲,變妒 或彎曲所造成的應力會傳遞到每個固態電解電容的 陰極部14上,對形成於陰極部内作為介電層之氧化 膜造成破壞’使得該固態電解電容器的效能 漏電流LC增加),而且’隨著疊層數 壞的程度愈大。 【發明内容】 因此’本發明之主要目的在提供一種多層晶片 型電解電容器之陽極堆疊機構,係使固態電解 電容器的效能不會受到晶片型 堆疊的層數所影響。 口癌電解電容器相互 本發明之次—目的在提供—種多層晶片型固綠 電解電容益之陽極堆疊機構’係使當多數個晶片型 6 200931460 =電容器相互垂直堆疊時, 的%極端,彼此幾乎相互平行。 i電解電谷器 本發明之再一目的在提供一種多芦日 電解電容器之陽極堆疊機構,當多數個二曰型雷=態 容器相互垂直堆疊時,在彼此相 :::: 器的陽極端之間,係設有一區隔用㈣體電解電谷 【實施方式】 ❹ ❹ 疊機ί發:二多層晶片型固態電解電容器之陽極堆 n其堆㈣層數可為2,層,兹僅以數層表 不,第5圖所示’多數個晶片型固態電解電容器2、 4相互堆疊時’晶片型固態電解電容器2、3、4 的陰極體51外部以導電銀膠52彼此相互連接,晶片 型固態電解電容器2、3、4的陽極體53和陰極體51 之門η又置絕緣層54,使陽極體53和陰極體5 i區隔, 數個固態電解電容器2、3、4的下端,並設置有 一陽極導線架55及陰極導線架56,陰極導線架刊 與下端陰極體51以導電膠連接。其中,每一個相鄰 的曰曰片型固態電解電容器2、3、4的陽極體53,以 及陽極體53和陽極導線架55之間,並設置有一導電 f生隔^機構6 ’使各個晶片型固態電解電容器2、3、 4的陽極體53,以及陽極體53和導線架55之間保持 水平相互隔離。 上述使用於隔離各晶片型固態電解電容器2、3、 7 200931460 4之陽極體53的導電性隔離機構6,得為固體狀 電體或是填入其間然後再硬化之導電膠。 本發明之上述機構’經由在晶片型固態 器2、3、4的各個陽極體53之間,以及陽極體53 和%極導線架55之間,設置導電性隔離機構6,曰 片型固態電解電容器2、3、4的陽極體53即可不: 晶片型固態電解電容器垂直相互堆疊的層 = ❹In order to reduce the amount of deformation of the anode portion 16, although a plurality of solid electrolytic capacitors can be divided into an upper laminated electrolytic capacitor 11G and a lower laminated solid electrolytic capacitor 12 () as shown in Fig. 3; however, the anode portion 16 is bonded to The deformation or bending of the lead frame 17 causes the stress caused by the deformation or bending to be transmitted to the cathode portion 14 of each solid electrolytic capacitor, causing damage to the oxide film formed as a dielectric layer in the cathode portion. The performance of the capacitor increases the leakage current LC), and 'the greater the degree of deterioration as the number of stacks. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide an anode stacking mechanism for a multilayer wafer type electrolytic capacitor in such a manner that the performance of the solid electrolytic capacitor is not affected by the number of layers of the wafer type stack. Oral cancer electrolytic capacitors are the second aspect of the present invention - the objective is to provide a multi-layer wafer type solid green electrolytic capacitor with an anode stacking mechanism'. When a plurality of wafer types 6 200931460 = capacitors are stacked vertically with each other, the extreme is almost Parallel to each other. A further object of the present invention is to provide an anode stacking mechanism for a multi-Auger electrolytic capacitor, when a plurality of two-type thunder-state containers are stacked vertically with each other, at the anode end of each other:::: Between the two, there is a zone (4) body electrolysis valley [Embodiment] ❹ ❹ 机 ί ί : : : : : : : 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 阳极 阳极 阳极 阳极 阳极 阳极 阳极 阳极 阳极 阳极 阳极 阳极 阳极 阳极In the case of a plurality of wafer type solid electrolytic capacitors 2, 4 stacked on each other, the cathode body 51 of the wafer type solid electrolytic capacitors 2, 3, 4 is connected to each other by a conductive silver paste 52, The anode body 53 of the wafer type solid electrolytic capacitors 2, 3, and 4 and the gate η of the cathode body 51 are further provided with an insulating layer 54, which separates the anode body 53 from the cathode body 5 i, and several solid electrolytic capacitors 2, 3, and 4 The lower end is provided with an anode lead frame 55 and a cathode lead frame 56. The cathode lead frame is connected to the lower end cathode body 51 by a conductive adhesive. Wherein, an adjacent anode body 53 of the solid-state electrolytic capacitors 2, 3, 4, and an anode body 53 and an anode lead frame 55 are provided with a conductive f-separating mechanism 6' for each wafer. The anode body 53 of the solid electrolytic capacitors 2, 3, 4, and the anode body 53 and the lead frame 55 are horizontally isolated from each other. The above-mentioned conductive isolation mechanism 6 for isolating the anode body 53 of each of the wafer type solid electrolytic capacitors 2, 3, 7 200931460 4 is a solid electric body or a conductive paste filled therein and then hardened. The above mechanism of the present invention is provided between the anode bodies 53 of the wafer type solid-state devices 2, 3, 4, and between the anode body 53 and the % pole lead frame 55, and a conductive isolation mechanism 6 is provided. The anode body 53 of the capacitors 2, 3, 4 can be omitted: a layer in which wafer type solid electrolytic capacitors are vertically stacked on each other = ❹

響’陽極體53均能保持水平狀,當整體以樹脂封;: 時’即可避免因為應力的傳遞而導致陰極體氧化膜層 的破壞。 θ 6圖所示,利用銀膠7將晶片 3、4的各個陽極端53被覆起 實施時,亦可如第 型固態電解電容器2、 來並水平區隔。 實施時,亦可利用含浸(Dipping)的方式使多數 :晶片型固態電解電容器2、3、4的陽極端53被覆 几銀膠之後,再利用取放裝置(Piek&plaee)導入點交 機上進行與導線架之導電膠進行黏結。 或者’亦可在現有製程進行焊接之前,利用點勝 ^陽極處點上錫或錫其合金’由於錫或錫其合金的 广點約m〜250。(: ’使用較低之焊接功率可將應力降 '如此纟T以減低高熱對等效串聯電阻(ESR)的 t壞’錫或錫其合金黏結層的設置相當於陽極隔離機 ,可減少漏電流LC的破壞’亦有助於陽極的焊接,The anode body 53 can be kept horizontal, and when it is sealed with a resin as a whole, it can avoid the destruction of the oxide film layer of the cathode body due to the transfer of stress. As shown in Fig. 6, when the respective anode ends 53 of the wafers 3, 4 are covered by the silver paste 7, they may be horizontally separated as the first type solid electrolytic capacitor 2. In practice, most of the wafer-type solid electrolytic capacitors 2, 3, and 4 may be coated with a plurality of silver pastes by means of Dipping, and then introduced into the spotting machine by using a pick-and-place device (Piek & plaee). Bonding with the conductive paste of the lead frame. Or 'can also use the point to win the tin or tin alloy on the anode before soldering in the existing process' because the tin or tin alloy has a wide point of about m~250. (: 'Use lower welding power to reduce the stress' so 纟T to reduce the high heat to the equivalent series resistance (ESR) t bad 'tin or tin alloy bond layer setting equivalent to the anode isolators, can reduce leakage The destruction of the current LC' also contributes to the soldering of the anode.

S 200931460 避免假焊的發生。 由於陽極的空間很小,為了避免在點膠及焊接的 過程中跨過陰極造成漏電流上升或是短路,亦可採取 一般多層板穿孔(through-hole)的概念,如第7圖所 不,點膠時直接點至陽極的穿孔8内,而由於採取穿 孔(through-hole)的方式,導通表面積會大增,將有 助於降低等量串聯電阻(ESR;)之效果。 ,而設於陽極部之穿孔8可為方形孔、圓形孔、菱 形孔或其他形孔,孔數則得為一個孔、兩個孔或多數 個0 ‘ 〜综上所述,本發明之此種多層晶片型固態電解電 容器之陽極堆疊機構,為從來所無,符合本國發明專 利申請要件,爰依法提出申請,懇請賜准專利,實感 德便® ^需陳明者,以上所述者乃是本發明較佳具體的實 〇鉍例,若依本發明之構想所作之改變,其產生之功能 作用,仍未超出說明書與圖示所涵蓋之精神時,均^ 在本發明之範圍内,合予陳明。 〜 9 200931460 【圖式簡單說明】 第1圖係習見疊層式固態電解電電容器之剖 面示圖。 第 2圖係習見疊層式固態電解電電容器之剖 面示圖。 第3圖係另一習見疊層式固態電解電電容器 之剖面示圖。 第4圖係又一習見疊層式固態電解電電容器 ❹之剖面示圖。 第 5圖係本發明之多單元晶片型固態電解電 電容器之剖面示圖。 ‘第6圖係本發明之多單元晶片型固態電解電 電容器的另一實施例剖面示圖。 第7圖係本發明之多單元晶片型固態電解電 電容器的又一實施例剖面示圖。 200931460 【主要元件符號說明】 100 :固態電解電容器 101 :陽極部 201 :陰極部 202 :多孔性紹金屬箔 203 :氧化鋁介電層 204 :導電高分層 205 :碳膠層 206 :銀膠層 102 :絕緣層 1 : 疊層式固態電解電容器 11 晶片型固態電解電容器 12 陽極體 13 : 陰極體 14 導電膠 15 : 導線架 2 > 3、4 :晶片型固態電解電容器 51 陰極體 52 : 導電膠 54 絕緣層 55 : 導線架 56 陰極導線架 6 : 導電性隔離機構 7 : 隔離用銀膠 8 : 穿孔S 200931460 Avoid the occurrence of false welding. Since the space of the anode is small, in order to avoid leakage current increase or short circuit across the cathode during dispensing and soldering, a general multi-layer through-hole concept can also be adopted, as shown in FIG. When dispensing, it is directly placed into the perforation 8 of the anode, and the conduction surface area is greatly increased due to the through-hole method, which will help to reduce the effect of the equivalent series resistance (ESR;). The perforation 8 provided in the anode portion may be a square hole, a circular hole, a rhombic hole or other shaped holes, and the number of holes may be one hole, two holes or a plurality of 0'-integrated, the present invention The anode stacking mechanism of such a multi-layer wafer type solid electrolytic capacitor is never available, and meets the requirements of the national invention patent application, and the application is made according to law, and the patent is granted, and the real sense is that it needs to be clearly stated. It is a preferred embodiment of the present invention, and if the function of the present invention is changed, the function of the present invention is not within the scope of the present invention. Combined with Chen Ming. ~ 9 200931460 [Simple description of the drawing] Fig. 1 is a cross-sectional view showing a laminated solid electrolytic capacitor. Fig. 2 is a cross-sectional view showing a laminated solid electrolytic capacitor. Fig. 3 is a cross-sectional view showing another conventional laminated solid electrolytic capacitor. Fig. 4 is a cross-sectional view showing another example of a laminated solid electrolytic capacitor. Fig. 5 is a cross-sectional view showing a multi-unit wafer type solid electrolytic capacitor of the present invention. Fig. 6 is a cross-sectional view showing another embodiment of the multi-unit wafer type solid electrolytic capacitor of the present invention. Fig. 7 is a cross-sectional view showing still another embodiment of the multi-unit wafer type solid electrolytic capacitor of the present invention. 200931460 [Description of main component symbols] 100: Solid electrolytic capacitor 101: Anode part 201: Cathode part 202: Porous metal foil 203: Alumina dielectric layer 204: Conductive high layer 205: Carbon glue layer 206: Silver glue layer 102: insulating layer 1: laminated solid electrolytic capacitor 11 wafer type solid electrolytic capacitor 12 anode body 13: cathode body 14 conductive paste 15: lead frame 2 > 3, 4: wafer type solid electrolytic capacitor 51 cathode body 52: conductive Glue 54 Insulation 55 : Lead frame 56 Cathode lead frame 6 : Conductive isolation mechanism 7 : Silver paste for isolation 8 : Perforation

Claims (1)

200931460 十、申請專利範圍: ^構種/由層多\片曰型Η固態電解電容器之陽極堆疊機 構如由义數晶片_態電解 堆疊的方式所組成’各個晶片型固態電解電容 器’彼此以導電勝包覆於陰極體外部而相= 接^片型固態電解電容器之陽極體和陰極體之 間並没有絕緣層區隔,在陽 丨用牡隊極體和陰極體的下她 各設有一對外導通之|@ . ❹ ❹ π、i導線条,其特徵在於·· 彼此相鄰的晶片型固皞 個 間,以及底層陽極端和陽 呀桠而之 右一八久曰w , 導電架之間,係各設 2 k亚\曰曰垔固態電解電容器之陽極端保持 水平之陽極隔離機構者。 ’、、 、如申請專利範圍第 項之多層晶片型固能雷紐 電容器之陽極堆疊機盞 玉U心電解 a μ , 構,該賒極隔離機構係一可 運接各個晶片型固態電 個晶片型固態電解電容陽㈣’使各 導電體。 电合益之%極端保持水平之 3 如申請專利範圍第j項 電容器之陽極堆疊機構=晶片型固態電解 連接夂柄曰u 構遠IW極隔離機構係一可 逑接各個晶片型固態 個晶片型固態電解之陽極端,使各 銀及銀合金膠包覆層。 料保持水+之 如申請專利範圍第】 電容器之陽極堆疊機構二f晶片型固態電解 调構邊%極隔離機構係一可 4 200931460 電容器之陽極端,使各 之陽極端保持水平之 連接各個晶片型固態電解 個晶片型固態電解電容器 錫及錫合金膏β 5 6 如申請專利範圍第1項之多声曰 雷宏曰日日片支固態電解 電谷益之%極堆疊機構,各個晶片 容器之陽極端可炉成穿丨 心電解電 W往% 了形成穿孔,使陽極隔離機 於各個晶片型固能雷組雪办00 牙 i 陽極端時,陽極 隔離機構可穿過陽極端之穿孔。 2 =專利乾圍第5項之多層晶片型固態電解 令益之陽極堆疊機構,各個晶片型固態電解電 容器之陽極端的穿孔,可為圓形孔、方形孔或其 他形孔。 、 、如::#專利範圍帛5項之多層晶片型固態電解 電谷益之陽極堆疊機構,形成於各個晶片型固態 電解電谷器之陽極端的穿孔的孔數可為單個或 ❹ 二個以上之多數個。 13200931460 X. Patent application scope: ^The composition of the anode/stacking layer of the solid electrolytic capacitor is composed of a plurality of wafer-type solid electrolytic capacitors. Winning is coated on the outside of the cathode body and the phase is not separated by an insulating layer between the anode body and the cathode body of the solid-state electrolytic capacitor, and each of the anode and cathode bodies of the impotence is provided with a foreign body.导 | π i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i It is an anode isolation mechanism in which the anode end of the solid electrolytic capacitor of 2 k Asian and 曰曰垔 is kept horizontal. ',,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Type solid electrolytic capacitors yang (four) 'to make each conductor.合 电 极端 极端 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 = = = = = = = = = = 阳极 阳极 = 阳极 阳极 阳极 阳极 阳极 阳极 阳极 阳极 阳极The anode end of solid electrolyte is coated with each silver and silver alloy glue. Feeding water + as in the scope of patent application] Capacitor anode stacking mechanism 2 f-chip type solid-state electric demodulation edge % pole isolation mechanism can be 4 200931460 The anode end of the capacitor, so that the anode ends of each capacitor are horizontally connected to each wafer Solid-state electrolysis wafer-type solid electrolytic capacitor tin and tin alloy paste β 5 6 As claimed in the first paragraph of the patent scope, the multi-sound 曰 曰 曰 曰 片 支 固态 固态 固态 固态 固态 固态 固态 , , , , , The anode end can be formed into a perforation by the electrolysis of the core, so that the anode isolating mechanism can pass through the perforation of the anode end when the anode isolating machine is used at the anode end of each wafer type solid energy lightning group. 2 = Patented drywall No. 5 multilayer wafer type solid state electrolysis The anode stacking mechanism, the perforation of the anode end of each wafer type solid electrolytic capacitor may be a circular hole, a square hole or the like. , such as: ## Patent scope 帛5 items of multi-layer wafer type solid electrolytic electric furnace Guyi anode stacking mechanism, the number of holes formed in the anode end of each wafer type solid electrolytic electric grid can be single or ❹ two Most of the above. 13
TW97100260A 2008-01-04 2008-01-04 Anode-stacked mechanism of multi-layered chip-type solid-state electrolytic capacitor TW200931460A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI415149B (en) * 2011-07-11 2013-11-11 Can improve the capacitance of the solid electrolytic capacitor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI415149B (en) * 2011-07-11 2013-11-11 Can improve the capacitance of the solid electrolytic capacitor

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