200929868 九、發明說明： 【發明所屬之技術領域】 為一種諸如輸出緩衝器電路之輸出驅動器電路，尤指 一種具較低功率消耗之含輸出預置電路之輸出驅動器電 路。 【先前技術】 ❹ 如今在一積體電路之中使用諸如一具有輸出預置電 路之輸出緩衝器電路之類的輸出驅動器電路以驅動一輸出 數據是極為普遍的。例如，請參看第一圖，其顯示一如 Ishibashi等在美國專利第4,992,677號中所揭露之，用於一 輸出緩衝器電路之輸出預置電路的電路示意圖。在第一圖 中’該輸出預置電路包含兩個參考電壓（VH與VL)，兩個差 分放大器（OP1與OP2)，兩個N型金氧半導體(NM0S:M1與 M2)以及一電容C(一輸出負載），且每一該VH、VL、M2及 〇 C之一端均接地。VH、VL、OP1與OP2用於偵測C之一電壓 的輸出準位，且Ml與M2用於預置該C之電壓至VH或VL。 當C之電壓高於VH時，M2開啟而Ml關斷以下拉C之電壓至 VH，當C之電壓低於VL時，Ml開啟而M2關斷以上拉C之電 壓至VL。 雖然如第一圖所示之該輸出預置電路具有高之讀出 速率與低之雜訊，但其主要之缺點為該兩個差分放大器 OP1與Op2的内部架構相對較複雜，故造成高之功率消耗， 5 200929868 且其亦需額外產生該兩個參考電壓VH與VL。 面對今日能源危機與全球暖化現象之挑戰，以及配合 在積體電路中具有高密度之電子元件與低之功率消耗的趨 ‘ 勢，本發明之目的在於提供一具有高讀出速率、低切換雜 訊以及低功率消耗之輸出預置電路。 職是之故，發明人鑒於習知技術之缺失，終能提出本 案之「具低功率消耗之含輸出預置電路的輸出驅動器電路 及其控制方法」。 參 【發明内容】 本案之主要目的在於提供一種具有高讀出速率、低切 換雜訊以及低功率消耗之含輸出預置電路的輸出驅動器電 路。 本案之又一主要目的在於提供一種用於一輸出緩衝器 之輸出預置電路，包含一检鎖，具有一第一輸入端，一第 二輸入端與一輸出端，其中該第一輸入端接收一電力開啟 ❹ 重置信號，該第二輸入端接收該輸出缓衝器之一電壓，該 輸出端產生一栓鎖輸出信號，，一輸出預置裝置，包含一 上拉電路，接收一預置致能信號以及該栓鎖輸出信號，其 中當該預置致能信號活化及該栓鎖輸出信號在一高準位 時，該上拉電路使該輸出緩衝器之該電壓，自一接地準位 增加至一第一準位，以及一下拉電路，接收該預置致能信 號以及該栓鎖輸出信號，其中當該預置致能信號活化及該 栓鎖輸出信號在一低準位時，該下拉電路使該輸出緩衝器 6 200929868 之該電壓，自一電源電壓準位減低至一第二準位。 根據上述之構想，該輸出緩衝器更包括一輸出負載與 一輸出驅動器，該栓鎖更包括一第三輸入端，接收一内部 輸出致能信號，該輸出負載具有一第一端與一接地之第二 端。 根據上述之構想，該上拉電路包括一第一反相器，其 具有一輸入端與一輸出端，該輸入端接收該預置致能信 號，-反及閘，具有—第一輸入端、一第二輸入端與一輪 β A端’該第-輸人端輕合於該第—反相器之該輸出端，該 第二輸入端接收該栓鎖輸出信號，一第二反相器，具有— 輸入端及一輸出端，該輸入端耦合於該反及閘之該輸出 端’以及-第-開關’具有一第一端、一第二端及一控制 端’該第-端接收-電源電麗，該第二端搞合於該輸出負 载之該第-端，且該控制端耗合於該第二反相器之該輸出 ❹ 根據上述之構想，該下拉電路包括—反或閘，具有一 第-輸入端、-第二輸人端及—輸出端，該第—輸 收該預置致能錢，域第4人端純錄鎖輸出作 说’-第三反相器’具有-輸人端與—輪出端，且該輸二 端輕合於該反或閘之該輸出端，及—第二開關具有 =、-第—端與-控制端’該第合該輸出負载之該 第-端，該第二端接地，且該控制料合於 = 之該輸出端。 布一汉相盗 根據上述之構想，該第—_是―N型金氧半導體，該 7 200929868 第二開關是一 P型金氧半導體，該N型金氧半導體當該預置致 能信號活化，且該栓鎖輸出信號在該高準位時導通，該P型金氧 ' 半導體當該預置致能信號活化與該栓鎖輸出信號在該低準位時導 • 通，該第一準位等於該電源電壓與該N型金氧半導體之一臨界電 壓之一差，該第二準位等於該P型金氧半導體的一臨界電壓。 根據上述之構想，當該輸出致能信號不活化、該拴鎖 輸出信號在該高準位，且該内部輸出致能信號活化時，該 輸出驅動器致使該輸出緩衝器之該電壓自該第一準位增加 ❹ 至該電源電壓準位，當該輸出致能信號不活化、該拴鎖輸 出信號在該低準位，且該内部輸出致能信號活化時，該輸 出驅動器致使該輸出緩衝器之該跨壓自該第二準位減低至 一接地準位 根據上述之構想，當該輸出負載之該電壓達到該電源 電壓準位，且該内部輸出致能信號活化時，位在該高準位 之該栓鎖輸出信號被切換至該低準位，且當該輸出負載之 該電壓達到該接地準位，且該内部輸出致能信號活化時， © 位在該低準位之該栓鎖輸出信號被切換至該高準位。 根據上述之構想，該輸出驅動器透過該輸出負載輸出 一數據，且當一外部輸出致能信號降低時，該預置致能信 號自不活化移至活化，其維持在該活化至一預定之期間， 且在該期間之後回復至不活化，以預置該輸出負載之該電 壓。 根據上述之構想，該輸出缓衝器更包括一輸出負載， 該栓鎖更包括一第三輸入端，接收一内部輸出致能信號， 8 200929868 該輸出負載具有一第一端與一接地之第二端β ▲根據上述之構想，該上拉電路包括一及閘，其具有一 致此端、-輸入端與一輸出端’該致能端接收該預置致能 信號，且該輸入端接收該栓鎖輸出信號，一第一開關，具 有第一端、一第二端及一控制端，該第一端接收一電源 電壓’該第二_合於該輸出負載之該第—端，且該控制 端耦合於該及閘之該輸出端。 Ο 〇 根據上述之構想，該下拉電路包括一或閉，具有一第 輸入端、一第二輸入端及一輸出端，該第一輸入端接收 該=置致能信號，且該第二輸入端接收該栓鎖輸出信號， =開關具有一第一端、一第二端與一控制端，該第一 端耦合該輸出負載之該第一端， 端輕合於該或閘之該輸出端。〃第4接地，且該控制 2上述之構想，該輸出緩衝器更包括一輸出驅動 預置致能信號不活化、該栓鎖輸出信號在該高準 二該内部輸出致能信號活化時’該輸 :;負，之該電壓自該第-準位增加至該電源電壓準: 7该預置致能錢不活化、錄鎖“錢在該 4 ’且該内部輸出致能信號活化時，該輸出驅㈣走 輸出負載之該㈣自該第二準位減低至—接地準位。Μ 電路主要目的在於提供—種用於—輸出驅動器 控制方法，其中該輪出驅動器電路包括 與一具一於错夕询®負载 =栓鎖之輸出預置電路’且該栓鎖產 該方法包含下狀步驟：⑷活化-預置致能信2 9 200929868 重置該輸出負載之—電壓，使其自—接地準位增加至 -準位與自-電源電壓準位減低至一第二準位兩者 -，⑻，栓鎖輪^信號在—高準位時，增加該貞载之 壓至該南準位；以及(e)t㈣輸出信號在—低準 低該負載之該電壓至該低準位。 / 根據上述之構想，該控制方法更包括一步驟：（200929868 IX. Description of the Invention: [Technical Field] The present invention is an output driver circuit such as an output buffer circuit, and more particularly an output driver circuit including an output preset circuit having a lower power consumption. [Prior Art] It is now common to use an output driver circuit such as an output buffer circuit having an output preset circuit to drive an output data in an integrated circuit. For example, please refer to the first figure, which shows a circuit diagram of an output preset circuit for an output buffer circuit as disclosed in U.S. Patent No. 4,992,677. In the first figure, the output preset circuit contains two reference voltages (VH and VL), two differential amplifiers (OP1 and OP2), two N-type MOSs (NM0S: M1 and M2), and a capacitor C. (An output load), and one of each of the VH, VL, M2, and 〇C terminals is grounded. VH, VL, OP1 and OP2 are used to detect the output level of one of the C voltages, and M1 and M2 are used to preset the voltage of the C to VH or VL. When the voltage of C is higher than VH, M2 turns on and Ml turns off the voltage of C below to VH. When the voltage of C is lower than VL, Ml turns on and M2 turns off the voltage of C above to VL. Although the output preset circuit shown in the first figure has a high readout rate and low noise, the main disadvantage is that the internal structures of the two differential amplifiers OP1 and Op2 are relatively complicated, thereby causing high Power consumption, 5 200929868 and it is also necessary to additionally generate the two reference voltages VH and VL. Facing the challenges of today's energy crisis and global warming, and the trend of high-density electronic components and low power consumption in integrated circuits, the object of the present invention is to provide a high readout rate and low An output preset circuit that switches noise and low power consumption. As a result of the job, the inventor can finally propose the "output driver circuit with low power consumption and output control circuit and its control method" in view of the lack of the prior art. The main purpose of the present invention is to provide an output driver circuit including an output preset circuit having a high read rate, low switching noise, and low power consumption. Another main object of the present invention is to provide an output preset circuit for an output buffer, comprising a check lock having a first input end, a second input end and an output end, wherein the first input end receives a power-on ❹ reset signal, the second input receives a voltage of the output buffer, the output generates a latch output signal, and an output preset device includes a pull-up circuit to receive a preset An enable signal and the latch output signal, wherein when the preset enable signal is activated and the latch output signal is at a high level, the pull-up circuit causes the voltage of the output buffer to be from a ground level Adding to a first level, and pulling down the circuit, receiving the preset enable signal and the latch output signal, wherein when the preset enable signal is activated and the latch output signal is at a low level, The pull-down circuit reduces the voltage of the output buffer 6 200929868 from a power supply voltage level to a second level. According to the above concept, the output buffer further includes an output load and an output driver, the latch further includes a third input terminal for receiving an internal output enable signal, the output load having a first end and a ground Second end. According to the above concept, the pull-up circuit includes a first inverter having an input end and an output end, the input end receiving the preset enable signal, the anti-gate, having a first input terminal, a second input end is coupled with a round of β A terminal 'the first input terminal to the output end of the first inverter, the second input terminal receives the latch output signal, a second inverter, Having an input terminal and an output terminal coupled to the output terminal of the opposite gate and the -first switch having a first end, a second end and a control end 'the first end receiving - a power supply, the second end is engaged with the first end of the output load, and the control end is consuming the output of the second inverter. According to the above concept, the pull-down circuit includes an inverse or a gate , having a first input terminal, a second input terminal, and an output terminal, the first receiving and receiving the preset enabling money, and the fourth human terminal pure recording lock output is said to be a 'third inverter' Having a - input end and a round end, and the input end is lightly coupled to the output end of the reverse or gate, and - the second switch has =, - End - the control terminal 'of the first engagement section of the output load of the - terminal, the second terminal is grounded, and the control material bonded to the output terminal of =. According to the above concept, the first _ is an N-type MOS, the 7 200929868 second switch is a P-type MOS, and the N-type MOS is activated by the preset enable signal. And the latch output signal is turned on at the high level, and the P-type metal oxide semiconductor is turned on when the preset enable signal is activated and the latch output signal is at the low level, the first standard The bit is equal to a difference between the supply voltage and a threshold voltage of the N-type MOS, the second level being equal to a threshold voltage of the P-type MOS. According to the above concept, when the output enable signal is not activated, the shackle output signal is at the high level, and the internal output enable signal is activated, the output driver causes the voltage of the output buffer to be from the first The level is increased to the power supply voltage level. When the output enable signal is not activated, the shackle output signal is at the low level, and the internal output enable signal is activated, the output driver causes the output buffer to The voltage across the second level is reduced to a ground level. According to the above concept, when the voltage of the output load reaches the power supply voltage level, and the internal output enable signal is activated, the bit is at the high level. The latch output signal is switched to the low level, and when the voltage of the output load reaches the ground level and the internal output enable signal is activated, the latch bit outputs the bit at the low level The signal is switched to this high level. According to the above concept, the output driver outputs a data through the output load, and when an external output enable signal is lowered, the preset enable signal is moved from inactive to activated, and is maintained during the activation to a predetermined period. And return to inactive after this period to preset the voltage of the output load. According to the above concept, the output buffer further includes an output load, and the latch further includes a third input terminal for receiving an internal output enable signal, 8 200929868. The output load has a first end and a grounded first According to the above concept, the pull-up circuit includes a gate having a coincident end, an input terminal and an output terminal, the enable terminal receiving the preset enable signal, and the input terminal receives the a latching output signal, a first switch having a first end, a second end, and a control end, the first end receiving a power supply voltage 'the second end is coupled to the first end of the output load, and the A control terminal is coupled to the output of the AND gate. According to the above concept, the pull-down circuit includes a first or a closed end having a first input end, a second input end and an output end, the first input end receiving the = set enable signal, and the second input end Receiving the latch output signal, the = switch has a first end, a second end and a control end, the first end coupling the first end of the output load, and the end is lightly coupled to the output end of the OR gate. 〃 4th grounding, and the control 2 is as described above, the output buffer further includes an output driving preset enable signal not activated, and the latch output signal is activated when the internal output enable signal is activated by the high level 2 : negative, the voltage is increased from the first level to the power supply voltage level: 7 the preset enable energy is not activated, the recording "money is in the 4" and the internal output enable signal is activated, the output The drive (4) takes the output load (4) from the second level to the ground level. The main purpose of the circuit is to provide a method for controlling the output driver, wherein the wheel drive circuit includes one and one fault.询 ® ® load = latching output preset circuit 'and the latching method includes the following steps: (4) activation - preset enable signal 2 9 200929868 reset the output load - voltage, self-ground The level is increased to - the level and the self-supply voltage level is reduced to a second level - (8), when the latching wheel ^ signal is at the - high level, the pressure of the load is increased to the south level And (e) t (four) the output signal at - low and low the voltage of the load This low level. / Of the above conception, the control method further comprises a step of :(
Ο 一第一狀態與—第二狀態兩者其中之―，該第-狀態是春 該預置致能信號不活化、該栓鎖輸出信號在—高準位，: 該栓鎖所接收之-内部輸出致能信號活化時，該輸出 之該電壓自該第-準位增加至該電源電壓準位，該第 態是當該預置致能信號不活化、該栓鎖輸出信號在一低 位’且該内部輪出致能信號活化時，該輸出 自該第二準位減低至一接地準位。 /電壓 根據上述之構想，該步驟⑷更包括下列之步驟 當該輸出貞狀該電輯_電源電壓準位，且該 出致能信號活化時，_該检鎖輸出信號自該高準位至^ 低準位；以及(d2)當該輸出負載之該電壓達到該接地； 位’且該㈣輸纽能錢活 ⑽ 自該低準位至該高準位。 職魂 根據^述之構想’該輪出預置電路更包括—輪出預置襄置， /、具二上拉電路與—下拉電路，且該步驟⑷更包括下列之步驟： (al)、田外αρ輪出致能信號降低時，切換該預置致能信號自不活 化至活化躲持在活化至—預定之綱，且在該細之後回復 至不活化以預置該輸出貞載之該電壓；⑽當該栓鎖輸出信 200929868 號在該高準位時，導通該第一開關且關斷該第二開關，致使該輸 出負載之該電壓自該接地準位增加至該第一準位；以及（a3)當該 栓鎖輸出信號在該低準位時，關斷該第一開關且導通該第二開 ' 關，致使該輸出負載之該電壓自該電源電壓準位減低至該第二準 位。 根據上述之構想，該第一開關是一 N型金氧半導體，該第 二開關是一 P型金氧半導體，該第一準位等於該電源電壓與該N 型金氧半導體之一臨界電壓之一差，該第二準位等於該P型金氧 ❹ 半導體的一臨界電壓。 為了讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明 如下： 【實施方式】 請參看第二圖，其係顯示一依據本發明構想之輸出驅 動器電路之方塊圖。本發明所提出之輸出驅動器電路包括 〇 一輸出預置電路、一輸出驅動器、以及一輸出負載。該輸 出預置電路包括一栓鎖，其接收一輸出負載之一電壓， DPAD，及產生一上拉信號與一下拉信號，以及一輸出預置 裝置，當其位於一「預置開始」階段時，係處在一第一狀 態與一第二至狀態兩者其中之一，該第一狀態為其接收一 上拉信號及將該輸出緩衝器之該電壓DPAD，自一接地準位 (例如，GND(O))上拉至一第一準位（例如，該電源電壓準 位與該N型金氧半導體之一臨界電壓的一差，Vdd_VTN)，該第二 11 200929868 狀態為其接收一下拉信號及將該輸出負載之該電壓 DPAD，自一電源電壓準位(例如，vdd)下拉至一第二準位 (例如，VTP’其中VTP是P型金氧半導體之一臨界電壓）。當其 位於一「輸出開始」階段時’該輸出驅動器，係利用:將 該輸出負載之電壓’從該第一準位上拉至該電源電壓準 位’或從該第二準位下拉至該接地準位。在所提出之輸出 驅動器電路之各元件中，該栓鎖可以是任何類型之检鎖， 例如’一D型栓鎖或一D型正反器，該輸出驅動器可以是任 β 何類型之輸出驅動器’例如，一輸出缓衝器，且該輸出負 載可以是任何類型之輸出負載，例如，一電容器。 在第三圖（a)中’其係顯示一依據本發明構想之第一與 第二較佳實施例中，用於一輸出驅動電路的輸出預置電路 之一检鎖的電路不意圖。該检鎖具有·一第一輸入端，一第 二輸入端、一第三輸入端與一輸出端，其中該第一輸入端 用於接收一電力開啟重置信號POR，該第二輸入端用於接 收該輸出負載之一電壓DPAD，該第三輸入端用於接收一内 ❿ 部輸出致能信號HIZB，該輸出端產生一栓鎖輸出信號 DQB。該栓鎖輸出信號DQB透過設定在一高準位之該電力 開啟重置信號POR被初始化至一高準位。 參閱第三圖（b)，其係顯示一依據本發明構想之第一較 佳實施例中，用於一輸出驅動器電路之一輸出預置裝置、 一輸出驅動器及一輸出負載的電路示意圖。該依據本發明 構想之第一較佳實施例所提出之輸出驅動器電路，包括一 輸出預置電路、一輸出驅動器以及一輸出負載。在其中， 12 200929868 該輸出驅動器是耦合於該輸出負載，且該輸出預置電路包 括如第二圖（a)所示之該栓鎖以及一輸出預置裝置。該輸出 負載是一第一電容器d，且具有一第一端與一第二端，該 第二端耦接於—地GND。該輸出預置裝置包含一上拉電 路，包括一第一反相器IV1，具有一輸入端，接收一預置致 能信號OEOBTRIB以及一輸出端，一反及閘ND1具有一第 一輸入端耦合於該第一反相器IV1之該輸出端，一第二輸入 端，接收該栓鎖輸出信號DqB以及一輸出端，一第二反相 ❹ 器1V2 ’具有—輪入端耦合於該反及閘ND1之該輸出端，與 一輸出端，以及一第一開關Ml( —N型金氧半導體），具有 一第一端接收該電源電壓Vdd，一第二端耦合於該輸出負載 C1之該第一端，以及一控制端耦合於該第二反相器1¥2之 輸出端，以及一下拉電路，包括一反或閘NR1，具有一第 一端接收該預置致能信號OEOBTRIB，一第二端接收該栓 鎖輸出信號DQB，以及一輸出端，一第三反相器以3，具有 一輸入端耦合於該反或閘NR1之輸出端，與一輸出端，及 ❹一第二開關M2,具有一第一端耦合於該輸出負載C1之該第 一端，一第二端耦合於該接地GND，以及一控制端耦合於 該第三反相器IV3之輪出端。該上拉與該下拉信號如第二圖 所示’且各該信號包括該預置致能信號〇E〇BTRIB以及該 检鎖輸出#號DQfi。 在第三圖中，當該預置致能信號OEOBTRIB在一低 準位及該栓鎖輪出信號DQB在一高準位時，該上拉電路使 該輸出負載之該電壓DPAD自一接地準位(GND(O))增加至 13 200929868 該第一準仇(例如，該電源電壓準位與該N型金氧半導體之一 臨界電壓的一差：Vdd_-_V™)，當該預置致能信號OEOBTRIB 及該栓鎖輸出信號DQB均在一低準位時，該下拉電路使該 •輸出負载之該電壓DPAD，自一電源電壓準位Vdd減低至〜 第二準位（例如，Ο a first state and a second state, wherein the first state is that the preset enable signal is not activated, the latch output signal is at a high level, and the latch is received. When the internal output enable signal is activated, the voltage of the output is increased from the first level to the power supply voltage level, and the first state is when the preset enable signal is inactive and the latch output signal is in a low position. And when the internal wheel-out enable signal is activated, the output is reduced from the second level to a ground level. / Voltage According to the above concept, the step (4) further includes the following steps: when the output is in the state of the power supply voltage level, and the output enable signal is activated, the lock output signal is from the high level to the high level ^ low level; and (d2) when the voltage of the output load reaches the ground; bit 'and the (4) input energy (10) from the low level to the high level. According to the concept of the description of the job, the preset circuit further includes a wheeled preset device, /, a two pull-up circuit and a pull-down circuit, and the step (4) further comprises the following steps: (al), When the field αρ wheel-out enable signal is lowered, the preset enable signal is switched from inactive to activated to be activated to a predetermined sequence, and after the fine is returned to inactive to preset the output load. The voltage; (10) when the latch output letter 200929868 is at the high level, turning on the first switch and turning off the second switch, causing the voltage of the output load to increase from the ground level to the first standard And (a3) when the latch output signal is at the low level, turning off the first switch and turning on the second switch 'off, causing the voltage of the output load to decrease from the power supply voltage level to the Second level. According to the above concept, the first switch is an N-type MOS, the second switch is a P-type MOS, and the first level is equal to the power supply voltage and a threshold voltage of the N-type MOS. A second level is equal to a threshold voltage of the P-type MOS semiconductor. The above described objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims appended claims A block diagram of an output driver circuit in accordance with the teachings of the present invention is shown. The output driver circuit of the present invention includes an output pre-set circuit, an output driver, and an output load. The output preset circuit includes a latch that receives a voltage of an output load, a DPAD, and generates a pull-up signal and a pull-down signal, and an output preset device when it is in a "preset start" phase. One of a first state and a second state, the first state receiving a pull-up signal and the voltage DPAD of the output buffer from a ground level (eg, GND(O)) is pulled up to a first level (for example, a difference between the power supply voltage level and a threshold voltage of the N-type MOS, Vdd_VTN), and the second 11 200929868 state is received for pulling The signal and the voltage DPAD of the output load are pulled down from a supply voltage level (eg, vdd) to a second level (eg, VTP' where VTP is a threshold voltage of a P-type MOS). When it is in an "output start" phase, the output driver uses: pulls the voltage of the output load from the first level to the power supply voltage level or pulls down from the second level to the Grounding level. In each of the components of the proposed output driver circuit, the latch can be any type of lock, such as a 'D-type latch or a D-type flip-flop, which can be any type of output driver 'For example, an output buffer, and the output load can be any type of output load, for example, a capacitor. In the third diagram (a), it is shown that in the first and second preferred embodiments in accordance with the teachings of the present invention, the circuit for unlocking one of the output preset circuits for an output drive circuit is not intended. The check lock has a first input end, a second input end, a third input end and an output end, wherein the first input end is configured to receive a power on reset signal POR, and the second input end is used Receiving a voltage DPAD of the output load, the third input is for receiving an internal output enable signal HIZB, and the output generates a latch output signal DQB. The latch output signal DQB is initialized to a high level by the power on reset signal POR set at a high level. Referring to Fig. 3(b), there is shown a circuit diagram of an output presetting device, an output driver and an output load for an output driver circuit in a first preferred embodiment in accordance with the teachings of the present invention. The output driver circuit according to the first preferred embodiment of the present invention includes an output preset circuit, an output driver, and an output load. In which 12 200929868 the output driver is coupled to the output load, and the output preset circuit includes the latch as shown in the second figure (a) and an output preset device. The output load is a first capacitor d and has a first end and a second end, and the second end is coupled to the ground GND. The output presetting device comprises a pull-up circuit, comprising a first inverter IV1, having an input terminal for receiving a preset enable signal OEOBTRIB and an output terminal, and a reverse gate ND1 having a first input coupling At the output end of the first inverter IV1, a second input terminal receives the latch output signal DqB and an output terminal, and a second inverter device 1V2' has a wheeled end coupled to the opposite end. The output end of the gate ND1, and an output terminal, and a first switch M1 (N-type metal oxide semiconductor) having a first end receiving the power supply voltage Vdd and a second end coupled to the output load C1 The first end, and a control end coupled to the output end of the second inverter 1¥2, and the pull-down circuit, including a reverse OR gate NR1, having a first end receiving the preset enable signal OEOBTRIB, The second end receives the latch output signal DQB, and an output terminal, a third inverter is 3, has an input coupled to the output of the inverse or gate NR1, and an output terminal, and a second The switch M2 has a first end coupled to the first output of the output load C1 The second terminal is coupled to the ground GND, and a control terminal is coupled to the wheel terminal of the third inverter IV3. The pull-up and the pull-down signal are as shown in the second figure' and each of the signals includes the preset enable signal 〇E〇BTRIB and the check-lock output # number DQfi. In the third figure, when the preset enable signal OEOBTRIB is at a low level and the latching wheel signal DQB is at a high level, the pull-up circuit causes the voltage DPAD of the output load to be self-grounded. Bit (GND(O)) is increased to 13 200929868. The first vengeance (for example, the difference between the power supply voltage level and a threshold voltage of the N-type MOS: Vdd_-_VTM), when the preset When the energy signal OEOBTRIB and the latch output signal DQB are both at a low level, the pull-down circuit reduces the voltage DPAD of the output load from a power supply voltage level Vdd to a second level (for example,
Vtp， 其中Vtp是P型金氧半導體之一臨 壓）。此外當該預置致能信號OEOBTRIB在一高準位、該拾 鎖輸出信號DQB在該高準位，且該内部輸出致能信說 HIZB在一高準位時，該輸出驅動器致使該輸出負載之讀^ ❹壓DPAD自該第一準位Vdd - V™增加至該電源電壓準位 Vdd’當該預置致能信號OEOBTRIB不活化、該栓鎖輪出作 號DQB在該低準位，且該内部輸出致能信號HIZB在請高 準位時’該輸出驅動器致使該輸出負載之該電壓dpAd自 該第二準位Vtp減低至一接地準位GND(O)。此外，當該輪 出負載之該電壓DPAD達到該電源電壓準位Vdd，且該内部 輸出致能信號HIZB在該高準位時，該栓鎖輸出信號 自該高準位切換至該低準位，且當該輸出負載之該電壓 〇 DPAD達到該接地準位GND(〇)，且該内部輸出致能信鞔 HIZB在該高準位時’該栓鎖輸出信號dqb自該低準仅切 換至該高準位。該電力開啟重置信號與該預置致能信衆可 以依據設計者之定義而為低準位活化或高準位活化。在本 較佳實施例中’該預置致能信號〇E〇BTRIB在低電壓準位活 化’而在高電壓準位不活化。 請參看第三圖（c) ’其係顯示一依據本發明構想之第二 較佳實施例中，用於一輸出驅動電路之一輸出預置裝置、 14 200929868 一輸出驅動器及一輸出負載的電路示意圖。其中該及閘 AND1 ’其具一致能端、一輸入端與一輸出端是如該第三圖 (b)所示該反及閘ND1，該第一反相器ινί以及該第二反相 * 器IV2之一等效電路，該或閘OR1，其具一第一輸入端、 一第二輸入端與一輸出端是如該第三圖（b)所示該反或間 NR1與該第三反相器IV3之一等效電路，且第三圖（c)其餘 部分與第三圖（b)之其餘部分相同。另’如第三圖（a)與第三 圖（c)所示之輸出預置電路的運作原理與如第三圖（a)與第 ❹ 三圖（b)所示之輸出預置電路的運作原理相同。 參考第四圖0)，其係顯示一依據本發明構想之第一與 第二較佳實施例中的該電力開啟重置信號，p〇R，該栓鎖 輸出信號，DQB，内部輸出致能信號’ HIZB，該外部輸出 致能信號，OEB，該預置致能信號’ OEOBTRIB，該輸出 負載之該電壓，DPAD ’及流經Vdd之電流，IVDD，等各 自對應於時間之波形圖。其中’該栓鎖輸出信號’ DQB， 透過設定在一高準位之該電力開啟重置信號’ POR，被初 〇 始化至一高準位。當該輸出負載之該電壓DPAD達到該電 源電壓準位Vdd，立該内部輸出致能信號，HIZB’活化時， 該栓鎖輸出信號，DQB，自該高準位切換至該低準位，且 當該輸出負載之該電壓，DPAD，達到該接地準位， GND(〇)，且該内部輸出致能信號，HIZB，活化時，該检鎖 輸出信號DQB自該低準位切換至該高準位。當該「輸出開 始階段」開始時，該内部輸出致能信號’ HIZB ’自不活化 切換至活化，當該「輸出開始階段」結束時’該内部輸出 15 200929868 致能信號，HIZB，自活化切換至不活化，當一外部輸出致 能信號OEB降低時，該預置致能信號OEOBTRIB自不活 化移至活化，其維持在該低準位至一預定之期間（例如， 20ns)，且在該期間之後回復至該高準位，以預置該輸出負 載之該電壓DPAD。該DPAD之曲線顯示，該輸出負载之 該電壓在該「預置開始」階段，首先透過該輸出預置農置 自一接地準位（GND(O))上拉至該第一準位(例如，該vdd與 N型金氧半導體之一臨界電壓的一差：Vdd_VTN)，其次在該「輸 ❹ 出開始」階段藉由該輸出驅動器從該第一準位上拉至該電 源電壓準位，Vdd。其中該「預置開始」階段，維持一預定 之期間（例如’在本案例中是20ns)，該VTN是近似於〇. 7v， 以及該Vdd等於3v。IVDD是流經N型金氧半導體Ml(具 一臨界電壓：V™)及輸出負載之電流，且該IVDD曲線顯示 兩個鏈波。 在第四圖（b)中，其係顯示一依據本發明構想之第一與 第二較佳實施例中的該栓鎖輸出信號Dqb、内部輸出致能 ©信號HIZB、該外部輸出致能信號OEB、該預置致能信號 OEOBTRIB、該輸出負载之該電壓⑽他及流經gnd之電 流IGND等各自對應於時間之波形圖。該DpAD之曲線顯 不’首先該輸出負載之該電壓透過該輸出預置電路被從^ 下拉至該第二準位亦即ντρ(ρ型金氧半導體之—臨界電壓 其次藉由該輸出驅動器從該第二準位下拉至該接地準位， GND(O)。IGND是流經輸出負載及卩型金氧半導體且 p型金氧半導體之該臨界電壓：Vtp)之電流，且該獅曲線 16 200929868 亦顯示兩個鏈波。 由上述_明可知’本發明在於提供 率、低切換雜訊以及低功率消耗之含輪;：南讀出速 驅動器電路。 輸出預置電路的輸出 疋以，縱使本案已由上述之實補所詳細敘述柯由熟悉本 技藝之人士任紐思*為諸般修飾，鮮视如射請專利範圍 所欲保護者。 β 【圖式簡單說明】 第一圖：其係顯示一習知之用於一輸出負載電路的輸出預 置電路之電路示意圖； 第二圖：其係顯示一依據本發明構想之輸出驅動器電路之 方塊圖， 第三圖（a):其係顯示一依據本發明構想之第一與第二較佳 實施例中，用於一輸出驅動電路的輸出預置電路之一栓鎖 的電路示意圖； ❹第三圖（b):其係顯示一依據本發明構想之第一較佳實施例 中，用於一輸出驅動電路之一輸出預置裝置、一輸出驅動 器及一輸出負載的電路示意圖； 第三圖（c):其係顯示一依據本發明構想之第二較佳實施例 中，用於一輸出驅動電路之一輸出預置裝置、—輪出驅動 器及一輸出負載的電路示意圖； 第四圖（a):其係顯示一依據本發明構想之第一與第二較佳 實施例中的該電力開啟重置信號、該栓鎖輸出信號、該内 17 200929868 部輸出致能信號、該外部輸出致能信號、該預置致能信號、 該輸出負載之該電壓及流經vdd之電流等各自對應於時間 之波形圖；以及 第四圖（b):其係顯示一依據本發明構想之第一與第二較佳 實施例中的該栓鎖輸出信號、内部輸出致能信號、該外部 輸出致能信號、該預置致能信號、該輸出負載之該電壓及 流經GND之電流等各自對應於時間之波形圖。 〇 【主要元件符號說明】 無 ❹ 18Vtp, where Vtp is one of the P-type MOS semiconductors). In addition, when the preset enable signal OEOBTRIB is at a high level, the pickup output signal DQB is at the high level, and the internal output enable signal HIZB is at a high level, the output driver causes the output load The reading DP is increased from the first level Vdd - VTM to the power supply voltage level Vdd'. When the preset enable signal OEOBTRIB is not activated, the latching wheel DQB is at the low level. When the internal output enable signal HIZB is at a high level, the output driver causes the voltage dpAd of the output load to be reduced from the second level Vtp to a ground level GND(0). In addition, when the voltage DPAD of the wheel load reaches the power voltage level Vdd, and the internal output enable signal HIZB is at the high level, the latch output signal is switched from the high level to the low level. And when the voltage 〇DPAD of the output load reaches the grounding level GND(〇), and the internal output enable signal HIZB is at the high level, the latch output signal dqb is only switched from the low level to The high level. The power-on reset signal and the preset enable believer can be activated for low level activation or high level according to the designer's definition. In the preferred embodiment, the preset enable signal 〇E 〇 BTRIB is activated at a low voltage level and is not activated at a high voltage level. Please refer to FIG. 3(c), which shows a circuit for outputting a preset device, an output driver, an output driver and an output load in a second preferred embodiment according to the present invention. schematic diagram. Wherein the gate AND1' has a uniform energy end, an input end and an output end are the reverse gate ND1 as shown in the third figure (b), the first inverter ινί and the second inversion* An equivalent circuit of the device IV2, the OR gate OR1 having a first input end, a second input end and an output end as shown in the third figure (b), the reverse or intermediate NR1 and the third One of the inverters IV3 is equivalent, and the rest of the third figure (c) is the same as the rest of the third figure (b). The operation principle of the output preset circuit as shown in the third figure (a) and the third figure (c) and the output preset circuit as shown in the third figure (a) and the third figure (b) The principle of operation is the same. Referring to FIG. 4), the power-on reset signal in the first and second preferred embodiments according to the present invention is shown, p〇R, the latch output signal, DQB, and internal output enable. The signal 'HIZB, the external output enable signal, OEB, the preset enable signal 'OEOBTRIB, the voltage of the output load, DPAD' and the current flowing through Vdd, IVDD, etc. each correspond to a waveform of time. The 'lock-up output signal' DQB is initially initialized to a high level by the power-on reset signal 'POR' set at a high level. When the voltage DPAD of the output load reaches the power supply voltage level Vdd, the internal output enable signal is asserted, and when the HIZB' is activated, the latch output signal, DQB, is switched from the high level to the low level, and When the voltage of the output load, DPAD, reaches the grounding level, GND (〇), and the internal output enable signal, HIZB, is activated, the lock output signal DQB is switched from the low level to the high level Bit. When the "output start phase" starts, the internal output enable signal 'HIZB' switches from inactive to active. When the "output start phase" ends, the internal output 15 200929868 enable signal, HIZB, self-activation switch Until activated, when an external output enable signal OEB decreases, the preset enable signal OEOBTRIB moves from inactive to activated, which is maintained at the low level for a predetermined period (eg, 20 ns), and After the period, it returns to the high level to preset the voltage DPAD of the output load. The curve of the DPAD shows that the voltage of the output load is first pulled up from the grounding level (GND(O)) to the first level through the output preset in the "preset start" phase (for example a difference between the threshold voltage of the Vdd and the N-type MOS: Vdd_VTN), and secondly, the output driver is pulled up from the first level to the power supply voltage level by the output driver during the “start of output” phase. Vdd. The "preset start" phase is maintained for a predetermined period (e.g., 20 ns in this case), the VTN is approximately 〇. 7v, and the Vdd is equal to 3v. IVDD is a current flowing through the N-type MOS M1 (having a threshold voltage: VTM) and an output load, and the IVDD curve shows two chain waves. In the fourth diagram (b), the latch output signal Dqb, the internal output enable signal HIZB, and the external output enable signal in the first and second preferred embodiments according to the present invention are shown. The OEB, the preset enable signal OEOBTRIB, the voltage (10) of the output load, and the current IGND flowing through the gnd are each corresponding to a waveform of time. The curve of the DpAD is not 'firstly the voltage of the output load is pulled from the ^ to the second level through the output preset circuit, that is, ντρ (the ρ-type MOS-critical voltage is secondarily used by the output driver) The second level is pulled down to the ground level, GND(O). The IGND is the current flowing through the output load and the MOSFET and the threshold voltage of the p-type MOS: Vtp), and the lion curve 16 200929868 also shows two chain waves. It is apparent from the above that the present invention resides in a wheel including a rate, a low switching noise, and a low power consumption; a south sense speed driver circuit. The output of the pre-set circuit is outputted, even if the case has been described in detail by the above-mentioned actual supplement, Ke Ren, who is familiar with the art, is modified as such, and the image is intended to be protected by the scope of the patent. β [Simplified description of the figure] The first figure shows a circuit diagram of a conventional output presetting circuit for an output load circuit. The second figure shows a block of an output driver circuit according to the present invention. Figure 3 is a circuit diagram showing a latching of one of the output preset circuits for an output drive circuit in accordance with the first and second preferred embodiments of the present invention; FIG. 3(b) is a schematic diagram showing a circuit for outputting a preset device, an output driver and an output load in an output driving circuit according to a first preferred embodiment of the present invention; (c): a schematic diagram showing a circuit for outputting a preset device, a wheel-out driver and an output load in an output driving circuit according to a second preferred embodiment of the present invention; a): showing the power-on reset signal, the latch output signal, the inner 17 200929868 output enable signal, and the external output in the first and second preferred embodiments according to the present invention a signal, a preset enable signal, a voltage of the output load, a current flowing through the vdd, and the like, each corresponding to a waveform of time; and a fourth diagram (b): showing a first aspect in accordance with the inventive concept The latch output signal, the internal output enable signal, the external output enable signal, the preset enable signal, the voltage of the output load, and the current flowing through the GND in the second preferred embodiment respectively correspond to Waveform of time. 〇 [Main component symbol description] None ❹ 18