200929542 九、發明說明： 相關申請的交又引用 本申請是2007年9月11日提交的、共同申請的美國專利申請N〇 11/900,616、名稱為POWER MOS DEV丨CE的部分纊續申請，也是 2005年2月11日提交的、美國專利申請No· 11/056,346 (現在的專 利號為7,285,822)、名稱為POWER MOS DEV丨CE的繼績申請，出於 所有目的’將上述兩個文獻在此引入。 【發明所屬之技術領域】 0 本發明係有關一種金屬氧化物半導艘（MOS)元件及其製造方法。 【先前技術】 功率MOS元件通常在電子電路中使用。取決於應用，可能期待不 同的元件特性。一個範例應用是DC_DC轉換器，其包括一個功率M〇s 元件作為同步整流器（也稱為低端FET)，和另一個功率M〇s元件作 為控制開關（也稱為高端FET)。低端FET通常要求較小的導通電阻， 以便獲得較好的功率開關效率。高端FET通常要求較小的閘極電容， 以獲得快速開關和良好性能。 電晶體的導通電阻（Rdson)值通常與通道長度（L)成正比，與每 〇 單位面積（w)上的线單元數量成反比。#選擇RdsQn的值時，應當 考慮性能和擊穿電壓之間的權衡。為了減小Rds〇n的值，可以通過使用 較，的源極和本體來減小通道長度，以及可以通過減小單元尺寸來增大 每單位面積的單元數量。然而，由於擊穿現象，通道長度L通常受到限 制。每單位Φ積的單元數量也由於製造技術以及由於需要使單元的源極 區和本體區良好接觸而受到限制◦隨著通道長度和單元密度的増大，閘 極電容也増大。為了減小開關的損耗，較低的元件電容是優選的。在某 些應用（諸如’同步整流）中’存儲的電荷以及本體二極體的正向壓降 也會導致效率損耗。這些因素一起便限制了 DM〇s功率元件的性能。 5 200929542 值得期待的是，如果DMOS功率元件的導通電阻和閘極電容能夠 低於當前可達的水準，功率開關的可靠性和功率消耗都會改善。還可能 有用的是’開發出實用的製程，該製程能夠可靠地製造出改進的DM〇s 功率元件。 【發明内容】 為此，本發明提供了一種半導體元件及其製造方法，使得改善功率 開關的可靠性和功率消耗。 本發明提供一種形成在半導體基底上的半導體元件，包括：汲極； ❹覆蓋所述汲極的磊晶層；以及主動區，包括：本體，所述本體置於所述 磊晶層令，並具有本體頂表面；源極嵌入在所述本體中，並從所述本體 頂表面延伸至所述本體中；閘極溝槽延伸至所述磊晶層中；閘極置於所 述閘極溝槽中；主動區接觸溝槽係延伸通過所述源極並延伸到所述本體 中，主動區接觸電極則置於所述主動區接觸溝槽内；其中本體區的薄層 將所述主動區接觸電極與所述汲極分開。 另一方面，本發明提供一種製造半導體元件的方法，包括：在覆蓋 ，導體基底的蟲晶層巾形細極溝槽；在所述閘極溝槽中沉積閘極材 料，形成本體；形成源極；形成主動區接觸溝槽，所述主動區接觸溝槽 ❹延伸通過所I雜並延輕所述本财；以及在㈣絲區接觸溝槽内 沉積接觸電極；其中’本體區的薄層將所述主動區接觸電極與所述 分開。 底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發 明之目的、技術内容、特點及其所達成之功效。 【實施方式】 本發明可以衫種方式實現，包括實現為製程、裝置、祕、物的 組合、電腦可讀媒介，諸如，電腦可讀存儲媒介，或者電腦網路，其中， 程式指令被通過光鏈結或者通信鏈結發送^在本說明書中，這些實現， 或者本發明可啸㈣任何其他形^，都可哺為技術^被描述成“被 6 200929542 配置為執行任務的元件”（諸如處理器或者記憶體）既包括通用元件（其 被臨時配置為在給定時間執行任務）也包括專用元件（其被製造以執行 任務）。通常’在本發明範圍内，所公開的製程步驟的順序可以改變。 本發明的一個或多個實施例的具體描述在以下與表示本發明原理 的附圖一起提供。雖然結合這樣的實施例描述了本發明，但是本發明並 不限於任何實施例。本發明的範圍僅由申請專利範圍來限定，並且本發 明涵蓋了多種替代方式、改進以及等效物。在以下描述中提供多種具體 的細節是為了提供本發明的全面理解。這些細節是處於範例的目的而提 供的，並且本發明可以根據權利要求來實現，而無需這些具體細節的某 ❹些或者全部。為了清楚的目的，在有關本發明的技術領域中公知的技術 材料並沒有詳細描述，以避免本發明被不必要地混淆。 對金屬氧化物半導髏（MOS)元件及其製造進行描述。出於範例 的目的，在本說明書中詳細討論N通道元件，其具有N型材料製成的 源極和汲極以及P型材料製成的本體◦在此公開的技術和結構也適用 於P通道元件。 第1A-1F圖示出了若干雙擴散金屬氧化物半導體（DM〇s)元件 的實施例。第1A圖是DMOS元件的實施例的橫截面視圖。在此範例 中，元件100包括汲極，其形成在N+型半導體基底1〇3的背面。汲極 區延伸到覆蓋了基底103的、N.型半導體的磊晶（印丨）層1〇4中。在 蟲晶層104中#刻出閘極溝槽（諸如in、I”和115)。閘極氧化物 層121形成在閘極溝槽内。閘極131、133和135分別佈置在問極溝 槽111、113和115内，並且通過氧化物層而與蟲晶層絕緣。閉極是由 諸如多晶⑦（poly)的導電材料製成的，*氧化物層是由諸如熱氧化物 的絕緣材料製成的。具體地，閘極溝槽川位於端接區（termination region )巾’該端接區佈置有絲連接至_接觸金屬賴極導線(gate mnner) 131。出於該目的，與主動閘極溝槽113和115相比，閘極導 線溝槽111可以更寬且更深。進一步地，閘極導線溝槽川和其相鄰 7 200929542 的主動溝槽（在此情況下為溝槽113)之間的間距可以比主動閘極溝槽 113和115之間的間距大。 源極區150a-150d分別嵌入本體區I40a-140d中。源極區從本艘 的頂表面向下延伸到本體本身中。儘管本體區沿著所有閘極溝槽的側部 被植入’但是源極區僅僅在鄰近主動閘極溝槽處被植入，而不在閘極導 線溝槽處被植入。在所示實施例中，諸如133的閘極具有閘極頂表面， 該閘極頂表面基本上在嵌入有源極的本體的頂表面之上延伸。這樣的配 置保證了閘極和源極的重疊，從而允許源極區比具有凹陷閘極的元件的 内源極區淺，並且這樣的配置增大了元件的效率和性能。閘極多晶矽頂表 ® 面在源極-本體接面之上延伸的量可以針對不同實施例而改變。在某些 實施例中，元件的閘極不在源極區/本體區的頂表面上延伸，而是從源 極區/本艘區的頂表面凹陷。 在操作期間，汲極區和本體區一起作為二極體的作用，稱為本體二 極體。介電材料層160被佈置於閘極的上面，以便將閘極與源極_本體 接觸絕緣。介電材料在閘極的頂上以及在本體區和源極區的頂上形成了 絕緣區’諸如160a-160c。適當的介電材料包括熱氧化物、低溫氧化物 (LTO)、硼磷矽玻璃（BpSG)等。 q 大量的接觸溝槽112a-112b形成在源極區和本體區附近的主動閘 極溝槽之間。這些溝槽被稱為主動區接觸溝槽，因為這些溝槽鄰近元件 的主動區（由源極區和本體區形成的> 例如，接觸溝槽112a延伸通 過源極和本體’形成了鄰近溝槽的源極區150a_150b和本體區 140a-140b。相反，形成在閘極導線131頂上的溝槽117並不位於主 動區附近，因此，溝槽117不是主動區接觸溝槽。溝槽117被稱為閘 極接觸溝槽或者閘極導線溝槽，因為連接至閘極信號的金屬層172a沉 積在溝槽内。通過溝槽111、113和115之間在第三維度（未示出）中 的互連’將閘極信號饋送給有源閘極133和135。金屬層172a與金屬 層172b分離，金屬層172b通過接觸溝槽1123_1120連接至源極區和 8 200929542 本逋區，以提供電源。在所示範例中，主動區接觸溝槽和閘極接觸溝槽 具有基本上相同的深度。 元件1〇〇具有主動區接觸溝槽112a-112b，它們都比本體淺。此 配置提供了良好的擊穿性能、更低的電阻和更低的洩漏電流。另外，由 於主動接觸溝槽和閘極接觸溝槽是使用一步製程形成的，由此它們具有 相同的深度，所以具有比本體淺的主動接觸溝槽可以避免閘極接觸溝槽 穿過諸如131的閘極導線。 ❹200929542 IX. Invention Description: The application is also a follow-up application filed on September 11, 2007, and the US patent application N〇11/900,616, which is jointly filed, is a part of the subsequent application of POWER MOS DEV丨CE. U.S. Patent Application No. 11/056,346 (now Patent No. 7,285,822), filed on February 11, 2005, entitled POWER MOS DEV 丨 CE, for all purposes 'together the above two documents here Introduced. TECHNICAL FIELD OF THE INVENTION The present invention relates to a metal oxide semiconductor package (MOS) device and a method of fabricating the same. [Prior Art] Power MOS elements are commonly used in electronic circuits. Depending on the application, different component characteristics may be expected. An example application is a DC_DC converter that includes a power M〇s component as a synchronous rectifier (also known as a low-side FET) and another power M〇s component as a control switch (also known as a high-side FET). Low-side FETs typically require less on-resistance for better power switching efficiency. High-side FETs typically require smaller gate capacitance for fast switching and good performance. The on-resistance (Rdson) value of the transistor is usually proportional to the channel length (L) and inversely proportional to the number of line cells per unit area (w). # When choosing the value of RdsQn, the trade-off between performance and breakdown voltage should be considered. In order to reduce the value of Rds〇n, the channel length can be reduced by using the source and the body, and the number of cells per unit area can be increased by reducing the cell size. However, the channel length L is usually limited due to the breakdown phenomenon. The number of cells per unit of Φ product is also limited by manufacturing techniques and due to the need to make the source and body regions of the cell in good contact. As the channel length and cell density increase, the gate capacitance is also large. In order to reduce the loss of the switch, a lower component capacitance is preferred. The charge stored in certain applications (such as 'synchronous rectification') and the forward voltage drop of the body diode can also cause efficiency losses. Together, these factors limit the performance of DM〇s power components. 5 200929542 It is worth expecting that if the on-resistance and gate capacitance of the DMOS power components can be lower than the current level, the reliability and power consumption of the power switches will improve. It may also be useful to develop a practical process that reliably produces improved DM〇s power components. SUMMARY OF THE INVENTION Accordingly, the present invention provides a semiconductor device and a method of fabricating the same that improve reliability and power consumption of a power switch. The present invention provides a semiconductor device formed on a semiconductor substrate, comprising: a drain; an epitaxial layer covering the drain; and an active region comprising: a body, the body being placed in the epitaxial layer, and Having a body top surface; a source embedded in the body and extending from the top surface of the body into the body; a gate trench extending into the epitaxial layer; a gate being disposed in the gate trench In the slot; an active contact trench extends through the source and into the body, and an active contact electrode is disposed in the active contact trench; wherein a thin layer of the body region centers the active region The contact electrode is separated from the drain. In another aspect, the present invention provides a method of fabricating a semiconductor device, comprising: covering a thin-grained trench of a conductor layer of a conductor substrate; depositing a gate material in the gate trench to form a body; forming a source Forming an active region contact trench, the active region contact trench ❹ extending through the impurity and extending the current; and depositing a contact electrode in the (four) silk region contact trench; wherein the thin layer of the 'body region The active area contact electrode is separated from the said. The purpose, technical contents, features, and effects achieved by the present invention will become more apparent from the detailed description of the embodiments of the invention. [Embodiment] The present invention can be implemented in a woven manner, including as a process, a device, a combination of secrets, a computer readable medium, such as a computer readable storage medium, or a computer network, wherein program instructions are passed through the light. Chain or communication link transmission ^ In this specification, these implementations, or the invention can be whistling (4) any other form, can be fed into the technology ^ is described as "components configured to perform tasks by 6 200929542" (such as processing) The device or memory) includes both general purpose components (which are temporarily configured to perform tasks at a given time) and dedicated components (which are manufactured to perform tasks). Generally, the order of the disclosed process steps may vary within the scope of the invention. A detailed description of one or more embodiments of the invention is set forth below in the accompanying drawings in which FIG. Although the invention has been described in connection with such embodiments, the invention is not limited to any embodiment. The scope of the invention is to be limited only by the scope of the invention, and the invention In the following description, numerous specific details are set forth to provide a thorough understanding of the invention. The details are provided for the purpose of example, and the invention may be practiced in accordance with the appended claims. The technical material that is well known in the technical field of the present invention has not been described in detail in order to avoid unnecessarily obscuring the present invention. Metal oxide semi-conductive germanium (MOS) devices and their manufacture are described. For purposes of example, N-channel elements are discussed in detail in this specification, having source and drain electrodes made of N-type materials and bodies made of P-type materials. The techniques and structures disclosed herein are also applicable to P-channels. element. The 1A-1F diagram shows an embodiment of several double-diffused metal oxide semiconductor (DM 〇s) elements. Figure 1A is a cross-sectional view of an embodiment of a DMOS device. In this example, the element 100 includes a drain formed on the back side of the N+ type semiconductor substrate 1〇3. The drain region extends into the epitaxial layer 1〇4 of the N. type semiconductor covering the substrate 103. A gate trench (such as in, I" and 115) is formed in the germane layer 104. A gate oxide layer 121 is formed in the gate trench. Gates 131, 133, and 135 are respectively disposed in the gate trench Inside the grooves 111, 113 and 115, and insulated from the insect layer by an oxide layer. The closed electrode is made of a conductive material such as polycrystalline (poly), and the * oxide layer is insulated by a material such as thermal oxide. Specifically, the gate trench is located in a termination region. The termination region is provided with a wire connected to a contact metal rmner 131. For this purpose, The gate conductor trenches 111 can be wider and deeper than the active gate trenches 113 and 115. Further, the gate conductor trenches and their adjacent 7 200929542 active trenches (in this case trenches) The spacing between 113) may be greater than the spacing between the active gate trenches 113 and 115. The source regions 150a-150d are respectively embedded in the body regions I40a-140d. The source regions extend downward from the top surface of the vessel to In the body itself. Although the body region is implanted along the sides of all gate trenches, the source region is only adjacent The active gate trench is implanted without being implanted at the gate conductor trench. In the illustrated embodiment, the gate such as 133 has a gate top surface that is substantially embedded in the source Extending over the top surface of the body. Such a configuration ensures overlap of the gate and source, thereby allowing the source region to be shallower than the inner and source regions of the component having the recessed gate, and such an arrangement increases the component's Efficiency and performance. The amount of gate polycrystalline top surface® surface extending over the source-body junction can vary for different embodiments. In some embodiments, the gate of the component is not in the source/body region. The top surface extends, but is recessed from the top surface of the source region/the ship region. During operation, the drain region and the body region together function as a diode, referred to as a body diode. Dielectric material layer 160 Arranged above the gate to insulate the gate from the source-body contact. The dielectric material forms an insulating region such as 160a-160c on top of the gate and on top of the body region and the source region. Dielectric materials include thermal oxides, Warm oxide (LTO), borophosphoquinone glass (BpSG), etc. q A large number of contact trenches 112a-112b are formed between the source region and the active gate trench near the body region. These trenches are called active The regions contact the trenches because the trenches are adjacent to the active region of the component (formed by the source region and the body region). For example, the contact trench 112a extends through the source and body ' to form a source region 150a-150b adjacent to the trench and The body regions 140a-140b. Conversely, the trenches 117 formed on top of the gate wires 131 are not located near the active regions, and therefore, the trenches 117 are not active region contact trenches. The trenches 117 are referred to as gate contact trenches or The gate conductor trench is deposited in the trench because the metal layer 172a connected to the gate signal. The gate signal is fed to the active gates 133 and 135 through the interconnections between the trenches 111, 113 and 115 in a third dimension (not shown). The metal layer 172a is separated from the metal layer 172b, and the metal layer 172b is connected to the source region and the base region of the 200929542 through the contact trenches 1123_1120 to provide power. In the illustrated example, the active region contact trench and the gate contact trench have substantially the same depth. Element 1 has active zone contact trenches 112a-112b which are both shallower than the body. This configuration provides good breakdown performance, lower resistance and lower leakage current. In addition, since the active contact trench and the gate contact trench are formed using a one-step process, whereby they have the same depth, having an active contact trench shallower than the body can prevent the gate contact trench from passing through, for example, 131. Gate wire. ❹
G 在所示範例中，FET通道沿著源極/本艘接面和本髏/没極接面之間 的主動區閘極溝槽側壁形成。在具有短通道區的元件中，隨著源極和汲 極之間電壓的增大，空乏區擴大，並且可能最终到達源極接面。這種現 象’稱為擊穿，限制了通道可被縮短的程度。在某些實施例中，為了避 免擊穿，利用P型材料來對諸如沿著主動區接觸溝槽壁的區域 170a-170d的區域進行重摻雜以形成p+型區β p+型區避免了空乏區侵 佔源極區。這樣，這些植入有時稱為抗擊穿植入或者避免擊穿植入。在 某些實施财，為了實現聲稱的抗擊穿效果，p+區盡可能_通道區近 和/或如製造對準能力和P+側壁摻雜渗透控制所允許的那樣近。在某些 實施例中’溝槽接觸和溝槽之間的不對準通過對接觸進行自行對準來最 小化’以及將溝槽接觸盡可能置域近溝槽之間的巾心處。這些結構上 的增強允許通道被脑，娜通道料㈣射 理，的未受賴結射聽料所㈣料電荷。除了料;^觸㊁ 阻穿植入還使得構建非常淺溝槽的短通道元件成為可能。在所 溝槽112a_112b比本體區她侧淺並且不會 在元件的導通電阻1和閘極電容被減小。 觸電極rmr2b^_溝槽117巾佈__形成接 著接觸溝槽的麻Γ，於擊穿植入沿著接觸溝槽的側壁設置，而不沿 ，_接戦極__ 1G4補觸。接觸 電極和没麵-梅了嶋卿（細 9 200929542 二極體減小了本體二極趙正向壓降並將存儲的電荷最小化，使得 MOSFET更加有效率。能夠同時形成到N·没極的蕭特基接觸和到p+ 本體和N+源極的良好的歐姆接觸的一種金屬被用來形成電極 180a-180b。諸如鈦（Ti)、鉑（R)、鈀（Pd)、鎢（w)或者任何其 他適當的金屬都可以使用。在某些實施例中，金屬層172由鋁丨）或 者由Ti/TiN/A丨疊層製成。 蕭特基二極體的洩漏電流與蕭特基能障高度有關。隨著能障高度的 增大，洩漏電流減小，以及正向壓降也增大。在所示範例中，通過在主 ^ 動區溝槽彳12a-<l12b的底部周圍植入薄的摻雜物層，將可選的蕭特基 能障控制層190a-190b (也稱為香農（Shannon)層）形成在接觸電極 之下。在此範例中，摻雜物具有與磊晶層相反的極性，並且屬於p型。 香農植入比較淺並且是低劑量的；因此，完全被耗盡而與偏壓無關。蕭 特基能障控制層用來控制蕭特基能障高度，從而允許對洩漏電流進行更 好的控制，以及改進蕭特基二極體的反向恢復特性。以下描述形成蕭特 基能障控制層的細節。 第1B圖是DMOS元件的另一實施例的橫截面視圖。元件1〇2也 包括蕭特基能障控制層190a-190b，位於主動區接觸溝槽的底部周圍。 Q 在此範例中，閘極接觸溝槽117的深度與主動區接觸溝槽112a-112b 的深度不同。主動區接觸溝槽比本體區14〇a-140d深，並且主動區接 觸溝槽延伸超過了本體區。由於主動接觸溝槽較深，所以主動接觸溝槽 為沿著侧壁製作歐姆接觸提供了更多區域，並且帶來了更好的非箝位元 感應開關（UIS)能力。而且，通過使閘極接觸溝槽比主動接觸溝槽淺’ 閘極接觸溝槽將不太可能在蝕刻製程期間穿透閘極導線多晶矽，而這對 於具有相對淺的閘極多晶矽的元件（諸如，使用這樣製程製造的元件， 即，該製程會導致閘極多晶矽不會在本體的頂表面之上延伸）是有用的。 第1C圖是DMOS元件的另一實施例。在此範例中，閘極接觸溝 槽117和主動區接觸溝槽112a-ll2b具有不同的深度。另外，每個主 200929542 動區接觸溝槽的深度並不一致’因為溝槽深度在平行於基底表面的方向 上會變化。如以下更詳細所述，主動區接觸溝槽是使用兩步製程形成 的，導致第一接觸開口（例如’ 120a-120b)比第二接觸開口（例如， 119a-119b)寬。主動區接觸溝槽的輪廓形狀允許更大的歐姆接觸區域 並且通過抗擊穿植入170a-170d更好的避免擊穿，並且改進了元件的 UIS能力。香農植入沿著第二接觸開口的侧壁和底部分佈，形成了蕭特 基能障控制層190a-190b。 第1D-1F圖示出了整合低注入本體二極體的DMOS元件的實施 . 例。元件106、108和110具有比本體區淺的主動區接觸溝槽。在某些 Ο 實施例中厚度約為0.01〜〇·5μπι的本體層將主動區溝槽的底部舆磊晶層 分開，形成了本體/沒極接面之下的低注入二極饉。薄體層的厚度和摻 雜水準（該薄體層位於主動區接觸溝槽和汲極之間）被調整，以使得在 反向偏壓中，此薄體層幾乎完全耗盡，而在正向偏壓中，薄體層不會耗 盡。由於載子已經極大減少，所以整合低注入二極體的元件1〇6、108 和110相比於常規的本體二極體提供了性能上的改進。在適當控制薄 體層的情況下，低注入本體二極體可以提供與蕭特基二極體相當的性 能’帶來的優勢在於：由於可以省去蕭特基能障控制層的形成，而帶來 的簡化製程。 ® 第2圖是示出了降壓型（buck)轉換器電路範例的示意圖。在此 範例中，所示電路200使用了高端FET元件201和低端FET元件207。 高端元件201包括電晶體202和本體二極體204。低端元件207可以 使用諸如第1A-1F圖中示出的1〇〇、1〇2或者1〇4的元件來實現。元 件207包括電晶體208、本體二極體210和蕭特基二極體212。負載 包括電感器214、電容器216和電阻器218。在正常操作期間，元件 201被導通以將功率從輸入源傳送到負載。這會引起電流在電感器中上 升。當元件201被截止時，電感器電流仍然流動，並轉換方向至元件 207的本體二極體21〇。在短暫的延遲後，控制電路使元件2〇7導通， 200929542 其導通電晶體208的通道，並大幅度地降低沿著元件208的淡極-源極 端子的正向壓降。在沒有蕭特基二極體212的情況下，本體二極體傳 導損耗以及移除元件2〇7的本體二極體210中存儲的電荷帶來的損耗 可能較大。然而，如果蕭特基二極體212構建在元件207中，並且如 果蕭特基二極鱧具有低的正向壓降，傳導損耗會極大減小。由於沿著蕭 特基二極體的低的正向壓降低於本體二極體的接面壓降，所以在箭特基 一極體傳導時’沒有存儲的電荷植入，進一步改善了二極體恢復所涉及 的損失》 第3圓是示出了用於構建DMOS元件的製程的實施例的流程圖。 在步称302，在覆蓋半導艘基底的蟲晶層中形成閉極溝槽。在步称3〇4， 將閘極材料沉積於閘極溝槽中。在步驟3〇6和3〇8，形成本體和源極。 在步驟3彳〇，形成接觸溝槽。如下面更詳細所述，在某些實施例中，在 一個步驟中形成主動區接觸溝槽和閘極區溝槽；在某些實施例中，溝槽 在多個步驟中形成，以獲得不同的深度。在步驟312，將接觸電極佈置 於接觸溝槽内。製程3GG及其步驟可以修改，以產生M〇s元件的不同 實施例，諸如第1A-1F圖中示出的102-110。 第4A-4U圖是元件的橫截面視圖，詳細示出了用於製造M〇s元件 〇的細製程。在此H例中，N型基底（即，其上生長有N_蟲晶層的阶 石夕片）被用作元件的;及極。 第4A-4J圖示出了閘極的形成。在第4A圖中，通過沉積 在N型基底400上形成二氧化石夕⑽〇廣4〇2。在各種實施例中， 氧化㈣厚度在100A-3GGGG A的範圍。其他厚度也可以使用。該厚度 可以取決於期待_極高度而進行調^將光阻層4G4旋塗在氧化物 層的頂上，並且使用溝槽罩幕來圖案化。 在第4B圖中，暴露區域中的Si〇2被移除，留下了用於㈣刻的 Si〇2硬罩幕410。在第4C圖中，異向性地侧石夕，留下了諸如42〇 的溝槽。將閘極材料沉積在溝槽中。之後形成在溝槽中的閘極具有基本 12 200929542 上與基底的頂表面垂直的側面。在第4D囷中，對Si〇2硬罩幕410進 行一定量的回蝕刻，使得溝槽壁在稍後的蝕刻步驟之後基本上與硬罩幕 的邊保持對準。Si〇2是在本實施例中使用的罩幕材料，因為使用Si〇2 硬罩幕的蝕刻會留下與軍幕的側部相互對準的相對直的溝槽壁。如果合 適’也可以使用其他材料。傳統上用於硬罩幕蚀刻的某些其他類型的材 料’諸如SbN4，會留下帶有曲率的蝕刻後的溝槽壁，這對於在下述步 驟中形成閘極而言欠佳。 Ο Ο 在第4E圖中，等向性地蚀刻基底以將溝槽的底部圓化。在某些實 施例中’溝槽約為0.5-2.5μΓη深，約為〇·2-1_5μΓΤΐ寬；其他尺寸也可以 使用。為了給生長閘極介電材料提供光滑的表面，在溝槽中生長Si〇2 的犧牲層430。然後，通過濕蝕刻製程移除該犧牲層。在第4G囷中， 在溝槽中熱生長Si〇2的層432作為介電材料。 在第4H圖中’沉積多晶梦440以填充溝槽。在這種情況下，多 晶矽被摻雜以獲取適當的閘極電阻。在某些實施例中，在（原位）沉積 多晶矽層時進行摻雜。在某些實施例中，在沉積後對多晶矽進行摻雜。 在第4I圖中，對Si〇2頂上的多晶矽層進行回蝕刻以形成諸如442的閘 極。在這點上，閘極的頂表面444相對於Si〇2的頂表面448而言仍然 是凹陷的；然而，取決於硬罩幕層410的厚度，閘極的頂表面444可 以高於矽的頂層446。在某些實施例中，在多晶矽回蝕刻中不使用罩 幕。在某些實施例中，在多晶矽回蝕刻中使用罩幕來避免在下述的本體 植入製程中使用附加的罩幕。在第4J圖中，移除Si〇2硬罩幕。在某些 實施例中’使用幹蚀刻來移除硬罩幕。在遇到頂部矽表面時蚀刻製程停 止’從而使多晶矽閘極在基底表面（其中將會植入源極摻雜物和本體摻 雜物）上延伸。在某些實施例中，閘極在基底表面之上延伸約 300A-20000A。其他值也可以使用。在這些實施例中使用s丨&硬罩幕， 因為它以可控制的方式在矽表面上提供了期待量的閘極延伸。隨後，可 以在晶圓上生長遮罩氧化物。以上的製程步驟可以針對製造具有凹陷的 13 200929542 閘極多晶矽的元件而簡化。例如’在某些實施例中，在形成溝槽期間使 用光阻罩幕或者非常薄的Si〇2硬罩幕，並且因此所得到的閘極多晶妙 不會在發表面上延伸。 第4Κ·4Ν圖示出了源極和本體的形成。在第4K圖中，使用本體罩 幕在本體表面上對光阻層450進行圚案化。未遮蔽的區域植入有本體 摻雜物。諸如硼離子的摻雜物被植入。在此處未示出的某些實施例中， 在沒有本艎阻擔物450的情況下執行本體植入，從而在主動溝槽之間 形成了連續的本體區。在第4L囷中，移除光阻，並且加熱晶圓以通過 有時稱為本體駆動（body drive)的製程來將植入的本體摻雜物熱擴散。 ❹隨後，形成了本體區460a»460d。在某些實施例中，用來植入本體摻雜 物的能量約在30〜600keV之間，劑量約在5e12>4e13離子/cm2，並且 所得到的最終本艎深度約在0·3-2·4μητι之間。通過改變因數，包括植入 能量、劑量和擴散溫度，可以獲得不同的深度。在擴散製程期間，形成 了氧化物層462。 在第4Μ圊中’使用源極罩幕對光阻層464進行圖案化。在所示實 施例中，源極罩幕464不會阻擋主動溝槽之間的任何區域。在某些實 施例中，源極罩幕464也對主動溝槽之間的中央區域（未示出）進行 ^ 阻擋。將源極摻雜物植入未遮蔽區域466。在此範例中，砷離子滲入未 遮蔽區域中的矽，以形成Ν+型源極。在某些實施例中，用於植入源極 摻雜物的能量約在10〜100keV之間，劑量約在1e15_iei6離子/cm2 之間，以及所得到的源極深度約在〇.〇5-〇.5μιτι之間。可以通過改變因 數，諸如摻雜能量和劑量，來實現進一步的深度減小。適當的話，其他 植入製程也可以使用。在第4Ν圖中，移除光阻，並且加熱晶圓以通過 源極驅動製程來對植入的源極摻雜物進行熱擴散。在源極驅動後將介 電（例如，BPSG)層465佈置於元件的頂表面上，並且可選地，在某 些實施例中可以將其緻密化。 第40-4Τ圖示出了接觸溝槽的形成以及沿著接觸溝槽的各種植 200929542 入。在第40圖中’光阻層472沉積在介電層上，並且使用接觸罩幕來 囷案化。執行第一接觸蝕刻來形成溝槽468和470。在某些實施例中， 第一接觸溝槽的深度在〇.2-2·5μπι之間。 在第4Ρ圖中，移除光阻層，利用植入的離子來轟擊溝槽47〇底部 周圍區域以形成擊穿防止層。在某些實施例中，使用劑量約為i-5e15 離子/cm2的硼離子。植入能量約為i〇_6〇keV。在某些實施例中，使用 劑量約為1-5e15離子/cm2、植入能量為40-100keV的BF2離子。在某 些實施例中’植入BF2和硼以形成擊穿防止層。植入傾角約在〇_45度 之間。在第4Q圈中，對植入物進行熱擴散。 © 在第4R圖中，進行第二接觸蝕刻。由於蝕刻製程不會影響介電層， 所以第二接觸蚀刻不需要額外的罩幕。在某些實施例中，溝槽的深度增 大了 0·2-0·5μηη。將擊穿防止層刻蝕穿，沿著溝槽壁留下抗擊穿植入物 474a-474b。在第4S圖中，使用離子植入來形成低劑量淺ρ型蕭特基 能障控制層476。在某些實施例中，使用劑量在2eii-3e13離子/cm2 之間、植入能量在10-100keV之間的硼或BF2。在第4T圖中，通過熱 擴散啟動蕭特基能障控制層。與抗擊穿植入相比，蕭特基能障控制層需 要較低劑量，並且由此產生了較低摻雜和較薄的植入層。在某些實施例 中，蕭特基能障控制層約為0.01·0_05μηι厚。蕭特基能障控制層可以調 整能障高度，因為植入物調整在接觸電極和半導體之間的表面能量。 在第4U圖中，示出了完整的元件490。金屬層478被沉積、在適 當情況下蝕刻以及退火。在沉積保護層（pass|vatj〇n |ayer)48〇之後 製作保護開口。還可以執行需要用來完成製造的附加步驟，諸如晶圓研 磨以及後端金屬沉積。 可以使用選擇性的製程。例如，為了製造第1D_1F圖中示出的元 件106-110，對第4K圖中示出的本體植入製程進行修改，並且在主動 區中沒有本體阻擋物。本體摻雜物被直接植入、覆蓋暴露的區域以及在 閘極之間形成連續的本體區。在接觸蝕刻期間，將溝槽蝕刻到比本體區 15 200929542 底部淺的深度，使本體層低於接觸溝槽。選擇性地，可以將主動接觸溝 槽僅刻蝕穿過本體，以暴露外延没極區，隨後是利用良好控制的能董和 摻雜物的附加本體摻雜植入來穿過接觸溝槽側壁和底部形成薄的本髏 層。 在某些實施例中，為了形成蕭特基能障控制層，通過化學氣相沉積 (CVD)來沉積諸如SiGe的窄能隙材料，以在磊晶層的頂表面上形成 層。在某些實施例中，窄能隙材料層的厚度在從100A到1000A的範 圍内。例如，在某些實施例中使用200A的富矽SiGe層。在某些實施 例中’富梦SiGe層包括80%的S丨和20%的Ge。在某些實施例中， 〇 利用N型摻雜物以2e17-2e18/cm3的濃度來對窄能隙材料層進行原位 掺雜。隨後’在窄能隙層之上沉積低溫氧化物層，然後對該低溫氧化物 層進行圖案化以形成硬罩幕，用於將溝槽乾蚀刻到磊晶層中。在乾姓刻 製程期間，硬罩幕保護下面的窄能隙層的部分。 第5A-6B圖示出了製造步驟的附加可選實施例。例如，第5A圖進 行擊穿防止層擴散（參見第4Q圖）。使用第二接觸罩幕來對光阻層502 進行圖案化’以阻擋閘極溝槽504。在第5B圖中，發生第二钱刻以增 大主動區接觸溝槽506的深度。然後移除光阻，並以類似於第4S圖和 q 第4T圖中的方式對蕭特基能障控制層進行植入。包括金屬沉積和保護 的附加完成步驟仍然實施（參見第4U圖）。所得到的元件類似於第ΐβ 圖所示的元件102’其中閘極溝槽具有與主動區接觸溝槽不同的深度。 通過使用針對第二接觸溝槽姓刻的單獨的罩幕，以實現不同的閘極溝槽 和主動區接觸溝槽的深度，可以使閘極溝槽接觸制得更淺，並且可以緩 和對於在蚀刻期間擊穿閘極多晶梦的擔心。這樣，通常使用該製程來製 造具有短閘極多晶梦的元件，包括具有不在基底表面之上延伸的閘極多 晶發的實施例。 第6A圖也進行了擊穿防止層擴散（參見第4Q圖）。使用第二接觸 罩幕來對光阻層602進行圖案化以阻擒閘極溝槽6〇4，以及以便在主動 200929542 區接觸溝槽606之上形成比第一蝕刻的接觸開口小的接觸開口。在第 6B圖中，進行第二接觸蝕刻，以形成更深的、更窄的溝槽部分608。 移除光阻，並且實施從第4S-4U圖的剩餘步驟。所得到的元件類似於 第1C圊所示的103。 第7-10圖示出了製程的選擇性改進，這些改進可以在某些實施例 中使用以進一步增強元件性能。 第7圖中所示選擇性改進可以在形成閘極（第4G圖）之後且在使 用本體阻擋罩幕（圓4K)之前進行。遍及磊晶層，沉積具有與磊晶層 相反極性的全面性植入702。在某些實施例中，高能量、低劑量 ® (5e11-1e13，20〇-600keV)的硼被用來在形成主本體植入之前形成 全面性植入702 〇全面性植入用來調整磊晶層輪廓，而不會導致遙晶層 中極性的改變。全面性植入改變了本體底部區域中的本體輪廓，並且在 不明顯增大Rdson的情況下增強了擊穿電壓。 第8圖中所示可選改進可以在沉積香農植入（第4S圖）之後、但 是在其啟動（第4T圖）之前進行。磊晶層輪廓調諧植入被植入到主動 區接觸溝槽之下。蠢晶層輪廓調諧植入具有與磊晶層相反的極性。在某 些實施例中’高能量、低劑量的硼或者BF2 (例如，5e11-1e13， Q 6〇-3〇0keV)被用來植入❶該植入調諧磊晶層輪廓而不改變磊晶層極 性，並且增強了擊穿電壓。 第9圖中所示可選改進可以在沉積香農植入（圖4S)之後、但是 在其啟動之前（第4T圖）進行。高能量、中劑量（j e12-5ei 3,60-300keV )G In the example shown, the FET channel is formed along the active region gate trench sidewalls between the source/own ship junction and the local/no-pole junction. In an element having a short channel region, as the voltage between the source and the drain increases, the depletion region expands and may eventually reach the source junction. This phenomenon, called breakdown, limits the extent to which the channel can be shortened. In some embodiments, to avoid breakdown, the P-type material is used to heavily dope regions such as regions 170a-170d that contact the trench walls along the active region to form a p+-type region βp+-type region to avoid depletion. The area encroached on the source area. As such, these implants are sometimes referred to as anti-puncture implants or to avoid puncture implants. In some implementations, in order to achieve the claimed anti-penetration effect, the p+ region is as close as possible to the channel region and/or as permitted by the manufacturing alignment capability and P+ sidewall doping control. In some embodiments, the misalignment between the trench contacts and the trenches is minimized by self-aligning the contacts and the trench contacts are placed as close as possible to the center of the trench between the trenches. These structural enhancements allow the channel to be charged by the brain, the Na channel material (4), and the unaffected junction material (4). In addition to the material; ^2 barrier implants also make it possible to construct short channel elements with very shallow trenches. The trenches 112a-112b are shallower than the body region and do not reduce the on-resistance 1 and gate capacitance of the device. The contact electrode rmr2b^_trench 117 towel __ forms a paralysis that contacts the groove, and is disposed along the sidewall of the contact groove at the breakdown implant, without the _ _ _ 1G4 contact. Contact electrode and no face - Mei Zheqing (fine 9 200929542 diode reduces the forward voltage drop of the body diode Zhao and minimizes the stored charge, making the MOSFET more efficient. Can be formed simultaneously to N· A Schottky contact and a metal to a good ohmic contact of the p+ body and the N+ source are used to form electrodes 180a-180b. Such as titanium (Ti), platinum (R), palladium (Pd), tungsten (w) Or any other suitable metal may be used. In some embodiments, the metal layer 172 is made of aluminum ruthenium or by a Ti/TiN/A ruthenium laminate. The leakage current of the Schottky diode is related to the height of the Schottky barrier. As the height of the energy barrier increases, the leakage current decreases and the forward voltage drop also increases. In the illustrated example, an optional Schottky barrier control layer 190a-190b (also known as a thin dopant layer) is implanted around the bottom of the trenches 12a-<l12b. A Shannon layer is formed under the contact electrode. In this example, the dopant has a polarity opposite to that of the epitaxial layer and is of the p-type. Shannon implants are shallow and low dose; therefore, they are completely depleted regardless of bias. The Schottky Energy Barrier Control Layer is used to control the Schottky barrier height, allowing for better control of leakage currents and improved reverse recovery characteristics of the Schottky diode. The details of forming the Schottky barrier control layer are described below. Figure 1B is a cross-sectional view of another embodiment of a DMOS device. Element 1 〇 2 also includes Schottky barrier control layers 190a-190b located around the bottom of the active area contact trench. Q In this example, the depth of the gate contact trench 117 is different from the depth of the active region contact trenches 112a-112b. The active area contact trenches are deeper than the body regions 14a-140d and the active area contact trenches extend beyond the body regions. Since the active contact trenches are deep, the active contact trenches provide more area for ohmic contact along the sidewalls and provide better non-clamp-inductive switch (UIS) capability. Moreover, by making the gate contact trench shallower than the active contact trench, the gate contact trench will be less likely to penetrate the gate wire polysilicon during the etch process, which is for components with relatively shallow gate polysilicon (such as It is useful to use components fabricated in such a process that the process will cause the gate polysilicon to not extend over the top surface of the body. Figure 1C is another embodiment of a DMOS device. In this example, the gate contact trench 117 and the active contact trenches 112a-ll2b have different depths. In addition, the depth of each main 200929542 moving zone contact groove is not uniform 'because the groove depth varies in a direction parallel to the substrate surface. As described in more detail below, the active region contact trenches are formed using a two-step process resulting in the first contact openings (e.g., '120a-120b) being wider than the second contact openings (e.g., 119a-119b). The contoured shape of the active area contact trench allows for a larger ohmic contact area and better avoidance of breakdown by the anti-breakdown implants 170a-170d and improves the UIS capability of the element. The Shannon implants are distributed along the sidewalls and bottom of the second contact opening to form a Schottky barrier control layer 190a-190b. The 1D-1F diagram shows an implementation of a DMOS device incorporating a low injection body diode. Elements 106, 108, and 110 have active area contact trenches that are shallower than the body area. In some embodiments, a body layer having a thickness of about 0.01 Å to 5 μm separates the bottom 舆 epitaxial layer of the active region trench to form a low implanted ruthenium under the bulk/bump junction. The thickness of the thin body layer and the doping level (which is located between the active region contact trench and the drain) are adjusted such that in the reverse bias, the thin body layer is almost completely depleted while being forward biased In the middle, the thin layer will not be exhausted. Since the carriers have been greatly reduced, the components 1〇6, 108, and 110 that integrate the low-injection diodes provide performance improvements over conventional body diodes. With proper control of the thin body layer, the low-injection body diode can provide comparable performance to the Schottky diode', which has the advantage of eliminating the formation of the Schottky barrier control layer. The simplified process. ® Figure 2 is a schematic diagram showing an example of a buck converter circuit. In this example, the illustrated circuit 200 uses a high side FET element 201 and a low side FET element 207. The high end component 201 includes a transistor 202 and a body diode 204. The low-end element 207 can be implemented using an element such as 1 〇〇, 1 〇 2 or 1 〇 4 shown in Figures 1A-1F. Element 207 includes a transistor 208, a body diode 210, and a Schottky diode 212. The load includes an inductor 214, a capacitor 216, and a resistor 218. During normal operation, component 201 is turned on to transfer power from the input source to the load. This causes the current to rise in the inductor. When the element 201 is turned off, the inductor current still flows and the direction is switched to the body diode 21 of the element 207. After a brief delay, the control circuit turns on component 2〇7, which turns on the channel of transistor 208 and substantially reduces the forward voltage drop across the low-source terminal of component 208. In the absence of the Schottky diode 212, the bulk diode conduction loss and the loss of charge stored in the body diode 210 of the removal element 2〇7 may be large. However, if the Schottky diode 212 is built into element 207, and if the Schottky diode has a low forward voltage drop, the conduction losses are greatly reduced. Since the low forward voltage along the Schottky diode decreases below the junction voltage drop of the body diode, there is no stored charge implant during the conduction of the arrow-based diode, further improving the pole Loss involved in volume recovery. The third circle is a flow chart showing an embodiment of a process for constructing a DMOS device. At step 302, a closed-pole trench is formed in the worm layer covering the semi-conductor substrate. At step 3〇4, the gate material is deposited in the gate trench. At steps 3〇6 and 3〇8, the body and source are formed. At step 3, a contact trench is formed. As described in more detail below, in some embodiments, active region contact trenches and gate region trenches are formed in one step; in some embodiments, trenches are formed in multiple steps to achieve different depth. At step 312, the contact electrodes are disposed within the contact trenches. Process 3GG and its steps can be modified to produce different embodiments of M〇s elements, such as 102-110 shown in Figures 1A-1F. Figure 4A-4U is a cross-sectional view of the component, showing in detail the fine process used to fabricate the M〇s component. In this H example, an N-type substrate (i.e., a stepped stone sheet on which an N-worm layer is grown) is used as an element; 4A-4J illustrate the formation of a gate. In Fig. 4A, a white oxide (10) 〇 〇 4 〇 2 is formed on the N-type substrate 400 by deposition. In various embodiments, the oxidation (iv) thickness is in the range of 100A-3GGGG A. Other thicknesses can also be used. The thickness can be adjusted depending on the expected _ pole height to spin the photoresist layer 4G4 on top of the oxide layer and patterned using a trench mask. In Figure 4B, Si〇2 in the exposed area is removed, leaving a Si〇2 hard mask 410 for (four) engraving. In Fig. 4C, the anisotropic side is left, leaving a groove such as 42 。. A gate material is deposited in the trench. The gate formed in the trench then has a side substantially perpendicular to the top surface of the substrate on 2009 200929542. In the 4D, a certain amount of etch back is applied to the Si〇2 hard mask 410 such that the trench walls remain substantially aligned with the edges of the hard mask after a later etching step. Si〇2 is the mask material used in this embodiment because etching using a Si〇2 hard mask leaves relatively straight trench walls that are aligned with the sides of the military curtain. Other materials may be used if appropriate. Certain other types of materials conventionally used for hard mask etching, such as SbN4, leave an etched trench wall with curvature which is less desirable for forming a gate in the following steps. Ο Ο In Figure 4E, the substrate is isotropically etched to round the bottom of the trench. In some embodiments, the 'trench is about 0.5-2.5 μΓη deep, about 2-1·2-1_5 μΓΤΐ wide; other dimensions can be used. In order to provide a smooth surface to the growth gate dielectric material, a sacrificial layer 430 of Si 〇 2 is grown in the trench. The sacrificial layer is then removed by a wet etch process. In the fourth layer, the layer 432 of Si〇2 is thermally grown in the trench as a dielectric material. Polycrystalline Dream 440 is deposited in Figure 4H to fill the trench. In this case, the polysilicon is doped to obtain an appropriate gate resistance. In some embodiments, doping is performed while depositing the polycrystalline germanium layer (in situ). In some embodiments, the polysilicon is doped after deposition. In Fig. 4I, the polysilicon layer on top of Si〇2 is etched back to form a gate such as 442. In this regard, the top surface 444 of the gate is still recessed relative to the top surface 448 of the Si 〇 2; however, depending on the thickness of the hard mask layer 410, the top surface 444 of the gate may be higher than the 矽Top level 446. In some embodiments, no mask is used in the polysilicon etchback. In some embodiments, a mask is used in polysilicon etchback to avoid the use of additional masks in the body implant process described below. In Figure 4J, the Si〇2 hard mask is removed. In some embodiments, dry etching is used to remove the hard mask. The etch process stops when the top germanium surface is encountered, thereby causing the polysilicon gate to extend over the substrate surface where the source dopant and bulk dopant will be implanted. In some embodiments, the gate extends about 300A-20000A above the surface of the substrate. Other values can also be used. The s丨 & hard mask is used in these embodiments because it provides a desired amount of gate extension on the crucible surface in a controlled manner. The mask oxide can then be grown on the wafer. The above process steps can be simplified for the fabrication of components having recessed 13 200929542 gate polysilicon. For example, in some embodiments, a photoresist mask or a very thin Si〇2 hard mask is used during trench formation, and thus the resulting gate polycrystal does not extend over the publication surface. The fourth figure shows the formation of the source and the body. In Fig. 4K, the photoresist layer 450 is patterned on the surface of the body using a body mask. Unmasked areas are implanted with bulk dopants. A dopant such as boron ions is implanted. In some embodiments not shown herein, bulk implantation is performed without the native barrier 450, thereby forming a continuous body region between the active trenches. In the 4L, the photoresist is removed and the wafer is heated to thermally diffuse the implanted body dopant by a process sometimes referred to as a body drive. Subsequently, body regions 460a»460d are formed. In some embodiments, the energy used to implant the bulk dopant is between about 30 and 600 keV, the dose is about 5e12 > 4e13 ions/cm2, and the resulting final depth is about 0. 3-2. · between 4μητι. Different depths can be obtained by varying the factors, including implant energy, dose and diffusion temperature. During the diffusion process, an oxide layer 462 is formed. In the fourth layer, the photoresist layer 464 is patterned using a source mask. In the illustrated embodiment, the source shield 464 does not block any areas between the active trenches. In some embodiments, the source mask 464 also blocks the central region (not shown) between the active trenches. A source dopant is implanted into the unmasked region 466. In this example, arsenic ions penetrate into the ruthenium in the unmasked region to form a Ν+ source. In some embodiments, the energy used to implant the source dopant is between about 10 and 100 keV, the dose is between about 1e15_iei6 ions/cm2, and the resulting source depth is about 〇.〇5- 〇.5μιτι between. Further depth reduction can be achieved by varying the factors such as doping energy and dose. Other implant processes can be used as appropriate. In Figure 4, the photoresist is removed and the wafer is heated to thermally diffuse the implanted source dopant through a source drive process. A dielectric (e.g., BPSG) layer 465 is disposed on the top surface of the component after source driving, and optionally, may be densified in some embodiments. Figure 40-4 shows the formation of contact trenches and the various implants along the contact trenches 200929542. In Fig. 40, the photoresist layer 472 is deposited on the dielectric layer and patterned using a contact mask. A first contact etch is performed to form trenches 468 and 470. In some embodiments, the depth of the first contact trench is between 2.2-2·5μπι. In the fourth diagram, the photoresist layer is removed, and the implanted ions are used to bombard the area around the bottom of the trench 47 to form a breakdown prevention layer. In certain embodiments, boron ions at a dose of about i-5e15 ions/cm2 are used. The implant energy is approximately i〇_6〇keV. In certain embodiments, BF2 ions having a dose of about 1-5e15 ions/cm2 and an implantation energy of 40-100 keV are used. In some embodiments, BF2 and boron are implanted to form a breakdown prevention layer. The implantation angle is approximately between 〇45 degrees. In the 4th Qth, the implant was thermally diffused. © In the 4Rth picture, a second contact etch is performed. Since the etching process does not affect the dielectric layer, the second contact etch does not require an additional mask. In some embodiments, the depth of the trench is increased by 0·2-0·5μηη. The breakdown prevention layer is etched through, leaving anti-breakdown implants 474a-474b along the walls of the trench. In Figure 4S, ion implantation is used to form a low dose shallow p-type Schottky barrier control layer 476. In certain embodiments, boron or BF2 having a dose between 2eii and 3e13 ions/cm2 and implanting energy between 10 and 100 keV is used. In the 4T diagram, the Schottky barrier control layer is activated by thermal diffusion. The Schottky barrier control layer requires a lower dose than the anti-breakdown implant and results in a lower doped and thinner implant layer. In some embodiments, the Schottky barrier layer is about 0.01·0_05 μηι thick. The Schottky barrier can adjust the barrier height because the implant adjusts the surface energy between the contact electrode and the semiconductor. In the 4U diagram, the complete component 490 is shown. Metal layer 478 is deposited, etched and etched as appropriate. A protective opening is made after the deposition of the protective layer (pass|vatj〇n |ayer) 48〇. Additional steps required to complete the fabrication, such as wafer polishing and backside metal deposition, can also be performed. A selective process can be used. For example, to fabricate the elements 106-110 shown in the 1D_1F diagram, the body implant process illustrated in Figure 4K is modified and there is no body barrier in the active region. The bulk dopant is implanted directly, covering the exposed areas and forming a continuous body region between the gates. During the contact etch, the trench is etched to a shallower depth than the bottom of the body region 15 200929542 such that the body layer is lower than the contact trench. Alternatively, the active contact trenches may be etched only through the body to expose the epitaxial regions, followed by additional body doping implants with well-controlled energy and dopants to pass through the sidewalls of the contact trenches. A thin layer of the base is formed at the bottom. In some embodiments, to form a Schottky barrier control layer, a narrow gap material such as SiGe is deposited by chemical vapor deposition (CVD) to form a layer on the top surface of the epitaxial layer. In some embodiments, the thickness of the layer of narrow energy gap material ranges from 100A to 1000A. For example, a 200A ytterbium-rich SiGe layer is used in some embodiments. In some embodiments, the 'Fu dream SiGe layer includes 80% S丨 and 20% Ge. In some embodiments, 窄 the in-situ doping of the narrow gap material layer is performed at a concentration of 2e17-2e18/cm3 using an N-type dopant. A low temperature oxide layer is then deposited over the narrow energy gap layer and the low temperature oxide layer is then patterned to form a hard mask for dry etching the trench into the epitaxial layer. During the dry-end engraving process, the hard mask protects portions of the underlying narrow gap layer. 5A-6B illustrate additional alternative embodiments of the manufacturing steps. For example, Figure 5A performs a breakdown prevention layer diffusion (see Figure 4Q). The photoresist layer 502 is patterned using a second contact mask to block the gate trenches 504. In Figure 5B, a second cost is incurred to increase the depth of the active area contact trench 506. The photoresist is then removed and the Schottky barrier control layer is implanted in a manner similar to that of Figures 4S and q. Additional completion steps including metal deposition and protection are still implemented (see Figure 4U). The resulting component is similar to element 102' shown in Figure 其中 where the gate trench has a different depth than the active region contact trench. By using a separate mask for the second contact trench to achieve different gate trench and active region contact trench depths, the gate trench contact can be made shallower and can be mitigated for Worry about the breakdown of the gate polycrystalline dream during etching. Thus, the process is typically used to fabricate components having a short gate polycrystal dream, including embodiments having a gate polysilicon that does not extend over the surface of the substrate. The breakdown prevention layer diffusion is also performed in Fig. 6A (see Fig. 4Q). The second contact mask is used to pattern the photoresist layer 602 to resist the gate trenches 6〇4, and to form a contact opening on the active 200929542 area contact trenches 606 that is smaller than the first etched contact openings. . In Figure 6B, a second contact etch is performed to form a deeper, narrower trench portion 608. The photoresist is removed and the remaining steps from the 4S-4U diagram are implemented. The resulting component is similar to 103 shown in Figure 1C. Figures 7-10 illustrate alternative improvements in the process that may be used in certain embodiments to further enhance component performance. The selective improvement shown in Fig. 7 can be performed after forming the gate (Fig. 4G) and before using the body barrier mask (circle 4K). A full implant 702 having a polarity opposite to that of the epitaxial layer is deposited throughout the epitaxial layer. In some embodiments, high energy, low dose® (5e11-1e13, 20〇-600keV) boron is used to form a comprehensive implant 702 prior to implantation of the main body. 〇 Comprehensive implants are used to adjust the Lei The contour of the layer does not cause a change in polarity in the crystal layer. The full implant changes the body profile in the bottom region of the body and enhances the breakdown voltage without significantly increasing Rdson. The optional improvement shown in Figure 8 can be performed after deposition of the Shannon implant (Fig. 4S), but prior to its initiation (Fig. 4T). The epitaxial layer profile tuned implant is implanted under the active region contact trench. The stray layer contour tuning implant has a polarity opposite to that of the epitaxial layer. In certain embodiments, 'high energy, low dose boron or BF2 (eg, 5e11-1e13, Q6〇-3〇0keV) is used to implant the implanted tuned epitaxial layer profile without changing epitaxial Layer polarity and enhanced breakdown voltage. The optional improvement shown in Figure 9 can be performed after deposition of the Shannon implant (Figure 4S), but prior to its initiation (Fig. 4T). High energy, medium dose (j e12-5ei 3,60-300keV)
的蝴被植入以形成P型島9〇2，該p型島9〇2位於接觸溝槽之下的N 型蟲晶層中’並且與本體區斷開連接。浮動的p型島也增強了擊穿電 壓。 第10圖中所示的可選改進可以在形成接觸溝槽（第40圖）之後 且在進行香農植入（第4P圖）之前進行。由於尖銳的角會積累電荷、 產生兩電場和較低的擊穿電壓，所以使溝槽底部的角1〇〇2a_1〇〇2b圓 17 200929542 化以減少電荷的積累並改善擊穿電壓。 儘管出於清楚的理解這一目的，在某些細節中描述了前述實施例， 但是本發明並不限於所提供的細節。可以存在可選的方式來實現本發 明。所公開的實施例僅是範例的說明而不是限制性的。 【圖式簡單說明】 第1A-1F圖顯示若干雙擴散金屬氧化物半導體（DM〇s)元件的實施例。 第2圖降壓型（buck)轉換器電路範例的示意圖》 第3圖顯示用於構造DMOS元件的製程的實施例的流程囷。 ❹ 第4A4U圖是具體顯示用於製造m〇S元件的範例製程的元件橫截面視圓。 第5A-6B圖顯示製造步驟的附加可選實施例。 第7-10圖顯示本製程的選擇性改進，其中這些改進在某些實施例中使The butterfly is implanted to form a P-type island 9 〇 2 which is located in the N-type worm layer below the contact trench and is disconnected from the body region. The floating p-type island also enhances the breakdown voltage. The optional improvement shown in Fig. 10 can be performed after the formation of the contact grooves (Fig. 40) and before the Shannon implantation (Fig. 4P). Since the sharp corners accumulate charge, generate two electric fields and a lower breakdown voltage, the angle 1 〇〇 2a_1 〇〇 2b of the bottom of the trench is reduced to reduce the accumulation of charge and improve the breakdown voltage. Although the foregoing embodiments are described in some detail for purposes of clarity of understanding, the invention is not limited to the details provided. There may be alternative ways to implement the invention. The disclosed embodiments are merely illustrative and not restrictive. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A-1F show an embodiment of several double-diffused metal oxide semiconductor (DM〇s) devices. Fig. 2 is a schematic diagram of an example of a buck converter circuit. Fig. 3 shows a flow chart of an embodiment of a process for constructing a DMOS device. ❹ Section 4A4U is a cross-sectional view of a component that specifically shows an example process for fabricating a m〇S component. Figures 5A-6B show additional alternative embodiments of the manufacturing steps. Figures 7-10 show alternative improvements in the process, where these improvements are made in some embodiments
用以進一步增強元件性能。 【主要元件符號說明】 100元件 104磊晶層 112a-112b接觸溝槽 120a-120b第一接觸開口 131、133、135 閘極 133、135主動閘極 140a-140d本體區 160a-160c絕緣區 172a-172b金屬層 190a-190b蕭特基能障控制層 200電路 202電晶體 207低端FET元件 210本體二極體 103基底 111、113、115、117 閘極溝槽 119a-119b第二接觸開口 121閘極氧化物層 131閘極導線 150a-150d源極區 160介電材料層 170a-170d 區域 180a-180b 電極 102、106、108、110 元件 201高端FET元件 204本體二極體 208電晶體 212蕭特基二極體 200929542 214電感器 218電阻器 402 Si〇2 層 410Si〇2硬罩幕 430犧牲層 440多晶矽 444閘極的頂表面 448Si〇2的頂表面 460a-460d本體區 ❹ 464光阻層 466未掩蔽區域 472光阻層 478金屬層 490元件 504閘極溝槽 602光阻層 606接觸溝槽 702全面性注入 ® 1002a-1002b 角 216電容器 400 N型基底 404光阻層 420溝槽 432 Si〇2 層 442閘極 446 >ε夕的頂層 450光阻層 462氧化物層 465介電層 468、470 溝槽 474a-474b抗擊穿注入物 480純化層 502光阻層 506接觸溝槽 604閘極溝槽 608溝槽部分 902 P型島 19Used to further enhance component performance. [Major component symbol description] 100 element 104 epitaxial layer 112a-112b contact trench 120a-120b first contact opening 131, 133, 135 gate 133, 135 active gate 140a-140d body region 160a-160c insulating region 172a- 172b metal layer 190a-190b Schottky barrier control layer 200 circuit 202 transistor 207 low side FET element 210 body diode 103 substrate 111, 113, 115, 117 gate trench 119a-119b second contact opening 121 gate Polar oxide layer 131 gate wire 150a-150d source region 160 dielectric material layer 170a-170d region 180a-180b electrode 102, 106, 108, 110 element 201 high side FET element 204 body diode 208 transistor 212 Schott Base diode 200929542 214 inductor 218 resistor 402 Si〇2 layer 410Si〇2 hard mask 430 sacrificial layer 440 polysilicon 444 gate top surface 448Si〇2 top surface 460a-460d body region 464 464 photoresist layer 466 Unmasked region 472 photoresist layer 478 metal layer 490 element 504 gate trench 602 photoresist layer 606 contact trench 702 comprehensive implant® 1002a-1002b angle 216 capacitor 400 N-type substrate 404 photoresist layer 420 trench 432 Si〇 2 layers 442 gate 446 > top layer of Essence 4 50 photoresist layer 462 oxide layer 465 dielectric layer 468, 470 trench 474a-474b anti-breakdown implant 480 purification layer 502 photoresist layer 506 contact trench 604 gate trench 608 trench portion 902 P-type island 19