200926596 九、發明說明： 【發明所屬之技術領域】 - 本案係關於一種雙緣觸發正反器，尤其是關於一種低功 .. 率雙緣觸發正反器。 【先前技術】 先前文獻中，一般的單緣觸發正反器皆屬於邊緣觸發， 即所謂的正緣或負緣觸發。而雙緣觸發正反器則可同時在 正緣和負緣作抓取、儲存資料訊號的動作，不需增加其他 〇 邏輯單元的前提下而能加倍資料產量。 參考圖1 ’其顯示習知雙緣觸發正反器之電路示意圖（先 前技術文獻[1])。習知雙緣觸發正反器10包括一第一 D型 正反器11、一第二D型正反器12及一多工器13。第一 d型 正反器11及第D型正反器12為相對平行的正反器，以作為 正緣和負緣觸發的根據，後級並連接多工器13來切換，以 構成方程式：少= <友+ 0。因此，多工器13就可以選擇所要 輸出的Q1值。此方法藉由兩個正反器分別對正緣和負緣做 〇 沈 資料的控制，來達到雙緣觸發正反器的效果。 但是上述方法與電路因為使用兩個正反器而相當耗電， 故如何減少功率的消耗，是現近1C設計探討的重點。美國 專利第 US7，180,351、US7,096,433 及 US6,937,079 號均提出 - 適用的雙緣觸發正反器，但這些專利所使用到的電晶體數 • 目較多’因此面種較大，對於積體電路設計成本而言為極 大的負擔。先前技術文獻[2]及[3]亦敘述習知雙緣觸發正 反器。 125319.doc 200926596 另外’電路的總功率消耗主要是由靜態功率消耗（static200926596 IX. Description of the invention: [Technical field to which the invention pertains] - This case relates to a double-edge triggering flip-flop, in particular to a low-power.. rate double-edge triggering flip-flop. [Prior Art] In the prior literature, a general single-edge flip-flop is an edge trigger, a so-called positive or negative edge trigger. The double-edge triggering flip-flop can simultaneously capture and store data signals at the positive and negative edges, and can double the data output without adding other 逻辑 logic units. Referring to Fig. 1', a circuit diagram showing a conventional double-edge flip-flop is shown (prior art document [1]). The conventional double-edge flip-flop 10 includes a first D-type flip-flop 11, a second D-type flip-flop 12, and a multiplexer 13. The first d-type flip-flop 11 and the D-type flip-flop 12 are relatively parallel flip-flops as a basis for positive-edge and negative-edge triggering, and the latter stage is connected to the multiplexer 13 to switch to form an equation: Less = <Friends + 0. Therefore, the multiplexer 13 can select the Q1 value to be output. In this method, the two flip-flops control the sag data of the positive and negative edges respectively to achieve the effect of the double-edge triggering flip-flop. However, the above method and circuit consume considerable power because two flip-flops are used, so how to reduce the power consumption is the focus of the recent 1C design discussion. US Patent Nos. 7,180,351, US 7,096,433, and US 6,937,079 all disclose the use of a dual-edge-triggered flip-flop, but the number of transistors used in these patents is relatively large, so that the surface is large, The circuit design cost is a great burden. The prior art documents [2] and [3] also describe conventional double-edge triggering flip-flops. 125319.doc 200926596 In addition, the total power consumption of the circuit is mainly caused by static power consumption (static
dissipation)加上動態功率消耗（dynamic dissipation) β 其中 動態功率消耗主要是在CMOS (Complementary Metal--. Oxide-Semiconductor)電路設計中，當 PMOS 電路和 NMOS 電路兩者在轉態的過程中，會有瞬間同時導通（ON)的現 象，而產生瞬間短路電流（short-circuit current)經由電源 (VDD)流到參考點（GND)。而靜態功率消耗是為當電晶體 不導通（OFF)時，並非完全不導通，而是有一微小漏電流 〇 (leakage current)產生，進而造成功率消耗。另外，轉態所 造成的功率消耗，是指有效的負 載，^是指電壓的擺幅，尨是指切換的頻率，亦即若要改 善功率消耗可透過降低電壓的擺幅和切換頻率，來達到省 電的功能。所以如何降低功率消耗，減少訊號延遲，使功 率延遲積（power delay product)減少，正是目前許多研究改 善的重點。 因此，實有必要提供一種創新且富進步性之低功率雙緣 觸發正反器，以解決上述問題。 先前技術文獻： [1] M. Afghahi, and J. Yuan, "Double edge-triggered D-flip-flop for highspeed CMOS circuits," IEEE J. Solid-Stats Circuits, vol. 26, no. 8, pp. 1168-1170, Aug. 1991.Dissipation) plus dynamic dissipation (β) where the dynamic power consumption is mainly in the CMOS (Complementary Metal--. Oxide-Semiconductor) circuit design, when both the PMOS circuit and the NMOS circuit are in the transition state, There is a moment of simultaneous ON (ON), and a short-circuit current is generated to flow to the reference point (GND) via the power supply (VDD). The static power consumption is such that when the transistor is not turned "OFF", it is not completely non-conductive, but a small leakage current is generated, which causes power consumption. In addition, the power consumption caused by the transition state refers to the effective load, ^ refers to the swing of the voltage, and 尨 refers to the frequency of switching, that is, if the power consumption is to be improved, the swing and switching frequency of the voltage can be reduced. Achieve power saving features. So how to reduce power consumption, reduce signal delay, and reduce the power delay product is the focus of many research improvements. Therefore, it is necessary to provide an innovative and progressive low-power dual-edge triggered flip-flop to solve the above problems. Prior Technical Literature: [1] M. Afghahi, and J. Yuan, "Double edge-triggered D-flip-flop for highspeed CMOS circuits," IEEE J. Solid-Stats Circuits, vol. 26, no. Pp. 1168-1170, Aug. 1991.
[2] T.-A. Johnson, and I.-S. Kourtev, "A single latch, high speed double- * edge triggered flip-flop(DETFF)," IEEE International Conference on[2] T.-A. Johnson, and I.-S. Kourtev, "A single latch, high speed double- * edge triggered flip-flop(DETFF)," IEEE International Conference on
Electronics, Circuits and Systems, vol. 1, pp. 189-192, Sept. 2001.Electronics, Circuits and Systems, vol. 1, pp. 189-192, Sept. 2001.
[3] Y.-Y. Sung, and R.-C. Chang, novel CMOS double-edge triggered 125319.doc 200926596 flip-flop for low-power applications," IEEE International Symposium on Circuits and Systems, pp. 665-668, May 2004. 【發明内容】 - 本發明提供一種低功率雙緣觸發正反器，其包括：一訊[3] Y.-Y. Sung, and R.-C. Chang, novel CMOS double-edge triggered 125319.doc 200926596 flip-flop for low-power applications," IEEE International Symposium on Circuits and Systems, pp. 665 -668, May 2004. SUMMARY OF THE INVENTION - The present invention provides a low power dual edge triggering flip-flop, which includes:
號延遲電路、一互斥或（XOR)電路及一栓鎖電路.該訊號 延遲電路具有複數個反相器’該等正反器串接，該訊號延 遲電路接收一系統時脈，並輸出一第一時脈訊號及一第二 時脈訊號。該互斥或電路具有複數個p型電晶體及複數個N ❹ 型電晶體，該互斥或電路用以依據該系統時脈、該第一時 脈訊號及該第二時脈訊號’輸出一互斥或輸出訊號，該互 斥或輸出訊號為該系統時脈及該第一時脈訊號之互斥或結 果，該等P型電晶體及N型電晶體為高臨界電壓電晶體。該 栓鎖電路具有一第三P型電晶體、一第三N型電晶體、一第 四P型電晶體、一第四N型電晶髖及一第六反相器，該第三 p型電晶體及第四p型電晶體為低臨界電壓電晶體，該第三 N型電晶體及該第四）^型電晶體為高臨界電壓電晶體，依 ❹ 冑該互斥或輸出訊號及—輸人資料，該栓鎖電路輸出一對 互補資料輸出訊號。 本發明之雙緣觸發正反器只利用單一的栓鎖電路以達到 雙緣觸發正反器的功效，不僅面積小，效能也提升。並 • i #用多臨界電壓電晶體，可降低漏電流造成的靜態功 • ㈣耗，提升整體功率效能，相高速且低功率之功效。 【實施方式】 圖2為本發明低功率雙緣觸發正反器之電路示意圖。本 125319.doc 200926596 發明之低功率雙緣觸發正反器40包括：一訊號延遲電路 41、一亙斥或（XOR)電路42及一栓鎖電路43。該訊號延遲 — 電路41具有複數個反相器411、412、413、414。該等正反 -- 器串接，該訊號延遲電路接收一系統時脈X4,並輸出一第 一時脈訊號Y4及一第二時脈訊號Z4。 在本實施例中，該訊號延遲電路41具有一第一反相器 411、一第二反相器4丨2、一第三反相器413及一第四反相 器414 ’其依序串接，該系統時脈X4輸入至該第一反相器 〇 411之輸入端，該第三反相器413之輸出端輸出該第一時脈 訊號Y4，該第四反相器414之輸出端輸出該第二時脈訊號 Z4。因此，對於原本系統時脈χ2，假設每經過一個反相 器會有訊號延遲（τ) ’當經過三個反相器後，對於原本系統 時脈會有三倍的訊號延遲（即3τ·)。亦即，相對於該系統時 脈X4 ’該第一時脈訊號Y4具有三倍的訊號延遲（即3r)。 該互斥或電路42具有複數個P型電晶艎及複數個n型電 ❹ 晶體，該互斥或電路42用以依據該系統時脈χ4、該第一時 脈訊號Y4及該第二時脈訊號Z4,輸出一互斥或輸出訊 號’該互斥或輸出訊號為該系統時脈χ4及該第一時脈訊號 Y4之互斥或結果，該等p型電晶體及N型電晶體為高臨界 電壓（High Vth)電晶體。 - 在本實施例中’該互斥或電路42具有一第一p型電晶體 • PM41、一第一N型電晶體⑽41、一第二P型電晶體PM42 及一第二N型電晶體丽42。其中，該第一p型電晶體pM41 與該第-N型電晶體NM41之閘極相接，並接收該系統時脈 125319.doc -9· 200926596 X4’該第一P型電晶艘PM41之源_合至該第一時脈訊號 Y4，該第一N型電晶體NM41之源極耦合至該第二時脈訊 號Z4。該第二P型電晶體PM42之閘極耦合至該第一時脈訊 - 號Y4，該第二N型電晶體NM42之閘極耦合至該第二時脈 訊號Z4，該第二P型電晶體PM42之源極與該第型電晶 體NM42之源極相接並耦合至該系統時脈χ4,而第二p型電 晶體PM42之汲極與第二N型電晶體NM42之汲極相接為該 互斥或輸出訊號A4,並耦合至該栓鎖電路43之輸入端。 ❹ 參考圖3，其顯不訊號之波形不意圖。假設第一個波形 為上述系統時脈X4之波形，第二個波形為上述經過第三反 相器413後之該第一時脈訊號Υ4β此時系統時脈χ4波形及 第一時脈訊號Υ4波形經過互斥邏輯運算便可產生第三個波 形’第二個波形為上述互斥或輸出訊號Α4β該互斥或輸出 訊號Α4在正緣和負緣皆會有對應的一小段低準位（，，〇，，）脈 波訊號。而此對應於正負緣的脈波訊號便可驅動後級的栓 鎖電路43來做抓值或問值的動作，如此便能產生正緣和負 緣皆可觸發的訊號線》 該栓鎖電路43具有一第三Ρ型電晶體卩厘“、一第三^^型 電晶體NM43、一第四P型電晶體！^44、一第01^型電晶體 NM44及一第六反相器431，該第三p型電晶體pM43及第四 - P型電晶體PM44為低臨界電壓（l〇w vth)電晶趙，該第三n . 型電晶體NM43及該第四N型電晶體^^河私為高臨界電壓 (High Vth)電晶體，依據該互斥或輸出訊號及一輸入資料 D4，該栓鎖電路43輸出一對互補資料輸出訊號。 125319.doc •10- 200926596 在本實施例中，該第三”電晶體PM43之閘極和該第三 N型電晶體麵43之間極相接為該栓鎖電路43之輸人端，該 第二P型電晶逋PM43之源極耦合至該輸入資料D4，且其汲 . 極與該第三N型電晶體NM43之源極相接，並連接至該第四 P型電晶體PM44之閘極及該第型電晶體]^]^144之閘極， 該第四P型電晶體PM44之源極搞合至一電源端，且其沒極 與該第四N型電晶體NM44之汲極相接，並與該第六反相器 431之輸入端相接，該第六反相器431之輸出端與該第三N Ϊ 型電晶體NM43之汲極相接，並輸出該資料輸出訊號Q4, 該第六反相器431之輸入端輸出該互補之資料輸出訊號。 在本實施例中，該第四P型電晶體PM44及該第四N型電 晶艘NM44組成一第五反相器’該第五反相器與該第六反 相器431串接。 假汉一開始系統時脈X4為"0"、第一時脈訊號Y4為"1"及 第二時脈訊號Z4為"0"，當系統時脈χ4由"0"充電至"1，， D 時’當假設每經過一個反相器時脈延遲τ，在經過3τ的訊 號延遲到第一時脈訊號Υ4時仍會有短暫的π 1 ”，到第二時 脈訊號Ζ4會有4τ延遲而產生短暫的"〇" «>此時第一 ρ型電晶 體ΡΜ41、第二Ρ型電晶體ΡΜ42和第二Ν型電晶體ΝΜ42不 導通，第一 Ν型電晶體ΝΜ41導通，互斥或輸出訊號入4會 因為第一Ν型電晶體ΝΜ41導通而放電。 當經過3τ的訊號延遲之後，第一時脈訊號Υ4放電至"〇" 使第二Ρ型電晶韹ΡΜ42導通，另外經過4?·之後，第二時脈 訊號Ζ4充電為"1"使第二Ν型電晶體ΝΜ42導通，此時互斥 125319,d〇c -11- 200926596 或輸出訊號A4會因第一 N型電晶體NM41、第二N型電晶體 NM42和第二P型電晶體!>]^42導通而充電，完成了上升緣 … 的觸發動作。相同地’當系統時脈X4由"1"放電為，’〇"時， -- 因第一時脈訊號Y4仍為"〇"，第二時脈訊號Z4仍為"1"，使 得第一 P型電晶體PM41、第二p型電晶體PM42和第二N型 電晶體NM42導通，第一N型電晶體NM41不導通’使得互 斥或輪出訊號A4放電，便完成了下降緣的動作，如此一來 便能產生如同互斥或輸出訊號A4波形所示對應於正負緣的 〇 脈波訊號（參考圖3)。 當輸入資料D4傳入栓鎖電路43之後，會因互斥或輸出訊 號A4為"〇"，使得第三卩型電晶體pM43導通，第三N型電晶 體NM43不導通，此時資料便經由第五反相器（第四p型電 晶體PM44及第四N型電晶及第六反相器431將資 料栓鎖住。當互斥或輸出訊號A4為"丨"時，第三N型電晶體 NM43導通’第三p型電㈣pM43不導通，使f料無法傳 ❹ 入，並將之前的資料予以保留。因此，資料輸出訊號(^4便 能輸出正確的結果。 然而位於關鍵路徑上的第三P型電晶體pM43，若使用的 電晶趙其臨I電壓越高時，t因其臨界電壓的影響使連接 點B4無法立即充放電，造成了資料抓取的錯誤甚至於導 •致資料會延後-個時脈才動作，所以第三？型電晶體pM43 • 選用低臨界電壓電晶趙（Low Vth)。以第三P型電晶趙pM43 而言，因為輸入與輸出均是在汲極與源極，構成一共問極 放大器，所以其增益正比於轉導，但是 125319.doc -12· 200926596 (匕-κ) ’所以選用低臨界電壓電晶體，雖然面積相 對地會增大，但在功率和速度方面卻有顯著的改善。 … 再者，由於第三P型電晶體PM43為PMOS，無法完全放 .· 電至"0" ’所以當連接點B4由"1”放電為，，〇，，的過程中’無法 完全放電至"0"。接著因第三N型電晶體NM43為NMOS導 通，使輸出端C4充電為"1",造成資料誤判錯誤，而第 型電晶體NM43的汲極是接到輸出端C4，為了容易傳送資 料輸出訊號Q4 ’必須減少負載’若第三n型電晶體NM43 〇 使用低臨界電壓電晶體’會受到汲極輸出阻抗 (V =〜降低的影響’所以第三n型電晶體並 不適合使用低臨界電壓電晶體，故第三N型電晶體NM43為 高臨界電壓電晶體。 由於第四P型電晶體pM44和第四N型電晶體NM44組成的 第五反相器用來驅動第六反相器431，以栓鎖資料。但因 第四P型電晶體PM44和第四N型電晶體NM44所構成第五反 ❹ 相器的輸入端為連接點B4，而連接點B4也是第三p型電晶 趙PM43和第三N型電晶體1^^143兩個1^〇3的輸出點，可視 為一個「浮接」的反相器，因它並沒有直接耦合到該電源 端VDD和接地端GND的路徑，造成連接點B4的訊號微弱。 若第四P型電晶體PM44選用的電晶體其臨界電壓越高時， •當輸入資料D4為"0"時，經由第三p型電晶體pM43流出的 - 電流’會因第四P型電晶體PM44無法立即充電至"Γ，，使 速度變慢。因此為了增快速度，彳以增加第四？型電晶體 PM44的尺寸，但相對地，電麼、電流的效應也會增大， 125319.doc 13 200926596 故將第四ρ型電晶體ΡΜ44 、 用低Ew界電廢電晶體，則可以 避免上述不必要的錯誤及影響。 本發明之雙緣觸發正反器只利用單一的栓鎖電路以達到 雙緣觸發正反器的功效’不僅面積小，效能也提升。並 且’利用多臨界電壓電晶體’可降低漏電流造成的靜態功 率消耗，提升整艘功率效能，達到高速且低功率之功效。 准上述實施例僅為說明本發明之原理及其功效而非限 制本發明。因此，習於此技術之人士對上述實施例進行修a delay circuit, a mutually exclusive or (XOR) circuit and a latch circuit. The signal delay circuit has a plurality of inverters 'these flip-flops are serially connected, the signal delay circuit receives a system clock and outputs a The first clock signal and a second clock signal. The mutually exclusive circuit has a plurality of p-type transistors and a plurality of N-type transistors, and the mutually exclusive circuit is configured to output one according to the system clock, the first clock signal, and the second clock signal The mutual exclusion or output signal is a mutual exclusion or result of the system clock and the first clock signal, and the P-type transistor and the N-type transistor are high threshold voltage transistors. The latch circuit has a third P-type transistor, a third N-type transistor, a fourth P-type transistor, a fourth N-type electro-crystal hip and a sixth inverter, and the third p-type The transistor and the fourth p-type transistor are low-threshold voltage transistors, and the third N-type transistor and the fourth-type transistor are high-threshold voltage transistors, depending on the mutual exclusion or output signal and Input data, the latch circuit outputs a pair of complementary data output signals. The double-edge triggering flip-flop of the invention only utilizes a single latching circuit to achieve the dual-edge triggering flip-flop, which not only has a small area but also improves the performance. And • i # multi-threshold voltage transistor can reduce the static power caused by leakage current. (4) Consumption, improve overall power efficiency, high speed and low power. Embodiment 2 FIG. 2 is a schematic circuit diagram of a low-power dual-edge flip-flop device according to the present invention. The low power dual edge flip-flop 40 of the invention includes a signal delay circuit 41, a snubber circuit (XOR) circuit 42 and a latch circuit 43. The signal delay - circuit 41 has a plurality of inverters 411, 412, 413, 414. The forward and reverse signals are connected in series, and the signal delay circuit receives a system clock X4 and outputs a first clock signal Y4 and a second clock signal Z4. In this embodiment, the signal delay circuit 41 has a first inverter 411, a second inverter 4丨2, a third inverter 413, and a fourth inverter 414'. The system clock X4 is input to the input end of the first inverter 411, and the output of the third inverter 413 outputs the first clock signal Y4, and the output of the fourth inverter 414 The second clock signal Z4 is output. Therefore, for the original system clock ,2, it is assumed that there will be a signal delay (τ) ’ every time an inverter passes, and after three inverters, there will be three times the signal delay (ie, 3τ·) for the original system clock. That is, the first clock signal Y4 has three times the signal delay (i.e., 3r) with respect to the system clock X4'. The multiplex circuit 42 has a plurality of P-type transistors and a plurality of n-type transistors, and the multiplex circuit 42 is configured to use the system clock χ4, the first clock signal Y4, and the second time. The pulse signal Z4 outputs a mutual exclusion or output signal 'The mutual exclusion or output signal is a mutual exclusion or result of the system clock 4 and the first clock signal Y4, and the p-type transistor and the N-type transistor are High Vth transistor. - In this embodiment, the mutual exclusion circuit 42 has a first p-type transistor, PM41, a first N-type transistor (10) 41, a second P-type transistor PM42, and a second N-type transistor. 42. The first p-type transistor pM41 is connected to the gate of the first-N transistor NM41, and receives the system clock 125319.doc -9· 200926596 X4' the first P-type electric crystal boat PM41 The source is coupled to the first clock signal Y4, and the source of the first N-type transistor NM41 is coupled to the second clock signal Z4. The gate of the second P-type transistor PM42 is coupled to the first clock signal-number Y4, and the gate of the second N-type transistor NM42 is coupled to the second clock signal Z4, the second P-type battery The source of the crystal PM42 is connected to the source of the first transistor NM42 and coupled to the system clock χ4, and the drain of the second p-type transistor PM42 is connected to the drain of the second N-type transistor NM42. The exclusive or output signal A4 is coupled to the input of the latch circuit 43. ❹ Referring to Figure 3, the waveform of the signal is not intended. Suppose the first waveform is the waveform of the system clock X4, and the second waveform is the first clock signal Υ4β after the third inverter 413, and the system clock χ4 waveform and the first clock signal Υ4 The waveform is subjected to a mutually exclusive logic operation to generate a third waveform. The second waveform is the above-mentioned mutually exclusive or output signal Α4β. The mutually exclusive or output signal Α4 has a corresponding low level at both the positive and negative edges ( ,,〇,,) Pulse signal. The pulse signal corresponding to the positive and negative edges can drive the latching circuit 43 of the subsequent stage to perform the value of grabbing or questioning, so that the signal line can be triggered by both the positive and negative edges. 43 has a third 电 type transistor 卩 “, a third ^ ^ type transistor NM43, a fourth P type transistor! ^ 44, a 01 ^ type transistor NM44 and a sixth inverter 431 The third p-type transistor pM43 and the fourth-p-type transistor PM44 are low threshold voltages (l〇w vth), the third n-type transistor NM43 and the fourth N-type transistor ^ ^The river is a high threshold voltage (High Vth) transistor, according to the mutual exclusion or output signal and an input data D4, the latch circuit 43 outputs a pair of complementary data output signals. 125319.doc •10- 200926596 In this implementation In an example, the gate of the third "transistor PM43" and the third N-type transistor surface 43 are in contact with each other as the input end of the latch circuit 43, and the source of the second P-type transistor 4353 The pole is coupled to the input data D4, and the pole is connected to the source of the third N-type transistor NM43, and is connected to the gate of the fourth P-type transistor PM44 and The gate of the first type transistor ^^^^144, the source of the fourth P-type transistor PM44 is coupled to a power supply terminal, and the pole of the fourth P-type transistor NM44 is connected to the drain of the fourth N-type transistor NM44. And connected to the input end of the sixth inverter 431, the output end of the sixth inverter 431 is connected to the drain of the third N-type transistor NM43, and outputs the data output signal Q4, The input end of the sixth inverter 431 outputs the complementary data output signal. In the present embodiment, the fourth P-type transistor PM44 and the fourth N-type transistor NM44 constitute a fifth inverter. The fifth inverter is connected in series with the sixth inverter 431. At the beginning of the fake, the system clock X4 is "0", the first clock signal Y4 is "1" and the second clock signal Z4 is "0", when the system clock is charged by "0""1,, D when 'when it is assumed that the pulse delay τ after each inverter is delayed, there will still be a short π 1 ” after the 3τ signal is delayed until the first clock signal Υ4, to the second clock signal Ζ4 will have a 4τ delay and produce a short "〇"«> At this time, the first ρ-type transistor ΡΜ41, the second 电-type transistor ΡΜ42, and the second 电-type transistor ΝΜ42 are not turned on, and the first type of electricity The crystal ΝΜ41 is turned on, and the mutual annihilation or output signal input 4 will be discharged because the first Ν type transistor ΝΜ41 is turned on. When the signal of 3τ is delayed, the first clock signal Υ4 is discharged to "〇" The transistor 42 is turned on, and after 4?, the second clock signal Ζ4 is charged as "1" to turn on the second transistor ΝΜ42, at this time mutually exclusive 125319, d〇c -11-200926596 or output Signal A4 will be due to the first N-type transistor NM41, the second N-type transistor NM42, and the second P-type transistor!>]^42 Turning on and charging, completes the triggering action of rising edge... Same as 'When system clock X4 is discharged by "1", '〇", -- because the first clock signal Y4 is still "〇" The second clock signal Z4 is still "1", so that the first P-type transistor PM41, the second p-type transistor PM42, and the second N-type transistor NM42 are turned on, and the first N-type transistor NM41 is not turned on. 'When the mutual exclusion or turn-off signal A4 is discharged, the action of the falling edge is completed, so that the pulse signal corresponding to the positive and negative edges as shown by the mutual exclusion or output signal A4 waveform can be generated (refer to FIG. 3). When the input data D4 is transmitted to the latch circuit 43, the third-type transistor pM43 is turned on due to the mutual exclusion or output signal A4 being "〇", and the third N-type transistor NM43 is not turned on. The data pin is locked via the fifth inverter (the fourth p-type transistor PM44 and the fourth N-type transistor and the sixth inverter 431. When the mutual exclusion or output signal A4 is "丨" The third N-type transistor NM43 is turned on, 'the third p-type electric (four) pM43 is not turned on, so that the f material cannot be transferred, and The data is retained. Therefore, the data output signal (^4 can output the correct result. However, the third P-type transistor pM43 located on the critical path, if the electro-optic crystal is used, the higher the I voltage, t is due to its criticality. The influence of the voltage makes the connection point B4 unable to be charged and discharged immediately, which causes the error of data acquisition and even the data to be delayed - the clock will act, so the third? Type transistor pM43 • Low voltage voltage Low Vth is used. In the case of the third P-type electro-optic crystal pM43, since the input and output are both at the drain and the source, forming a common-pole amplifier, the gain is proportional to the transduction, but 125319.doc -12· 200926596 (匕- κ) 'So the use of low-threshold voltage transistors, although the area will increase relatively, but there is a significant improvement in power and speed. ... Moreover, since the third P-type transistor PM43 is a PMOS, it cannot be completely discharged. · Electric to "0" 'So when the connection point B4 is discharged by "1", the process of ',,, 'cannot be completely Discharge to "0". Then, because the third N-type transistor NM43 is NMOS turned on, the output terminal C4 is charged to "1", causing data misjudgment error, and the drain of the first type transistor NM43 is connected to the output terminal. C4, in order to easily transmit the data output signal Q4 'must reduce the load' if the third n-type transistor NM43 〇 use a low threshold voltage transistor 'will suffer from the bucker output impedance (V = ~ reduce the impact ' so the third n-type The crystal is not suitable for using a low-threshold voltage transistor, so the third N-type transistor NM43 is a high-threshold voltage transistor. The fifth inverter composed of the fourth P-type transistor pM44 and the fourth N-type transistor NM44 is used to drive The sixth inverter 431 is for latching the data, but the input end of the fifth reverse phase phase device formed by the fourth P-type transistor PM44 and the fourth N-type transistor NM44 is the connection point B4, and the connection point B4 is also The third p-type electro-crystal Zhao PM43 and the third N-type transistor 1^^143 The output points of the two 1^3 can be regarded as a "floating" inverter, because it is not directly coupled to the path of the power terminal VDD and the ground GND, resulting in a weak signal at the connection point B4. When the threshold voltage of the transistor selected by the four P-type transistor PM44 is higher, • When the input data D4 is "0", the current flowing through the third p-type transistor pM43 will be due to the fourth P-type transistor. PM44 can't be charged immediately to "Γ, so the speed is slower. Therefore, in order to increase the speed, 彳 to increase the size of the fourth type of transistor PM44, but relatively, the effect of electricity, current will increase, 125319 .doc 13 200926596 Therefore, the fourth p-type transistor ΡΜ44 and the low Ew boundary electric waste crystal can avoid the above unnecessary errors and effects. The double-edge triggering flip-flop of the present invention uses only a single latch circuit. In order to achieve the dual-edge triggering the function of the flip-flops, not only the small area, but also the performance is improved. And 'Using multi-threshold voltage transistors' can reduce the static power consumption caused by leakage current, improve the whole power efficiency, and achieve high speed and low power. Efficacy. The above-described embodiments are illustrative only of the principles of the present invention and the efficacy of the present invention and not limitation. Thus, those of the above-described conventional technique in this embodiment be repaired
Ο 改及變化仍不脫本發明之精神。本發明之權利範圍應如後 述之申請專利範圍所列。 【圖式簡單說明】 圖1顯示習知雙緣觸發正反器之電路示意圖； 圖2為本發明低功率雙緣觸發正反器之電路示意圖；及 圖3顯示本發明訊號之波形示意圖。 【主要元件符號說明】 10 習知雙緣觸發正反器 11 第一 D型正反器 12 第二D型正反器 13 多工器 40 本發明之低功率雙緣觸發正反器 41 訊號延遲電路 42 互斥或（XOR)電路 43 栓鎖電路 411 第一反相器 125319.doc • 14· 200926596 412 413 414 . 431 PM41 PM42 PM43 PM44 ❹ NM41 NM42 NM43 NM44 第二反相器 第三反相器 第四反相器 第六反相器 第一 P型電晶體 第二P型電晶體 第三P型電晶體 第四P型電晶體 第一 N型電晶體 第二N型電晶體 第三N型電晶體 第四N型電晶體 ❹ 125319.doc -15-Modifications and changes remain without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic circuit diagram of a conventional dual-edge triggering flip-flop; FIG. 2 is a schematic diagram of a circuit of a low-power dual-edge flip-flop in accordance with the present invention; and FIG. 3 is a schematic diagram showing the waveform of the signal of the present invention. [Main component symbol description] 10 conventional double edge triggering flip-flop 11 first D-type flip-flop 12 second D-type flip-flop 13 multiplexer 40 low-power double-edge flip-flop 41 of the present invention signal delay Circuit 42 Mutually Exclusive or (XOR) Circuit 43 Latch Circuit 411 First Inverter 125319.doc • 14· 200926596 412 413 414 . 431 PM41 PM42 PM43 PM44 ❹ NM41 NM42 NM43 NM44 Second Inverter Third Inverter Fourth inverter sixth inverter first P-type transistor second P-type transistor third P-type transistor fourth P-type transistor first N-type transistor second N-type transistor third N-type Transistor fourth N-type transistor ❹ 125319.doc -15-