200923787 /^i34twT.aoc/n 九、發明說明： 【發明所屬之技術領域】 本發明是關於-種電腦系統和其控 別是關於-種電腦系統，為 -的方法’特 生不可預期行為的方法。 -轉換知作模式時產 【先前技術】 〇 當-電腦系統巾的處理器要改變 «亥處理器的操作狀態相對的必需被調整，且、二守= 的動作通常由另一個裝置來完成。舉了：=: 支有工作可以被執行時，通常會進入;= i =by MQde)° _處㈣關大部份的電路 =的】_等待喚醒(Wake Up)事件發生，然後盘 ^則一致(__叫的操作狀態。當該 二 處理器會將它的新操作狀態告St 作電壓及 入待機模式賴始調整那些操作^里早4在處理器進 出至；份現代的處理器都會將待機模式的告知信號送 Γ科元’來使處理11管理單元_調整操作 ;二5處理器管理單元卻沒有可以告知處理器操作模 完成的信號。因此’如果於處理器正處於待 =板式而處理器管理單元還在調整其操作狀態時發生喚醒 事件’例如中斷(interrupt)。則該處理器會被過早喚醒然後 200923787 23154twtdoc/n ==在不ZT的態7前後广致(一， 預』的仃為如观賽狀況(racing condition) 或不穩疋(mstabi丨ity)將會發生。 利用述的不可預獅行為，傳統的解決方法是 利用今電理盗之外的特設的系統層次的邏輯電路， 隔尚在調整操作狀態時期的喚醒動作。然 季统声送喚轉件給處理1^魏，因此該 士，此外’該系統層次的邏輯電路就必需偵測操作狀 :二ΐ否完成。這將導致系統層次的邏輯電路的 於處理器及處理器設計也會受限 隔唤醒事件的靈活度也合被限:：力=面。必然的，阻 個&早被喚醒的問題’不可預測的行為就會發 生’正個電腦系統的穩定度及可靠度將會被影響。 【發明内容】 法的目的是在提供-種控制處理器的方 =此方法疋在處理器及處理器管理單元間相互交流传 號，以避免處理ϋ過早被倾而發生不可_的行為。 本發财提供-種電m㈣統❹—種交握 (/ndshakmg)機制’用以確定處理器會在其操作 穩定以後才會被喚醒。 :、 ‘〜' 本發明提出-種控制處理器的方法。此方法包括下面 200923787 23154twi.d〇c/n 爺:V驟。。百先，一處理器或另一處理器依據該處理器所 而m的新操作狀恶的改變來程式規劃(program)處理器管 兀。接下來’該處理器在其進人待機模式的同時送出 固:知彳过給處理器管理單元。處理器管理單元在接到 i作後最新狀態的需求，開始調整該處理器的 _二琅、，’ς，在刼作狀態的變更穩定以後，處理器管 早凡送出一個完成信號給該處理器。 ^本發明之控制處理器之方法的—實施例中 =號給處理器二，並 個可選模式下，處理器進入待機模式， 號時被喚醒。在第三個可選 二的-成仏 並不，告知信號，並且開始監控喚;事:有模式 存器寫Πίΐ述實施例中，處理器藉由對待機控制暫 寫入第一數值，存器被 理器管理單元，並且於收到處理給處 開始監控喚醒事件。若待機控制暫存器成信號後 ==入待機模式，送出告知信號給處理器管理單 在收到處卿料挪攸成蝴她。=機= Γ c 200923787 23154twfdoc/n t存器被寫人第三數值，_處_進人待機模式，但不送 u知信號給處理n管理單元，並且開始監控喚醒事件。 在上述的實施例中，處理器之操作狀態至少包括下列其 中之-.處理器的供應電源、處理器的操作頻率、處理 存器值、以及處理器的操作參數。而操作參數被i存在 。 玄處理盗中或另一處理器中或—儲存元件中。 在上述的實施例中，處理器包括多數個功能單元， 處理器的操作狀態包括這些功能單元的啟動和關閉狀離。σ f上義實施射，處理_包括錄_城 =處理器的操作狀態包括這麵立執行單摘啟動和關閉 本發明另提供—種電腦系統，此電㈣統包括了—個 =上的處理ϋ及-個處理器管理單元。處理器管理單元可 =處理雜倾態的改__纽器或其它處理 ^劃。當即將改變操作狀態的處理器進人待機模式，‘二 ^知信號給處理綠料元。處·約釋元 J之=據上述的操作狀態改變開始調整該處理器戈= =亚在處理器的操作狀態變更完成穩定了以後， ^號給該處理器。 几成 。。在本發日⑽電㈣統及處理器控制方法巾 :與^里器管理單元間’於操作狀態變更期間使用的交2 ，制。此讀機制髓過早終止操作狀㈣調整 ς理器的喚醒在該處理器的新操作狀態調整穩成 200923787 ^3X54twi.aoc/n 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉較佳實施例’並配合所_式，作詳細說明如下。 【實施方式】 Ο =電腦系統中處理器的操作模式需要被改變時，若註 操:狀態穩定後才恢復正常操作，不能預期的電 的仃為’例如競賽狀況’將可以被避免。因此本發 日其控制處理㈣方法。為了使本發 據以者瞭’以下特舉實施例作為本發明確實能夠 據以只知的乾例。並且以附圖加以說明。 社夫為依照本發明—實施例之電腦系統方塊圖。 二Si 例之電腦系統⑽包括處理器⑽，處 要變更它的=20及另一處理器130。有時處理器110需 它的-部份舉例而言’處理器11G可能要關閉 要被改變時*作，數起始位址。當操作狀態需 的改變，對處m或另—處理器130依據操作狀態 器叫進入彳科=2()作程式規劃，接下來處理 120。處理器总理„：式且运出—告知信號給處理器管理單元 s理單几120在接收到主知作辨始分祕L丄 的操作狀態改變，術採Γ1號後依據上述 —個完成M / 11G的齡㈣，接著送出 是安全的^以σ知處理器、110此時被喚醒繼續正常工作 在本發明的—個實施例中，處理器110的操作狀態可 200923787 23154twi.doc/n 以包括處理器110的電源電壓、處理 處理器110的暫存器的值、處理。。。1ω的操作頻率、 作參數可以儲存在處理||11()中0 ^的操作參數。其操 儲存在電腦系統100之記悻 處理器〗3〇中、或 理器m可以包含多個=中單(圖中未綠示）。此外，處200923787 /^i34twT.aoc/n Nine, invention description: [Technical field of invention] The present invention relates to a computer system and its control is related to a computer system, the method of 'special unpredictable behavior method. - Conversion of the production mode production [Prior Art] 〇 When the processor of the computer system towel is to be changed «The operating state of the processor must be adjusted relative to each other, and the action of the second suffix = is usually done by another device. Raise: =: When a work can be executed, it usually enters; = i = by MQde) ° _ at (4) off most of the circuit = _ Wait for wake up (Wake Up) event, then ^ Consistent (__calling the operating state. When the second processor will tell its new operating state St voltage and into the standby mode to adjust those operations ^ 4 early in the processor in and out; a modern processor will Sending the notification signal of the standby mode to the Γ ' ' to make the processing 11 management unit _ adjustment operation; the second 5 processor management unit has no signal that can inform the processor to operate the modulo. Therefore, if the processor is waiting for the board While the processor management unit is still adjusting its operating state, a wake-up event, such as an interrupt, occurs. The processor will be prematurely awakened and then 200923787 23154twtdoc/n == in the absence of ZT state 7 (1, The pre-" 仃 仃 rac rac rac rac rac rac rac rac rac rac 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的 的Hierarchical logic circuit In the adjustment of the operating state of the wake-up action. However, the seasons sent the call to the processing 1 ^ Wei, so the taxi, in addition, the system level logic must detect the operation: the second is not completed. This will lead to the system level The logic of the processor and processor design is also limited by the flexibility of the wake-up event is also limited: force = face. Inevitably, the problem of blocking & early wake-up 'unpredictable behavior will The occurrence and stability of a computer system will be affected. [Invention] The purpose of the method is to provide a kind of control processor. This method is used to communicate between the processor and the processor management unit. No. To avoid dealing with behavior that is prematurely being dumped. This is a wealth-providing m- (four) reconciliation---handshake (/ndshakmg) mechanism to determine that the processor will be stable after its operation. Was awakened. :, '~' The present invention proposes a method of controlling a processor. The method includes the following 200923787 23154twi.d〇c/n 爷:V s.. One hundred processors, one processor or another processor according to The new operation of the processor The processor changes the program to program the processor. Next, the processor sends out the firmware while it enters the standby mode: the processor management unit is received. After the latest state of the demand, began to adjust the processor's _ 琅,, 'ς, after the change of the state of the state is stable, the processor tube sends a completion signal to the processor. ^Control processing of the present invention The method of the method - in the embodiment = the number is given to the processor 2, and in an optional mode, the processor enters the standby mode, and the number is awakened. In the third optional two - the 仏 is not, the signal is signaled, and Start monitoring; call: modal register write Π ΐ In the embodiment, the processor temporarily writes the first value to the standby control, the memory is managed by the processor, and the wake-up event is monitored after receiving the processing. . If the standby control register becomes a signal and then == enters the standby mode, the notification signal is sent to the processor management list. = machine = Γ c 200923787 23154twfdoc/n The register is written to the third value, _ _ enters standby mode, but does not send a signal to the processing n management unit, and starts monitoring the wake event. In the above embodiments, the operational state of the processor includes at least the following: the power supply of the processor, the operating frequency of the processor, the value of the processor, and the operating parameters of the processor. The operating parameters are stored by i. Xuan is in the process of stealing or in another processor or in a storage element. In the above embodiments, the processor includes a plurality of functional units, and the operational states of the processors include the activation and deactivation of the functional units. σ f is implemented on the right, processing _ including recording _ city = processor operating state including the implementation of the single-shot start and shutdown of the present invention provides a computer system, the power (four) system includes a = upper processing And a processor management unit. The processor management unit can handle the modified __ button or other processing. When the processor that is about to change the operating state enters the standby mode, the ‘two-know signal is sent to the processing green element. At the same time, according to the above-mentioned operation state change, the processor is adjusted. == Sub-After the operation state change of the processor is completed, the ^ number is given to the processor. A few. . On the date of this (10) power (four) system and processor control method towel: between the management unit and the operating state change period used during the change 2 system. This read mechanism prematurely terminates the operation (4) adjusts the wake of the processor in the new operating state of the processor to adjust the stability to 200923787 ^ 3X54twi.aoc / n in order to make the above features and advantages of the present invention more obvious, below DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) [Embodiment] Ο = When the operation mode of the processor in the computer system needs to be changed, if the operation is completed: the state is stabilized and the normal operation is resumed, and the unpredictable electric power such as "competition condition" can be avoided. Therefore, it is controlled by the method of (4). In order to make the present invention the following specific embodiments, the present invention can be surely known as a dry example. And the description will be made with reference to the drawings. The social network is a block diagram of a computer system in accordance with the present invention. The computer system (10) of the second Si case includes a processor (10) to be changed its =20 and another processor 130. Sometimes the processor 110 needs its - part for example - the processor 11G may have to be turned off to be changed, the number of starting addresses. When the operating state needs to be changed, the pair m or the other processor 130 is programmed according to the operating state to enter the branch = 2 (), and then the processing 120. The processor prime minister „:式的出出—informs the signal to the processor management unit s of the management unit 120 to receive the operation status change of the master knows the secret division L丄, after the operation picks the number 1 and completes the M according to the above-mentioned / 11G age (four), then sent is safe ^ σ know the processor, 110 is now awakened to continue normal operation. In an embodiment of the present invention, the operating state of the processor 110 can be 200923787 23154twi.doc / n The power supply voltage of the processor 110, the value of the register of the processing processor 110, the processing frequency of the operation of 1ω, and the operating parameter of 0^ can be stored in the processing ||11(). In the computer system 100, the processor 〇 3 、, or the processor m can contain a plurality of = medium (not shown in the figure).
Arith.eticandLo.ic^,^；；- Ο 1 態可包括這些功能單元的啟動跟關閉作狀 110可含有多個獨立的執行 —亦或者處理器 有自己的指令管線晌―以^ jessing)。在這種情況下，處理 括這些獨立執行單元的啟動和_狀態。攸作狀態可包 機控行待機指令或寫入-預設值到待 杈式，而預設值可以在三種數值 的 種可選模式相當於對待機以 令的t種可選模式相#於對待機控制暫存器寫二 控制暫存器寫人第ίί;的t種可選模式相當於對待機 佶、，Ϊ第：：種可選模式中（或待機控制暫存器寫入第-數 處理@ UG進人待機模式，送出告知信號給處理器管 德二 120 ’ ί於接收到處理器管理單元送達的完成信號 理；醒事件。在這個可選模式下’只有小部份處 °的電路會被用來監控喚醒事件，因此處理器110 200923787 23]54twi,doc/n ，操作狀態可以被調整到最低的消耗功率。值得注意的 疋，在處理斋110進入待機模式之後以及在處理器Ho開 始監控喚醒事件以前發生的任何喚醒事件(例如，鍵盤上因 按鍵導致的巾斷或傳送來的網路封包)都會減略掉。也因 此避免掉過早地唤醒處理器110的可能。 ΟArith.eticandLo.ic^,^;;- Ο 1 state may include the start and close of these functional units 110 may contain multiple independent executions - or the processor has its own instruction pipeline 晌 - ^ jessing). In this case, the start and _ states of these independent execution units are processed. The state of the operation can be controlled by the chart machine to control the standby command or the write-preset value to the standby mode, and the preset value can be in the three types of the selectable mode equivalent to the standby mode to the t-selectable mode phase. The standby control register writes two control register writers. The t-selectable mode is equivalent to standby 佶, Ϊ:: selectable mode (or standby control register writes the first-number) Handle @ UG into standby mode, send a notification signal to the processor Guan De 2 120 ' ί received the completion of the processor management unit signal; wake up event. In this optional mode 'only a small part ° The circuit will be used to monitor the wake event, so the processor 110 200923787 23] 54twi, doc / n, the operating state can be adjusted to the lowest power consumption. It is worth noting that after processing the fast 110 into standby mode and in the processor Ho starts monitoring any wake-up events that occurred before the wake-up event (for example, a network packet on the keyboard that was triggered by a button or a transmitted network packet) will be reduced, thus avoiding the possibility of waking up the processor 110 prematurely.
在第二種可選模式中（或待機控制暫存器寫入第二數 值i’處理器110進入待機模式’送出告知信號給處理器管 理單兀120，並且在收到處理器管理單元12〇送達的完成 信，時立刻被唤醒。因此，處理器m可以在調整操二狀 完成後立職復運作。和第—可職式補似，在處理 器ϋ進人待機模式之後以及在處㈣11()_來自於處 理^理單το UG送達的完成信號前所發生的任何唤醒 件^會被忽略掉。也因此避免掉過早地倾處理器11〇 的可月匕0 在第三種可選模式中（或待機控制暫存器寫 值）’處理H 11G進人待機模式，並*送出奸信號; 器管理單元120。接著處理器UG便開始監控喚醒事. 这個可選模式可用在當處理器㈣需要等待切事件而; 需要改變猶狀態時。所以此第三種可選模 =了節省功耗而由處理器110執行的傳統㈣ (idle waiting loop) 〇 為了闡明處理器110和處理器管理單元間⑶ 機制，以下進一步說明在電腦系統100中 = 的方法。圖2是本實施例中，依待機指令的第 11 200923787 231Mtwt.doc/n 2imsit ug的控制方法流程圖。參照圖2，在步驟 將發生的操作狀能130根據處理器110即 削。例如，處規劃處理器管理單元 出匯流排，依新;;處理器130π經由—輪入輸 元120。 ，、*作狀L參數來程式賴處理器管理單 M-Tt ]?〇 Jk,、 並且心出一告知信號給處理哭管理 早兀120。如之前所提及的，處理哭" 时&理 種可選模式的待機指 =了猎由執行第- 存器來進入待機模式Γ戈猎由寫入第一數值到待機控制暫 號後在理單元120接收到告知信 告知的操作狀態的變更來調整處理 Ο 在處理考iln 1 &、°在步驟240卜處理器管理單元120 處理哭:值祕f態變更穩定後’送出—完成信號給 後到：到it: 2欢處理器110在進入待機模式 几成k唬刖，將忽略掉所有的喚醒事件。 後，驟250中’在處理器110收到完成信號之 酉累塞ί開始監控喚醒事件。從現在開始，任何唤 =件的發生’都將喚醒處理器110。處理器11〇在被喚 醒後’將以新的操作狀態工作。 的處=t實施例中，依待機指令的第二種可選模式下 处里β 110的控制方法流程圖。參照圖3，在步驟31〇 12 200923787 23154twtdoc/n 日士兮择射而要在另—個不同的操作模式下工作 π ’〜操作核式的改變可以經由處理器u 130程式規劃於處理器管理單元12〇 ^另處理益 ^器_由執行第二種可選模式㈣機指 ==待機控制暫存器來進入待機模式，並丄送= /在步驟330中，處理器管理單元12〇在 Ο 操:狀Ϊ的變，調整處理器110:如二 兀120發送-完成錢給處理器llG。 &理&理早 在步驟350巾，處理器11〇在收 ;新=處:器管理單元m設定的新== 機模式1::;==下，處理器⑽在進入待 醒。以Pw略所有的喚醒事件，直到被完成信號所喚 如果處理器110不需要調整操作狀態，處理器η 間的信號交換就不需要。圖:是利用 程圖。㈣圖指令控做理器UG的實施例的流 ,、 在步驟410中，處理器110進入待播禮 ;而不送出任何信號給處理器管理單元⑽驟0 的方:。根二ί:=:種^ Κ _ Λ施例 種在處理器與處理5|營王？ 凡日的父握機制被用來避免於處理器調整操作狀態期 13 200923787 /3iD4iwr.aoc/n 間，因過早的喚醒事件而導致的無法預期的行為。電腦系 統的穩定性和可靠度必然因此而提升。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作些許之更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 【圖式簡單說明】 圖1是依照本發明一實施例之電腦系統的方塊圖。 圖2-4是本發明之實施例之不同的處理器控制方法的 流程圖。 【主要元件符號說明】 100 .電腦糸統 110 :處理器 Ο 120:處理器管理單元 130 :另一處理器 210〜250 :流程圖之步驟 310〜350 :流程圖之步驟 410〜420 :流程圖之步驟 14In the second optional mode (or the standby control register writes the second value i' processor 110 enters the standby mode' sends a notification signal to the processor management unit 120, and upon receipt of the processor management unit 12 The delivery completion letter is immediately awakened. Therefore, the processor m can be re-established after the adjustment operation is completed. And the first-service complement, after the processor breaks into the standby mode and at the place (four) 11 () _ Any wake-ups from the processing signal sent by the processing unit το UG will be ignored. Therefore, avoiding the premature tilting of the processor 11〇 can be avoided. In the mode (or the standby control register write value) 'process H 11G into the standby mode, and * send the rape signal; the device management unit 120. Then the processor UG starts monitoring the wake-up event. This optional mode can be used when The processor (4) needs to wait for the event to be cut; when it is necessary to change the state of the state, so this third type of mode = the traditional (four) (waiting loop) that is saved by the processor 110 to save power consumption, in order to clarify the processor 110 and processing Management unit (3) The method of controlling in the computer system 100 is further described below. Fig. 2 is a flow chart showing the control method of the 11th 200923787 231Mtwt.doc/n 2imsit ug according to the standby instruction in the present embodiment. Referring to Fig. 2, the step will occur. The operating state energy 130 is cut according to the processor 110. For example, the processor management unit outputs a bus bar, which is new; the processor 130π passes the wheel-input unit 120. The device management single M-Tt]?〇Jk,, and the heart out a signal to deal with cry management early 120. As mentioned before, the processing of crying "time & Hunting is performed by executing the first register to enter the standby mode. The hunter is adjusted by the change of the operation state notified by the notification unit after the first value is written to the standby control continuation Ο in the processing unit Ο in the processing test iln 1 & ;, in step 240, the processor management unit 120 processes the crying: the value of the secret state is stable after the 'send-complete signal to the back: to it: 2 Huan processor 110 enters the standby mode a few k唬刖, Ignore all wakeup events. After that, step 25 0 in 'When the processor 110 receives the completion signal, the sluice starts to monitor the wake-up event. From now on, any occurrence of the call will wake up the processor 110. After the processor 11 is awake, 'will The new operating state is working. In the embodiment, the flow chart of the control method of β 110 in the second optional mode according to the standby instruction. Referring to FIG. 3, in step 31〇12 200923787 23154twtdoc/n兮 射 而 要 要 要 要 要 ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ ～ Optional mode (4) machine finger == standby control register to enter standby mode, and send = / in step 330, the processor management unit 12 is in the process: the change of the processor 110: two兀 120 send - complete the money to the processor llG. &&&&&&&&&&&&&&&&&&<RTIgt; A slight wake-up event with Pw until the signal is completed. If the processor 110 does not need to adjust the operating state, the signal exchange between the processors η is not needed. Figure: is the use of the map. (4) The flow of the embodiment of the command instruction processor UG, in step 410, the processor 110 enters the to-be-broadcast; and does not send any signal to the processor management unit (10). Root two ί:=: kind ^ Κ _ Λ 例 Example in the processor and processing 5 | camp king? The parental gripping mechanism of the day is used to avoid unpredictable behavior caused by premature wake-up events between the processor adjustment operating state period 13 200923787 /3iD4iwr.aoc/n. The stability and reliability of the computer system must therefore increase. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a computer system in accordance with an embodiment of the present invention. 2-4 are flow diagrams of different processor control methods in accordance with an embodiment of the present invention. [Description of main component symbols] 100. Computer system 110: Processor Ο 120: Processor management unit 130: Another processor 210 to 250: Steps 310 to 350 of the flowchart: Steps 410 to 420 of the flowchart: Flowchart Step 14