200921911 UMCD-2007-0l67 24987twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於積體電路及其製造方法，且特別是有 關於半導體元件及其製造方法。 【先前技術】 I乳牛氣日曰體疋一種廣泛使用於諸如是記憶元件、影 像感測器或是顯示器等各種半導體元件的基本結構。典型 的金氧半電晶體包括氧化矽介電層、閘極導電層以及濃摻 摻雜源極/汲極接觸區。隨著線寬的縮減，半導體元件的尺 寸縮小，典型的金氧半電晶體因為閘極寬度縮減，使得其 通道長度也因而縮小。由於啟始電壓變小而次啟始電流增 加，因而衍生短通道效應。另—方面，閘極寬度縮小之後曰， t於源極歧極之_電場增加，目4致賊子效應的 生。因此，通道在接近汲極區之處會產生許多的載子， 造成電崩潰效應。為避免擊穿現象，必須特足夠的通道 長度’”如此’將使得所形成的金氧半電晶體無法被應用之。 解決上述問題的—種方法是制淡摻騎極(LDD)之 =式。淡_汲_方式是將接近通道的源極/汲區的濃度 2 ’即形成赫雜極區，#以減少源極與汲極之間電 造成的熱载子效應。然而’由於淡摻雜汲極區的 度低’因此，其修較高，造成通道區之電子移動 =率減小％件的操作速度變慢，並歸導致消耗功率的增 利用通迢中機械應力(Mechanical_str㈣的控制來改變 200921911 UMCD-2007-0J67 24987twf.doc/n =4=中ΐΓ速度’是一種可以增加電晶體 室从树、又的方法。白知已有提出利用矽化鍺(SiGe)磊晶 =做為電晶體_/沒極接觸區的主要組成之技術。以 做為源極/汲極接觸區的主要組成，與料 ^匕較，由於鍺具有較大的原子體積，可施予通道一壓縮 鍺做_成源概極接_之主要材料 o 進而提升元件的效能 棚松新a in轉半f晶體來說，摻雜區中所摻雜的 蝴払貝易向外擴散，而導致元株姦命 ’、 為解決蝴擴散的問題，提出在摻雜區:基底之二::: 無摻雜的矽化鍺緩衝層之方麸—a曰σ層 ::錯中仍然非常易於擴散到通ΐ區:通; ί厚時，對於換雜區阻值的影響就愈大，元== 【發明内容】 蝴的擴iΜ疋在提供—種半導體元件，其可以有效阻擔 層即可有效阻致其:需非常薄的緩衝 題。 4不會導致讀產生電性上的問 本發明就是在提供—種丰莲 以透過簡單的製縣形成5 ^造方法，其可 ，、衝層以有效阻擋硼的擴散。 200921911 UMCD-2007-0167 24987twf.doc/n 本發明提出一種半導體元件’包括閘極結構、二摻雜 區以及二緩衝層。閘極結構，位於基底上。二摻雜區，其 材質包括摻雜硼之矽化鍺(SiGeB)，位於閘極結構兩側的基 底中。二緩衝層’其材質包括摻雜碳之矽化鍺(SiGeC),分 別位於摻雜區與基底之間。 依照本發明實施例所述，上述半導體元件中，摻雜區 中更摻雜碳。 依照本發明實施例所述，上述半導體元件中，緩衝層 中更摻雜爛’其所雜之硼濃度低於摻_之爛濃度。 依照本發明實施例所述’上述半導體元件中，換雜區 中更摻雜碳。 發明實施例所述’上述半導體元件中，緩衝層 中的奴浪度介於0.05-1%之間。 材併實施例所述，上述半導體树中，基底之 材貝/、摻才准區不同，或與緩衝層不同。 八別實施酬述，上料賴元件巾，緩衝層 刀另衣繞於各摻雜區周圍。 依π本發明實施例所述，上述半導體元 士 構包括閘極介電層與閘極導電層。 、、Ό 依照本發明實施例所丄 為源極/汲極接_。 上抖導體讀中，摻雜區 依照本發明實施例所 極/汲極延伸區，位㈣㈣抖賴π件更包括二源 太心 衝層之間的基底中。 柄月提出—種半導體元件的製造方法。此方法在基 200921911 UMCD-2007-0167 24987twf.doc/n 形l極結構。接著’在閘極結構兩側的基底中分別 ==槽。之後，於各凹射形成緩衝層與第—摻雜區， 碳:=Γίί底;第一摻雜區之間，其材質包括摻雜 反之夕化錯’各苐―掺雜區之材質包括摻_之石夕化鍺。 中=本Γ實施例所述’上述半導體元件的製造方法 衝層所採用之第—反應氣體至少包括碳換 貝源、發源以及錯源。 上述半導體元件的製造方法 之石夕烷；矽源包括不含烷基 錯燒。 依照本發明實施例所述， 中’其中碳摻質源包括含烷基 之矽烷或齒矽烷以及鍺源包括 發明實施例所述，上述半導體元件的製造方法 n基之魏包括曱基；不含絲之雜或齒 石夕垸包括石夕曱烧或二氣石夕曱燒。 =本發明實施觸述，上财導體林的製造方法200921911 UMCD-2007-0l67 24987twf.doc/n IX. Description of the Invention: TECHNICAL FIELD The present invention relates to an integrated circuit and a method of manufacturing the same, and more particularly to a semiconductor device and a method of fabricating the same. [Prior Art] I is a basic structure widely used for various semiconductor elements such as a memory element, an image sensor, or a display. A typical MOS transistor includes a yttrium oxide dielectric layer, a gate conductive layer, and a heavily doped dopant source/drain contact region. As the line width is reduced, the size of the semiconductor element is reduced, and the typical MOS transistor is reduced in length due to the reduction of the gate width. Since the starting voltage becomes smaller and the secondary starting current increases, a short channel effect is derived. On the other hand, after the width of the gate is reduced, the electric field of the source is increased, and the electric field of the thief is increased. Therefore, the channel will generate a lot of carriers near the bungee region, causing an electrical collapse effect. In order to avoid the breakdown phenomenon, it is necessary to have a sufficient channel length ''so that') that the formed gold-oxygen semi-transistor cannot be applied. The solution to the above problem is to make a light-doped rider (LDD) The light_汲_ method is to bring the concentration of the source/deuterium region close to the channel 2' to form the Hebi-polar region, # to reduce the thermal carrier effect caused by the electricity between the source and the drain. However, due to the light blending The degree of the hybrid pole region is low. Therefore, the repair is higher, resulting in the electronic movement of the channel area. The rate of operation is slowed down, and the operating speed of the component is slowed down, and the power consumption is increased. The mechanical stress in the overnight (Mechanical_str (4) control To change 200921911 UMCD-2007-0J67 24987twf.doc / n = 4 = the speed of the middle is a way to increase the crystal chamber from the tree, and the method has been proposed to use the bismuth telluride (SiGe) epitaxy = as electricity The main component of the crystal _/ immersion contact zone is used as the main component of the source/drain contact zone. Compared with the material, since the ruthenium has a large atomic volume, a channel can be applied to compress it. _ Chengyuan is connected to the main material o and further enhances the components In the case of a new singular semi-f crystal, the doped shells in the doped area are easily diffused outwards, which leads to the problem of the singularity of the slabs. Substrate 2::: Undoped bismuth telluride buffer layer of square bran - a 曰 σ layer:: the fault is still very easy to diffuse into the Tongyu area: pass; ί thick, the influence of the resistance of the change zone The larger, the yuan == [Inventive content] The expansion of the butterfly is to provide a kind of semiconductor component, which can effectively resist the layer to effectively block it: it needs a very thin buffer problem. 4 does not lead to read electricity. The present invention is to provide a kind of Fenglian to form a 5^ method through a simple county, which can, and can be used to effectively block the diffusion of boron. 200921911 UMCD-2007-0167 24987twf.doc/n The present invention A semiconductor device includes a gate structure, a two-doped region and a two-buffer layer. The gate structure is located on the substrate. The two-doped region is made of boron-doped germanium telluride (SiGeB) and is located in the gate structure. In the side of the substrate. The two buffer layer's material includes carbon-doped bismuth telluride (SiGeC), respectively Between the doped region and the substrate. According to the embodiment of the invention, in the semiconductor device, the doped region is more doped with carbon. According to the embodiment of the invention, the buffer layer is more doped in the semiconductor device. The boron concentration of the semiconductor element is lower than that of the doping. According to the embodiment of the present invention, in the semiconductor element, the impurity-changing region is more doped with carbon. In the above semiconductor device, the buffer layer is described in the embodiment of the invention. The slave wave in the middle is between 0.05-1%. According to the material and the embodiment, in the above semiconductor tree, the base material of the base material, the doping area is different, or is different from the buffer layer. The material is applied to the material, and the buffer layer is wrapped around the doped regions. According to the embodiment of the invention, the semiconductor structure comprises a gate dielectric layer and a gate conductive layer. Ό, 源 is a source/drain connection _ according to an embodiment of the invention. In the upper chatter conductor read, the doped region is in accordance with the pole/drain extension of the embodiment of the invention, and the bit (4) (d) is further included in the substrate between the two source and the overlying layer. The stalk is proposed as a method of manufacturing a semiconductor element. This method is based on the base structure 200921911 UMCD-2007-0167 24987twf.doc/n. Then 'in the substrate on both sides of the gate structure == slot. Thereafter, a buffer layer and a first doped region are formed in each of the recesses, and carbon:=Γίί bottom; between the first doped regions, the material thereof includes doping and vice versa. _ The stone 夕 锗 锗. In the method of manufacturing the above semiconductor device, the first reaction gas used in the stamping layer includes at least a carbon source, a source, and a source of error. The above-described method for producing a semiconductor device, the source of germanium; the source of germanium includes no alkyl-based mis-fired. According to an embodiment of the present invention, wherein the carbon dopant source comprises an alkyl group-containing decane or a dentane and a ruthenium source, as described in the embodiments of the invention, the method for manufacturing the above semiconductor element includes a ruthenium group; Silk or tooth stone 垸 垸 includes Shi Xi 曱 or two gas stone 曱 曱. = implementation of the present invention, the manufacturing method of Shangcai Conductor Forest
I二；;t體中還通人做，使緩衝層中還摻雜棚， 其所摻雜之硼濃度低於第一摻雜區之硼濃戶。 依照本發明實施例所述，上述半導體元件的製造方法 ’形成第-摻雜區所採用之第二反應氣體至少包括石夕 、鍺源以及硼摻質源。 中 源 ，照本發明實施例所述，上述半導體元件的製造方法 鍺、原體之矽源包括不含烷基之矽烷或鹵矽烷; 鍺源包括鍺烷以及硼摻質源包括硼烷。 依照本發明實施例所述，上述半導體元件的製造方法 ’第二反應驗之*含絲之魏或_錢包括梦甲烧 200921911 UMCD-2007-0167 24987twf.doc/n 依照本發明實施例所述，上述半 中，第二反應氣體中更包括含烷基之石耀70件的製造方法 雜碳。 70土矽烷，使摻雜區更摻 依照本發明實施例所述，上述半 中，形成第一摻雜區所採用之第三，兀件的製造方法 源以及硼摻質源。 Μ氣體包括矽源、鍺 依照本發明實施例所述，上述 石夕源包料含絲之赠件的製造方法 及棚摻質源包括爛烧。 儿’錯源包括諸炫以 依照本發明實關所述，上述 _ t，不含絲之魏或鹵魏包括 t件的製造方法 依照本發明實施例所述，上述=或-氯石夕f嫁。 中’第三反應氣體中更包括含燒c牛的製造方： 摻雜碳。 7烷，以使摻雜區更 依照本發明實施例所述，上述半 中，含烧基之石夕院包括曱基石夕甲燒。⑦件的製造方> 依照本發明實_所述，上述 中，緩衝層令的碟濃度介於〇·〇5，之^件的製造方法 依照本發明實施例所述，上述半^ 中，形成閘極結構的方法包括在基的—70的製造柯 案化閘極介電層與圖案化閘極導電層的表面上依序形成圖 依照本發明實施例所述，上述 更包括在緩衝層之間的基底中形成：第：製造心 200921911 UMCD-2007-0167 24987twf.doc/n 中 依照本發明實施例 第二摻雜區是在第〜^，上述半導體元件的製造方法 中 依照本發明實施例所形J。 第二摻雜區是在第—上述+寺體凡件的製造方法 散 本發明實施例之半導^區形成之後形成。 件，其可以有效阻擔棚的擴 本發明實施例之半暮辨_ 即可有效阻揚硼的擴散m非常薄的缓衝層 本發明實施例夕主道"冷致凡件產生電性上的問題。 簡單的製程細彡倾_體元件的製造方法，其可以透過 為讓本發明之有效阻擋·擴散。 易懂，下他目的、特徵和優點能更明顯 明如下。’牛4實施例，並配合所關式，作詳細說 【實施方式】 示之一種半導體元件的剖 圖1是依照本發明實施例所繪 面示意圖。 二賴® 1 ’本發明提出—種半導體元件15。。此元 +例如疋金氧半導體元件。此元件150包括基底1〇〇、 ^ °構101、摻雜區112、114以及缓衝層12〇、122。基 =100之材質例如是半導體如⑦’或是半導體化合物，抑 層上有鄉01)基底。在—實施例中，基底100為 沾聖払質之矽，或是具有N型井區之P型摻質之矽。閘極 結構^01位於隔離結構102所定義的主動區上。當此元件 為金氧半導體元件時，閘極結構1G1包括圖案化的閑極介 200921911 mCD-2VU7-〇167 24987iw£d〇c/n ，電層⑽之材質包括電常數材料。間 =、未摻雜石夕、摻雜多晶石夕或二例如是摻雜 备閘極導電層1〇6 —摻雜夕日日矽之其中之一。 石夕或多晶石夕t的摻質可接雜石夕或換雜多晶石夕時，在 閉極結㈣也可叹p型終 圖案化的閘極導電岸10 “圖案化的材料層⑽，其位於 金屬矽化物層或是圖案化的材料層109可以是 石夕化金屬層，例如5二金f石夕化物層包括耐火金屬之 101的側壁還可包極結構 隙壁或是多層間隙辟壁110可以是單層間 如是氧化石夕或氮^。曰—材質包括介電材料例 中，12 114位於閘極結構1Gl兩側的基底100 114之材伸而突出於基底⑽的表面。摻雜區⑴、 質之半之材質不相同，其包括換雜p型摻 雏區ιί 2 換胸之石夕化錯。在一實施例中，摻 A 114之材質為摻雜硼但無摻雜碳之矽化鍺。在另 :實施例巾’摻_ 112、H4之材質為摻_且摻雜碳之 f匕錯。推雜區112、114可包括石夕化金屬層130,以降低 值。石夕化金屬層n〇包括耐火金屬之石夕化金屬層，例 如疋鎳、钻、鈦、鋼、钥、担、鎮、_、結、始與這些金 11 200921911 UMCD-2007-0167 24987twf.doc/n 屬的δ I的矽化物之其中之一。在—徐 金氧半導體元件，摻雜區Π2、114例歹1此疋件為 區。當推雜請、U4娜及二;=極， 體元件還可包括另—摻雜區116、118，==礼半導 伸區’其位於間隙壁11〇下方，兩摻 2源極/及極延 摻雜，116、118之材質可與基底100之材質相同^間。 在-實施例中，摻雜區116、118 其/相異。 在一實施例中，摻雜區116、118之^'^^相同。 質之石夕，其Ρ型摻質例如_。1如4雜ρ型摻 濃度可以相同於或低於摻雜區二：⑽中的摻質 緩衝層12(Μ22分別位於摻雜區 。 雜區η2、114中摻質植：ΐί。: 4==層120、122分別介於摻雜_、二 錶£ 116、118之間且環繞在摻 緩衝層120、122之材質盥美麻”时2、114的周圍。 括具有碳摻雜之半導體化；Γ物材f不同，其材質包 一實施财，藉衛Γ 科如摻雜碳之石夕化錯。在 on%之間。在、122中所摻雜的後的濃度介於 雜埃之,Ζ在且衝層12°、122材質為摻 且其中含有二;=二質為換雜伽 低於摻雜區112、u 接貝如硼’但其摻質之濃度 以在沈積的時候臨場捭雜二衝:120、⑵中的m參質可 ，雜以16、118°在—實施例中，摻雜區112、 12 200921911 〇ινι^-^υυ/-υι67 24987twf.doc/n 114之中的蝴摻質在熱循環製程中會擴散到缓衝層ι2〇、 122並且還向外擴散到緩衝層12〇、122之外的基底1〇〇之 中。但是，由於缓衝層12〇、122的材質包含碳，可以阻陷 住(trap)摻雜區112、114中之摻質，有效阻擋摻質擴散到 通道區，因此其所需之厚度非常薄。舉例來說，緩衝層 i2〇、m的厚度僅需20_150埃，即可達到阻擔換雜區112、 114之摻質擴散到通道區的目的。由於緩衝層厚 度非#薄’因此’其對於元件之阻值的影響非常小。 以上所述之半導體元件可以採用各種方法來形成 之。以下舉實關來說明之，然其並_以限制本發明。 至犯是依照本發明—實施觸㈣之—種半導 體凡件的製造方法的流程剖面示意圖。 請參照圖2A，提供—基底1〇〇。 是半導體如％，或是半導料人& / _之材貝例如 ，。在一實施例中，基底 二 Ο 有N型井區之P型师切。接著^ ，或疋具 離結構102。隔離結構102的形成 =^中形成隔 結構法。 7烕方法例如是淺溝渠隔離 全氧S在基底100上形成閘極結構101。當此元件為 c體元件時’閘極結構101 = 層刚、圖案化的閘極導電層106 茶化的閘極介電 閘極介電層刚之材s例如是、氮切、、^^層108。 電常數材料，形成的方法例如是熱氧化法=化秒或高介 積法。閘極導電層106的材質為_ ':疋化學氣相沈 買為摻雜K摻雜多晶石夕時， 13 200921911 a67 24987twf.d〇c/n 在矽或多晶矽中的摻質可 質。頂蓋層108之材質例如：：摻質:也可以是P型摻 化學氣相沈積法。接著，1 矽，形成的方法例如是 間隙壁110a。補償間隙二，結構1G1 _壁形成補償 成的方法例如是熱氧化^。職之材質例如是氧切，形 Γ 為P型，例如為硼。摻:雜區116 118之換質 由離子植入法以形成之「、118的形成方法可以經 其後，請參，昭HI 1 壁110a上形成間隙辟’閉極結構101鍾的補償間隙 隙壁.間隙壁間隙壁⑽構成間I 2;; t body is also made by people, so that the buffer layer is also doped shed, the doping boron concentration is lower than the boron doping of the first doping region. According to an embodiment of the invention, the method for fabricating the above-described semiconductor device's second reactive gas used to form the first doped region includes at least a source of germanium, a germanium source, and a boron dopant. The source of the semiconductor device according to the embodiment of the present invention, the source of the ruthenium, the source of the ruthenium includes an alkyl-free decane or a halodecane; the ruthenium source includes a decane and the boron dopant source includes a borane. According to an embodiment of the present invention, the method for manufacturing the above-mentioned semiconductor device 'the second reaction test* contains the silk or the money including the meteor burning 200921911 UMCD-2007-0167 24987twf.doc/n according to the embodiment of the present invention In the above half, the second reaction gas further includes a method for producing carbonaceous carbon containing 70 pieces of an alkyl group. 70 methane, the doping region is further doped. According to an embodiment of the invention, the third half is used to form the first doping region, the source of the manufacturing method of the element, and the boron dopant source. The helium gas includes a helium source and a crucible. According to an embodiment of the present invention, the method for manufacturing the Shiyueyuan package containing silk gift and the shed dopant source include rotten burning. The erroneous source includes the spurs according to the present invention, the above-mentioned method, the method for manufacturing the wire-free or halogen-containing, including the t-piece, according to the embodiment of the present invention, the above-mentioned = or - chlorite marry. The middle third reaction gas further includes a manufacturer containing burnt c cattle: doped carbon. The alkane is such that the doped region is further described in accordance with an embodiment of the present invention. In the above half, the stone-containing stone court comprises a sulfide stone. According to the present invention, in the above, the buffer layer has a disc concentration of 〇·〇5, and the manufacturing method of the member is as described in the embodiment of the present invention. A method of forming a gate structure includes sequentially forming a pattern on a surface of a silicon-based gate dielectric layer and a patterned gate conductive layer of a base 70, which is further included in a buffer layer, in accordance with an embodiment of the present invention. Formed in the substrate: a manufacturing core 200921911 UMCD-2007-0167 24987twf.doc/n A second doping region according to an embodiment of the present invention is implemented in the above method for manufacturing a semiconductor device according to the present invention. Example is J. The second doping region is formed after the formation of the semi-conducting region of the first embodiment of the present invention. The device can effectively block the expansion of the shed. The invention can effectively prevent the diffusion of boron. m. A very thin buffer layer. The embodiment of the present invention has the electrical property of the cold main body. The problem. A simple process for manufacturing a thin body element that can be effectively blocked and diffused for the purpose of the present invention. Easy to understand, his purpose, characteristics and advantages can be more clearly as follows. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A cross-sectional view of a semiconductor device shown in Fig. 1 is a schematic view of an embodiment of the present invention. The present invention proposes a semiconductor element 15. . This element + is for example a germanium oxynitride component. This element 150 includes a substrate 1 , a structure 101 , doped regions 112 , 114 , and buffer layers 12 , 122 . The material of the base = 100 is, for example, a semiconductor such as 7' or a semiconductor compound, and the substrate has a substrate of 01). In the embodiment, the substrate 100 is a tantalum crucible or a P-type dopant having an N-type well region. The gate structure ^01 is located on the active region defined by the isolation structure 102. When the component is a MOS device, the gate structure 1G1 includes a patterned dummy electrode 200921911 mCD-2VU7-〇167 24987iw£d〇c/n, and the material of the electrical layer (10) includes an electrically constant material. Between =, undoped shi, doped polycrystalline or bis, for example, one of the doped gate conductive layers 1 〇 6 - doped eve. The mineralization of Shi Xi or polycrystalline stone tt can be mixed with Shishi or replaced with polycrystalline stone. In the closed pole junction (4), the p-type final patterned gate conductive shore 10 is also stunned. (10), the metal telluride layer or the patterned material layer 109 may be a shihua metal layer, for example, the 5 bis gold f lithium layer includes the sidewall of the refractory metal 101 or may have a polar structure gap or multiple layers. The gap opening wall 110 may be a single layer such as oxidized stone or nitrogen. In the case of a dielectric material, 12 114 is located on the surface of the substrate 100 114 on both sides of the gate structure 1G1 and protrudes from the surface of the substrate (10). The material of the doped region (1) and the half of the material is different, and includes the replacement of the p-type doping region ιί 2 for the replacement of the chest. In one embodiment, the material doped with A 114 is doped with boron but no In addition, the material of the embodiment is characterized in that the material of the doped film 112 is mixed with and mixed with carbon. The doping regions 112 and 114 may include the metal layer 130 to reduce the metal layer 130. The stone layer of the shixihua metal layer includes a layer of refractory metal such as ruthenium nickel, diamond, titanium, steel, key, dan, town, _, And one of the δ I bismuth compounds of the genus 11 200921911 UMCD-2007-0167 24987 twf.doc/n. In the - Xu Jin oxygen semiconductor component, doped region Π 2, 114 cases 歹 1 Zone. When pushing, U4 Na and II; = pole, the body component may also include another - doped region 116, 118, == 礼半导伸区' which is located below the spacer 11〇, two doped 2 source / and extremely doped, the material of 116, 118 may be the same as the material of the substrate 100. In the embodiment, the doping regions 116, 118 are/different. In an embodiment, the doping region 116, 118^^^^ is the same. The quality of the stone, its Ρ type dopant such as _. 1 such as 4 hetero ρ type doping concentration can be the same or lower than the doping zone two: (10) in the dopant buffer layer 12 (Μ22 They are respectively located in the doped region. The doped regions η2, 114 are doped: ΐί.: 4 == layers 120, 122 are respectively between doping_, two tables £116, 118 and surround the buffer layer 120, 122 The material is 盥 盥 ” 时 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 2、 Between %. In, 1 The concentration after doping in 22 is between the doped, the Ζ 且 and the layer 12°, 122 is doped and contains two; = the second is the impurity gamma lower than the doping region 112, u Boron' but the concentration of its dopant is such that it is noisy at the time of deposition: 120, the m parameter in (2) can be mixed with 16,118° in the embodiment, the doping region 112, 12 200921911 〇ινι The butterfly dopant in ^-^υυ/-υι67 24987twf.doc/n 114 diffuses into the buffer layer ι2〇, 122 in the thermal cycle process and also diffuses outward to the substrate other than the buffer layers 12〇, 122. 1〇〇. However, since the material of the buffer layers 12, 122 contains carbon, the dopants in the doped regions 112, 114 can be trapped, effectively blocking the diffusion of the dopant into the channel region, so the required thickness is very thin. . For example, the thickness of the buffer layer i2〇, m is only 20-150 angstroms, so that the dopants of the resistive replacement regions 112, 114 can be diffused into the channel region. Since the thickness of the buffer layer is not thin, the effect on the resistance of the element is very small. The above semiconductor elements can be formed by various methods. The following is a description of the matter, but it is intended to limit the invention. The sin is a schematic cross-sectional view of a method for manufacturing a semiconductor article in accordance with the present invention. Referring to FIG. 2A, a substrate 1 is provided. It is a semiconductor such as %, or a semi-conductor & In one embodiment, the substrate has a P-type cut in the N-well region. Then ^, or the 离 is away from the structure 102. The formation of the isolation structure 102 forms a spacer structure. The 7 烕 method is, for example, shallow trench isolation. The total oxygen S forms a gate structure 101 on the substrate 100. When the component is a c-body component, the gate structure 101 = the layered, patterned gate conductive layer 106, the gate dielectric gate dielectric layer, such as a nitrogen cut, ^^ Layer 108. The electric constant material is formed by, for example, a thermal oxidation method = a second or a high dielectric method. The material of the gate conductive layer 106 is _ ': 疋 chemical vapor deposition is purchased as a doped K-doped polycrystalline stone, 13 200921911 a67 24987twf.d〇c / n dopant in the ruthenium or polycrystalline ruthenium. The material of the cap layer 108 is, for example, a dopant: it may also be a P-type doped chemical vapor deposition method. Next, 1 矽, the method of formation is, for example, the spacer 110a. Compensation gap 2, the structure 1G1 _ wall formation compensation method is, for example, thermal oxidation. The material of the job is, for example, oxygen cut, and the shape is P type, for example, boron. The doping of the impurity region 116 118 is formed by ion implantation. The formation method of 118 can be followed by the formation of a gap between the opening and closing walls of the HI 1 wall 110a. Wall. Gap spacer (10)
O 示者，其也可上與層數並不限於圖式所緣 ΐ=程乾 反瘅Α體為*;-:衣程例如是電漿蝕刻製程，所通入的 二= ^脚等向性侧製程例 式敍刻製程為電^刻製程。在-實施例中，乾 〇2、二通入的反應氣體為叫、 液(BOE)做為綱、夜方法例如是以緩衝氧化物兹刻溶 14 200921911 UMCU-2UU/-Ui67 24987tw£doc/n 之後，請參照圖2C，在凹槽124與i2 :Γ=_120、122_〜3 具有碳摻雜之半導體化合物材料如摻i 反之石夕化錯，其石炭的濃度介於0.05-1%之門。每雜 中，緩衝層120、122材質為換崎石山少 曰1在只施例 硕摻質。緩衝層120、122的彤：U化鍺’且其中不含 積法進行石夕的選擇£域石曰^法可以採用化學氣相沈 fO shows that the number of layers and layers is not limited to the figure ΐ = Cheng dry 瘅Α body is *; -: the process is, for example, a plasma etching process, the two passes = ^ foot The sexual side process exemplification process is an electric engraving process. In the embodiment, the reaction gases of the dry and the second pass are called the liquid (BOE), and the night method is, for example, a buffered oxide. 14 200921911 UMCU-2UU/-Ui67 24987 TW/doc/ After n, please refer to FIG. 2C, in the groove 124 and i2: Γ=_120, 122_~3, the semiconductor compound material having carbon doping, such as doping i, and vice versa, the concentration of carbon charcoal is between 0.05-1%. door. In each miscellaneous, the buffer layers 120 and 122 are made of Kosaki Stone Mountain and less than 1 in the application. The buffer layer 120, 122 has a 彤: U 锗 ′ and the inclusion of the method for the shi 的 £ £ £ £ 可以 可以 可以 可以 可以 可以 可以 可以 可以
O 邱猫日日層所彳木用之反應氣體包括 《石夕说或—鎌騎駄及鍺〜絲 烷例如是甲基矽甲烷，不含俨美之^、“、° 3烷基之矽 甲燒或二氯石夕甲夕燒或南石夕垸例如是矽 括甲基石夕甲貌、二氯石夕甲二、錯烧以;^用f反應氣體包 別為 5-4GSCem、5G_2G()seem、1()^ ’其流量分 溫度為攝氏度；愿:以及】0删™ 緩衝層120、122材質I 托。在另—實施例中， 二㈣“二二了二^巧、量 亦或疋來自於摻雜區116、118 矛茨％臨％摻 m f的爾f向外擴散所“的^成之接雜區 在形成緩衝層12〇、〗22之後， 二，例如是源極/汲極接觸區之:以^ ^之材f不相同，其包括摻 如摻雜〜。在-實施例中以= 15 921911 叫〜67 24987twfd〇c/n 化鍺。摻雜區n2、m 長製程ϋ在沈積的過程;進行選擇區域磊晶成 植入製程來摻_，以形成摻雜由離子 臨場摻_的石夕化鍺蠢晶層=夕^蟲晶層。形成 石夕源;以者二:不含烧基之錢或齒彻為 石夕院做為_質源。不含炫基之 ”兀㈣矽烷例如是矽甲烷或二氯矽 每 中，所採用的反應氣體包括二氣峨；在:= :，其流量分別為5〇,〇_，儀·、 ΓΓ 5〇T?0_300sccm，·溫度為攝氏_養度；壓 f為50托。在另一實施例中，摻雜區112、114之材質 摻雜碳之魏緒。摻雜區112、u4中度O The reaction gas used for the eucalyptus in the day of the Qiu cat includes "Shi Xi said or - 镰 駄 駄 锗 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝 丝For example, it is a kind of methyl sulphate, a smectite, a smectite, and a misfiring; and a f-reaction gas is used as a 5-4GSCem, 5G_2G ()seem, 1()^ 'The flow rate is in degrees Celsius; wish: and] 0 delete TM buffer layer 120, 122 material I support. In another embodiment, two (four) "two two two two skillful, quantity Or 疋 from the doped regions 116, 118, the spears%%, the mf-doped f, the outwardly diffused region, after the formation of the buffer layer 12, 22, and the second, for example, the source / 汲 接触 contact area: ^ ^ material f is not the same, which includes doping as doping ~. In the embodiment = 15 921911 called ~ 67 24987twfd 〇 c / n 锗 锗. Doped area n2, m The long process is in the process of deposition; the selective region is epitaxially implanted into the implantation process to dope _ to form the doping layer of the Xixihuayu = = = = 离子 离子 离子 离子 离子 离子 离子 离子; The second one: no burning base Or the tooth is used as the source of _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ They are 5 〇, 〇 _, 仪·· ΓΓ 5〇T? 0_300sccm, · temperature is Celsius _ nutrition; pressure f is 50 Torr. In another embodiment, the doped regions 112, 114 are doped with carbon. Doped region 112, u4 moderate
Ci 廷擇£域猫晶成長製程並在沈積的過程中臨場摻雜蝴與碳 =成之’或疋採用化學氣相沈積法進行選擇區域蟲晶成 長‘程並在沈積的過程中臨場摻雜碳，先形成摻雜碳的矽 化錯蟲晶層，再經由離子植入製程來摻雜硼，以形成摻雜 删與碳的石夕化錯屋晶層。形成臨場摻雜硼與碳的石夕化錯磊 晶層的所使用之反應氣體包括碳摻質源、石夕源、錯源以及 硼摻質源。例如是以含烷基之矽烷做為碳摻質源；以不含 烷基之矽烷或i矽烷做為矽源；以鍺烷做為鍺源以及以硼 烷做為硼摻質源。含烷基之矽烷例如是曱基矽甲烷，不含 16 200921911 ^ν^-,υυ,-υι67 24987twf.d〇c/n 院基之石夕烷或鹵矽烷例如是矽甲烷或二氯矽曱烷。在一實 把例中，所採用的反應氣體包括曱基石夕甲烧、二氯石夕曱烧、 錯烧、氯化氫以及硼烷’其流量分別為5_4〇sccm、 50-200sccm、l〇-i〇〇sccm、i〇_2〇〇sccm 以及 5〇-3〇〇sccm ; 溫度為攝氏600-800度；壓力為5-50托。 其後’去除頂蓋層108。去除頂蓋層1〇8的方法可以 採用濕式蝕刻法例如是使用稀釋的氫氟酸溶液。 f) 之後’請參照圖2D，在摻雜區112、114以及閘極導 電層106上分別形成矽化金屬層128、132、130，以降低 其阻值。石夕化金屬層128、132、130的形成方法可以採用 自行對準矽化製程。矽化金屬層所使用之金屬包括对火金 屬，例如是鎳、姑、鈦、銅、铜、钽、鎮、铒、錯、銘與 該些金屬的合金。 圖3A至3D是依照本發明另一實施例所繪示之一種半 導體元件的製造方法的流程剖面示意圖。 請參照圖3A，提供一基底1〇〇。基底1〇〇之材質例如 〇 是半導體如矽，或是半導體化合物，抑或是絕緣層上有咬 基底。在一實施例中，基底100為Ν型摻質之矽，或是具 有Ν型井區之Ρ型摻質之矽。接著，在基底1〇〇中形成隔 離結構102。隔離結構102的形成方法例如是淺溝罕隔離 結構法。 然後，在基底100上形成閘極結構101。當此元件為 金氧半導體元件時，閘極結構101包括圖案化的閘極介電 層104、圖案化的閘極導電層106與圖案化的頂蓋層1〇8。 17 200921911 *67 24987twf.doc/n 開極介電層1〇4之材質例如是、氮〜 電常數材料，形成的方法例如是執氧化法^化石夕或高介 積法。閘極導電層1〇6的。當間極1〇6之學氣相沈 推雜多晶石夕時，在石夕或多晶石夕中的換質可以=為摻雜石夕或 也可以是P师質。頂蓋層⑽之材㈣^^型摻質， 成的方法例如是化學氣相沈積法 二乳化石夕，形 的側壁形成補償間隙壁咖。在閱極結構101 如是氧化石夕，形成的方法例如是埶法%_10a之材質例 側壁的補償間隙壁11Ga上形成間隙壁開極結構101 隙壁UGa構朗隙壁UG。卿 ’ W與補償間 材料例如是氧化石夕或是氮化石夕。开Γ成二ί材質包括介電 電材料層，之後再進行非等向性法=先形成介 形狀並不限於圖式崎示者 牵間隙壁1U)之 包括更多層間隙壁。 、也了以疋其他的形狀，或 其後，以頂蓋層108以及間隙壁 刻製程’餘刻閘極結構101之 為罩幕’進行餘 124與凹槽126。钱刻製程包括非形成凹槽 反應氣體為氟煙例:是所通入的 ，她i製程或是濕式向，製程例 式钱刻製程為轉細m程^在施例中，乾 〇2、ci2。濕式餘刻製程之二氣體為NF3、 液做為蝕刻液。 疋以緩衝氧化物蝕刻溶 200921911 24987twf.d〇c/n /之後，清參照圖3B，分別在凹槽124與126之中先形 成，衝層120、122。緩衝層120、122材質與基底1〇〇之 材質=同’其材質包括具有碳摻雜之半導體化合物材料如 摻雜碳之矽化鍺，其碳的濃度介於0.05-1%之間。在—實 施例中’緩衝層120、122材質為摻雜碳之石夕化錯，且Α中 不含蝴摻質°緩衝層12〇、122的形成方法可以採用化學氣 相/尤積法進行選擇區域蟲晶成長製程並在沈積的過程中臨 場摻雜碳’以軸_碳_化鍺i晶層。形成摻雜碳的 砍化錯蟲晶層所使㈣反應氣體包括碳摻f源、砍源以及 鍺源。例如是以含絲之魏做為碳摻質源、不含烧基之 魏或i魏做切源以及舰做為_ ς :ΐί:Γ厂烧。在一實施例中，所採用的反應氣體包 別氯化氣，其流量分 设 <、、、 SCCm、0_200sccm、l〇-l〇〇sccm 以及 i〇_2〇〇s · 溫度為攝氏600-800度；壓力為5_5〇托。在另— ’ =衝層120、122材質為摻雜碳之石夕化錯，且含 微旦 成摻雜撕繼晶製程= :二=ΓΓη6、118或是後續形成之摻雜區 2 114之中的硼摻質向外擴散所造成的。 在形成_層12G、122之後，接著，形成 ’例如是源極/汲極接觸區。摻雜區112、: ϋ 100之材質不相同，其包括換雜P型 ^與 合物如摻_之石夕化鍺。在一實施例中，摻雜體化 之材質為摻胸但無摻雜碳之魏錯。摻_ 112= 19 200921911 -167 24987twf.d〇c/n 化鍺_，再= 臨場摻_的魏錯產晶層 ^ j，成 錯源以及_原。例如是=體包括石夕源、 ===鍺源;以故為爾源。不含烧 基之魏或鹵魏例如是㈣炫如二氣 Π二制么反？氣體包括二財^、錯院氯，匕氫 讀職5G_2GGseem、办職隨、 -OOsccm以及50_300sccm ;溫度為攝氏·_度；壓 力為5-50托。在另一實施例中，摻雜區112、114之材質 為摻雜硼且摻雜碳之矽化鍺。摻雜區112、114的形成方法 可以採用化學氣相沈積法進行選龍域蟲晶成長製程並在 沈積的過程中臨場摻雜硼與碳以形成之，或是採用選擇區 域，晶成長製程並在沈積的過程中臨場摻雜碳，先形成摻 雜碳的矽化鍺磊晶層，再經由離子植入製程來摻雜硼，以 形成摻雜硼與碳的矽化鍺磊晶層。形成臨場摻雜硼與碳的 矽化鍺磊晶層所使用的反應氣體包括碳掺質源、矽源、鍺 源以及硼摻質源。方法例如是以含烷基之矽烷做為碳摻質 源，以不含烷基之矽烷或鹵矽烷做為矽源；以鍺烷做為鍺 源以及以硼烷做為硼摻質源。含烷基之矽烷例如是曱基矽 曱烧’不含烧基之石夕烧或_石夕烧例如是石夕曱烧如二氯石夕甲 烧。在一實施例中，所採用的反應氣體包括曱基石夕曱烧、 二氯矽曱烷、鍺烷、氯化氫以及硼烷，其流量分別為 20 200921911 ,167 24987twf.doc/n 5-4〇SCCm、5〇-20〇sccm、10_1〇〇sccm、1〇_2〇〇sccm 以及 50-300sccm，溫度為攝氏6〇〇_8〇〇度；壓力為5_5〇托。 其後，睛參照圖3C，去除間隙壁u〇b，然後，在基 底1〇〇中形成摻雜區116、118，如源極級極延伸區。摻 亦隹區116、118之摻質為p型，例如為硼。摻雜區丨16、118 的形成方法可以經由離子植入法以形成之。 之後，凊參照圖3D，在補償間隙壁u〇a上形成另一 層間隙壁UGe。間賴⑽之材f包括介電材料例如是 氧化石夕或是氮化石夕。形成的方法可以先形成介電材料層， 之後再，行非等向性敍刻製程。其後，去除頂蓋層⑽。 =除頂蓋層108的方法可轉旧以侧 酸溶液。之後，在摻雜區112、114以及閉極4 層舰上为別形成石夕化金屬層128、132、13〇,以 程。魏金屬層所制之金屬包括耐火金 Ο 錄、鈦、銅、翻、组、鶴、_、錯、齡 該些金屬的合金。 /、 @^發1月2述實施财，在摻雜區的_形成的_ ’由於碳能阻擋住姻賴散，因此所需= g的厚度非常薄，對於元件之阻值的影響非常小。、 實施例中，在摻雜區的周圍形成含碳的 緩衝層的方法非本簡易，對於製程產率的影響不大 本發上，然其▲非用以限定 ^仕1了热1此技藝者，在不脫離本 圍内，當可作些許之更動與潤飾，因此本發明2以 21 200921911 〜，又w —…Vi67 24987twf.doc/n 當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是依照本發明實施例所繪示之一種半導體元件的剖 面示意圖。 圖2 A至2 D是依照本發明一實施例所繪示之一種半導 體元件的製造方法的流程剖面示意圖。 圖3A至3D是依照本發明另一實施例所繪示之一種半 導體元件的製造方法的流程剖面示意圖。 【主要元件符號說明】 100 基底 101 閘極結構 102 隔離結構 104 閘極介電層 106 閘極導電層 108 頂蓋層 109 材料層 110、110b、110c :間隙壁 110a :補償間隙壁 112、114、116、118 :摻雜區 120、122 :缓衝層 124、126 :凹槽 128、130、132 :矽化金屬層 150 :半導體元件 22Ci Ting chooses the domain of the cat crystal growth process and in the process of deposition, the on-site doping of the butterfly and the carbon=chengzhi' or the chemical vapor deposition method for the selective area of the crystal growth process and the on-site doping during the deposition process Carbon, first forming a carbon-doped bismuth crystal layer, and then doping boron through an ion implantation process to form a doped and carbon-deposited smectite layer. The reaction gases used to form the in-situ doped boron and carbon doped layer include a carbon dopant source, a Shixia source, a fault source, and a boron dopant source. For example, an alkyl-containing decane is used as a carbon source; an alkyl-free decane or i-decane is used as a ruthenium source; decane is used as a ruthenium source and borane is used as a boron source. The alkyl-containing decane is, for example, anthracenyl methane, which does not contain 16 200921911 ^ν^-, υυ, -υι67 24987twf.d〇c/n. The base-based alkane or halodecane is, for example, methane or dichloromethane. alkyl. In a practical example, the reaction gases used include sulfhydryl ketone, chlorite, mis-fired, hydrogen chloride, and borane, which have flow rates of 5_4 〇 sccm, 50-200 sccm, and l〇-i, respectively. 〇〇sccm, i〇_2〇〇sccm and 5〇-3〇〇sccm; temperature is 600-800 degrees Celsius; pressure is 5-50 Torr. Thereafter, the cap layer 108 is removed. The method of removing the cap layer 1 〇 8 may employ a wet etching method using, for example, a diluted hydrofluoric acid solution. f) Thereafter, referring to Fig. 2D, deuterated metal layers 128, 132, 130 are formed on doped regions 112, 114 and gate conductive layer 106, respectively, to reduce their resistance. The formation method of the Shihua chemical metal layers 128, 132, and 130 can be performed by self-alignment. The metal used in the deuterated metal layer includes alloys of fire metals such as nickel, australis, titanium, copper, copper, bismuth, town, bismuth, writh, and metals. 3A through 3D are schematic cross-sectional views showing a process of fabricating a semiconductor device in accordance with another embodiment of the present invention. Referring to FIG. 3A, a substrate 1 is provided. The material of the substrate 1 is, for example, a semiconductor such as germanium or a semiconductor compound, or a bite substrate on the insulating layer. In one embodiment, the substrate 100 is a ruthenium type dopant or a ruthenium type dopant having a ruthenium type well region. Next, an isolation structure 102 is formed in the substrate 1A. The method of forming the isolation structure 102 is, for example, a shallow trench isolation structure method. Then, a gate structure 101 is formed on the substrate 100. When the device is a MOS device, the gate structure 101 includes a patterned gate dielectric layer 104, a patterned gate conductive layer 106, and a patterned cap layer 1 〇8. 17 200921911 *67 24987twf.doc/n The material of the open dielectric layer 1〇4 is, for example, a nitrogen-to-electric constant material, and the method of formation is, for example, an oxidation method or a high-dielectric method. The gate conductive layer is 1〇6. When the inter-electrode 1 〇 6 is in the gas phase, the metamorphism in the day or the polycrystalline stone may be = doped stone or may be P. The top cover layer (10) is made of (4) ^^ type dopant, and the method is formed by chemical vapor deposition, emulsified stone, and the sidewall of the shape forms a compensation gap wall. In the case where the electrode structure 101 is an oxidized stone, for example, a method of forming a material of the %%_10a, the spacer opening wall 11Ga of the side wall is formed with a gap opening structure UGa. The material of the Qing's and the compensation room is, for example, oxidized stone or nitrite. The opening material is composed of a dielectric material layer, and then the anisotropic method is formed. The first shape is not limited to the pattern. The spacer 1U) includes more layers of spacers. Further, in other shapes, or thereafter, the cover layer 108 and the gap-cut process "the remaining gate structure 101 as a mask" are used to carry out the remaining 124 and the recess 126. The engraving process includes the non-groove reaction gas as fluorine smoke: it is imported, her process is either wet or wet, and the process is in the form of a fine m process. In the case, cognac 2 , ci2. The second gas of the wet remnant process is NF3, and the liquid is used as an etchant.疋 缓冲 缓冲 2009 219 219 219 219 219 219 219 219 219 219 219 219 219 219 219 219 219 219 219 219 219 219 219 219 219 219 219 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 The material of the buffer layers 120 and 122 and the material of the substrate 1 are the same as the material of the semiconductor compound having carbon doping such as carbon doped cerium, and the carbon concentration is between 0.05 and 1%. In the embodiment, the buffer layer 120 and 122 are made of doped carbon, and the method for forming the buffer layer 12〇, 122 is not included in the buffer. The chemical vapor phase/expansion method can be used. The regional insect crystal growth process is selected and the carbon-by-axis-carbon-chemical layer is deposited in the process of deposition. The formation of a carbon-doped chopped aerated layer causes the (IV) reaction gas to include a carbon-doped source, a source of chopping, and a source of germanium. For example, the silk containing Wei as a carbon source, the non-burning Wei or i Wei to cut the source and the ship as _ ς : ΐ ί: Γ factory burning. In one embodiment, the reaction gas used is encapsulated with chlorinated gas, and the flow rate thereof is set to <,,, SCCm, 0_200 sccm, l〇-l〇〇sccm, and i〇_2〇〇s. The temperature is 600 ° C. 800 degrees; pressure is 5_5 〇. In the other - ' = stamping layer 120, 122 material is doped carbon stone, and micro-denier doping and tearing process = = two = ΓΓη6, 118 or subsequently formed doping zone 2 114 Caused by the outward diffusion of boron dopants. After forming the _ layers 12G, 122, then, for example, a source/drain contact region is formed. The doped regions 112, ϋ 100 are different in material, and include a P-type compound and a compound such as yttrium. In one embodiment, the doped material is a brazed but undoped carbon. _ 112 = 19 200921911 -167 24987twf.d〇c / n 锗 _, then = the field of _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ For example, = body includes Shi Xiyuan, ===锗 source; For example, Wei or Halogen, which does not contain a burning base, is (4) dazzling like two gas. Gases include Er Cai ^, wrong courtyard chlorine, hydrogen hydrogen read 5G_2GGseem, office, -OOsccm and 50_300sccm; temperature is Celsius _ degrees; pressure is 5-50 Torr. In another embodiment, the doped regions 112, 114 are made of boron doped and carbon doped germanium. The method for forming the doping regions 112 and 114 may be performed by a chemical vapor deposition method for selecting a dragon crystal growth process and forming boron and carbon in the deposition process, or using a selective region and a crystal growth process. In the deposition process, carbon is implanted in the field, and a carbon-doped bismuth telluride epitaxial layer is formed first, and boron is doped through an ion implantation process to form a bismuth telluride epitaxial layer doped with boron and carbon. The reaction gases used to form the epitaxial layer of germanium telluride doped with boron and carbon include a carbon dopant source, a germanium source, a germanium source, and a boron dopant source. The method is, for example, an alkyl-containing decane as a carbon dopant source, an alkyl-free decane or a halodecane as a ruthenium source; decane as a ruthenium source and borane as a boron dopant source. The alkyl group-containing decane is, for example, fluorenyl hydrazine. The sulphur-free stone-free simmering or _ stone simmering is, for example, a sulphur-like smoldering such as a chlorite. In one embodiment, the reaction gases used include sulfhydryl sulfonium, dichlorodecane, decane, hydrogen chloride, and borane at flow rates of 20 200921911, 167 24987 twf.doc/n 5-4 〇 SCCm, respectively. 5〇-20〇sccm, 10_1〇〇sccm, 1〇_2〇〇sccm, and 50-300sccm, the temperature is 6〇〇_8〇〇 degrees Celsius; the pressure is 5_5〇. Thereafter, referring to Fig. 3C, the spacers u 〇 b are removed, and then doped regions 116, 118, such as source-level extension regions, are formed in the substrate 1 。. The dopants doped into the germanium regions 116, 118 are p-type, such as boron. The method of forming the doped regions 16, 118 can be formed by ion implantation. Thereafter, referring to Fig. 3D, another layer of spacers UGe is formed on the compensation spacers u〇a. The material f of the spacer (10) includes a dielectric material such as oxidized stone or nitrite. The method of forming may first form a layer of dielectric material, and then perform an anisotropic process. Thereafter, the cap layer (10) is removed. = The method of removing the top cover layer 108 can be used to convert the old side acid solution. Thereafter, the ferritic metal layers 128, 132, and 13 are formed on the doped regions 112, 114 and the closed-pole four-layer ship. The metals made of the Wei metal layer include refractory gold, titanium, copper, turn, group, crane, _, wrong, age alloys of these metals. /, @^ 发 January 2 implementation of the financial, in the doped area _ formed _ 'because carbon can block the marriage, so the thickness of the required = g is very thin, the impact on the resistance of the component is very small . In the embodiment, the method of forming the carbon-containing buffer layer around the doped region is not simple, and the effect on the process yield is not large, but the ▲ is not used to limit the skill. If you do not leave this area, you can make some changes and retouching, so the invention 2 is 21 200921911 ~, w... Vi67 24987twf.doc/n, as defined in the attached patent application scope . BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a semiconductor device in accordance with an embodiment of the present invention. 2A through 2D are schematic cross-sectional views showing a method of fabricating a semiconductor device according to an embodiment of the invention. 3A through 3D are schematic cross-sectional views showing a process of fabricating a semiconductor device in accordance with another embodiment of the present invention. [Main component symbol description] 100 substrate 101 gate structure 102 isolation structure 104 gate dielectric layer 106 gate conductive layer 108 top cover layer 109 material layer 110, 110b, 110c: spacer 110a: compensation spacers 112, 114, 116, 118: doped regions 120, 122: buffer layers 124, 126: recesses 128, 130, 132: deuterated metal layer 150: semiconductor component 22