200921348 ， 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種電源適配電路。 【先前技術】 電源不僅為電腦硬體提供電壓，還與主機板之間存在訊 號傳輸，且該等訊號於時間次序上有關係，即時序。時序係 電源與主機板良好配合之重要條件，亦係導致電腦無法正常 開機，以及電源與主機板不相容之最常見原因，其中時序中 最重要係系統電源之輸出電壓（通常以+5V為代表）與電源 狀態訊號PWR_GOOD、開機訊號PS_ON之間之關係，該電 源狀態訊號PWR_GOOD為高電平時代表電源準備就緒，其 為低電平時代表電源未準備就緒，該開機訊號PS_ON為低 電平時代表開機》其為局電平時代表不開機。電腦開機及關 機之工作過程如下： 一 ATX (Advanced Technology Extended)電源於通電 :: 後，輸出一 5V備用電源電壓（5V SB電壓）到主機板，主 、 一 機板上少數部分線路開始工作，並等待開機操作，這叫做待 機狀態；當按下主機開關時，主機板就把開機訊號PS_ON 變成低電平，該ATX電源接到低電平後開始啟動並產生所 有輸出電壓，於所有輸出電壓正常建立後100-500ms内，電 源將會把電源狀態訊號PWR_GOOD變成高電平傳回給主機 板，表示電源已經準備好，然後主機板開始啟動及運行；正 常關機時，主機板於完成所有關機操作後，把開機訊號 PS_0N恢復成高電平，ATX電源將關閉所有輸出電壓，只 7 200921348 ，保留該5V備用電源電壓輸出 PWR_G00D變為低電半I將電源狀悲訊號 ΑΤΧ電源4於各個電源生戶〜會採用各種 主機板於搭配某種電源時不 ：公不同，可能會導致 相容，而其主要原因之機板與電源不 對，不能滿足要求。’、才之延時時間不對或電壓不 【發明内容】 鑒於以上内容，有必要提供_ 決電腦主機板與電源之間不相容之困擾^配電路，用於解 一種電源適配電路，用於輪带 一第-開關元件、-第H％源狀態訊號，其包括 二極體、-第一電阻、—第二電阻第：開關-件、- 其中每-開關元件均包括-第—端— 二第電Λ及一電容， 端’一系統電源依序透過該第—電阻 ^鈿及—弟三 -開關元件之第-端與該第一電阻及電：後接地，該第 連，還與該二極體之陽極相、車，一及電谷之間之節點相 接一備用電源，還盘嗜第_ η弟―端透過該第二電阻連 端接地，該第二開關元件之第二端接 連，弟，二 三電阻連接於該系統電源，並作 3二端透過該第 端’該第三開關元件之第一端用於=源=電路之輸出 端接地，第三端與該二極體之陰極：：：：機訊號’第二. 低電平時，該第r f g M : D連，$該開機訊號為 件截止，該第-開關元件於兮-谷達到其間值電愿時導通，該第二開關元件截止件= 200921348 ，端輪出高電平使得該電源狀態訊號 .，高電平時，該第三開關元件導通，該電容心= 弟—開關元件截止，該第二開關元件導通 ^該 低電平使得該電㈣態訊號為低電平。4 一輪出 相較習知技術，前述電源適配電路藉由三個開 功能，根據該電源狀態訊號產生㈣機訊^$ 常數調整時序之延Ϊ時由該充電電路之時間 不相容之困擾。 間，可有效解決電腦主機板與電源 【實施方式】 第—Hi1 件”路之較佳實施方式包括— 第-電晶體Q1、一:文應電晶體Q3、-第二開關元件如- 電容c、曰 二開關70件如-第二電晶體Q2、— 电奋L、一第—電阻R1、一 —第四電阻R4月 ^ F R2、一弟三電阻R3、200921348, IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a power supply adaptation circuit. [Prior Art] The power supply not only supplies voltage to the computer hardware, but also transmits signals to and from the motherboard, and the signals are related in time sequence, that is, timing. The important conditions for the timing system to work well with the motherboard are the most common causes of the computer not being able to boot properly, and the power supply is incompatible with the motherboard. The most important factor in the timing is the output voltage of the system power supply (usually +5V). The relationship between the power state signal PWR_GOOD and the power-on signal PS_ON, the power state signal PWR_GOOD is high indicates that the power is ready, and when it is low, the power is not ready, and the power signal PS_ON is low. "Start" means that it is not turned on when it is at the office level. The working process of starting and shutting down the computer is as follows: After the ATX (Advanced Technology Extended) power supply is powered::, a 5V standby power supply voltage (5V SB voltage) is output to the motherboard, and a few lines of the main board and the first board start working. And waiting for the boot operation, this is called standby state; when the host switch is pressed, the motherboard will turn the power-on signal PS_ON to a low level, the ATX power supply is connected to a low level and starts to start and generate all output voltages at all output voltages. Within 100-500ms after normal establishment, the power supply will turn the power status signal PWR_GOOD high to the motherboard, indicating that the power supply is ready, then the motherboard starts up and running; when the system is shut down normally, the motherboard completes all shutdowns. After operation, the startup signal PS_0N is restored to a high level, the ATX power supply will turn off all output voltages, only 7 200921348, retain the 5V standby power supply voltage output PWR_G00D becomes low power half I will be power supply sad signal ΑΤΧ power supply 4 to each power supply Residents ~ will use a variety of motherboards when paired with a certain power supply is not: public, may lead to compatibility, The main reason of the power supply board is not right, not meet the requirements. ', the delay time is not right or the voltage is not [invention content] In view of the above, it is necessary to provide a complication between the computer motherboard and the power supply is incompatible with the circuit, used to solve a power adapter circuit, for The wheel has a first-switching element, an -H% source state signal, comprising a diode, a first resistor, a second resistor: a switch-piece, wherein each of the switching elements includes a - terminal - a second electric cymbal and a capacitor, the end of the 'system power supply sequentially through the first-resistance and the third-switching element of the first end and the first resistor and the electric: the rear ground, the first, and The anode phase of the diode, the node of the vehicle, and the node of the electric valley are connected to a standby power source, and the second phase of the second resistor is grounded through the second resistor, and the second switch component is second. Termination, brother, two or three resistors are connected to the system power supply, and the two ends are passed through the first end. The first end of the third switching element is used for = source=circuit output terminal grounding, the third end and the second Cathode of the polar body:::: machine signal 'second. When low level, the rfg M: D even, $ The power-on signal is turned off, and the first-switching element is turned on when the 兮-valley reaches its value. The second switching element cut-off element is 200921348, and the terminal wheel is at a high level to make the power state signal. The third switching element is turned on, the capacitor core = the switching element is turned off, and the second switching element is turned on to the low level so that the electrical (four) state signal is low. 4 A round of phase out of the conventional technology, the power supply adaptation circuit by three open functions, according to the power state signal generation (four) machine signal ^ $ constant adjustment timing delay caused by the time incompatibility of the charging circuit . Between the computer motherboard and the power supply [Embodiment] The preferred embodiment of the first-Hi1 device includes - the first transistor Q1, one: the transistor Q3, the second switching component such as - the capacitor c 70 switches, such as - second transistor Q2, - electric Fen L, a first - resistor R1, a - fourth resistor R4 month ^ F R2, a young three resistor R3,
Η Μ 二極體D，其中該第一、第H :關元件亦可根據需要選用其他元件，^及第三 體Q1、Q2均為NPN型電曰 " 及第一電晶Η Μ diode D, wherein the first and the H: off components can also be selected according to other components, and the third body Q1, Q2 are NPN type electric 曰 " and the first electric crystal
通道場效應電晶體。 柄效應電晶體《為N d::叉透過該第-電…電容 ，及電容c之間之極，於該第-電阻 相連，還透過該第二電阻们與二〜：曰曰體以之基極 連，源極接地，該第—電晶 備用電源5V—SB相 該第三電阻R3與該 怎之射極接地，集極透過 晶體Q!之隼枉作Λ 電源5V—SYS相連，該第一電 集極作為”源適配電路之輪出端，用於輸出 200921348 一電源狀態訊號PWR_GOOD，該場效應電晶體Q3之閘極 還與該二極體D之陽極相連，該二極體D之陰極與該第二 電晶體Q2之集極相連，該第二電晶體Q2之射極接地，基 極透過該第四電阻R4接收一開機訊號PS_ON。 下面對本發明電源適配電路之工作原理進行說明。前述 第一電晶體Q1、第二電晶體Q2及場效應電晶體Q3產生 控制開關之作用，該二極體D產生隔離及加速放電之作 用，該第一電阻R1及電容C組成一充電電路，該充電電 路之時間常數用於決定時序之延時時間，即該開機訊號 PS_ON為低電平時至該電源狀態訊號PWR_GOOD變為高 電平時之時間，該第一電阻R1為定時電阻，該第二電阻 R2及第三電阻R3均為上拉電阻，該第四電阻R4為限流 電阻，該電容C為定時電容，如果對該電源適配電路要求 不高，則可刪除該第四電阻R4，以節省該電源適配電路之 成本。 當按下主機開關時，主機板將該開機訊號PS_ON變為 ί· 低電平訊號，使得該第二電晶體Q2截止，該5 V系統電源 5V_SYS透過該第一電阻R1給電容C充電，當該電容C 之電壓達到該場效應電晶體Q 3之閾值電壓時5該場效應 電晶體Q3導通，其汲極變為低電平，該第一電晶體Q1之 基極亦是以變為低電平，使得該第一電晶體Q1截止，該 5 V系統電源5 V_SYS透過該第三電阻R3從該第一電晶體 Q1之集極輸出5V電壓，使得該電源狀態訊號PWR_GOOD 為高電平訊號，從而主機板得以啟動。其中，該開機訊號 PS_ON為低電平時至該電源狀態訊號1^\¥11_0000變為高 10 200921348 .電平時之延時時間即為該電容c被充電至該場效應電晶體 Q3之閾值電壓之時間，於設計中可靈活調整該第一電阻 * R1及電容C之參數，使得延時時間能夠滿足100-500ms 之要求。 當主機處於待機狀態時，主機板使得該開機訊號 PS_ON變為高電平，另，該5 V系統電源5 V_SYS停止輸 出，只有該5 V備用電源5 V_SB存在，此時該第一電晶體 Q1導通，該電容C之電壓將會透過該二極體D迅速釋放， 該場效應電晶體Q3之閘極亦是以迅速變為低電平而導致 該場效應電晶體Q3截止，其汲極由於透過該第二電阻R2 與該5 V備用電源5 V_SB相連而變為高電平，使得該第一 電晶體Q1導通，從而導致其集極迅速變為低電平，即該 電源狀態訊號PWR_GOOD亦變為低電平，談主機板即停 止工作。 請一併參閱圖2及圖3,其中圖2為對圖1進行仿真 驗證中開機訊號PS_ON之波形圖，圖3為對圖1進行仿真 驗證中電源狀態訊號PWR_GOOD之波形圖。從前述波形 圖可看出，當開機訊號PS_ON為低電平時，該電源狀態訊 號PWR—GOOD變為高電平之延時為269.82ms，滿足延時 100-500ms，電壓等於5V亦滿足電平要求，可實現開機之 要求；又，當該開機訊號PS_ON為高電平時，該電源狀態 訊號PWR_GO〇D為低電平，可實現當ATX電源處於待機 狀態時，該主機板即停止工作。 前述電源適配電路，藉由該第一電晶體Q1、第二電晶 11 200921348 , 體Q2及場效應電晶體Q3之開關功能，根據該開機訊號 PS_ON產生該電源狀態訊號PWR_GOOD，又，該第一電 阻R1與電容C組成充電電路，藉由該充電電路之時間常 數來調整該開機訊號PS_ON與電源狀態訊號PWR_GOOD 之間之延時時間，可有效解決電腦主機板與電源不相容之 困擾，而且該電源適配電路設計簡單，成本較低。 綜上所述，本發明符合發明專利要件，爰依法提出專 利申請。惟，以上所述者僅為本發明之較佳實施例，舉凡 熟悉本案技藝之人士，在爰依本發明精神所作之等效修飾 或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 圖1係本發明電源適配電路之較佳實施方式之電路 圖。 圖2係對圖1進行仿真驗證中開機訊號PS_ON之波形 圖。 圖3係對圖1進行仿真驗證中電源狀態訊號Channel field effect transistor. The handle effect transistor "for N d:: the fork through the first - electric ... capacitor, and the pole between the capacitor c, connected to the first - resistor, also through the second resistor and the second ~: the body The base is connected, the source is grounded, the first-electro-optic standby power supply 5V-SB phase, the third resistor R3 is grounded to the emitter, and the collector is connected to the power supply 5V-SYS through the crystal Q! The first collector is used as the "output terminal of the source adapter circuit" for outputting a power supply state signal PWR_GOOD of 200921348, and the gate of the field effect transistor Q3 is also connected to the anode of the diode D, the diode The cathode of D is connected to the collector of the second transistor Q2, the emitter of the second transistor Q2 is grounded, and the base receives a power-on signal PS_ON through the fourth resistor R4. The working principle of the power adapter circuit of the present invention is as follows. The first transistor Q1, the second transistor Q2, and the field effect transistor Q3 generate a control switch, and the diode D generates an isolation and an acceleration discharge. The first resistor R1 and the capacitor C form a a charging circuit, the time constant of the charging circuit is used to determine the timing The delay time, that is, the time when the power-on signal PS_ON is low to when the power state signal PWR_GOOD is high, the first resistor R1 is a timing resistor, and the second resistor R2 and the third resistor R3 are pull-up resistors. The fourth resistor R4 is a current limiting resistor, and the capacitor C is a timing capacitor. If the power adapter circuit is not required to be high, the fourth resistor R4 can be deleted to save the cost of the power adapter circuit. When the host switch is turned on, the motherboard changes the boot signal PS_ON to a ί·low level signal, so that the second transistor Q2 is turned off, and the 5 V system power supply 5V_SYS charges the capacitor C through the first resistor R1, when the capacitor When the voltage of C reaches the threshold voltage of the field effect transistor Q 3 , the field effect transistor Q3 is turned on, and the drain of the field is turned to a low level, and the base of the first transistor Q1 is also turned to a low level. The first transistor Q1 is turned off, and the 5 V system power supply 5 V_SYS outputs a voltage of 5 V from the collector of the first transistor Q1 through the third resistor R3, so that the power state signal PWR_GOOD is a high level signal, thereby The motherboard is booted. When the power-on signal PS_ON is low, the power state signal 1^\¥11_0000 becomes high 10 200921348. The delay time at the level is the time when the capacitor c is charged to the threshold voltage of the field effect transistor Q3. In the design, the parameters of the first resistor * R1 and the capacitor C can be flexibly adjusted, so that the delay time can meet the requirement of 100-500 ms. When the host is in the standby state, the motherboard causes the boot signal PS_ON to become a high level. In addition, the 5 V system power supply 5 V_SYS stops outputting, and only the 5 V standby power supply 5 V_SB exists. At this time, the first transistor Q1 is turned on, and the voltage of the capacitor C is quickly released through the diode D. The gate of the effect transistor Q3 is also turned to a low level to cause the field effect transistor Q3 to be turned off, and the drain thereof becomes high due to the connection of the 5 V standby power supply 5 V_SB through the second resistor R2. The first transistor Q1 is turned on, causing its collector to rapidly change to a low level, that is, the power state signal PWR_GOOD also becomes a low level, and the motherboard is stopped. Please refer to FIG. 2 and FIG. 3 together. FIG. 2 is a waveform diagram of the power-on signal PS_ON in the simulation verification of FIG. 1, and FIG. 3 is a waveform diagram of the power state signal PWR_GOOD in the simulation verification of FIG. It can be seen from the foregoing waveform diagram that when the power-on signal PS_ON is low, the delay of the power state signal PWR_GOOD becoming high level is 269.82 ms, satisfying the delay of 100-500 ms, and the voltage equal to 5 V also satisfies the level requirement. The power-on signal PWR_GO〇D is low when the power-on signal PS_ON is high, and the motherboard can stop working when the ATX power is in the standby state. The power supply matching circuit generates the power state signal PWR_GOOD according to the power-on signal PS_ON by the switching function of the first transistor Q1, the second transistor 11200921348, the body Q2, and the field effect transistor Q3. A resistor R1 and a capacitor C form a charging circuit, and the delay time between the power-on signal PS_ON and the power state signal PWR_GOOD is adjusted by the time constant of the charging circuit, thereby effectively solving the problem that the computer motherboard is incompatible with the power supply, and The power adapter circuit is simple in design and low in cost. In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a preferred embodiment of a power adapter circuit of the present invention. Fig. 2 is a waveform diagram of the boot signal PS_ON in the simulation verification of Fig. 1. Figure 3 is a power state signal in the simulation verification of Figure 1.
V PWR_GOOD之波形圖。 【主要元件符號說明】 第一電晶體 Q1 第四電阻 R4 第二電晶體 Q2 電容 C 場效應電晶體Q 3 二極體 D 第一電阻 R1 糸統電源 5V_SYS 第二電阻 R2 備用電源 5V_SB 第三電阻 R3 12Waveform of V PWR_GOOD. [Main component symbol description] First transistor Q1 Fourth resistor R4 Second transistor Q2 Capacitor C Field effect transistor Q 3 Diode D First resistor R1 System power supply 5V_SYS Second resistor R2 Backup power supply 5V_SB Third resistor R3 12