TW200921324A - Computer system - Google Patents

Abstract

A computer system including M microprocessors, a frequency control chip and a clock generator is provided. M microprocessors generate M frequency selection information according to working frequency thereof. The frequency control chip performs a series of operations to output one of M frequency selection information. The clock generator regulates a frequency of a clock signal outputted according to a output information of the frequency control chip. Since the frequency selection information outputted by the frequency control chip is produced by the microprocessor with the lowest working frequency, the clock signal is suitable for M microprocessors.

Description

200921324 υ/^480. lw zM58nvf.doc/p IX. Description of the invention: [Technical field of the invention] The present invention relates to a computer system, and in particular to the frequency of the automatic adjustment of the clock signal computer system. [Prior Art]

In the age of technology development, it is inevitable that computers have become an indispensable information processing tool in people's lives. The microprocessor is an indispensable component of the computer. The function of the friend computer is becoming more and more powerful. The computer system that originally only has a single microprocessor is developed into a dual microprocessor. The traditional computer system of the processor. Referring to Fig. 1, the first private system 1 includes a microprocessor, a selection circuit 130, and a clock generation _14. Among them, the microprocessor will generate a drunk selection #SELn according to its work rate. Similarly, the microprocessor 120I solves the problem of generating a fresh selection SEL1. After that, the frequency is poor. The SELU and SEL1; 2 are transmitted to the selection circuit 13A. In the tenth, the selection circuit 130 outputs the frequency selection information SELj arc 12 according to the level of the switching signal SWn. Among them, when the house==Γ is installed in the traditional computer system (10), the signal ‘to the fresh position, so that the output information of the choice slave (4) is the same as the information SELU. In other words, the time/generation state 140 at this time will generate a clock signal CLK1 that matches the operating frequency of the microprocessor 110 and is transmitted to the microprocessors 11A and 12A. , ', other aspects' when the traditional computer system, the system 10 only installs the microprocessor 12〇200921324 u/U4«o.xw ^458twf.doc/p 'the switching signal SW11 level will be switched to the high level, The output information s 〇 UTn of the selection circuit 130 and the frequency selection information SELi2 are caused. In other words, the clock generator 140 at this time will generate the clock signal CLK1 that matches the operating frequency of the microprocessor 120 and transmit it to the microprocessor 120. It is worth noting that the microprocessors 110 and 12〇 can only operate under the clock signal CLK1 equal to or at the operating frequency of the microprocessor. Therefore, when both the microprocessors 110 and 12 are installed in the conventional computer system 1 and the operating frequency of the microprocessor 110 is greater than the operating frequency of the microprocessor 120, the clock generation state is generated. The clock signal CLK1 will not be able to make the micro-processing cry 12 〇 normal action. In other words, for a computer system with multiple microprocessors, how to = phase: the clock signal to cause multiple microprocessors 5 in the computer system [send, has been the brains of various Weishang The problem to be solved. Cassia provides a computer system that uses the frequency control chip to clock 〇 #合== to cause the clock signal generated by the clock generator to be a plurality of microprocessors in the system. #制θ ^月 proposed - a computer system, including μ microprocessor, frequency. Pulse 11. Among them, one microprocessor will generate the first micro-M touch selection information, the j-th frequency will be selected, and the frequency control chip will be compared, in the if order and the first to the first fixed information mutual 200921324 U7U486.TW is 458twf.doc/p where 0 is an integer and 1 is smeared, 1 is an integer and (5) is said. _欠』=卜 Although the frequency of the selection of j, can not be compared with h to the first = which is - when the comparison is successful, the frequency control crystal

Hey. On the other hand, when the first to the ninth s7F5fL box frequency selection _Beidu and the first to nth are successful, the frequency control chip will turn t to the frequency corresponding to (4). Then, the value of the reference value = 2 pulse generator will compare the output information of the frequency selector with each other according to the preset information, and the preset value of the -clock signal: Among them, the first preset Beixun corresponds to the brother: a frequency preset value, the (i_1} frequency frequency preset value. By this, the frequency a final ^,; ^ two afternoons the day of the film output The frequency selection afl will come from the microprocessor with the lowest operating frequency, so a micro-processing cry will be able to operate normally according to the clock signal generated by the clock generator. ^ In the embodiment of the invention, the above frequency Control chip can be used for programmable gate array > FPGA) system, complex programmable logic device (c〇mplex pr〇gmmmabie _ device, CPLD) system, substrate management controller ((8) coffee management contr〇ner, BMQ or other circuits The invention realizes the frequency control chip to perform a series-operation operation on the frequency selection information sent by each microprocessor, so that the frequency selection information sent by the microprocessor with the lowest operating frequency can be intercepted. Therefore, the clock generator of the frequency control chip will generate a clock signal suitable for each microprocessor. 200921324 u/u^so.iw z3458twf.doc/p To make the above features and advantages of the present invention The present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 . . . . . . . . . . . . . . . . . . . . . . . . In addition, the computer system of the present invention only needs to provide a clock signal, whether it is a distribution, or a microprocessor. In other words, it is configured in the battery system of the present invention. The processing will be a total of (four) - a clock signal. As for the computer system of the present invention, how to make the microprocessor with the unique rate of the same - a clock 5 holes, will be further explained below. FIG. 2 is a circuit diagram of a computer system according to an embodiment of the present invention. The computer system includes a microprocessor 21〇2222, a crystal 230, and a clock generator 240. The frequency control is coupled to the microprocessor 21. 〇~220. The clock generator 24 is lightly connected to the frequency chip 23 and the microprocessors 210 to 22 〇. When the light is continued, referring to FIG. 2, the microprocessor 21G generates the selection information SELi according to its operating frequency. Similarly 'microprocessor 22() = raw Rate selection information fox 2. Next, the frequency control; the work 〇 糖 ^ ^ ^ 所 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 操作 SEL SEL SEL - Fruit to turn out the solution to select information fox] or frequency to select f-muscle 2. $Ray's explanation of the frequency control chip 230 before the operation of the clock = the frequency of the clock signal issued by the brain system 2GG Select one of the four frequency pre-reading VF1~VF4. In addition, as shown in Table i, * 200921324 υ/υ^δ〇.ι wz^458twf.doc/p frequency preset values VF!~VF4 One-to-one correspondence with the four preset information SDE wide SDE4, and four frequency preset values VFi~VF4 are arranged in order from small to large. For example, in the present embodiment, the frequency preset value VFi = 133 MIiz, the frequency preset value VF2 = 166 MHz, the frequency preset value VF3 = 266 MHz, and the frequency preset value VF4 = 333 MHz. ,

Please refer to FIG. 2 and FIG. 3 for the detailed operation and process of the frequency control chip 2 3 〇. In step S310, the frequency control chip 23 receives the frequency selection message SE^. In steps S311 to S314, the frequency control chip 23 aligns the frequency selection "SEL" with the preset information SDEi to SDE4 in order. When the frequency selection information SEL! is successfully compared with one of the preset information SDEi to SDE4, the frequency control wafer 230 will generate the frequency reference value FRi through one of the steps S315: S3i8. It is worth noting that the value of the fresh reference value FRi varies with the result of the different =. For example, when the frequency selection information (four) phase

When SDEl is transmitted, the value of the frequency reference value 将 will be set to 1 (step S315). When the frequency selection information is equal to the preset information SDE2, the value of the frequency reference value FRi will be set to % (step S316). By analogy, step S317 and step phantom 18.冉 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 竿 比 比 比 比 比 比 比 微处理器Second)). Therefore, the frequency control wafer 230 at this time will generate an oath signal (step S32). On the other hand, in step S330, the frequency control chip 23 receives the frequency 200921324 u458twf.doc/p selection information SEL2. Similarly, in steps S331 to S334, the frequency control chip 230 sequentially compares the frequency selection information SEL2 with the preset information SDE wide SDE4. Further, when the frequency selection information SEL2 is successfully aligned with one of the preset information SDE wide SDE4, the frequency control chip 23 〇 passes through one of the steps S335 to S338 to generate the frequency reference value FR2. In contrast, the frequency control chip 230 will generate an alert signal (step S32).

C. Further, when the frequency selection information SELi~SEL2 is successfully compared with the preset poor SDEr SDE4, it means that the microprocessors 210 and 220 are suitable for the computer system 2, so the frequency control at this time The wafer 230 will compare the frequency reference values 1^1 and 1^2 to output the frequency selection information corresponding to the minimum frequency reference value. It is worth noting that the smaller the value of the frequency reference value, the lower the operating frequency of the microprocessor. In other words, the frequency selection information output by the frequency control chip 230 is issued by the microprocessor having the lowest operating frequency. For example, in step S340, the frequency control chip 23 discriminates whether the frequency reference value FRi is smaller than the frequency reference value %. When the frequency reference value FR"] is at the frequency reference value FR2, the frequency control chip now selects the frequency selection information SEL<step illusion corresponding to the wheel frequency reference value FRj/f. = to ground 'When the frequency reference value FRi is greater than the frequency reference value, the control chip 23() _ _ _ _ _ _ _ SEL2 (step S342). 'Dry, choose poverty. Please continue to refer to Figure 2. The clock generator 240 receives the frequency selection ‘JΪ贝 S(10)’ and generates t based on the information it receives. ~LK. For example, if the frequency control chip is turned out 200921324 u / ν^ου. 1 w ^.J458twf.doc/p Information s〇UT is the frequency selection information SELi. At this time, the frequency selection information SEL I is generated and the TM240 is hung. Hehe rr* 斗 suppress...1 and Beixun SDEpSDE4 are compared with each other. Box: 4 raw 5 24G comparison frequency selection information When there is no poor SDEl, it will set the light city CLm rate to the state (13 fine 2).环^王至频 Γ得—提岐, because the frequency controlled by the frequency control chip 23G k is selected as the lowest processing micro-processing by the servant frequency, so the clock

The generator 24G is under the control of the frequency control chip. The clock signal CLK generated by it will be airworthy to the various microprocessors in the computer system. In addition, in this embodiment, a field pr〇grammable gate array (FpGA) system and a complex pr〇gramma We丨叩匕 device (CPLD) can be utilized by those skilled in the art. The system, substrate management controller (BMC) or other circuit components implement the frequency control wafer 230. For example, if the frequency control chip 230 is composed of basic logic gates, and it is assumed here that the frequency selection information SEL1 to SEl2 and the first to fourth preset information SDE^SDE4 each include three bits, And the first preset information 81^1 is set to 001 'the second preset information sde2 is set to 011, the third preset information SDE3 is set to 〇〇〇, and the fourth preset information SDE4 is set to 100 In this case, the state of the frequency selection information SELp SEL2 that the frequency control chip 230 can receive, and the state of its corresponding output information SOUT, will be as shown in the truth table of Table 2. Therefore, the internal structure of the frequency control chip 230 can be designed according to the truth table of Table 2, and the circuit diagram shown in FIG. 4 is designed. 4. The frequency control chip 230 includes AND gate ANDf AND6, mutual exclusion or gate x〇r wide x〇r2, anti-mutation or gate XNO&, or gate OR wide OR3, and reverse gate NOTI. Among them, bl[0,2] It is used to indicate the first to third bits in the frequency selection information SELi, b2[0, 2] is used to indicate the first to third bits in the frequency selection information SEL2, and b3[0, 2] is used to indicate The frequency control chip 230 outputs the first to third bits of the information SOUT. Here, the gate AND is used to receive the bit bl[2] and the bit b2[2]. The AND gate AND2 is used to receive the bit bl. [0] and bit b2[0]. Gate AND3 is used to receive bit bl[l] and bit b2[l]. Mutually exclusive or gate x〇Rl is used to receive bit 7L bl[〇] and bit Bl[1]. Mutex or gate x〇r2 is used to receive bit b2[0] and bit b2(1), or gate OR2 is used to receive bit bl[0] and bit b2[l]. To receive the bit bl[2] and the bit b2[〇]. The reverse gate NOT! is used to receive the bit b2[i].

The gate AND4 is connected to the output of the gate anD2 and the output of the gate ANE>3. The anti-mutation or gate XNO& is coupled to the wheel-out of the mutex or gate and the wheel-out of the mutex or gate x〇R2. Or the gate coupling = the output of HAND4 and the output of the anti-mutation or gate x 1 .屮二-6 is connected to and closes the output of the >5 and the leg of the reverse gate is lost to 屮i^. = 0R3 is connected to the output of the gate 0R2 and the last name of the gate >6, and the frequency control chip 230 will pass through the output of the gate AND1 to generate the minimum frequency & Bit-, frequency selection information, that is, the bit 兀b3[〇]~b[2] in the output information SOUT. 12 200921324 υ/wco.iw zj458twf.doc/p The value of knowing a long time: Although the computer system has drawn a possible pattern in the embodiment of Fig. 2, those skilled in the art should know that the computer system The number of microprocessors configured can be arbitrarily changed according to the needs of the designer. In addition, the frequency of the clock signal sent by the computer system can also change the number of frequency preset values and the corresponding preset information according to the needs of the designer. Therefore, the computer system of the embodiment of Fig. 2 will be further modified into a computer system as shown in Fig. 5 in accordance with the spirit of the present invention. Referring to FIG. 5, the computer system 5 includes M micro-processing crying 5HM~5 dragons, frequency control chip 53〇, and clock generator. The clock signal sent by the computer pure 500 can be selected - toggled among the n frequency preset values and the N frequency preset values correspond one-to-one with the N preset information. Its towel 'the first preset Zisaki should be the i-th frequency preset = and the fourth (four) side rate is the same as the third 率 rate ,, m and N are greater than 〇 integer 'i is an integer and 〗 Actuation, the microprocessors 510-1~510-M each generate a de-selection information according to the operating frequency, so that the disc_microprocessors 5HM~510_M are one-to-one. Another == control chip 53 will be μ \ ',; ί when the preset information, the frequency "select poverty is equal to the first difficult frequency reference value: where ^ integer frequency and == 530 will produce another side" When the j-th frequency selection cannot be compared with the N preset information 13 200921324 ό 458 tw f· do c/p 2 - the frequency control chip 53G will generate - 唬 to know that there is a microprocessor-WOW More than Putian, News = 50. Conversely 'When _ frequency selection capital =

= Among them - the comparison is successful, the frequency control chip will compare the value: the value of the value 'selects the frequency corresponding to the output minimum frequency reference value, the 'clock generator t will frequency selector 53G miscellaneous and N The preset information is compared with each other to adjust the frequency of the transmission to! ^ One of the frequency presets. The 5th to 51th cans of the device will be based on the clock signal. The frequency selection information output by the second==530 is the microprocessor from the lower operating frequency, so the clock generator ^ The signal will be described in the above-mentioned summary of the microprocessor and the training of the microprocessor. The present invention utilizes the frequency selection information sent by the frequency controller to perform a series of arithmetic processing.

Cj out. After that, the clock generates a clock signal suitable for each microprocessor. By this: Newming's computer system will be able to automatically provide each micro-processing = : = 2 to effectively enhance the market competition of the computer system; force: =: Although the invention has been disclosed in the preferred embodiment as above, the invention is defined, There is a general knowledge in the technical field; no, in the spirit and scope of the present invention, when some changes can be made and _ not 14 200921324 ^ 458twf.doc / p = the scope of the invention is attached to the application The definition of the scope of the [simplified description of the schema] Figure 1 shows the traditional computer system with dual microprocessors. Figure 2 is a circuit diagram of an electrical system in accordance with an embodiment of the present invention. Figure 3 is a flow chart for explaining the operation of the embodiment of Figure 2. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5 is a block diagram of a frequency control chip according to the present invention. FIG. 5 is a circuit diagram of a computer system according to another embodiment of the present invention. Set the value 盥 preset _ Beixun's comparison table. Table 2 is a table showing the accuracy of the frequency control wafer of the embodiment of Figure 4. 〃 [Main component symbol description] 100: Traditional computer system 110~120, 210~220, 510-1~510-Μ: Microprocessor 130: selection circuit 140, 240, 540: clock generator 200, 500: computer System 230, 530: frequency control chip AND wide AND6: and gate XOR wide XOR_2: mutual exclusion or gate 15 200921324 υ / υπου. ι νν z._; 458twf.d〇c/p XNORi: anti-mutation or gate OR OR3: or gate NOT!: reverse gates S310~S340, S311~S318, S331~S338, S341~S342 Step 16 in the operation flowchart of FIG.

Claims (1)

200921324 ---------- — 458tw£doc/p 卞, A, please patent scope: a computer system, including · a microprocessor, generate the first and the record (four) - the choice The poor news, when it is equal to the first preset information, will be the first; ^ : J: = i === the capital cannot be matched with the signal; otherwise, the frequency control chip generates a warning value than the m control chip. Size, the output minimum frequency loss '2M frequency reference message 'N is an integer greater than 0;;, the corresponding frequency selects 1 as N; and the number is integer and is full, i is an integer and - clock generation Transmitting the frequency selector 1 to the Nth preset information to each other (four) and the first to the N frequency preset values, wherein, === r two-time rate * two, and 1 "Setting frequency pre-amplifier value", the frequency gradient value is less than the i-th frequency preset rate batch, such as the computer system described in the first paragraph of the patent scope, wherein the frequency control wafer is one field. Programming the gate array system. 3. The computer system and system as described in the scope of the patent application, wherein the frequency control chip is a complex programmable logic 4. The computer system of claim 1, wherein the frequency control chip is a substrate management controller. 5. The computer system according to claim 1, wherein Γ o 200921324 \JI ν/^τον/. i rr 458twf.doc/p = frequency selection information and the 1st to 4th pre-5s and 5th, including the 3rd digit of the J. B2[x] is used to represent the X bit of the 2nd J. The frequency control chip includes: , the hand k is selected to receive the bit _ and the bit b2 [2]; a d'r receiving bit _ And the bit _ ” one; the receiving bit just and the bit just; the input = and the gate, the secret to the second and _ output and the fourth and Ϊ 'to receive the bit S Μ [σ1 and the bit Bl(1); is used to receive bit b2[o] and bit wise]; - di-reciprocal or sluice, coupled to the first - and the output of the second mutually exclusive or sluice; (d) output ^ mutual exclusion; = terminal _ to the fourth and the gate of the wheel and the first - anti-second or sluice, for receiving the bit wise] and the bit - fifth and sluice to receive the bit called 2] and bit Element b is reversed to receive bit b2 [l]; the output terminal = the gate to the fifth and the gate of the fifth gate and the reverse gate of the transmission = or gate, reduced to the second or gate of the wheel and the sixth and wafer The most frequent frequency selection information is generated by the first-and-gate, the first- or gate, and the wheel-end of the 4 or gate. \ is an integer and 〇'xg2. The corresponding value of the test 18