200917461 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種靜電放t防護電路；特別是一種利用電位耦 合與電位阻隔之靜電放電防護電路。 【先前技術】 隨著積體電路製程不斷進步，單一晶片中可整合更多電路，例 如數位控制電路、微處理器、微控制器、射頻電路、電源產生電 路、類比訊號產生電路…等等各種數位電路與類比電路。為因應 數位電路與類比電料同的電源需求，在單-日日日片中將存在著^ 種不同的電源供應電壓與接地路徑。 以金氧半場效電晶體構成之晶片為例，其内部存在著各種呈有 不同接地電位（或負電壓）的p型井區（则）與各種具有；同 正電位的N型井區，例如使用UV與5〜,做為雙電源供應，以及 數位接地端與類比接地端。當將㈣靜電放電施加於此晶片時， 會改變各絲的電位並且可能使原本具有相同電位的井區在瞬間 產生很大的電位差’進而造成原本電性連結而具有相同電位但彼 此分開的井區間相對電位之改變。 承上所述，當系統靜電放電發生時，井區間相對電位之改變將 可能擊穿金氧半場效電晶體之閘極 . 啤蚀興源/汲極間之閘極氧化層 (gate oxide) ’而造成電路永久性損壞。 因此，如何提供具有不同電路之單_ a 早曰曰片靜電放電防護，即成 為此領域之產業亟需努力的目標。 200917461 【發明内容】 本發明之一目的在於提供一種靜電放電 半導體電路之-電源供應端以及 卩刀別於- - 久輸入端之間，與一拉认*山，、，《 該輸入端之間提供電壓耗合功能 刀犯使系統靜電放電發生時，雷湃 供應端以及輸入端之間，與接地 ^電源 在一 flflm ^ 及輸入端之間之跨壓能限制 在一耗圍内，精此達成靜電放電防護效果。 本發明之另一目的在於提供一種 恨靜冤放電防護電路，以在二丰 Γ ‘體電路之輸入端與輸出端之間提 0欲… 電卩羯功能，H统靜電 放電么生時，阻隔一半導體電路 電位變化，以防止電位變化往 體電路傳遞，進而保護此另—半導體電路不受系統靜電 為達成上述目的，本發明揭露一種靜電放電防護電路，包含_ 第-電位粞合元件、-第二電位轉合元件及—電位阻隔元件。第 -放電麵合元件連結-半導體電路之—電源供應端及—輸入端； 第二放_合元件連結半導體電路之—接地端及輸人端；電位阻 隔元件串聯連結此半導體電路之輸人端與另—半導體電路之輸出 端。 為讓本發明之上述目的、技術特徵、和優點能更明顯易懂，下 文係以較佳實施例配合所附圓式進行詳細說明。 【實施方式】 以下將透過實施例來解釋本發明内容，其係關於一靜電放電防 護電路’用以將靜電放電現象產生之急遽電位改變齡為較穩定 之電位改變，以避免閘控元件之閘極氧化層被擊穿。然而，本發 200917461 明的實施例並非用以限制本發明需在如實施例所述之任何特定的 、應用或特殊方式方能實施。因此，關於實施例之說明僅為 闡釋本發明之目的’而非用以限制本發明。需說明者，以下實施 例及圖式中與本發明非直接相關之元件已省略而未繪示；且為 求容易瞭解起見’各元件間之尺寸關係乃以稍誇大之比例繪示出。 第1圖係為-利用本發明之半導體電路示意圖。半導體電路】 包含-輸入端u、一接地端12、一電源供應端13以及一輸出端 14。靜電放電防護電路15包含—第—電位輕合元件151以及—第 二電位輕合元件152。在本實施例t，半導體電路！包含—第一問 控元件16及一第二閘控元件17’構成-反相器，同時第一電位耦 合元件⑸係-電容性元件，第二電⑽合元件152亦為一電容 性元件。其中第—閘控元件16係—？型金氧半場效電晶體，包含 1和161源極162及—汲極163，第二閉控元件係一 N 型金氧半場效電晶體，包含—閘極m…源極Μ及—⑽173。 第厂閘控το件16之汲極163與第二間控元件17之沒極173呈電 !·生連結，且電性連結至輸出端14 ;第一閘控元件^之源極162 電性連結至«供應端13;第二閘控元件17之源極Μ電性連結 至接地端12 ’同時輸人端n分別連結至第—閘控元件μ之閘極 161及第二閘控元件17之閘極171 ;藉由上述連結，適可使第一 間控元件16與第二閘控元件17構成-反相器。 =意者，在本實施例中，第—閘控元件㈣第二開控元件Ρ 人不同極性，在其他實施例中，第一閘控元件⑺亦可為一 Ν 型金氧半場效電晶體， _200917461 IX. Description of the Invention: [Technical Field] The present invention relates to an electrostatic discharge protection circuit; in particular, an electrostatic discharge protection circuit utilizing potential coupling and potential blocking. [Prior Art] As the integrated circuit process continues to advance, more circuits can be integrated into a single chip, such as digital control circuits, microprocessors, microcontrollers, RF circuits, power generation circuits, analog signal generation circuits, etc. Digital circuits and analog circuits. In order to meet the same power requirements of digital circuits and analog materials, there will be different power supply voltages and ground paths in single-day and day-to-day films. Taking a wafer composed of a gold-oxygen half-field effect transistor as an example, there are various p-type well regions (then) having different ground potentials (or negative voltages) and various N-type well regions having the same positive potential, for example Use UV and 5~ as a dual power supply, as well as a digital ground and analog ground. When (4) electrostatic discharge is applied to the wafer, the potential of each filament is changed and a well region having the same potential may be generated to generate a large potential difference instantaneously, thereby causing a well that is originally electrically connected and has the same potential but separated from each other. The change in the relative potential of the interval. As mentioned above, when the system electrostatic discharge occurs, the relative potential change in the well interval may break through the gate of the gold-oxygen half-field effect transistor. The gate oxide of the galvanic source/bungee And cause permanent damage to the circuit. Therefore, how to provide a single-disc electrostatic discharge protection with different circuits is an urgent task for the industry in this field. An object of the present invention is to provide an electrostatic discharge semiconductor circuit - a power supply end and a file between the - long input end, and a pull between the mountain, and the "input" Providing the voltage consumption function knife to make the system electrostatic discharge occur, between the thunder supply end and the input end, and the grounding power supply between the flflm ^ and the input end of the cross-pressure energy is limited to a consumption, fine Achieve electrostatic discharge protection. Another object of the present invention is to provide a hate static discharge protection circuit for extracting 0 between the input end and the output end of the Erfeng Γ 'body circuit... The electric cymbal function, the H system electrostatic discharge is a real time, the barrier A potential change of a semiconductor circuit to prevent a potential change from being transmitted to a body circuit, thereby protecting the semiconductor circuit from static electricity of the system. The present invention discloses an electrostatic discharge protection circuit including a first-potential clamping component, The second potential switching element and the potential blocking element. The first discharge-distributing component is connected to the semiconductor circuit and the power supply terminal and the input terminal; the second discharge component is connected to the grounding terminal and the input terminal of the semiconductor circuit; and the potential blocking component is connected in series to the input end of the semiconductor circuit. And the output of the other-semiconductor circuit. The above objects, technical features, and advantages of the present invention will become more apparent from the following detailed description. [Embodiment] Hereinafter, the present invention will be explained by way of an embodiment, which relates to an electrostatic discharge protection circuit for changing the potential of the electrostatic discharge phenomenon to a relatively stable potential to avoid the gate of the gate control element. The polar oxide layer is broken down. However, the embodiment of the present invention is not intended to limit the invention to any particular application, application or special mode as described in the embodiments. Therefore, the description of the embodiments is merely illustrative of the invention and is not intended to limit the invention. It is to be noted that the elements of the following embodiments and drawings that are not directly related to the present invention have been omitted and are not shown; and for ease of understanding, the dimensional relationships between the elements are shown in a somewhat exaggerated proportion. Figure 1 is a schematic diagram of a semiconductor circuit utilizing the present invention. The semiconductor circuit includes an input terminal u, a ground terminal 12, a power supply terminal 13 and an output terminal 14. The electrostatic discharge protection circuit 15 includes a -first potential light combining element 151 and a second potential light combining element 152. In this embodiment t, the semiconductor circuit! Including - the first sensing element 16 and the second gate element 17' constitute an inverter, while the first potential coupling element (5) is a capacitive element and the second electrical (10) combining element 152 is also a capacitive element. The first - gate control component 16 -? The type of gold oxide half field effect transistor comprises 1 and 161 source 162 and 汲 pole 163, and the second closed control element is an N type MOS half field effect transistor comprising - gate m... source Μ and - (10) 173. The gate 163 of the first plant control device 16 and the electrode 173 of the second control device 17 are electrically connected to each other, and are electrically connected to the output terminal 14; the source 162 of the first gate control device is electrically Connected to the «supply terminal 13; the source of the second gate component 17 is electrically coupled to the ground terminal 12' while the input terminal n is connected to the gate 161 and the second gate component 17 of the first gate component μ, respectively. The gate 171; by the above connection, the first control element 16 and the second gate element 17 are configured to constitute an inverter. = In the present embodiment, the first gate control element (four) of the second control element has different polarities. In other embodiments, the first gate control element (7) may also be a type of gold oxide half field effect transistor. , _
Uf弟一閘控兀件17亦可為- Ρ型金氧半 200917461 場效電晶體。 承上所述，靜電放電防護電路15之第一電位躺合元件ΐ5ΐ即連 結電源供應端1 3及輪入被1 1 η 士 翰入^ U’同時第二電位搞合元件152即連结 接地端12及輸入端U。藉由電位輕合元件可輕合電壓，並將電位 耗合X件兩端之電壓差限制在—設定值，以在线靜電放電發生 寺刀另J對第閑控疋件^以及第二閘控元件Η提供防護。 為進-步說明靜電放電防護電路15於系統靜電放電發生時之作 月併乡考第1圖之半導體電路2及半導體電路3,以及第2 =”中第2圖係為第！圖所緣示電路示意圖之半導體結構示意 明去在此假設為利用Uv半導體製程所製造之半導體結構。需說 半導體電路2及半導體電路3與半導體電路〗呈電性連結， ^導體電路2與半導體電路丨位於相同之埋藏層（_ed咖） 同時半導體電路3單獨位於另—埋藏層内。埋藏層用以在半 ^結構巾提供不同絲狀絕緣仙，意即半導體電路3與半 t ί 導^路2及半導料路1藉由域層呈現絕緣狀態，僅能藉由 於埋藏&連結。由第2圖可知’半導體電路1與半導體電路2位 ;“層18内，同時半導體電路3位於埋藏層19内。 以^體電路2亦為-反相器，包含—P型金氧半場效電晶體26 21、— N型山金氧半場效電晶體27。半導體電路2包含一輸入端 也端22、—電源供應端23以及-輸出端24，其中接地 半導體、/導體^ 1之接地端U W性連結，電源供應端23與 -電路1之電源供應端13呈電性連結，輸出端24連結至一 ⑴襯塾4，系統靜電放電即由此輸出襯塾4進入整體電路。 200917461 以:::電路I·亦為一反相器，包含一"型金氧半場效電晶體36 型金氧半場效電晶體37。半導體電路3包 31、—接地端32、-電源供應端33以及—輸出端％，立中接地 =半:Γ電路1之接地端11呈電性連結_ 料1之電源供應端13呈電性連結，輸出端34連結至半 ==輸入端11，半導體電路3即藉此連結以輸出訊號至 電=5考第2圖，下文將以系統靜電放電為例說明靜電放電防護 乍用同時電晶體之各摻雜區域極性亦標示於圖上，以 便於理解〇火 、 备—具有正電壓之系統靜電放電訊號由輸出襯塾4進 入由於電晶體26之汲極263與電晶體26所在之井區265為 ㈣接面’因此系統靜電放電訊號將藉由汲極加進入井區况， V;S 265之電位暫時抬高為V卜為便於說明，在此假設 為15伏特⑺。接著’靜電放電訊號透過與井區265 性之一基體接觸區域164導出，而後藉由靜電放電防護電 之第一電位輕合元件151柄合至第一閘控元件Μ之問極 =。㈣服⑹1位暫時抬高為V2，在此假設㈣抬高為 /、、° 62與基體接觸區域164呈電性連結，因此源極 之電位亦暫時抬高為l5v;同時祕⑹二閘控元件Η 之閘極171呈電性递6士 、、.°，且連結至輸入端11 ’故閘極171與輸入 16血電亦暫時被抬高為UV。在此實施例中，第一閘控元件 Μ電晶體26共用基體接觸區域164。 述靜電放電防護電路15之第二電位耗合元件152會將 200917461 V2耦合至第二閘控元件17之源極172,使源極172之電位暫時抬 高為V3，在此假設V3被抬高為7V。此時第一閘控元件16之閘 極氧化層跨壓為丨乂2_¥1丨=丨11¥_15¥丨=4¥，同時第二閘控元件17之 閘極氧化層跨壓為j V2-V3丨=丨11V-7 V|=4V。可知藉由選擇靜電放電 防護電路之電位輪合元件’可將半導體電路内之閘控元件之間極 氧化層跨壓限制在一範圍内。以利用符合18V半導體製程所製造 之金氧半場效電晶體而言，其閘極氧化層耐壓約為5V，因此第一 閘控元件16與第二_元件17之閘極氧化層並不會被系統靜電 放電擊穿。 請繼續參考第2圖，當一具有負電塵之系統靜電放電訊號由輸 出襯塾4進入時’由於電晶體27之汲極273與電晶體η所在之 井區275為順偏接面，因此系統靜電放電訊號將藉由汲極273進 入井區275’而後將井區275之電位暫時拉低為v4。為便於說明， 在此假設V4被拉低為指，由於第m件Π之基體接觸區 ’ Π4與井區275具有相同極性，因此第二間控元件η之源極電Uf brother one gate control element 17 can also be - Ρ type gold oxide half 200917461 field effect transistor. As described above, the first potential of the ESD protection circuit 15 is connected to the power supply terminal 13 and the wheel is inserted into the power supply terminal 13 and the second potential engagement component 152 is connected to the ground. Terminal 12 and input terminal U. The potential of the light-emitting component can be lightly combined, and the voltage difference between the two ends of the potential is limited to the set value, so that the on-line electrostatic discharge occurs, and the second control is performed on the second control device. Component Η provides protection. For the step-by-step description, the electrostatic discharge protection circuit 15 is used in the semiconductor circuit 2 and the semiconductor circuit 3 of FIG. 1 in the case of the system electrostatic discharge, and the second picture in the second = "the second picture is the The semiconductor structure of the schematic circuit diagram is schematically assumed to be a semiconductor structure fabricated by using a Uv semiconductor process. It is to be said that the semiconductor circuit 2 and the semiconductor circuit 3 are electrically connected to the semiconductor circuit, and the conductor circuit 2 and the semiconductor circuit are located. The same buried layer (_ed coffee) at the same time, the semiconductor circuit 3 is separately located in the other buried layer. The buried layer is used to provide different filamentary insulation in the half-structured towel, that is, the semiconductor circuit 3 and the half circuit 2 The semiconductor channel 1 is in an insulated state by the domain layer, and can only be connected by burial & The second figure shows that the 'semiconductor circuit 1 and the semiconductor circuit are 2 bits; the layer 18 is inside, and the semiconductor circuit 3 is located at the buried layer 19 Inside. The body circuit 2 is also an inverter, and includes a P-type gold oxide half field effect transistor 26 21, an N-type mountain gold oxide half field effect transistor 27. The semiconductor circuit 2 includes an input terminal 22, a power supply terminal 23 and an output terminal 24, wherein the grounded semiconductor, the grounding end UW of the conductor ^1 is connected, and the power supply terminal 23 and the power supply terminal 13 of the circuit 1 Electrically connected, the output end 24 is coupled to a (1) lining 4, and the system electrostatic discharge thereby outputs the lining 4 into the overall circuit. 200917461 The ::: circuit I· is also an inverter, including a " type of gold oxide half field effect transistor type 36 gold oxide half field effect transistor 37. The semiconductor circuit 3 includes 31, the grounding terminal 32, the power supply terminal 33, and the output terminal %, and the grounding terminal = half: the grounding end 11 of the circuit 1 is electrically connected. The power supply terminal 13 of the material 1 is electrically connected. Connected, the output terminal 34 is connected to the half== input terminal 11, and the semiconductor circuit 3 is connected to output the signal to the electric=5 test. FIG. 2, the system electrostatic discharge is taken as an example to illustrate the electrostatic discharge protection and the simultaneous transistor. The polarity of each doped region is also shown on the figure to facilitate understanding of the bonfire, the system electrostatic discharge signal with positive voltage from the output lining 4 into the well region where the gate 263 of the transistor 26 and the transistor 26 are located. 265 is the (four) junction' so the system electrostatic discharge signal will be added to the well by the bungee, and the potential of V; S 265 is temporarily raised to V. For convenience of explanation, it is assumed to be 15 volts (7). The 'electrostatic discharge signal is then conducted through one of the substrate contact regions 164 of the well region 265, and then the first potential light-emitting element 151 of the electrostatic discharge protection is coupled to the first gate of the first gate control element. (4) Service (6) 1 person temporarily raises to V2, and assumes that (4) the elevation is /, and ° 62 is electrically connected to the substrate contact area 164, so the potential of the source is temporarily raised to l5v; at the same time, the secret (6) two gate control The gate 171 of the component 呈 is electrically transferred to 6 Ω, .°, and is connected to the input terminal 11 ′ so that the gate 171 and the input 16 blood electricity are temporarily raised to UV. In this embodiment, the first gate element Μ transistor 26 shares the body contact region 164. The second potential consuming element 152 of the ESD protection circuit 15 couples 200917461 V2 to the source 172 of the second thyristor 17 to temporarily raise the potential of the source 172 to V3, assuming that V3 is raised. It is 7V. At this time, the gate oxide layer of the first gate control element 16 has a voltage of 丨乂2_¥1丨=丨11¥_15¥丨=4¥, and the gate oxide layer of the second gate element 17 has a cross-voltage of j V2. -V3丨=丨11V-7 V|=4V. It can be seen that by selecting the potential wheel element ' of the ESD protection circuit, the voltage across the oxide layer between the gate elements in the semiconductor circuit can be limited to a range. In the case of a gold-oxygen half-field effect transistor manufactured by using an 18V semiconductor process, the gate oxide layer has a withstand voltage of about 5V, so the gate oxide layer of the first gate element 16 and the second_element 17 does not It is broken down by the system electrostatic discharge. Please continue to refer to FIG. 2, when a system electrostatic discharge signal with negative electric dust enters the output lining 4, 'because the drain 273 of the transistor 27 and the well region 275 where the transistor η is located are the same, the system The ESD signal will enter the well region 275' by the drain 273 and then temporarily pull the potential of the well region 275 down to v4. For convenience of explanation, it is assumed here that V4 is pulled down to mean that since the base contact region 'Π4 of the mth member has the same polarity as the well region 275, the source of the second control element η is electrically
㈣被暫時拉低為_13V<)接著，靜電放電訊號藉由靜電放電防護 電路15之第二電位耗合元件152叙合至第二閘控元件Π之閘極 將閘極171之電位暫時拉低為V5，在此假設v5被拉低為 由於源極172與基體接觸區域m呈電性連結，因此源極π 之電位亦暫時拉低為·13Υ’·同時閘極⑺與第-閘控元件16之閘 ‘呈電!生連結，且連結至輸入端u，故間極⑹與輸入端η 之電位亦暫時被拉低為-9V。 承上所述，靜電放電防護電路15之第一電位轉合元件⑸會將 10 200917461 V5搞合至第一閘控元件16之源極162,使源極162之電位暫時拉 低為V6 ’在此假設V6被拉低為-5V。此時第一閘控元件16之閑 極氧化層跨壓為丨V5-V6|=|-9V-(-5V)|=4V，同時第二閘控元件π之 閘極氧化層跨壓為|V5-V4|=|-9V-(-13V)|=4V。 由以上說明可知，藉由靜電放電防護電路15，當系統靜電放電 產生時，無論其具有正電壓或負電壓，半導體電路1皆不會因系 統靜電放電而損毀。在上述實施例中，電位耦合元件可由以下之 族群選出：金氧半場效電晶體（M0SFET)電容、多晶矽層間 (poly-insulator-poly)電容、金屬層間（metai_insulat〇r meta丨）電 容及元件寄生電容。 請繼續參考第3圖，其為另—利用本發明之半導體電路示意圖。 相較於第1圖繪示之實施例’其不同處為靜電放電防護電路35包 含-第-電位耦合元件35卜一第二電位耦合元件352、及一電位(4) being temporarily pulled down to _13V<), the electrostatic discharge signal is temporarily pulled by the second potential consuming element 152 of the ESD protection circuit 15 to the gate of the second thyristor Π The low is V5, and it is assumed that v5 is pulled low because the source 172 is electrically connected to the substrate contact region m, so the potential of the source π is temporarily pulled down to ·13Υ'· while the gate (7) and the first gate control The gate of the component 16 is electrically connected and connected to the input terminal u, so that the potential of the interpole (6) and the input terminal η is temporarily pulled down to -9V. As described above, the first potential switching element (5) of the ESD protection circuit 15 will engage 10 200917461 V5 to the source 162 of the first gate control element 16 to temporarily lower the potential of the source 162 to V6 ' This assumes that V6 is pulled down to -5V. At this time, the voltage of the idle oxide layer of the first gate control element 16 is 丨V5-V6|=|-9V-(-5V)|=4V, and the gate oxide layer of the second gate control element π is | V5-V4|=|-9V-(-13V)|=4V. As apparent from the above description, by the electrostatic discharge protection circuit 15, when the system is electrostatically discharged, the semiconductor circuit 1 is not damaged by the system electrostatic discharge regardless of whether it has a positive voltage or a negative voltage. In the above embodiments, the potential coupling element can be selected from the group consisting of: a metal oxide half field effect transistor (M0SFET) capacitor, a poly-insulator-poly capacitor, a metai_insulat〇r meta丨 capacitor, and a component parasitic capacitance. Please continue to refer to FIG. 3, which is a schematic diagram of a semiconductor circuit using the present invention. The difference from the embodiment shown in Fig. 1 is that the electrostatic discharge protection circuit 35 includes a -potential coupling element 35, a second potential coupling element 352, and a potential.
阻隔元件353。其中第一電位柄合元件351與第二電位耦合元件 352之作用如同前述實施例，在此不再贅述。電位阻隔元件扮 串聯連結至—半導體電路5之輸人端，_串料結至另一半導 體電路6之輸出端，使半導體電路5之輸入端因靜電放電防護電 路％之作用而於系統靜電放電期間產生—電位變化時，能藉由電 位阻隔讀353將此電位變化阻隔抑制，而防止電位變化往半導 2路6傳遞’進而保護半導體電路6不受系統靜電放電影響。 ^施例中’半導體電路5及6與前述之半導體電路丨及3分 =相同電路，在此不再贅述。在本實施例中，電位阻隔元件 扣係-阻抗器，可由電感及電阻其中之—來選出。 11 200917461 由上述實施例可知’本發明之靜電放電防護電路至少可適用於 夕井區且包含閘控疋件之半導體電路。本發明可於系統靜電放電 ♦生時提供對具有正電壓或負電壓之靜電放電完整之防護功 月b同時亦可抑制系統靜電放電發生時之電位變化，防止電位變 化往^他半導體電路傳遞，進而保護其他半導體電路。 上述之實鉍例僅用來例舉本發明之實施態樣，以及闡釋本發明 之技術特徵，並非用來限制本發明之保護範_。任何熟悉此技術 者可I易疋成之改變或均等性之安排均屬於本發明所主張之範 圍，本發明之權利保護範gj應以中請專利範圍為準。 【圖式簡單說明】 第1圖係為一利用本發明之半導體電路示意圖； 第圖係為第1圖所繪示電路示意圖之半導體結構示意圖；以 及 弟3圖係為另—利用本發明之半導體電路示意圖。Barrier element 353. The first potential shank element 351 and the second potential coupling element 352 function as the foregoing embodiments, and details are not described herein again. The potential blocking element is connected in series to the input end of the semiconductor circuit 5, and the _ string is connected to the output end of the other semiconductor circuit 6, so that the input end of the semiconductor circuit 5 is electrostatically discharged in the system due to the action of the electrostatic discharge protection circuit. During the period-potential change, the potential change can be suppressed by the potential blocking read 353, and the potential change is prevented from being transmitted to the semiconductor path 6 to protect the semiconductor circuit 6 from the system electrostatic discharge. In the embodiment, the semiconductor circuits 5 and 6 are the same as the above-mentioned semiconductor circuit and the same circuit, and will not be described again. In this embodiment, the potential blocking element buckle-resistor can be selected by an inductor and a resistor. 11 200917461 It can be seen from the above embodiments that the electrostatic discharge protection circuit of the present invention is applicable to at least a semiconductor circuit including a gate electrode. The invention can provide a complete protection power month b for electrostatic discharge with positive voltage or negative voltage when the system is electrostatically discharged, and can also suppress the potential change when the system electrostatic discharge occurs, and prevent the potential change from being transmitted to the semiconductor circuit. In turn, other semiconductor circuits are protected. The above examples are intended to exemplify the embodiments of the present invention and to explain the technical features of the present invention, and are not intended to limit the protection of the present invention. Any arrangement that changes or equalizes the skill of the present invention is within the scope of the present invention. The scope of the invention should be based on the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a semiconductor circuit using the present invention; FIG. 1 is a schematic diagram of a semiconductor structure of a schematic circuit diagram shown in FIG. 1; and FIG. 3 is another semiconductor using the present invention. Circuit diagram.
【主要元件符號說明】 1 : 半導體電路 3 ： 半導體電路 11 : 輸入端 13 ： 電源供應端 15 ： 靜電放電防護電路 152 : 第二電位耦合元件 17 : 閘控元件 162 : 源極 2 ： 半導體電路 4 ： 輸出襯墊 12 ： 接地端 14 ： 輸出端 151 ： 第一電位耦合元件 16 ： 閘控元件 161 ： 閘極 163 ： 沒極 12 200917461 164 ： 基體接觸區域 171 ： 閘極 172 : 源極 173 ： 汲極 174 ： 基體接觸區域 18 ： 埋藏層 19 ： 埋藏層 21 ： 輸入端 22 ： 接地端 23 ： 電源供應端 24 ： 輸出端 26 ： 電晶體 27 ： 電晶體 263 ： 汲極 265 : 井區 273 ： 汲極 275 ： 井區 31 ： 輸入端 32 ： 接地端 33 ： 電源供應端 34 ： 輸出端 36 ： 電晶體 37 ： 電晶體 5 ： 半導體電路 6 ： 半導體電路 35 ： 靜電放電防護電路 351 ： 第一電位耦合元件 352 ： 第二電位耦合元件 353 ： 電位阻隔元件 13[Main component symbol description] 1 : Semiconductor circuit 3 : Semiconductor circuit 11 : Input terminal 13 : Power supply terminal 15 : Electrostatic discharge protection circuit 152 : Second potential coupling element 17 : Gate control element 162 : Source 2 : Semiconductor circuit 4 : Output pad 12 : Ground terminal 14 : Output terminal 151 : First potential coupling element 16 : Gate control element 161 : Gate 163 : No pole 12 200917461 164 : Base contact area 171 : Gate 172 : Source 173 : 汲Pole 174: substrate contact region 18: buried layer 19: buried layer 21: input terminal 22: ground terminal 23: power supply terminal 24: output terminal 26: transistor 27: transistor 263: drain 265: well region 273: 汲Pole 275 : Well 31 : Input 32 : Ground 33 : Power supply 34 : Output 36 : Transistor 37 : Transistor 5 : Semiconductor circuit 6 : Semiconductor circuit 35 : Electrostatic discharge protection circuit 351 : First potential coupling Element 352: second potential coupling element 353: potential blocking element 13