200917385 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種多晶片主動面朝上堆疊技術， 特別係有關於一種適用於多晶片堆疊之晶片組裝方法及其 結構。 【先前技術】 習知多晶片堆疊結構係將複數個半導體晶片逐一往 上堆疊在一基板，並且該些半導體晶片之主動面皆為朝 上而遠離基板’在每一晶片設置之後並以打線形成之銲 線電性連接該晶片至該基板。為了防止該些銲線被上方堆 邊之晶片壓迫’在多晶片堆疊過程中會在晶片與晶片之間設 置一間隔片（spacer)，該間隔片之高度需高於其間銲線之弧 高，此一間隔片習知可以是聚亞醯胺膠帶（PI tape)、虛晶片 (dummy chip)、金屬片（metal piate)等等，並應黏著上下晶 片。故多晶片堆疊過程必須經過一道間隔片設置步驟，會 ^ 增加製程複雜度及增加生產成本與時間。 如第1圖所示’一種習知之多晶片主動面朝上堆疊結 構100主要包含一基板110、一第一晶片120、一曰 中一曰a片 130、—間隔片140以及複數個銲線151、152。依該多晶片 主動面朝上堆疊結構1 00之製造流程可見於第2圖所示，主 要包括「提供一基板」1 1、「設置第一晶片」i 2、「第一 電性連接」1 3、「設置間隔片」1 4、「設置第二晶片」 1 5與「第二電性連接」1 6等步驟，茲說明如下。 首先在步驟11中’配合參閱第1圖，先提供一基板 5 200917385BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-wafer active face-up stacking technique, and more particularly to a wafer assembling method suitable for multi-wafer stacking and a structure thereof. [Prior Art] A conventional multi-wafer stack structure stacks a plurality of semiconductor wafers one by one on a substrate, and the active faces of the semiconductor wafers are all facing upward and away from the substrate 'after each wafer is disposed and formed by wire bonding. The bonding wire electrically connects the wafer to the substrate. In order to prevent the soldering wires from being pressed by the wafers above the stacking edge, a spacer is disposed between the wafer and the wafer during the multi-wafer stacking process, and the height of the spacers is higher than the arc height of the bonding wires therebetween. Such a spacer may be a PI tape, a dummy chip, a metal piate, etc., and should be attached to the upper and lower wafers. Therefore, the multi-wafer stacking process must go through a spacer setting step, which increases the complexity of the process and increases the production cost and time. As shown in FIG. 1 , a conventional multi-wafer active face-up stack structure 100 mainly includes a substrate 110 , a first wafer 120 , a 曰 a 130 a sheet 130 , a spacer 140 , and a plurality of bonding wires 151 . 152. The manufacturing process according to the multi-chip active surface-up stacking structure 100 can be seen in FIG. 2, and mainly includes "providing a substrate" 1 1 "setting a first wafer" i 2. "first electrical connection" 1 3. "Setting the spacer" 1 4, "Setting the second wafer" 1 5 and "Second electrical connection" 16 and other steps, as explained below. First, in step 11, 'with reference to Figure 1, first provide a substrate 5 200917385
11〇,該基板no係具有在其上表面之複數個連接指ιη。 之後’在步驟12中’在該基板110上方設置一第一晶片12〇, 其係具有一主動面121與一相對之背面122並具有複數個位 於該主動面121之第一銲墊123。該第一晶片12〇之該背面 122設置於該基板110上。之後，在步驟13中，打線形成複 數個第一銲線151，以電性連接該第一晶片12〇之該些第一 銲墊123至該基板110之該些連接指ln。之後，在步驟μ 中，一間隔片140係設置於該第一晶片12〇之主動面i2i中 央而不覆蓋該些第一銲墊123。通常該間隔片14〇之下表面 可預先形成一第一黏著層161以黏接到該第一晶片12〇，而 該間隔片140應提供一支撐厚度，高於該些第一銲線15丨之 打線弧高。 之後在步驟1 5中，將一第二晶片1 3 0設置於該間隔片 140上，以其主動面m遠離該基板ιι〇之方式往上堆疊。 利用一第二黏著層162黏著該第二晶片13〇之—背面Η)與 3 1隔片140之上表面。遠第二黏著層162可預先形成於該 f二晶片130之背面132，亦可預先形成於該間隔片140上 錯由該間隔片140可防止該些第一銲線151被上方堆疊之第 一曰曰片130壓迫而造成短路。該第二晶片13〇更具有複數 個位於該主動面之第二銲塾133。之後，在步驟16 中，以複數個第二銲線152電性連接該第二晶片13〇之 忒些第二銲墊133至該基板11〇之該些連接指1H，以達 成電性連接。 因此，在習知的多晶片堆疊過程中，「設置間隔片」步驟 200917385 14為一必要步驟以在第一晶片12〇與第二晶片13〇之間設置 該間隔Μ 140’增加了製程複雜度與時間。又該間隔片 上下表面之黏著層162與161會增加晶片堆疊間隙，導致多 晶片堆疊高度增加，若直接薄化晶片12〇與13〇之厚度則容 易有晶片麵曲之缺點。 【發明内容】 本發明之主要目的係在於提供一種適用於多晶片堆 疊之晶片組裝方法及其結構，能在晶圓等級型態—次形 成複數個晶片上之間隔片並整合在晶背研磨製程内，可 簡化製程、節省時間與成本，達到量產的效益。 本發明之次一目的係在於提供一種適用於多晶片堆 豐之晶片組裝方法及其結構，可減少習知多晶片堆疊製 程中之間隔片設置步驟並能降低多晶片堆疊結構之高 度。 本發明的目的及解決其技術問題是採用以下技術方 ρ 案來實現的。依據本發明之一種適用於多晶片堆疊之晶 片組裝方法主要包含以下步驟。首先提供提供—晶圓， 包含複數個晶片並具有一主動面與一背面，每一晶片於該主 動面係设有複數個銲墊。接著，貼附一晶背研磨保護膠帶於 該晶圓之該主動面，該晶背研磨保護膠帶係嵌埋有複數個間 隔片’其係位置對應於該些晶片。之後，研磨該晶圓之該背 面’以減少該些晶片之厚度。之後，以選擇性去除該晶背研 磨保護膠帶之黏性方式，由該晶圓分離該晶背研磨保護勝 帶’並使該些間隔片被保留以貼附於該些晶片上，並顯露該 200917385 些銲墊。最後’切割該晶圓，以使該些貼附 $間搞片之曰y 為分離。另揭示由該方法製得之晶片組裝蛀 曰日 、、、〇 不霉。 本發明的目的及解決其技術問題還 措施進一步實現。 蘇用以下技術 在前述的適用於多晶片堆疊之晶片組骏方法 擇性去除黏性之方法係可為紫外光（uv)照射。/’上述選 在前述的適用於多晶片堆疊之晶片組裝方法 ^ 研磨保護膠帶與該些間隔片之界面係可為暫時性紫：：背 者，而該些間隔片與該些晶片之界面係 i先點 黏著。 .、，、固丨生或熱塑性 在已 在前述的適用於多晶片堆疊之晶片組裝方法中 分離曰曰:片上之該些間隔片係可為半固化樹脂。 上述 在前述的適用於多晶片堆疊之晶片組裝方法中 選擇性去除黏性少古i ^ ^ 黏生之方法係可為圖案化照射。 在前述的適用於多晶 門阻y / 疊晶片組裝方法中，該也 間片係可具有一抗應 一 之翹曲度。 4強度以減少該些晶片研磨後 【實施方式】 依據本發明之—且 ，、體貫施例，具體揭示一種適用於 多曰曰片堆疊之晶片組裝方法及其結構。 配合參閱第3A至 步驟；値皮 F圖，本發明之晶片組裝方法之 戈驟順序詳述如下。 2 ] n ^ 先如第3A圖所示，提供一晶圓 0，其係包含複數個坌— 北 弟—日日片2〗丨並具有一主動面212與 —'月面213，每一第—曰u 曰曰片211於該主動面2 12係設有複數 200917385 個銲塾214。更提供有-晶背研磨保護膠帶22q，其内部和 埋有複數個間隔片221。接著’如第3B圖所示，貼附該晶 背研磨保護膠帶220於該晶圓21G之該主動面212，以保^ 該晶圓210,避免該晶圓210破裂或翹曲。並且該晶背研 磨保護膠帶220所嵌埋之複數個間隔片221係位置對應於該 些第一晶片2 11之中央位置。 該晶背研磨保護膠帶220與該些間隔片221在同一貼附 表面係具有不同之黏著特性，（列如，該晶背研磨保護膠帶22〇 對該些間隔片221與該些第一晶片211之第一黏著界面222 係可為暫時性紫外光黏著，而該些間隔片221與該些第一晶 片211之第二黏著界面223係可為熱固性或熱塑性黏著。在 一具體實施例中，該些間隔片221之第二黏著界面⑵之點 著強度係可較穩定於該晶背研磨保護膠帶22〇之第一黏著界 面222之黏著強度。該些間隔片221係可為半固化樹脂。 在不同實施例[該些間隔片221係可為任意材質。 之後如第3C圖所不，以一研磨台31Q研磨該晶圓⑴ 之5玄为面2 1 3，以滅少兮此泣 a u 乂減夕忒些4 一晶片211之厚度至達到預定 厚度。 之後如第3D及3E圖所示，以—uv照射燈32〇照射 =晶背研磨保護膠帶22〇,以選擇性去除該晶背研磨保護膠 π =20之黏性方式’在該步驟之後，該晶背研磨保護膠帶2汕 之第黏著界面222之黏著強度將被弱化，以明顯小於該些 間片221之第二黏著界面223之黏著強度。其中，上述選 擇!·生去除黏性之方法係可為紫外光(υν)照射或圖案化照 200917385 射如3E ®所τ，能由該晶圓2】〇分離該晶背研磨保護谬 帶220 ’並使該些間隔片22】被保留以貼附於該些第一晶片 211之主動面212上，並顯露該些銲墊2】4。由於在該— 照射燈32〇照射之後會產生之υν光能使該第一黏著界面 222喪失黏性而容易分離’而第二黏著界面223則不會有任 何弱化現象以保持黏著於該些第U2n。該晶背研磨保 護膠帶220可輕易撕離。 最後，如第3F圖所千，妥丨r田 , 圖所不，利用一切割刀纟33〇沿著該晶圓 2 1 0之切丄線2 1 5切割’以使該些已貼附有間隔片η }之第 一晶片211為分離’得到複數個可供多晶片主動面朝上堆疊 之曰曰片組裝結構。而該切割刀具33〇可以為—鑽石劃線器、 鑽石m射劃線器之其中-種。在晶圓切割過程，該晶圓 210之背面可貼附 附至&位膠帶（®中未繪…，或稱為blue -X地，在該些已分離第一晶片211上之該歧間隔 221仍可維持在半固化樹脂。利用調整該些間隔片 川之熱膨服係數，該些間隔片221係可具有— 強度’以減少該些第一晶片2"研磨後之 二 已貼附有間隔片22丨之當 曰 又。該t 上堆疊之應用，具有劁铲飭# 動面朝 明逸…、與堆疊高度降低之功效。本發 月進 7 °兄明依上述方法所製得日片έ且裝钍Α 牛，“ U侍曰曰片組裝結構的應用方 / 知案的功效。請參閱第5圖所示 已貼附有間隘U， 丨尤用上連 寸有間…21之第一晶片211之多 「裎报一μ l *此万法包含 人」“、5又置第一晶片」22、「室 ^ ο， 「 第一電 e又置第二晶片 24斑「第_ 」 ，、弟—電性連接 連接.”「μ m ' 第一電把 10 200917385 25等步驟’可以省略習知多晶片堆疊過程中設置間隔 片之步驟。 首先在步驟21中’請配合參閱第4A圖，先提供一 基板240，該基板240係具有複數個連接指241。該美板 係可為一導線架或一電路基板。並在步驟22中，在兮其板 240上方設置一第一晶片211，該第一晶片211已利用本發 明之方法於晶圓等級預先形成一間隔片221。該第—晶片2ιι 係具有一主動面2 12與一相對之背面2 13。該第—晶片2 j i 係具有複數個位於該主動面212周邊之第一銲塾214。藉由 一黏晶層250之黏貼’使該第一晶片211之該背面213役置 於該基板240。 之後’在步驟23中’請參閱第4B圖所示，做第一電性 連接，以打線形成之複數個第一銲線26 1連接該些第一銲塾 214至該基板240之該些連接指241。並且，該些第—鲜線 26 1之打線弧高應低於該間隔片240，以避免該些第一銲線 261被後續堆疊於其上方之晶片（第二晶片231)碰觸到而造 成短路。可利用一黏著膠27〇覆蓋該第一晶片21丨之周邊區 以及該些第一銲線261之一端，藉以固定該些第—銲線261 以防止沖線、增強該第二晶片231之打線支撐性等功效（如 第4C圖所示）。 之後，在步驟24中，如第4C圖所示’設置一第二晶片 231於該間隔片221之上方。較佳地該第二晶片23ι與該 第一晶片211係為同尺寸.例如，該第一晶片21 j與該第二 晶片231係可為記憶體晶片。該第二晶片231係具有一主動 200917385 2”相對之s面233 ’以該主動面23 1遠離該基板240 之方式在上堆疊。s亥第一晶片231之複數個第二銲墊234 係如同該第一晶片211這般形成在該主動面232之周 邊。該第二晶片23 1係可預先形成有一間隔片221(圖中 未繪出）’或者亦可不形成。之後，在步驟25中，以複數 個第二銲線262連接該些第二銲墊234至該基板24〇上 表面之該些連接指241，以達成電性連接。較佳地，可在完 成堆疊該第二晶片23 1或更多晶片之後，以一封膠體（圖中 未會出）始封所有的堆疊晶片，提供適當的封裝保護以防 止電性短路與塵埃污染。 因此，本發明揭示一種適用於多晶片主動面朝上堆疊 之晶片組装方法及其結構，可以減少習知多晶片堆疊製 权中之間隔片設置步驟，並能降低多晶片堆疊結構之高 度。間隔片之設置已有效合併於晶圓等級之晶背研磨過 私，不會增加製程步驟，利用此一晶圓級形成間隔片之 "方式，可以簡化製作流程及節省製程時間與成本，並可 達到量產之之效益。 以上所㈤’僅是本發明的較佳實施例而已，並非對 本七月作任何形式上的限制’本發明技術方案範圍當依 所附申請專利範圍為準。你何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例’但凡是未脫離本發明技術方案的内 容’依據本發明的技術實質對以上實施例所作的任何簡 早修改、等同變化與修•，均仍屬於本發明技術方案的 12 200917385 範圍内。 【圖式簡單說明】 第1圖：習知多晶片主動面朝上堆疊結構之截面示意圖。 第2圖：習知多晶片主動面朝上堆疊方法之流程示意圖。 第3 A至3 F圖：依據本發明之一具體實施例，一種適 用於多晶片堆疊之晶片組裝過程中元件截面示意 圖。 第4A至4C圖：依據本發明之一具體實施例，利用該 ' 晶片組裝進行多晶片主動面朝上堆疊之元件截面 示意圖。 第5圖：依據本發明之一具體實施例，利用該晶片組裝 結構實施一種多晶片主動面朝上堆疊方法之流程 示意圖。 【主要元件符號說明】 11 提供 -"― 基板 12 設置 第 一晶 片 13 第一 電 性連接 14 設置 間 隔片 15 設置 第 二晶 片 16 第二 電 性連接 21 提供 一 基板 22 設置 第 一晶 片 23 第一 電 性連接 24 設置 第 二晶 片 13 200917385 25 第二電性連接 100 多 晶 片 主動1 面朝上堆疊結構 110 基板 111 連接指 120 第 一 晶 片 121 主動 面 122 背 面 123 第 一 銲墊 130 第 二 晶 片 131 主動 面 132 背 面 133 第 二 銲 墊 140 間 隔 片 151 第一 黏著層 152 第 二黏著 161 第 一 銲 線 162 第二 銲線 210 晶 圓 211 第一 晶片 212 主 動面 213 背 面 214 第一 銲墊 215 切 割線 220 晶 背 研 磨保' 護膠帶 221 間 隔片 222 第 一 黏 著界 面223 第二 黏著界面 231 第 二 晶 片 232 主動 面 233 背 面 234 第 二 銲 墊 240 基板 241 連接指 250 黏 晶 層 261 第一 銲線 262 第 二銲線 270 黏 著 膠 3 10 研 磨 台 320 UV a ?、射燈 330 切 割刀具 1411〇, the substrate no has a plurality of connection fingers on its upper surface. A first wafer 12A is disposed above the substrate 110 in a step 12, and has an active surface 121 and an opposite back surface 122 and has a plurality of first pads 123 on the active surface 121. The back surface 122 of the first wafer 12 is disposed on the substrate 110. Then, in step 13, a plurality of first bonding wires 151 are formed to electrically connect the first pads 123 of the first wafer 12 to the connecting fingers ln of the substrate 110. Thereafter, in step μ, a spacer 140 is disposed at the center of the active surface i2i of the first wafer 12 without covering the first pads 123. Generally, a surface of the lower surface of the spacer 14 is pre-formed with a first adhesive layer 161 for bonding to the first wafer 12A, and the spacer 140 should provide a supporting thickness higher than the first bonding wires 15丨. The arc is high. Then, in step 15, a second wafer 130 is disposed on the spacer 140, and the active surface m is stacked upwardly away from the substrate. A second adhesive layer 162 is adhered to the upper surface of the second wafer 13 and the upper surface of the spacer 130. The far second adhesive layer 162 may be formed on the back surface 132 of the f-die 130, or may be formed on the spacer 140 in advance. The spacer 140 may prevent the first bonding wires 151 from being stacked above. The cymbal 130 is pressed to cause a short circuit. The second wafer 13 further has a plurality of second pads 133 located on the active surface. Then, in step 16, a plurality of second bonding wires 152 are electrically connected to the second pads 133 of the second wafer 13 to the connecting fingers 1H of the substrate 11 to form an electrical connection. Therefore, in the conventional multi-wafer stacking process, the "set spacer" step 200917385 14 is a necessary step to set the spacer Μ 140' between the first wafer 12 〇 and the second wafer 13 增加 to increase the process complexity. With time. Moreover, the adhesive layers 162 and 161 on the upper and lower surfaces of the spacer increase the wafer stack gap, resulting in an increase in the stack height of the multi-wafer. If the thickness of the wafers 12 and 13 is directly thinned, the wafer surface curvature is easily disadvantageous. SUMMARY OF THE INVENTION The main object of the present invention is to provide a wafer assembly method suitable for multi-wafer stacking and a structure thereof, which can form spacers on a plurality of wafers in a wafer level type and integrate them in a crystal back grinding process. In the process, the process can be simplified, time and cost can be saved, and the benefits of mass production can be achieved. A second object of the present invention is to provide a wafer assembly method suitable for multi-wafer stacking and a structure thereof, which can reduce the spacer setting step in the conventional multi-wafer stacking process and can reduce the height of the multi-wafer stack structure. The object of the present invention and solving the technical problems thereof are achieved by the following technical methods. A wafer assembly method suitable for multi-wafer stacking according to the present invention mainly comprises the following steps. First, a wafer is provided, comprising a plurality of wafers and having an active surface and a back surface, each wafer having a plurality of pads on the active surface. Next, a crystal back-grinding protective tape is attached to the active surface of the wafer, and the back-grinding protective tape is embedded with a plurality of spacers' positions corresponding to the wafers. Thereafter, the back side of the wafer is ground to reduce the thickness of the wafers. Thereafter, in order to selectively remove the adhesive manner of the back-grinding protective tape, the wafer back-grinding protection tape is separated from the wafer and the spacers are retained to be attached to the wafers, and the 200917385 Some pads. Finally, the wafer is cut so that the affixes of the affixed $ are separated. It is also disclosed that the wafers produced by the method are assembled on the next day, and are not mildewed. The object of the present invention and the technical problems thereof are further solved. The following techniques are used in the above-described wafer stacking method suitable for multi-wafer stacking. The method of selectively removing the viscosity is ultraviolet (uv) irradiation. The above-mentioned wafer assembly method suitable for multi-wafer stacking ^ the interface between the polishing protective tape and the spacers may be temporary violet:: the back, and the interface between the spacers and the wafers i stick first. . . . , Solid-state or thermoplastic In the above-described wafer assembly method suitable for multi-wafer stacking, the spacers may be semi-cured. The above method for selectively removing the less viscous paste in the wafer assembly method suitable for multi-wafer stacking may be patterned illumination. In the foregoing method for assembling a polycrystalline gate-resistance y/stack wafer, the inter-sheet system may have a warpage of an anti-correspondence. 4 Intensity to reduce the polishing of the wafers [Embodiment] According to the present invention, and in a physical embodiment, a wafer assembling method suitable for multi-layer stacking and a structure thereof are specifically disclosed. Referring to Figs. 3A to 3, the steps of the wafer assembly method of the present invention are detailed as follows. 2 ] n ^ First, as shown in FIG. 3A, a wafer 0 is provided, which includes a plurality of 坌-Beidi-Japanese film 2 丨 and has an active surface 212 and a 'moon surface 213, each of the first The 曰u 曰曰 211 is provided with a plurality of 200917385 weld 214 on the active surface 2 12 . Further, a back-grinding protective tape 22q is provided, and a plurality of spacers 221 are embedded inside and inside. Next, as shown in FIG. 3B, the back-grinding protective tape 220 is attached to the active surface 212 of the wafer 21G to protect the wafer 210 from being broken or warped. And the plurality of spacers 221 embedded in the back grinding protective tape 220 are located at positions corresponding to the central positions of the first wafers 2 11 . The back-grinding protective tape 220 and the spacers 221 have different adhesive properties on the same attaching surface (for example, the back-grinding protective tape 22 〇 the spacers 221 and the first wafers 211 The first adhesive interface 222 may be a temporary ultraviolet light adhesion, and the spacers 221 and the second adhesive interface 223 of the first wafers 211 may be thermosetting or thermoplastic adhesive. In a specific embodiment, the The strength of the second adhesive interface (2) of the spacers 221 is relatively stable to the adhesion strength of the first adhesive interface 222 of the back-grinding protective tape 22. The spacers 221 may be semi-cured resins. Different embodiments [the spacers 221 can be any material. After that, as shown in FIG. 3C, the polishing table 31Q is used to polish the surface of the wafer (1) by 2 1 3 to eliminate the weeping au 乂After the thickness of the wafer 211 is reached to a predetermined thickness, as shown in FIGS. 3D and 3E, the uv irradiation lamp 32 〇 irradiation = crystal back grinding protective tape 22 〇 to selectively remove the crystal back grinding Protective adhesive π = 20 viscous mode 'after this step The adhesion strength of the adhesive interface 222 of the back grinding protection tape 2 will be weakened to be significantly smaller than the adhesion strength of the second adhesive interface 223 of the interlayer 221. Among them, the above selection! The method can be irradiated by ultraviolet light (υν) or patterned according to 200917385, such as 3E ® τ, and the wafer back grinding protection tape 220 ' can be separated from the wafer 2 并使 and the spacers 22 are retained. Attaching to the active surface 212 of the first wafer 211, and exposing the solder pads 2] 4. The first adhesive interface 222 can be lost due to the υν light generated after the irradiation of the illumination lamp 32〇. It is viscous and easy to separate 'the second adhesive interface 223 does not have any weakening phenomenon to remain adhered to the U2n. The crystal back grinding protection tape 220 can be easily peeled off. Finally, as shown in Figure 3F,丨r田, the figure is not, using a dicing blade 〇33〇 along the tangent line 2 1 5 of the wafer 2 1 'cut ' so that the first wafer 211 to which the spacer η } has been attached is Separating 'a plurality of cymbal assembly structures for multi-wafer active face-up stacking. The cutting tool 33 can be one of a diamond scribe and a diamond m scribe. In the wafer cutting process, the back of the wafer 210 can be attached to the & tape (not drawn in the ®) ... or blue-X, the spacing 221 on the separated first wafers 211 can still be maintained in the semi-cured resin. By adjusting the thermal expansion coefficient of the spacers, the spacers The 221 series can have - strength 'to reduce the number of the first wafers 2 " the second after grinding has been attached with the spacers 22 。. The application of the stacking on the t has a shovel 饬# moving face towards Mingyi ..., with the effect of reducing the height of the stack. This month, the 7° brothers made the Japanese έ 依 έ 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依 依There is a 隘U, 丨 用 用 用 ... ... ... 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 , "The first electric e is placed on the second chip 24 spot "the _", the younger - the electrical connection is connected." "μ m 'the first electric handle 10 200917385 25 steps ' can be omitted in the conventional multi-wafer stacking process Steps of the spacers. First, in step 21, please refer to FIG. 4A to provide a substrate 240 having a plurality of connecting fingers 241. The board can be a lead frame or a circuit substrate. In step 22, a first wafer 211 is disposed over the plate 240. The first wafer 211 has been pre-formed with a spacer 221 at the wafer level by the method of the present invention. The first wafer 2 ιι has an active surface. 2 12 opposite to the back side 2 13. The first wafer 2 ji has a plurality of weeks located on the active surface 212 a first solder fillet 214. The back surface 213 of the first wafer 211 is placed on the substrate 240 by adhesion of a bonding layer 250. Then, in step 23, please refer to FIG. 4B. A first electrical connection is formed, and the plurality of first bonding wires 26 1 formed by wire bonding are connected to the first bonding pads 214 to the connecting fingers 241 of the substrate 240. And, the first fresh wires 26 1 are wired. The arc height should be lower than the spacer 240 to prevent the first bonding wires 261 from being short-circuited by the wafer (second wafer 231) stacked thereon. The adhesive can be covered with an adhesive 27 The peripheral region of a wafer 21丨 and one of the first bonding wires 261 are used to fix the first bonding wires 261 to prevent punching and enhance the wire bonding support of the second wafer 231 (eg, FIG. 4C) Then, in step 24, as shown in FIG. 4C, a second wafer 231 is disposed above the spacer 221. Preferably, the second wafer 23i is the same size as the first wafer 211. For example, the first wafer 21 j and the second wafer 231 can be a memory wafer. The second wafer 231 is provided. An active 2009173852 "s of the opposing surface 233 'to the remote from the active surface 231 of substrate 240 are stacked on. A plurality of second pads 234 of the first wafer 231 are formed around the active surface 232 as the first wafer 211. The second wafer 23 1 may be formed with a spacer 221 (not shown) in advance or may not be formed. Then, in step 25, the second pads 234 are connected to the connecting fingers 241 on the upper surface of the substrate 24 by a plurality of second bonding wires 262 to achieve electrical connection. Preferably, after stacking the second wafer 23 1 or more wafers, all the stacked wafers are sealed with a gel (not shown) to provide proper package protection to prevent electrical short circuits and dust. Pollution. Accordingly, the present invention discloses a wafer assembly method and a structure suitable for multi-wafer active face-up stacking, which can reduce the spacer setting steps in the conventional multi-wafer stacking and reduce the height of the multi-wafer stack structure. The spacer setting has been effectively combined with the wafer level of the crystal back grinding, which does not increase the process steps. By using the wafer level to form the spacer, the manufacturing process can be simplified and the process time and cost can be saved. The benefits of mass production can be achieved. The above (f) is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Those skilled in the art will be able to make a few changes or modifications to the equivalent embodiments of the present invention by using the technical contents disclosed above. However, the present invention does not depart from the technical solutions of the present invention. Any short modifications, equivalent changes, and modifications made by the invention still fall within the scope of 12 200917385 of the technical solution of the present invention. [Simple description of the drawing] Fig. 1 is a schematic cross-sectional view of a conventional multi-wafer active face-up stacking structure. Figure 2: Schematic diagram of a conventional multi-wafer active face-up stacking method. Figures 3A through 3F are schematic cross-sectional views of components during wafer assembly for multi-wafer stacking in accordance with an embodiment of the present invention. 4A-4C are schematic cross-sectional views of elements of a multi-wafer active face-up stack using the 'wafer assembly' in accordance with an embodiment of the present invention. Figure 5 is a flow diagram showing the flow of a multi-wafer active face-up stacking method using the wafer assembly structure in accordance with an embodiment of the present invention. [Main component symbol description] 11 Providing -" substrate 12 arranging first wafer 13 first electrical connection 14 arranging spacer 15 arranging second wafer 16 second electrical connection 21 providing a substrate 22 arranging the first wafer 23 An electrical connection 24 sets the second wafer 13 200917385 25 second electrical connection 100 multi-chip active 1 face up stack structure 110 substrate 111 connection finger 120 first wafer 121 active surface 122 back 123 first pad 130 second wafer 131 active surface 132 back surface 133 second solder pad 140 spacer 151 first adhesive layer 152 second adhesive 161 first bonding wire 162 second bonding wire 210 wafer 211 first wafer 212 active surface 213 back surface 214 first solder pad 215 Cutting line 220 crystal back grinding protection tape 221 spacer 222 first adhesive interface 223 second adhesive interface 231 second wafer 232 active surface 233 back 234 second solder pad 240 substrate 241 connection finger 250 adhesive layer 261 first solder Line 262 second wire 270 Adhesive 3 10 Grinding table 320 UV a ?, spotlight 330 cutting tool 14