TW200917017A - Mass production testing of USB flash cards with various flash memory cells - Google Patents

Abstract

A high volume testing/formatting process is provided for Universal Serial Bus-based (USB-based) electronic data flash cards (USB devices) that meets the increasing demand for USB electronic data flash cards (USB devices). A test host is simultaneously coupled to the multiple USB devices (e. g. , using a multi-port card reader or a probe fixture), a controller endpoint value is read from each of the USB devices and verified with a known good value, and then testing/formatting is performed on each of the USB devices by writing predetermined data into each USB device in a pipelined manner, then reading out and testing the predetermined data. In one embodiment, the test host implements a special USB driver that blocks standard USB registration procedures upon detecting the plurality of USB devices. Control and/or boot code data are written onto the flash memory device (i. e. , instead of being provided on a controller ROM)

Description

200917017 IX. INSTRUCTIONS: This application is a continuation (CIP) of "High Volume Testing for USB Electronic Data Flash Cards" of U.S. Patent Application Serial No. 11/626,347, the entire disclosure of which is incorporated herein by reference. The application period of 626, 347 is January 23, 2007. The case is also the US Patent Application No. 09/478, 720 of the "Electronic Data Storage Medium with Fingerprint Verification Capability" filed on January 6, 2000. The US case filed on August 23, 2006 - Part of the serial file (CIP) of the "Flash Memory Controller For Electronic Data Flash Card" numbered 11/466, 759, and the US application number 11/466,759 is for 2004 The US case filed on February 26, but the partial case (CIP) of the application number 10/789,333 "System and Method for controlling Flash Memory" has been withdrawn. This application is also related to the US Application Serial No. 09/366,976 filed on August 4, 1999, and the "Integrated circuit card with fingerprint verification capability" of the patent number 6, 547, 130. A partial continuous case (CIP) of "Cell-Downgrading and Reference-Voltage Adjustment for a Multi-bit-cell Flash Memory" of U.S. Patent Application Serial No. 11/737,336, the entire disclosure of which is incorporated herein by reference. US Patent Application for January 6, 2000 - Application No. 09/478, 720 "Electronic Data Storage Medium with Fingerprint Verification Capability" and US Patent Application No. 11/466, 759, filed on August 23, 2006 "Flash 200917017"

Part of the Continuous Case (CIP) of the Memory Controller For Electronic Data Flash Card, and US Application No. 11/466,759 is the US case filed on February 26, 2004, but the application number that has been revoked is now l〇/789,333" Partial Continuity (CIP) for System and Method for control 1 ing Flash Memory. This application is also a continuation-in-part of U.S. Patent Application Serial No. 11/864,696, entitled "Backward Compatible Extended Usb plug And Receptable With Dual Personality", filed September 28, 2007, in which Patent Application No. 11/864,696 is again in 2007. U.S. Patent Application Serial No. 11/624,667, the entire disclosure of which is incorporated herein by reference. The division of /478, 720 is also a partial succession of the US Application No. 11/674,645 "Recycling Partially-Stale Flash Blocks Using a Sliding Window for Multi-Level-Cell (MLC) Flash Memory" filed on February 13, 2007. The present application is a partial continuation of US Patent Application No. 11/742,270, "Two-Level RAM Lookup Table for Block and Page Allocation and Wear-Leveling in Limited Write Flash-Memories", filed on April 30, 2007; U.S. Patent Application Serial No. 11/624,667, filed Jan. A continuation of the ication Capability, and the patent application No. 11/624,667 is a division of US Patent Application No. 09/478,720, filed on Jan. 6, 2000, filed on Jan. 25, 2004. A contiguous version of the application Serial No. 10/854, 004, "Extended Secure-Digital Card Devices and Hosts", and the patent application number 10/854, 004 is U.S. Patent Application Serial No. 10/708,172, which is hereby incorporated herein by reference. This application is also a partial continuation (CIP) of "Extended USB Plug, USB PCBA and MLC USB Flash Drive with Dua Personality" of U.S. Patent Application Serial No. 11/866,927, filed on Oct. 3, 2007. The disclosures of the above-identified applications and patents are hereby incorporated by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an electronic data flash card, and more particularly to a system and method for testing a USB electronic data flash card during manufacture. [Prior Art] Confidential data files are often stored in a soft disk drive (fl〇ppy disk), or transmitted through a weight or t code to ensure security #network, and the confidential data file will be borrowed during transmission. By adding a security stamp (new and watermark) to send. However, once the password, encryption code, security stamp and imprint are cracked, confidential information and documents are exposed to danger, resulting in no permission This confidential information can be used. Because flash memory technology has become more advanced & advanced, the flash memory card is gradually replacing the traditional disk drive as a storage medium for the mobile system. Flash memory has a significant 200917017 advantage over soft wall smashers or magnetic hard disks', for example, high G shock resistance and low power consumption. Due to the small size of the flash memory, it is more conductive to the mobile system. Therefore, due to its compatibility with portable (mobile) systems and low power features, the trend of flash memory has gradually grown. USB electronic data flash card (flashc) Ard) is a portable and low-power device that uses Universal Serial Bus (USB) technology as the interface for the flash memory device of the host computer and flash card. The j_USB electronic data flash card has various forms, such as Pen drive (10) storage device, MP3 player, digital camera. In each case, USB electronic data flash memory card generally includes a flash memory, a processor and a USB interface circuit. The fast-paced card is popular, and the manufacturing volume of the β3β electronic data memory card (or USB flash card) continues to grow. With the increase in manufacturing volume, the problem facing the manufacturing industry is how to be effective and reliable before shipment to the end user. Test the USB flash card. For the reasons of low cost, compatibility and reliability, the traditional test method uses the personal computer (10) to test the language _ flash + (that is, the most end user - the general use of USB The flash card is connected to the pC and will be able to use the USB flash card quickly and reliably after purchase. This is a problem with the PC test method: k PC window (or) operating system only once Aid some USB devices, and for the operating system to speculate and Wei_flash card, it takes a lot of time to manually insert the "every-USB flash card, and then manually remove each-na flash card. Therefore, Xi Known test methods can not keep up with the increase in manufacturing yield. There is a need for a large number of test methods to meet the need for which 200917017 sub-data flash card needs to be increased. [Summary of the Invention] Providing an electronic data flash card, comprising a flash memory device, an optional fingerprint sensor, an input/output interface circuit, and a processor. The electronic data flash card is suitable for receiving the host Used by computers, such as personal computers, notebook computers, or other electronic hosts. Since the electronic data flash card is easy to carry and durable, the personal data can be stored in the flash memory in an encrypted manner. Therefore, the fingerprint sensor can be combined with the card body, so that only the fingerprint can be matched. Use a memory card to ensure that a non-authorized person cannot use the memory card.

The present invention also provides a large number of test/formatting processes for electronic data flash cards (USB devices) based on Universal Serial Bus (USB_based) to meet the increased demand for electronic data flash cards (USB devices). The present invention provides a method and system for extensive testing/formatting of a device, using a test host coupled to a multi-head USB device (eg, a multi-slot card reader or a probe fixture), from each usb The device retrieves a controller endpoint value and confirms the controller endpoint value with a known good value, and then formats each USB device to write a predetermined subscription to each USB device in a "pipeline" manner. data. The USB device is then read out for testing to test the predetermined data. In one embodiment, the test host utilizes a particular usb drive to block the standard USB registration process when most USB devices are detected. Prior to testing/formatting, the present invention ignores the conventional USB registration procedure and confirms the controller endpoint value' by deleting the time consuming and unnecessary registration process to facilitate efficient and extensive testing/formatting of the USB device. In addition, the present invention writes data in a "pipeline" manner into a USB 2009 17017 device, which aids in the large number of test/format USB devices' greatly reducing production time. In accordance with one aspect of the invention, each USB device is modified to store the selected control code and activation code data 'device information and configuration information' on the flash memory to reduce the size of the controller ROM. Because the conventional USB registration process requires the use of many such control codes, boot codes, device information, and configuration information (because the conventional USB registration process assumes that such codes and information are retrieved from the controller ROM), The conventional USB registration process provides a function to avoid system failure or long delay, because when an unformatted USB device (with a blank flash memory device) is coupled to the test host system, the host system will wait for this control, the boot code and News. In accordance with another aspect of the invention, the purpose of the test/formatting process includes checking that all of the wafers are properly soldered, whether the current level of consumption meets specifications, and each component device (eg, controller and flash memory device). Compatible with the test/formatting implemented by the test host. The formatting process provides all the entry point values needed to download the correct controller operation, erases the flash memory, creates the remaining bad-block-list file for later bad block management, and Provides low-level formatting to aid in OS recognition. In accordance with an embodiment of the present invention, the control read during the initial phase of the test/saling process has no value-only configuration descriptor values, a large number of stored class values, and a product identification value. When the controller endpoint value read from each device matches a good value stored on the test host, the flag displayed on the test host monitor indicates a successful status (eg, the flag changes from red to green) . 200917017 According to another embodiment of the present invention, the test/formatting process includes storing one or more of the bad broom block data in a flash memory device to confirm the storage capacity of each flash memory device. Whether a predetermined size is equal (for example, a specific ratio of the entire memory capacity), at least two copies of the bad block data are written to the flash memory device, and the control code and/or the boot code are written to the flash memory. In the device, the provided customer data is written into the flash memory device, and the update serial number, the date code, and the product version code value are written into the flash memory device. The purpose, technical contents, features and effects achieved by the present invention will become more apparent from the detailed description of the embodiments and the accompanying drawings. [Embodiment] The present invention relates to an improvement on a method for manufacturing an electronic data flash card. Although the present invention uses a USB electronic data flash card as a specific reference below, the innovation of the present invention can be used for a wide range of fast. Flash card type manufacturing, including pci,

Secure Digital (SD)^ Memory Stick (MS) · Compact Flash (CF) > IDE and SATA flash memory, but not limited to these types of flash cards. Referring to FIG. 1(A), an electronic data flash card 10 is transmitted through an external (host) computer 9 through any interface bus 13 or card reader according to an embodiment of the present invention (in the figure) Not shown) or other interface mechanism (not shown) and electronic: the material flash card 1 〇 includes a card body, a processing unit 2, a flash or a flash, a memory device 3, Optional fingerprint sensor (security device) Input/output interface circuit 5' - Optional display unit 6, an optional power supply 7 (eg battery)' and - optional functional buttons Group 8. 12 200917017 The flash memory device 3 is mounted on the card body 1 and stores the data file, the reference password and the fingerprint reference data in a well-known manner. The fingerprint reference data is scanned by the person who has the right to use the data file. Obtained by fingerprint. The data file can be a picture file or a text file. It will be further suggested below that the flash memory device 3 also includes starter code data and control code data. The fingerprint sensor 4 is located on the card body 1 and is used to scan the fingerprint of the user of the electronic data flash card to generate fingerprint scanning data. An example of a fingerprint sensor 4 for use in the present invention is disclosed in "INTEGRATED CIRCUIT CARD WITH FINGERPRINT VERIFICATION CAPABILITY" in U.S. Patent No. 6,547,130, the entire disclosure of which is incorporated herein by reference. The fingerprint sensor described in the above patent includes a scan unit array to define a fingerprint scan area. The fingerprint broom data includes a plurality of scan line data obtained by scanning the eyebrow line corresponding to the array of scan cells. Moreover, the sweeping cat line of the swept cat unit array is scanned in the lateral and longitudinal directions of the array. Each of the scanning units generates a first logic signal when detecting the fingerprint portion of the holder of the card body, and the fingerprint of the holder of the card body is recessed (va 11 ey) A second logic signal is generated. The input/output interface circuit 5 is located on the card body 1. The interface bus 5B or a card reader uses a suitable socket to be activated to establish a communication relationship with the host computer. In one embodiment, the input/output interface circuit 5 includes circuitry and control logic 'where the control logic is associated with one of the Universal Serial Bus (USB) 'PCmca, 13 2009 17017 RS232 interface structure to connect to a host The computer 9 is connected or a socket located on the host computer 9. In another embodiment, the input/output interface circuit 5 can include an SD interface circuit, an MMC interface circuit, a CF interface circuit, an MS interface circuit, a PCI-Express interface circuit, and an integrated driver electronics (IDE) interface. One of the circuit and a SATA interface circuit is in contact with the host computer 9 via the interface bus 13 or the card reader. The processing unit 2 is fastened to the card body 1, and is connected to the memory device 3, the fingerprint sensor 4, and the input/output interface circuit 5 by means of related conductive lines or wires positioned on the card body 1. In one embodiment, processing unit 2 may be one of the 8051, 8052, 80286 microprocessors produced by Intel Corporation. In other embodiments, processing unit 2 includes a RISC, ARM, Μ IPS or other signal processor. According to one aspect of the invention, the processing unit 2 is controlled by a program at least partially stored in the flash memory device 3, such that the processing unit is selectively operable in: (1) a programming mode The processing unit 2 actuates the input/output interface circuit 5 to receive the data file from the host computer, the boot code data and the control code data, the optional fingerprint reference data, and the stored and stored data in the flash memory device (optional compression) The format increases the storage space of the memory device); (2) - reset mode, wherein the boot code data and the control code data are read from the flash memory device 3 and used for setting and controlling processing The operation of the unit; (3) - data retrieving mode, wherein the processing unit 2 reads the fingerprint scan data from the fingerprint sensor 4, and scans the fingerprint data with the flash memory device 3 14 200917017 Compare at least a portion of the fingerprint reference data to confirm whether the user of the electronic data flash card has the right to use the information stored in the flash memory device 3 File, and once it is confirmed that the user has the right to use the data file stored in the flash memory device 3, the input/output interface circuit 5 is activated to transmit the data file to the host computer 9; (4) One code update mode (code updat) i ng mode ), update the startup code data and control code data in the flash memory device; (5) - data reset mode, erase the data file and fingerprint reference from the flash memory device 3 data. In operation, the host computer 9 transmits the write request and read request to the electronic data flash card 10 through the card reader or interface bus 13, and the input/output interface circuit transmits to the processing unit 2' in turn using the flash memory control. The device reads or writes to one or more flash memory devices 3. In an embodiment, the processing unit 2 detects that the data file and the fingerprint reference data are stored in the memory device 3. After a predetermined time period has elapsed, the data reset mode operation is automatically initialized. The 8051, 8052, and 80286 are microprocessors developed by Intel Corporation that use complex instruction sets. The 8051 and 8052 have an 8-bit data bus, and the 80286 has a 16-bit data bus. RIsc, ARM, and MIPS use microprocessors that reduce the instruction set architecture. The 8051 and 8052 are widely used in low cost applications. The 80286 can be used for high speed operation applications. RISC, ARM, and Mips are more expensive microprocessors' for more complex applications such as advanced error correction code (ECC) and data decoding. An optional power supply 7 is located on the card body 1 and is connected to the processing unit 2 and its associated unit on the card body to supply its required power. An optional functional button set 8 is attached to the card body 1 and connected to the processing unit 2, and is operable to process the unit 2 in a stylization, reset, data capture, code update or data reset mode. Choose one of them to get started. The functional button set 8 is operable to provide an input password to the processing unit 2. The processing unit 2 compares the input password with the reference password stored in the flash memory device 3, and upon confirming that the input password matches the reference password, the electronic data flash card 10 begins the authorization operation. The optional display unit 6 is located on the card body 1 and is connected to the processing unit 2 and controlled by the processing unit 2 for displaying the data file exchanged with the host computer 9 and displaying the operation of the electronic data flash card 10. status. The following are some of the advantages of the present invention: First, the electronic data memory card has a small size but a large storage capacity, thereby facilitating the data transfer process; second, because each person has a unique fingerprint. Therefore, the electronic data flash card only allows authorized users to use the data files stored in it to enhance security. Other features and advantages of the present invention are further set forth below. Fig. 1(B) is a block diagram showing an electronic data flash card 10A according to another embodiment of the present invention, in which a general sensor unit 4A is provided instead of the above-described fingerprint sensor. The exemplary sensor unit includes a retinal scanner or sound recognition device capable of detecting physiological characteristics of a privileged user, and operates in a manner similar to fingerprint sensor 4 described above. 16 200917017 Figure 1(C) is a block diagram showing an electronic f flash card 10B in accordance with another embodiment of the present invention. The electronic data flash card (10) removes the fingerprint sensor and related user identification process. In order to reduce the cost, the electronic data flash card (10) also includes a highly integrated processing unit it 2B, which contains an input/intake interface circuit and a fast memory controller 21. The input/output interface circuit includes a transceiver block and a continuous interface block (seHai shirt (3) engine bl〇ck), a data buffer, a register, and an interrupt logic. The input/output interface circuit 5B is pure to the (4) bus bar to allow communication between the different components of the input/output interface circuit 5B and the components of the flash memory controller 21 to the components of the flash memory controller. The flash memory controller 21 includes a micro processing unit... a read only memory (_), a static random access memory (_, a controller logic, a false positive code logic, a universal input wheel). In the present embodiment, the type of input output (GPIG) logic _ plural diodes is used as the age indicator, for example, indicating good power or reading/writing flashing, tongue The GPI0 is logically connected to other I/O devices. The flash memory controller 21 is connected to one or more flash memory devices 3B. In this embodiment, the host computer @9δ includes a functional button. Group 8B' is used when the electronic data flash card is operating, and is connected to the processing unit 70. The functional button group 8 is available; ^ & ..s. j is used for the program 'Reset, data capture, program,, update or data reset mode 1Πβ ^ 'Selectively set electronic data flash card. Functional button group 8β 9Ββ processing single ~ Provide - Input password to host computer structure Enter the password and compare it with the reference code of the flash memory device 3Β 2009-1717 Confirming the input password and the reference password - the electronic data flash card (10) starts the authorization operation. Also in this embodiment, the host computer 9B includes - the display unit 6B, when the electronic data f flash card 1GB is in operation 'through reading The card machine or interface bus is connected to the processing unit 2B. The display unit 6B is used to display the data file exchanged with the host computer 8 and display the operation status of the electronic data flash card 10B. The processing unit 2 includes a flash memory type singularity method (flash ah type alg 〇 hm hm), which is used for (4) flash memory personnel, and is not supported by the flash memory. Factors of cost and capacity 'The advancement of flash memory has produced a variety of flash memory types. And because of the potential gaps and cost factors, 'the need for flash memory source flexibility and the need for unique control systems (4) memory Sex, it is important that Xiang has a processing unit of intelligent algorithms to detect and use different types of flash memory. The general flash memory contains identification (10) codes to identify the type of flash memory. Characteristics/parameters of flash memory, such as page (barrier) capacity, block size, organization, capacity, etc. The intelligent algorithm control processing unit 2 is reset ((10)(4) state read flash memory 3), and compare this table with the flash memory controller (4). If the flash memory 3 is not affected, the door "It's controlled by the body control H" flash memory controller You will not be able to use the flash: 3 does not correspond to the lED indicated by the output of the flash memory controller. If the flash memory is subject to control, use the flash memory controller to start using 200917017.

Before flashing the memory, the flash memory controller is performed in the following manner. A flash memory controller having such a smart algorithm is disclosed in, for example, "FUSiI MEM〇RY CONTROLLER FOR ELECTRONIC DATA FLASH CARD" in U.S. Patent No. 11/466,759, the entire disclosure of which is incorporated herein by reference. . The electronic data flash card is a flash memory system that uses flash memory for data storage. Generally, the system architecture of the flash memory system includes a flash memory controller with a processor, R〇M and ram, wherein The start code and control code are located in r〇m as the _ code. Once the power rises, the processor grabs the boot code to execute, and the boot code initializes the system to compose and download the control code into the RAM. Once the control code is downloaded to the RAM, the control code is in control of the system. The control code includes drivers to perform basic tasks such as controlling and assigning memory 'priority of processing instructions, controlling inputs and transferring materials. Control code A includes flash type detection algorithm and flash memory parameter data.匪 is a kind of read-only memory. When the flash memory controller is designed and put into production, the software code in the S ROM is fixed and cannot be changed to support the new flash type that will be supplied to the market in the future. . In this situation, it is necessary to develop a new flash memory controller to support new flash memory from time to time, which is time consuming and costly. The first (D) diagram shows the processing unit 2 of the i-th (8) diagram in more detail. Electronic Data The flash card UM includes a power regulator to provide one or more power supplies. The power conditioner provides different voltages to the processing unit 2a and other related components of the electronic flash card depending on the power demand. In order to maintain power hung, a capacitor of 19 200917017 (not shown) may be required. The electronic data flash card 10A includes a reset circuit 23 for providing a reset signal to the processing unit 2A. Once the power rises, the reset circuit 23 asserts the reset signal to all of the processing units 2A. After the internal voltage reaches a steady state, the reset signal does not exist, and a register and a capacitor (not shown) are provided to appropriately reset the time adjustment. The electronic data flash card 10A also includes a quartz crystal oscillator (not shown) to provide a fundamental frequency to the PLL within the processing unit 2A. According to an embodiment of the present invention, the input/output interface circuit 5A is integrated or partially integrated with the reset circuit 23 and the power conditioner 22 in the processing unit 2A. High integration reduces overall space requirements and reduces complexity and manufacturing costs. For removable devices, such as the electronic data flash card described herein, compactness and cost reduction are key factors. Today's 1C packages allow different 1C components to be integrated into a single IC package with different technologies and materials. For example, the input/output interface circuit is an analog/digital hybrid circuit that can also be integrated into a Multi-Chip package (MCP) having a processing unit. The nature of the hybrid signal 1C technology allows for the mixing of analog and digital circuits. Therefore, high integration can be incorporated into the same wafer/die, with the processing unit containing input/output interface circuitry, flash memory controller, reset circuitry, power regulator. In accordance with another aspect of the present invention, an electronic data flash card includes a boot code and a control code stored in a flash memory rather than in a ROM of a flash memory controller. Therefore, the boot code and control code can be updated in this field without changing the flash memory controller. For example, in the "FLASH MEMORY CONTROLLER FOR ELECTRONIC DATA FLASH CARD" of U.S. Patent Application Serial No. 11/611,811, filed on Dec. I will refer to it here. 2 is a flow chart showing a main method of manufacturing a USB device according to another embodiment of the present invention, and a simplified plan view from the 3rd (A) to 3(B) drawings, showing during different stages of the manufacturing process. USB device. Referring to block 50 of Figure 2, the method of fabrication begins with the use of surface mount technology (SMT) to mount all components of the USB device on the panel (eg, flash memory, controller, and all passive components). Such as resistors and capacitors, where the panel comprises a plurality of printed circuit boards pCB. Figure 3(A) shows an exemplary SMT panel 211 having a plurality of printed circuit board assemblies 211 connected along individual edges to facilitate efficient assembly of different SMT components. Controller wafers, flash wafers, and other components. The pcB device 212 includes circuitry to facilitate electrical connection between different SMT components and between the controller die 212 and the four USB pins 217 (i.e., VDD, D+, D-, and GND). Please refer to Figure 2 again. Then test/format the individual PCBs. According to the process used in this month, the steps are revealed below. In one embodiment, panel 211 (see Figure 3(4)) is based on singulation (block 52A) whereby individual PCBs can be cut or separated from each other and then a single pcB device 212 (see page 3 (A). ®) is based on the test/format program (block 52B). In another embodiment, when the PCB device 212 is still connected to the panel 211 for testing (block 53A), then the formatted/tested PCB device is subjected to a single pass (block 53B). Among them, the invention 200917017 currently prefers the test/formatted PCB device 212 to allow multiple PCB devices 212 to be maintained in a fixed relationship for testing by a single fixture, thereby avoiding additional processing time. Each PCB device 212 is processed (e.g., the PCB device 212 is inserted into a single test fixture). Referring again to FIG. 2, each of the PCB devices 212 that have successfully completed the test/format will receive the product package (block 54), mold or mount a body on the components of each PCB device 212, and then complete the USB. The final test of device 10B (block 55) is ready for shipment. Also, note that the final test performed at block 55 is different from the test/formatting performed at blocks 52B and 53A because all of the initial content is downloaded to each packaged device 10B, as performed at block 55. The final test is about a simple plug-in test test, such as verifying device capabilities to ensure end user satisfaction. 4(A) and 4(B) are diagrams each showing an exemplary system for testing/formatting a USB device in accordance with the present invention. Fig. 4(A) shows a first system for testing a single PCB device according to block 52B of Fig. 2 (refer to the underlying device under test (DUT)). The first system includes a PC test host (e.g., a general purpose personal computer) 202, a monitor 201, a USB composite card reader 204, and other necessary peripheral I/O devices, such as a keyboard and mouse (not shown). In one embodiment, all of the test parameters are displayed on monitor 201 to monitor the test status, wherein a colored flag is used to resolve the pass or fail of the test, and some of the parameters used during the test can be manipulated. Input, such as the parameters shown on monitor 201. The USB card reader 204 includes a plurality of (16 or more) USB slots, each of which is based on the monitor 22 200917017. The flag of i has - specify money (for example, ^ ##2, etc.). The card reader 20 is connected to the test 4 host 2Q2 via a standard ϋδΒ transmission line connected to the standard brain slot 203 of the test host. When each test device (leg) is inserted into the multi-feeder 204 - corresponding 槔 (p〇n), the multi-card reader 2 〇 4 is connected to the test host 202 through the leg slot 'When it is left for each insertion The leg will generate a corresponding flag on the monitor 201 to reflect the detection result (for example, once the debt is detected, the corresponding flag will change from red to green). Figure 4(8) shows a second system 'Using the probe fixture - bing(4)) to test the pre-installed panel and still connect the panel 211 & PCB device 212. The second system includes an SMT probe test host (e.g., a general purpose computer) 207' monitor, e.g., probe fixture 2G5, and other necessary peripheral K) devices. The probe fixture 2G5 includes a plurality of test probes 2〇6 that are gathered to contact the USB pins 217 of each pCB device 212 when the fixture 205 is lowered onto the panel 211. Probe 206 provides four signal paths for formatting/testing each device on panel 211. In addition, a collection cable 208 is used to connect the fixture 2A to the test host 207. Figure 5(A) is a simplified flow diagram showing the conventional USB test system using a conventional host operating system (?s) driver (block 301) to test and format a conventional USB device. As shown in block 3〇2, once a conventional USB device is connected to a host system, the host 〇s temporarily stores the pre-established USB protocol used by the conventional USB test device (DUT). This pre-established USB protocol is based on the assumption that the specific device data (e.g., the device identification and serial number can be the same before the test) is stored in the predetermined location of the controller provided on the DUT. In addition, the pre-established (4) agreement requires that the registration procedure be owed to one DUT (that is, before starting the registration process for another implicit, it must be done before - a registration procedure). And, if it fails, all will wait until the operator re-installs the program before starting. As shown in block 3G2, the problems with these pre-established coffee protocols are spent _ more time to register each one, and to store these registration data in the registry bank of the host OS ( And finally there is a hard disk in the host) and it is not suitable for testing/formatting a large number of DUTs at the same time. The additional problem with using this pre-established USB protocol is that it does not work with new USB devices (the boot code, control code, and component and device identification data are stored in the flash memory device), not in ROM. At the predetermined location). As shown in blocks 3〇4 and 3〇5, since the untested/unformatted device formed according to the present invention does not include the component identification number and the product identification number, it is known that the prior USB protocol may cause the host test system. Hang up (block 306), or take a while to complete the test (block 307), and/or just fail to complete formatting/testing (blocks 3-8). Figure 5(B) is a simplified flow diagram showing the testing and formatting of a new USB device in accordance with another embodiment of the present invention. As shown in block 501, the new software is hacked to the test host to perform a dedicated USB test to block the USB drive of the legacy operating system (OS). The purpose of blocking the USB drive of the conventional device is to shorten the test time by deleting the time required for the registration process. This dedicated USB test passes the partial registration procedure to request data from the USB device (not written to the flash memory device), and the controller of the USB device directly writes the start code, controls the drink and 24 200917017 device identification. At least one of the data—to the Flash Center to begin the test/format process. In particular, as shown in block 502, in order to avoid the need for more than 16 USB devices, the test/format soft system in the test line system is modified to read the controller's hard code. The descriptors (hard-coded descnptQr) values are compared to the stored program parameters to confirm that the DUT is ready to be formatted and provide the correct parameters for the DUT for normal operation. Only continuous inspections will continue the software process. Then, as shown in block 5〇3, in order for the USB device to be used by the end user user, the main boot block (MBR), the file configuration table (FAT), and the initial system file are written to Inside the flash device. Since the conventional USB device is correctly programmed using the read-only memory (ROM) in the initial system operation, the conventional USB device will not perform the formatting process. This stylization step is important for the purpose of making software and for subsequent use. In addition, as indicated by block 504, several values written to the flash device satisfy the USB specification. The device serial number is such a value, and the device serial number written to each device is input with the software by the test operator. The starting values are randomly or continuously changed. Other variables, such as product identification numbers (IDs), also need to be changed by different product or volumetric capacities. Furthermore, the USB driver of the conventional operating system (OS) does not perform these values and variable writing programs, thus making the capacity USB test impossible. As shown in blocks 505, 506, and 507, the present invention provides several benefits to the USB registration driver of the conventional operating system, that is, because the present invention utilizes a specially specified system 25 200917017 software, format/test a large number of USB devices. The time is reduced. In addition, the segmentation (capacity, drive letter) can be tailored to meet each of the different needs in accordance with well-known techniques. Figure 6 is a simplified flow diagram showing a method of manufacturing formatting/testing of a USB device in accordance with a particular embodiment of the present invention. The method of Figure 6 can be used for a single or multiple devices connected to the panel to achieve a high speed "pipel ine" formatting/testing procedure, rather than a slow individual DUT test (as in Figure 3(A) Show). As indicated by block 101, prior to beginning the formatting/testing process for a selected DUT (group DUT), the modified USB driver software is installed on the test host system to operate the blocking custom operating system USB is identified as "" HCDI, sys" drive section. Software instructions that are used to prevent execution of the segment "HCDI, sys" are known to those skilled in the art. In one embodiment, some small files of the USB sink driver of the operating system are replaced for this reason, as will be appreciated by those skilled in the art. As represented by block 102, one or more "brand new" (unformatted and untested) USB devices formed in accordance with the present invention are probed, inserted or otherwise coupled to a suitable fixture (eg, 4(A) and one of the fixtures shown in Figure 4(B)). As indicated by block 110, an initial simple check of the plurality of USB devices is then performed by examining the contents of the hard-coded values of the controller to identify most of the common errors. In particular, as shown in FIG. 6(A), once the USB device is coupled, the count value of the 2009 2009 1717 is set to " Γ , the host test software reads at least some hard coded data stored in the - device - (eg, '- or more hard-coded configuration, interface and endpoint descriptors (block 120)) in the controller read-only memory, storing a large number of class codes (blocks 121), Vendor identification (VID) and product identification (piD) values (block 122), and comparing the hard marshalling data to predetermined well-known good values to determine if the non-synchronized device is coupled to the test host (block 123). If an incorrect device is detected ("No" path at block 123), pass through a corresponding DUT (such as 卯 丨 或 or dut [2], one

The colored (such as red) colored flag (such as red) that is designated as DUT[C0UNT], the flag is generated - the warning signal 'warns the operator to remove the incorrect device. After a continuous short check of the selected device (in block 123, the "path"), the colored (such as yellow) flag or its closing signal is displayed on the host test system (blocks). In block 1G3C, the device count value is compared to the predetermined maximum device number according to the number of currently tested devices (all devices connected to the panel). If the count value 疋v is at the maximum device number, then the count is increased (block 1)) and repeat the short check on the USB device of the other-coupled test system (ie, block 1 () 2_123 and block 103) 'until each device that has been reduced to the host test line has been continuously subjected to a short check (in the block) The bottle "is, the path", and the count value is reset at this time. As shown in block 103D, once all of the devices under test (10) τ) have completed initialization, the program can selectively select the pause and wait by the operator - "continuous, signal (eg, pressing a blank key on the host system or using a mouse) Pressing the stART 27 200917017 pattern on the monitor. This pause allows the operator time to visually check the display flags of all DUTs, replacing any DUTs designated as defective (in this case 'for the new DUT, the initialization process It will be repeated. According to the method of the present invention, at least some hard coded data is briefly checked before testing and/or formatting the flash memory device to facilitate an efficient and reliable procedure of the USB device. Figure, once a brief initial check of all USB devices is completed, the test host performs the actual test and formatted flash memory device. This test/format process begins with saving the flash memory for temporary storage of the code entry point (code) The first block of entry point (Fig. 6 'block 130). As shown in Fig. 6(B), in one embodiment, for each DUT During the save process, continuously set the count value to “ Γ (block 131), select the current DUT (DUT[Count]), and save the first block in the current DUT for the flash memory for the entry point register. (Block 133) 'The count value is then incremented (blocks 135, 137)' and the process is re-saved to the next DUT until all DUTs have been processed ("Yes" path at block 135). Finally, the code entry point stored in the storage space includes an operating system (〇s) entry point, a firmware entry point and a non-volatile register entry point. Note that after the test/format process is completed, the actual code entry point values are written (downloaded) in the relevant area of the first block being saved. Next, the capacity of the flash memory provided in each USB device is checked (Fig. 6, block 140). The sixth (C) diagram is a flow chart of the capacity inspection process per unit according to the embodiment. The process begins with the estimated count value of “Γ (Section 141). Reading, by reading the initial bad block data provided in the Neiyi memory device, the memory capacity check is performed for each leg (ie 28 200917017) The reading position is in the fixed position of the device (4), and the manufacturer or supplier of the memory device is programmed; block 142). After that, the bad block data generated from the sweep is used for the decision. Whether a specific proportion of the stored memory exists (blocks 143 and 144), if the insufficient reserve memory (reservedmem〇ry) is provided, the DUT is rejected. According to the test specification for the future bad block data re-link ( That is, #—a good block—one or more flash memory units copy data from a good block when a certain point fails, and re-in--reserve a good memory block to locate the data) Clock (indicating the whole, good, one specific ratio of memory) - predetermined size (eg 2Q%). Note that for USB devices with even (two or more) flash memory chips, when detecting Measured a high proportion Good block, the dual channel operation is not Osato powder production, and therefore only a single recommendation - checking each channel in the flash memory format - age flash memory capacity of the USB device, the present invention contributes to early

q The internal block identification data of the μgong is stored in the flash memory storage area

, 14丫), and capacity check and bad block data storage until all (10) UT has been processed (in block 146, ear " 卩, 10,000 block 14γ), the process will be connected, continue to repeat in each - 29 200917017 is the path). Then 'in accordance with the present invention, the process column' uses the burst writing process (burst writing 乂 control code data and startup code are written to the IFlash 4 _ body block (block 6 of the 6th circle) The system controls the selected memory controller of the memory. The control firmware generated by the surface can help the subsequent control and the device, including the two types of control codes and dynamic control codes. The control code of the addictable, static and used for production ~ recognition + / by an initial reset jump address (fine (10) position) can 1 yummy (four) 敝 蝴 蝴 / 写 写 写 写 写 写 写For example, a static control code contains a relatively long write time delay that assists in writing to the "most responsive" (slowest) _memory_). According to the present invention, the static control code stored in the face is controlled by the controller. Obtained at the start (start_up). The dynamic control code includes the time_control information to be affected by the Xiali _ flash memory type (such as the number of best write operations) 'corrected to help the most appropriate _ remember (four) Facilitating the adaptability of the field. According to another embodiment of the invention, the dynamic control system is at the age of In the selected block of the flash memory, to reduce the control of the H grain size and promote the field adaptability ^ after the control body is written into the flash memory body, one of the leg control bit systems is reset. The control of the clear processor is moved from the static control code to the dynamic object code. To assist in moving to the dynamic body, the static, jump start "feed start" system provided in _ includes the entry point of the dynamic control code. The address is used for further execution. Figure 6(D) is a simple flow chart showing the use of the "pipeline" mode to write control firmware to each DUT to reduce processing time. The count value of the DUT is initialized (block 151), and then a page (or block) of instructions or/and data is written to the SRAM (volatile) buffer of the 2009-1717 DUT (block 152). As shown on the right, a page of instructions or / and data includes writing the control firmware to the block immediately following the bad block. After writing this page, the host system orders the write command/data from the SRAM buffer. To the flash memory unit (square Block 153). Note that during the formatting/testing process, the dynamic control code has not been written to the flash memory, so the write process used by the DUT is based on a slower static control code. In accordance with the present invention, This write process is performed in an aging manner. Once a page of instructions/data is written to the SRAM and the DUT is ordered to perform this write operation, the host system proceeds to the next MN (ie, at block 157' the count value is incremented, then The host system writes the same instruction/data to the next DUT. Finally, the -page instruction/data is written to each (at block 155, is the "path"). The instruction materials have been written to everyone. If not, the count value is initialized (block 151), the write process is repeated, and the next page of instructions/data is written to the DUT. When the instruction/data of the second page is written to the first 酣 (ie, 丽[(1), the first-DUT has completed the instruction/data process from the view buffer, the first page, to the block specified by the memory. With this, in the pipeline mode, the process of writing the human dynamic control code to each of the processes is performed in a highly efficient manner, avoiding waiting for the host system to wait for each message to be written into the flash memory. The long delay caused by the control. In one embodiment of the present invention, one or more blocks of the flash memory are designated to be scaly buffers, and these are configured to write (10) In-protection information', for example, after storage is used and the value lost by the electrical test, such as the number of capacity divisions and the password of the immortal. Whether it is in the above-mentioned cluster, or the control code is written to each After earning the subsequent (such as the second) burst writing process, the information is written into every 厮200917017. Note that the dynamic control code can be used to speed up the writing process after using the continuation of the burst writing process. Next, as shown in block 160 (Figure 6) Low-level formatting of flash memory, where low-order formatting is based on user specifications provided. In an embodiment, 'low-level formatting includes the main boot area (MBR) The file configuration table (FAT) and the initial root directory data are written to the selected memory block of the flash memory. Without this information, the USB device cannot be used by the end user. Note that if a terminal user obtains A USB device that has not been formatted in a low-level format, the USB device will not be usable, and the terminal user cannot use the operating system provided by the formatting software to perform this step. However, after completing the low-level formatting, the terminal user It is possible to change the FAT format they want. During any of the above-mentioned burst write processes or during the subsequent burst write process after the dynamic control code is written to each DUT, the low-order format information is written to Each mile (eg, block 160A of Figure 6(d)). After the low-order formatting, update sequence number, date code, and product version code values are written to the non-volatile scratchpad (block 170 of Figure 6) ), during any of the above-mentioned burst write processes or during the burst write process (eg, page 6) after the dynamic control code is written to each DUT, as shown in block 17A of the figure) The information is written to each DUT. Next, the test host reads all the information written to the flash memory (block 18〇), and then compares the information with the value in the buffer of the host system pre-existing. It is confirmed that the USB device is properly formatted. According to the consistent embodiment of the present invention, the confirmation process (veri f icati〇n pr〇Cess) is displayed in the 6th (E) diagram. The count value is set to " Γ (square (8) ), then the host system indicates 32 200917017 The current DUT reads the scheduled information from the flash memory weight. Note that the reread process is performed using the dynamic control code previously written to the DUT. Thereafter, the information read from the DUT is compared to the pre-stored data in the host system (block 183). If any of the data read from the USB device is incorrect ("No" path at block 184), a corresponding flag (eg, a red flag) is displayed on the host test system monitor to indicate the operator The device failed in the test/format process (block 185A). Conversely, if the data read from the current USB device is correct, displaying the corresponding flag (eg, the green flag) on the host test system's Newline|| indicates that the test/formatting process was successful ( Block 185B). Thereafter, at block 187, the device calculated value is compared to the maximum number of devices based on the number of current parent test devices (e.g., all devices connected to the panel). If the calculated value is less than the maximum number of devices, the device calculations are repeated one by one to repeat the test process with the other device to the test host until each device to the host test system has been checked (at block 187). The "Yes, Path" is then terminated by the test host program. Figure 7 is a simplified block diagram showing a sample hall device (10) in accordance with a particular embodiment of the present invention. As described above, the USB device includes a flash. The card controls $214 with one or more flash memory devices 215. Referring to the left half of Figure 7, the flash memory 215 is depicted in simplified form in Figure 7, /, under the needle field, The flash memory 215 includes an entry point register 420 and a defective product and a material 413 to control the selection bit 415A, and the control body 415B, and the non-volatile register are not used by the controller 214 and the flash memory. The communication between the bodies 215 is directly related to the functions performed by the entry point register s', wherein the entry point temporary storage H 420 indicates that the controller requires 33 2009 17017 to control the firmware 415B and the non-volatile register 42 〇. Refer to Figure 7 In the half, the controller 214 includes a microprocessor 45, a control e_〇int register 451 and an address locator, a static random access memory (RAM), - Read-only memory (_), an input/output interface circuit stub. The control endpoint register 451 provides the system default address required by each controller (she trained add face). The control endpoint register is used for Communicates with this device, even if the address changes later. Static ROM 453 includes - RAM buffer (buffer) leg and fast flash access time register (1) her access timing register) 453B. Buffer includes - enough memory to store fast At least a "block" of the flash memory 215 and, for example, when performing a block copy job (such as reading data from the flash memory 215 and writing to the face), the buffer can be used to increase the execution speed. During communication with the flash memory 215, the flash memory fetches the time register and stores the instruction code (Fig. and code) utilized by the controller 214. The read only memory 454 includes hard-wired data (ie, cannot be Repair (10) information), which is a hard link package The jump start firmware 454A and the research bonus 454b. The jump start firmware 45M includes - resetting her vector (making t add veeto), which causes the microprocessor 450 to perform a large degree of jump operation (扣 卯 〇 〇 ) ) 至 至 至 至 至 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快 快. · "timing state maehine" f material and block instructions. In addition, the jump start secret includes writing a static instruction code of the flash memory time register 453B, and the static instruction code is used as the system default time (eg, ^咐t face g) 'for example' from the flash memory 215 During the initial read/write instruction or during the initial read/write instruction of flash memory 34 200917017. Note, however, that the dynamic control code used to support different types of flash memory is present in the stellar side of the Quick Locator 215 to aid in the update. The different descriptor value side is also the hard code in face 454, and this descriptor value _ is used when the test host requests a special input from the device (10). When it is unable to respond to the error value, it will be said to be rejected by the test host, and it is determined that a controller failed. A more detailed description of the miscellaneous „sequence_large__(10)_ gamma zero c(four) specification. The controller 214 includes - only a large number of passes (Buik - 〇niy Qiqing. ^, b〇t) instruction decoding _ to help utilize The win command communicates with the flash memory 2ΐ5. The logical block address-physical block address (LBA, _PBA) converter/decoder side decodes the logical address generated by the calendar instruction decoder. The human/output interface circuit 4?G includes a physical layer USB transceiver 470A for transmitting and receiving different audio signals. A continuous interface engine 470B is used to execute the sequence and the Hsen is defeated (1). Parallel/serial Uparallel to serial), a data buffer is used to buffer the input/output (incoming/kiss data frame, and because the speed matching is different, so use the continuous interface engine 470B, different registers And the interrupt processing logic fox handles the protocol. Figure 8 is a simplified block diagram depicting the different address structures and partitions of the flash memory 215 after the test/formatting process (described previously) is completed. As shown in the left half, flash flash The body 215 is mainly divided into a read-only area and a read/write area. The read-only area 4G5 includes a entry point register, a bad block list (badb off (4)) 413 reserve block 414 'controls the body, mainly Boot block (10) s you B〇〇t B1〇ck) 35 200917017 416 and non-volatile register 42 As shown in the right half of Figure 8, the entry point register seems to include a control _ body entry point The address plane stores the location of the control body, the non-volatile register access point address 420A stores the location where the non-volatile register 421 has different values, and an operating system (OS) enters the address 420C. The location of the primary boot block 416 is stored. The read only memory 405 can only be updated by the manufacturing test software and cannot be changed by the general user host % system. The control 415B is executed by the microprocessor n 450 of the controller 214. (See Figure 7), and the control 415B is only read (i.e., cannot be updated by the end user). Similarly, the non-volatile register 421 stores values that can be updated during the test/format process. (eg product serial number or II) number) 'but these values cannot be accepted by the terminal The user is changed. The read/write area 406 includes a memory block for use by the end user. In one embodiment, the 'read/write area side includes a basic standard structure, so the file can be affected. The host operating system reads/writes ' and can be divided into several partitions (partitions i, 2, 3, 4). The first partition (partition 1) includes file configuration table (FAT) 1417A and rights Configuration table (fat) 2 side, a directory 418, and file cluster. According to the embodiment of the present invention, when the USB device 1 (M starts, the static control code is read from the jump start body to Fast flash memory time register. In the initial step (block 110 of FIG. 6), the controller 214 uses the flash memory 215 using the system default timing provided by the static control code, such as reading the product identification data of the flash memory 215. . The identification time of the production time is transmitted; ^ to the host system, the main age system compares the product to the storage line to identify the time parameters (or, before the initial reduction process, the operator can provide the flash memory first) The product identification of the body is given to the host system). The host system then writes the updated 36 200917017 time parameter to the controller's control to have these updated time parameters present in the flash memory time slot. - Find the touch, control _ curry, _ has updated the time parameter to write the person to format the information into the flash memory, thereby reducing the manufacturing time ^ Note, once the formatting is completed, the control selection bit ship is set to flash In the memory 215, when the device gamma is activated (4), the selection bit 415A causes the controller 214 to write from the control of the body lake dynamic control code to the flash memory time register 453B. Figure 9 is a diagram showing the presence of a dead zone in the case of a flash memory in the case of a flash memory in accordance with the embodiment of the present invention - a good memory block, a binary The G" value indicates that the bad memory block. The badly stored block data is related to the two copies of 413B' to ensure that bad block data is available even if one copy is damaged. The other two blocks (see Figure 8) are temporarily reserved for use in the future - a list of bad blocks and 413B. During the manufacturing test, the manufacturing test software controls the update of all bad blocks. According to the process defined by the control code! etiquette, if a bad block occurs during normal operation, the list of the Rylin block will be approximated. Moreover, (4) When there is another bad block found in ##, there will be another bit updated to "", so before updating the list of bad blocks with the lion, such as the new block of the mosquito, it is Yong Weng It is necessary to erase all bits 7G to 1. Therefore, the reliability of the block for storing the bad block data is higher. FIG. 10(A) is a flow chart for manufacturing a software calculation rule according to another embodiment of the present invention. The figure is used to test/format the USB-tested device (10)T). When the tester inputs all the parameters to the test host and is immediately read by the test host, the test starts (block 601). Job-Getaipto (Wei) touch the gift age (10) take _ hard description 37 200917017 descriptor value (block 602) 'then' software execution - set_descriptor command to set the correct value (correct value) and add or change descriptors, and Rather than adding or changing descriptors in the RAM registers of the controller (block 603). Then, when executing an igumti plus instruction 'software spike initial configuration value (configUrati〇n vaiue) (block 4), then Set_configuration software download A different configuration value (block 6〇5>, then the software reads an interface descriptor value, responds to a Get_interface command (block 6〇6), and then the software uses the Get-interface command to download the correct value (block 607). Download the fixed address of the device to the USB device and respond to the Set-address command of the software. When successful, a related colored flag will change in response to the connection power status (plUg-in status) (squares, then reset the device temporarily) The device register value is in response to a ciear-feature instruction (block 609), and some special features, such as remote-wakeup or endp〇int_halt capabilities, are subject to the software set-feature (block 610). The USB device can be A variety of different types, such as large storage types 'and can be subject to different types of specific instructions, such as Uke-max_lun (block 611)' to read the number of partitions supported by the software, for unformatted devices, the software will order Set the system default (default), where the system default value is based on the number of splits of the flash device. After that, use a Get_status command to check the program. Whether it succeeds (block 612). If successful, the color of each pattern on the s-type host monitor changes to indicate a successful stylized state (block 613). Figure 10(B) is another The flowchart of the manufacturing software calculation rule of the embodiment is used for calculating a USB device under test (DUT). When the dut is plugged into the test hub, which is connected in turn to the test host (for example, a normal pc), the 38 200917017 calculation process begins. Since the DUT is not tested, either the D+ or D- pin should have a 1 ohm pull up resistor connection and be recognized at full speed or low speed (block 7〇2) if the resistance value is incorrect or not connected 'colored The flag will indicate that it is a defective device and should be rejected. Once the test host PC recognizes the DUT 'test host driver a Reset command to the DUT for at least 10 seconds (block 703). If the DUT responds appropriately to the reset command and indicates Is a successful reset state 'test host is issued to the DUT using the default control endpoint (block 704). After testing the host PC, send Get_descriptor to the DUT controller hard code value to obtain The MaxPacketSize parameter (block 705), and the DUT responds by transmitting its transfer package size (block 706). The test host pc then transmits Set_Address to the DUT to assign a unique address. If the test host pc and MN All communication between the two is successful here (block 7〇7A, is the "path"), after which a short version of the mass storage drive is transmitted DUT, wait until the communication is used again (square penalty). After that, the test host sends a Get_descript〇r command to 酣, compares the device descriptor value with the system default value that has been set by the system, and any inconsistency will be reflected in the test host. The DUT rejects the DUT on the pc (block 709). If the device descriptor value is correct, the test host pc transmits a set_configuration command, sets the number of configurations (block 71〇), and writes all necessary values to the DUT. In the flash memory, the calculation is completed by this (block 711). Figure 11 is a flow chart showing the operation of the test host system for USB flashing according to another embodiment of the present invention. In part, the operator starts the test (block 801), and all the configurations and all possible _, _ notes are assigned to the program towel (block view), these rights 39 200917017 download to the program secret hard disk After the program, the program will wait for the correct person to test the correct parameters, such as 'the start of the test device (DUT) of the mosquitoes or even the actuation program. At the bottom of the block, there are two paths of age that she wants to be decoded and executed: low-order formatting (right branch under block 8Q4) and flash memory software configuration (left branch under block 804) Referring to the lower right part of Figure 11, low-level formatting involves performing a flash block on all flash memory blocks - flash / read / write field 4, because the memory may be first used by other management vendors. And generally there will be no _calculation rules to mark bad blocks, so the test take / write (R / W) mode writes have a flash memory area record (block 810A). Thereafter, each R/W mode is read and the R/w mode is compared to the desired result. Then, although the secret block has been marked as bad, it depends on all the __ blocks being erased. After that, 'only good blocks are erased to all binary bits!', during the value period, low-order formatting is performed (block 811). However, because the flash memory may be contaminated by the use of green, it may be recorded. · (4) Art loser (p eter SGan coffee seieetiQn entry) Complete scan of the bad blocks. Then 'each memory card's individual information is written to the flash memory card to update the individual memory card information. (block 812). In the embodiment, the information includes a serial number, a product id, a vendor 1]} and an LED light mode (block 817). Then the control body is written into the flash memory (block 8i3), For example, 'copy the second (four) (image) file to the flash memory (block 818). In addition, the record is in the non-volatile temporary storage of the flash memory _ body into the address. After that, the flash memory According to the customer's request, the software will load the 〇s stored in the non-volatile register into the pre-programmed pin of 200917017. After the customer requests, the initial project will be Copy to flash memory (box 815 > these files The slot that can automatically execute the image Z execution is applied to the pre-copy directory of the test host (4) (block 819). After that, the stored data is read back from the DUT and stored in the test host hard disk device. For testing and future reference (block 816). The 11th left part includes a selective procedure for updating, such as the flash time stored in the dynamic control code. Initially, some parameters are subject to change, for example, due to In the test program, I have already remembered the change of _, so it may be necessary to confirm whether the test operator password is correctly rounded, and confirm whether the updated flash time is input. However, the process of the u-th image is continuous. Used to test 丽 with the same flash device, you do not need to perform the selective process on the left side of the u-Fig 14 because the program retains the correct parameters for the test. Refer to the left part of Figure 11 for the low P white format. Pour the system (four) record (four) software domain, flash flash configuration configuration begins to check the operator's fingerprint password (box 8 (6). Flash flash card software is limited to authorized personnel (such as device manufacturers), An unauthorised person without a password will be rejected by the age and will not be able to use it. Once the correct password is confirmed, the operator will enter the instruction (box 805A). 1. The system is composed of many different suppliers. It is produced and has many different parameter settings 'because the memory capacity continues to increase from each vendor. The first step in the software configuration is to identify the specific flash memory (square surface) used for the target 'DUT. The program is sound, the order of flashing 5 recall type is pre-synthesis for elasticity purposes (block 8D7), and the user can update this order 'and for easy modification' all the update information is displayed on the device monitor On the device (block 808) 'The change is then in the deposit slot for future reference. 41 200917017 Sections 12 (Α) K and 12(8) are simplified diagrams showing the double route (_冰如(8) and single route (singIe channe 缺陷 快 flash memory wafer operation. 13th (A) _ and 13 (8) It is a block diagram depicting the configuration of the relevant Fastang memory. When there are dual numbers of flash memory chips integrated with the device, these two options can be applied: single route or dual route operation. As shown in Figure 12(1) For the dual route operation, the data bus is divided into two from the controller 214. The P knife. The shell material data [7:0] is connected to the flash memory chip group, and the data line data is connected to the flash memory. Chipset (4), in which both memories share the same controller address and control busbar 9〇. The advantage of the dual route operation as in U) is that the speed is fast. The pottery busbar becomes special (4) (A) The shortcomings shown in the figure are the bad blocks in the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ And reduce the good two groups that can be used quickly The address of the chip is also staggered in order to reflect the connection of the data bus. Connection: To the capital: two: "Line operation' Two of the memory groups 215-U and 215, 13 (8) are not 'not as the 13th ( A) _ teaches the double-track operation to lead to the situation of the younger block. According to this, the single-route operation can be expanded to erase the shortcomings of the missing m-line^ caused by the reserved purpose of the bad area. Slow, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Figure 14 shows a block diagram of the parameters stored in the different memory fields of each device. All parameters can be changed by the operator and divided into two categories: device information and groups. The device information is stored in a block (area) where each device is located in the upper area as in Figure 10, block 905 includes the maximum device capacity (e.g., 256 MB). Blocks 9〇1 & include by the device manufacturer Recording capacity Quantity (for example, a device with 25_max capacity, the effective device capacity can be set at 25_ 'The remaining 6MB is reserved for bad block management.) The block includes the flash memory part, for example, the manufacturer Part of the number is established by Samsung (Sa_g) or Infineon (such as Samsung's K9K8G〇8_'s de-cafe flash memory) box 903 includes - flash memory ID information, which is fast The flash initial command address is deleted and used for & flash-smoothing device is correct, because some flash memory has different time properties but enjoy the same-ID code. This feature is provided to facilitate the adjustment of the fast (4) in order to allow the end customer to enter the different flash speed specifications. Block 9〇4 includes the number of flash wafers that should be used in a particular device. During formatting/testing and subsequent modification of the device, blocks 905A, 905B, and 905C store different passwords for use. Since the operator password is very important for controlling the manufacturing process, and for the maintenance of the test sample f, the password modification (block 嶋) and the confirmation (square) are critical for the formal access of the MIS control test program. The configuration information of device 10B is disclosed in the block diagram below the device information of Figure 1. Block 906 includes a product line number (producti〇n line number), which is used to produce an operator ID number that controls 43 200917017 information. Block 9G7 includes pre-sweeping cat flash type information, which includes different methods of broom flash memory (erase/read/write), _ fast back block value (_back block value) (block 907A) ), a full broom value for all blocks (Box 9〇7B), - sweep the cat's good block and skip the manufacturer's female bad block tag value (square). For devices that use (iv) memory TL devices, it is recommended to sweep the cat and re-establish the bad block list (bad_block_list) (block 907B). Block 908 includes a major serial number (serial _ber, S/N), and the square face includes the initial S/N of the semaphore, with the updated face number information of the square face' and whether the serial number is generated using a preset sequence or randomly generated ( That is, the sequence number can be increased or decreased 'can also be generated by the operator's rotation (such as software call - random number generator and - seed parameter (such as host tester time / date) to ensure its randomness), the main principle is For each device according to the USB specification, the serial number f is different. Block 9 (10) includes the current specifications and limits of the device (e.g., the maximum current usage), where the device exceeds this number as an indication of device failure (e.g., 5 (10) legs are the maximum specific current listed in the device). Block _ includes the interval and brightness values of the device LEDs under different conditions, and is used to inform the operator of the operational status (eg, #Like or success or the device is idle or in use). Block 917 includes the supplier/product melon number of the correct controller for allowing the test to be performed in a variety of processes, where the county is in this scale, and initially will be rejected by the test/format system. Block 911 includes the vendor name and product context decoding resource ‘block with the product φ column name (string n successor) and version information. Block Μ Save-statistics, indicating the number of pass/fail tests for the products tested on the test product line (block 913Α is used to reset this value), block 915 includes the maximum number of test products line 200944 200917017, because the test It is initially set by a specific operator and this information is used to provide useful statistical information for the operator. Block 919 includes the maximum reserve ratio of the flash memory (i.e., the number of spare memories required for poor block configuration for future operational purposes). The block 921 includes a write protection switch (on or off), and the block 92A includes a capacity allocation number for recording that the flash memory can be allocated to a plurality of different areas during storage for data classification purposes. Block 920 stores a v〇lume label, such as D: (E:, F:, and so on). Finally, block 920 contains the leg number for each slot for each device, and this message is used to reveal an error code when the device fails during the test/format process. Since the multi-layer cell (MLC) flash memory has a larger storage density than the single-layer cell flash memory of the same size, the flash memory is becoming more and more popular. «Partial embodiments of the present invention, the techniques described above can be applied to mass production of MLC flash memory or production testing of MLC flash memory. For a more detailed reference to the above-mentioned content and U.S. Patent Application Serial No. 11/737,336, the entire disclosure of which is assigned to the same assignee. Fig. 15 is a view showing a multi-layer voltage sensing of an MLC memory unit L) according to a conventional embodiment of the present invention, and the system as shown in Fig. 15 can be used together with the above technique. A flash memory has a flash memory cell (flash array, which is set in line (and), column (four) wake up), and selects the flash memory cell array according to the row portion of the address and the column portion of the address. The address can be generated by the logger (seq job er) depending on the area address or page address placed in the flash memory chip. The third part of the address is the effective selection of the memory cell (10) bit. 45 200917017 Control Engine 1052 receives the address and selects at the selected row and column intersection

Yes, but only the bit division is shown. Referring to Figure 15, the control drives one or more flash memory units (logic) 1060, so that each is forgotten, the selected flash memory unit bit line 1058 is pulled up (puu up) ^56 first charged It is at the parent fork of the row and column of the U, and the flash memory unit 1054 has a gate voltage VG 'which is applied when the channel is opened' depending on the state of the flash memory cell deletion. Different shapes 'sorry can be programmed into flash memory unit 1 () 54, each state has a different amount of charge on the floating gate of the flash memory unit, so each state causes different sizes of channel currents. Flow through the flash memory unit 1〇54' from bit line 1〇58 to ground. The adjustable variable current flows through the flash memory unit 1054, and a pull-up current is pulled up from the pull-up 1056 to form a voltage divider. The voltage on bit line 1〇58 thus changes as it is programmed into the state in flash memory unit 1〇54. The bit line 1058 serves as an inverting input of the comparators 1030-1040, and the non-inverting input is a reference voltage to the comparators 1030-1040, which is referenced by the reference current generator 1041- Produced by 1051. The voltage generated by the reference-current generators 1041-1051 is controlled by the control engine 1052 and responsive to these reference state voltages, higher state voltages, lower state voltages for sensing the state of the four memory cells. The voltage generated by the reference voltage generators 1041-1051 is a continuous high voltage, so the bit 46 200917017 line voltage exceeds the lower reference voltage, clearing the lower state comparison (4) output, and when the bit line voltage cannot exceed the higher The reference voltage is such that the higher state reference voltage output is maintained at the original setting. The transition from the comparator 30-40 of output 0 to the position of the comparator 1〇3〇~1〇4〇 of the output 1 is the induced voltage of the bit line 1058. For example, when the comparator output 〇 is compared to the comparator output 1, comparators 1037 and 1038 undergo a 0 to 1 transition. Voltage IU2 is applied to comparator 1〇37, and voltage IR3 is applied to comparator 1038. The voltage of bit line 1038 is between IU2 and iR3 and is read as state 3 (01). The Interpretation Logic 1_ receives n comparator outputs from the comparator and detects the transition from 0 to 1. Interpreting logic 1060 produces a number of outputs, such as read data bits D1, DO' which are 2-bits for decoding the status read from the memory unit. A 4-bit MLC will have an interpretation logic that outputs four read data bits 兕, D2, D, and DO. Other outputs from the interpretation logic 1060 are useful during the staging of the memory unit. During the programming, the memory cell is slowly charged or discharged, so the voltage on the bit line 1〇58 changes. Once the required data is read from the data-read output, D〇, the work stops. However, to ensure a sufficient noise margin, the bit line voltage should be between the higher and lower state voltages, such as between VL2 and VU2, rather than the adjacent read_reference voltage. Between, for example, between VR2 and VR3. When the bit line voltage is between VR2 and VL2, start the imder-prOgram output. When the bit line voltage is between and between, start the 〇ver pr〇gram output. When the bit line voltage is between VL2 and VU3, neither under_ program output nor over-program output is started. 47 200917017 When the value of the desired material is already in place, it can also be given a round that is smaller than the scale. The bit is selected to be less than or can be supplied with the write data to the interpretation logic to allow the output to be less than or equal to the target. Mray's face can be used as a silk (truth blessing + because the reference current flows through the resistor - reference cage, so when the comparator __ is the current comparator, the reference-distribution mG41_ Cong can generate the reference current or reference voltage Figure 16 shows a programmable continuous reference generator and operational amplifier. The voltage reference generator 112D generates a higher reference voltage applied to the upper operational amplifier ιΐ6ι and the resistor thief 1101. Calibration register 1122 can be programmed to different values to adjust the highest reference voltage value produced by voltage reference generator 1120. A higher reference voltage is applied to a series of resistors 1101-1111 to form a voltage divider to ground. The resistance of each resistor 11〇1_mi can be the same size' so the voltage difference between the higher reference voltage and the ground can be divided into u equal voltage segments, resulting in 11 divided voltages. Or 'per-resistance can be There is a different programmable value to provide more voltage control. Each of the voltage dividers 1101-1111 is applied to one of the operational amplifiers 1161-1 The non-inverting input terminal (1) of 171, the output end of each operational amplifier 1161_1171 is connected with the inverting input terminal for high efficiency. The inverting output terminal is connected to the ground via a grounding resistor, and the grounding resistance of the device is 1181- 1191 has a phase _ electric thief. Each of the operational amplifiers 1161-1171 generates a -reference voltage 'which is equal to the partial pressure applied to the non-inverting input terminal. Thus, 11 reference voltages are generated, which have a higher value. The reference current corresponds to the reference current generated by the reference-voltage generator 1041_!〇51 of Fig. 15. 48 200917017 When reading the flash 垔 _ ^ ° 70 There is a data error between the powers, the reference with the bit line voltage comparison The electric J will be tried again, and the memory unit (10) will be replaced. For example, the leakage (Ieakage) °, the electric charge in the floating electrode of the unit 5& The fast flashing fresh element 1G54 channel (4) 5 figure). Therefore, the bit line is independent. The correction register 1122 can be reprogrammed to reduce the maximum reference voltage generated by the electrical age tester. The low line voltage can now fall within the correct reference value, allowing the data to be read without exceeding the maximum allowable rainbow error number. The correction register H22 can be gradually changed until the data to be read is correct. ECC bytes can be used to detect errors, so when the χ checker reports that there are few or no errors, the reference-voltage adjustment can stop and read the data. The block can be reassigned. MLC degradation during write or erase operations (-domain (8) flowchart. An error occurred during a write or erase operation, step 1 go?, during the low activity, the ECC checker flagged too many errors, then Start the downgrade process. 2 The bits-pene (1) indicator is sold from the redundant area of the block or special block, step 1204. When the § memory bit indicator is already one step per unit of caution unit 1 ' The memory unit will first be downgraded to the minimum density, and the error:: send: 兀 downgrade is unsuccessful. Step 1208, by clearing the bits in the redundant area of the block 4 Byte, marking the block For the bad block, so this block: see: (d) from the future to make _ 121 〇 'fake (b) if you want to choose another 49 200917017 a block to operate. When the block has its memory bit indicator to set each Block of 2 or more bits of a memory unit Thereafter, the level can be degraded. In step 1214, the number of bits/memory units read from the memory bit indicator of the redundant area of the block is reduced to the next lower level 'eg, 4 bits from each memory soap element ( The 4-bit/memory unit is dropped to the 3-bit (3-bit/memory unit) of each & recall unit. The size of the block may be reduced, or the arrangement of the block may be changed to match each memory unit. The number of bits reduced. For example, from 4-bit/memory unit to 3-bit/memory unit, the block size can be cut in half. After degrading, the page of the block can have half the number of logical splitters. 1216, the reduced bit/memory unit is written to the memory bit indicator to demote the block. The write or wipe operation can be re-executed on the degraded block. When the degradation process is exceeded due to a read error Subject to actuation, the block can be erased once the data has been read and reconfigured to another block.

Figure 18 shows the use of ECC bytes and reading the error by adjusting the voltage reference. Corrected Flowchart ◊ Read errors can be detected by verifying the data being read into the ECC byte. For example, a non-zero symptom from a data and an ECC byte can signal an error, and the location of the error bit and the error correction signal. In step 1220, when a read error is detected, the process is activated. Step 1222, when the number and location of errors are allowed to use the ECC byte to correct the error, then the ECC byte can be used to correct the read error, step 242. In step 1230, the data may be reconfigured in another block using the memory bit indicator to erase and selectively degrade the block. The number of correctable errors is a fixed number, such as an ECC limit or a change in error location, such as any 3 bits in a tuple, or any 4 bad bits in a string. The ECC limit can also be arbitrarily set or set to a lower correctable value, but it is still unpleasant, indicating that the block should be downgraded, even if the error is correctable. At step 1222, when the number of errors exceeds the ECC limit, the ECC mechanism cannot correct all errors and the data may be lost. Therefore, attempts are made to recover lost data by adjusting the reference voltage level compared to the bit line voltage. At step 1224, the correction register 1122 writes a new value data to cause the voltage reference generator 1120 to generate a higher reference voltage. This causes all the reference voltages to gradually increase in series. The tribute in the block is purchased using these more south reference voltages at step 1226'. After that, use the ECC byte to check if the data is wrong. At step 1228, when the number of errors is reduced below the ECC limit, increasing the reference voltage is successful. At step 1232, the ECC byte can be used to modify all remaining errors. At step 1230, the data is then relocated to other blocks. This block can be downgraded through the call downgrade process in Figure 17. When the amount of negative charge stored in the flash memory unit increases, sometimes the reference voltage system is successfully increased. Moreover, the increase in negative charge is due to memory cell disturbances resulting from reading or staging adjacent memory cells. Excessive negative charge requires a higher gate voltage to compensate, so increasing the reference voltage is effective. 51 200917017 In step 1228, when the number of errors still exceeds the ECC limit, then increasing the reference voltage will not succeed. Wherein, the reference voltage can be boosted by repeating steps 1224-1228 (not shown) several times. When the reference voltage is raised but the data cannot be recovered, the reference voltage can be lowered. In step 1234, the correction register 1122 of Fig. 16 writes the new value data to cause the voltage reference generator 1120 to generate a lower reference voltage. This causes all of the reference voltages to gradually decrease. At step 1236, the data in the block is read using these lower reference voltages. After that, use the ECC byte to check if the data is wrong. At step 1238, the reduced reference voltage is successful when the number of errors is reduced below the ECC limit. At step 1242, the ECC byte can be used to modify all remaining errors. At step 1230, the data is then relocated to other blocks. This block can be downgraded through the call downgrade process in Figure 17. When the amount of negative charge stored in the flash memory unit is reduced, the reference voltage system is sometimes lowered successfully. Moreover, leakage can cause a reduction in negative charge. The reduced negative charge causes excess channel current to flow through the selected memory cell in response to a fixed gate voltage. The excess channel current causes the bit line voltage to be lower than usual, so the reference voltage must be reduced to compensate for memory cell leakage. At step 1238, when the number of errors still exceeds the ECC limit, then lowering the reference voltage will not succeed. Here, the reference voltage can be lowered by repeating steps 1234-1238 (not shown) several times. However, when the number of data errors did not fall below the ECC limit, the data was lost. At step 1240, a signal is sent that cannot respond to the error 52 200917017 error. More detailed information on the above process can be found in conjunction with U.S. Patent Application Serial No. 11/737,336. According to some embodiments, the MLC flash memory can be used on a USB device with a dual USB plug to support multiple communication interfaces, that is, duality. 19A-19C are perspective views showing a USB expansion plug having multiple properties in accordance with an embodiment of the present invention. Referring to Fig. 19A, the USB expansion plug is shown in the full figure 1301 and the exploded view 1302. In one embodiment, the USB expansion plug 1300 includes a housing or housing 1303 and a USB connector substrate 1304, wherein the USB connector substrate 1304 can be inserted into the housing 1303, and the housing 1303 is made of metal, that is, metal. case. The connector substrate 1304 includes a first terminal and a second terminal, wherein the first terminal has a plurality of metal fingers or tabs 1305, and the second terminal includes a plurality of electronic contact pins 13A. In a particular embodiment, pin 1307 has nine pins. The connector substrate 1304 further includes one or more springs 1306 for providing pressure to the other USB connector to make substantial contact with the contact fingers 13A5 when other USB connectors are inserted into the opening of the USB expansion plug. In one embodiment, the contact fingers 13〇5 can be positioned on one of the upper surfaces of the connector substrate 13〇4, and other contact fingers (not shown) can be positioned on a lower surface of the connector substrate 1304. For example, the contact finger 13〇5 conforms to the standard USB specification, and the other contact fingers 5 are counted to match other interfaces, such as the PCI Express or IEEE 1349 specification interface. Therefore, the USB expansion plug 1300 can be used for a plurality of different communication interfaces, that is, duality. A more detailed information on the dual-purpose USB expansion plug can be found in the above-mentioned application or patent, for example, U.S. Patent No. 7,021,971 and U.S. Patent Application Serial No. 11/864,696, which are incorporated herein by reference. . Referring now to Figure 19B, the USB expansion plug 13A can be connected to the PCBA, wherein the PCBA has a memory device and a memory controller for controlling the memory device. The top view of Fig. 19B, the side view 13〇9, and the lower plan view 1310 are connected to the PCB substrate 1311, for example, by soldering the pins 1307 on the PCB substrate 1311. In addition, a memory device such as a flash memory device can be placed on one surface of the PCB substrate 1311, and a memory controller such as a flash controller is located on other surfaces. In this example, the memory device 315 is positioned on the bottom surface 1313 of the PCB substrate 1311, and the memory controller 1314 is positioned on the upper surface 1312 of the PCB substrate 1311. In one embodiment, the memory device 1315 can be an MLC compatible memory, and the memory controller 1314 can be an MLC compatible memory control ic. According to another embodiment, the technique described in the 19A-19B diagram can also be applied to a flash memory and a flash controller integrated in a single package, such as the chip on board shown in FIG. 19C. , COB) package. Referring to FIG. 19C, a (3) beta package 1316 can be an MLC package that can be positioned on the upper surface 1312 of the pcb substrate 1311, wherein the COB package 1316 can be contacted by one or more contacts on the surface of the c〇B package 1316. (contact finger) 1317 connection (eg soldering). 20A and 20B are perspective views showing a USB expansion plug having multiple properties in accordance with an embodiment of the present invention. Referring to Fig. 20A, the USB extension plug is shown in 54 200917017 70 full picture 1401 and exploded view 1402. In one embodiment, the USB expansion plug 1400 includes a housing or housing 1403 and a USB connector substrate 1404, wherein the USB connector substrate 1404 can be inserted into the housing 14〇3, and the housing 14〇3 is made of metal. It is also a metal body. The connector substrate 14A4 includes a first terminal and a second terminal, wherein the first terminal has a plurality of electronic contact fingers or tabs, and the second terminal includes a plurality of electronic contact pins 14A. In a particular embodiment, pin 14A has a first column and a second column, wherein the first column has five pins and the second column has four pins. The connector substrate 14A4 further includes one or more springs for providing pressure to the other USB connector to make substantial contact with the contact fingers 14A5 when the other USB connector is inserted into the opening of the USB expansion plug. In an embodiment, similar to the USB expansion plug 1300, the contact fingers 14〇5 can be positioned on the immediate upper surface of the connector substrate, and other contact fingers (not shown) can be placed under one of the connection benefit substrates 14〇4. On the surface. For example, the contact finger just matches the standard USB specification, and the other contacts can be designed to match other interfaces, such as Express or! EEE 1349 interface specification. Therefore, the USB expansion plug μ (10) can be used for a plurality of different communication interfaces, that is, duality. Referring now to Figure 20B, the USB expansion plug 14A can be connected to a pCBA, wherein the PC BA has a -memory device and a memory controller for controlling the memory device. As shown in the top view of Fig. 20B, the top view of the side view 14〇9' is shown in the top view. The expansion plug is just connected to the (10) substrate, for example, by soldering the pin 1407 on the PCB substrate. As in the example shown in side view 14〇9, pin 55 200917017 pin 1407 is on the PCB substrate. As in the example shown in side view 1409, the first row of pins 1407 can be soldered to one of the upper surfaces of the PCB substrate and the second row can be soldered to one of the lower surfaces of the PCB substrate and vice versa. In addition, a memory device, such as a flash memory device, can be placed on one surface of a PCB substrate, and a memory controller such as a flash controller can be placed on other surfaces of the PCB substrate. In this example, similar to the 19th (A)-19(B) diagram, a memory device is positioned on the bottom surface of the pcB substrate, and the memory controller is positioned on the upper surface of the PCB substrate. Moreover, the memory device can be an MLC compatible memory, and the memory controller can be a compatible memory control 1C. Similarly, according to still another embodiment, the technique described in the second 〇(A)_2〇(B) diagram can also be applied to a flash memory and a flash controller system integrated in a single package, such as the 20th ( C) The C0B package shown in the figure. Other forms of packaging are also available. 21(A)-21(I) shows an embodiment of a USB expansion connector and a socket having a metal contact pin, wherein the metal contact pin is tied to the upper surface and the lower surface of the pin substrate. The embodiment shown in Figures 21(a)-21(I) can be connected to any of the foregoing embodiments. Referring to Figure 2i (A), the expansion connector has a plastic housing. The holder 6 is held by the user when the user inserts the II plug into the slot. The pin substrate 21 is provided with four metal contact pins 2188 on the upper surface thereof, and the towel substrate 2nQ is an insulating material such as Tauman, (4) or other materials. Metal leads or wires may be passed through the pin substrate 217G to connect the metal contact pins 2188 to the wires in the plastic housing UK for connecting the peripheral devices. 56 200917017 Five back metal contact pins 2172 are fastened to the bottom of the pin substrate and near the end of the connector plug. The back metal contact pin 2172 is an additional pin for extending the signal 'such as the PCI E ess signal. A metal (4) or wire may be passed through the pin substrate 2170 to connect the metal contact pin 2172 to the wire in the plastic housing 2176 for connecting the peripheral device. In some embodiments, the metal cover 2173 is a rectangular tube that surrounds the pin substrate 217. And having an open end. One is on the pin substrate 217. The opening in the bottom metal cover 2173 allows the back metal contact pin 2172 to be exposed. Figure 21(8) shows a USB extension with four metal contact pins on the upper surface of the pin substrate. Five metal contact pins are located on the lower surface of the pin substrate. The contact substrate 2184 has four metal contact pins 2186 formed on the bottom surface of the __, the bottom surface facing the groove for the pin substrate 2m of the connector to be inserted. The pin substrate (10) also has a lower substrate extension (10) having a _L shaped pin substrate which is not found in conventional USB slots. The five metal contact pins 218G are positioned at the lower substrate extension (10) adjacent the open end of the recess. —Bumps or springs can be formed on the metal contact pins. For example, by means of (four) folded flat metal pins, one bump material (four) contact pin contacts the back (four) metal contact pins 2172, which are connected to each other (4) The pin substrate 2170. The recess is formed by the bottom surface of the interposer substrate, the upper surface of the lower pin substrate 2185, and the back surface of the pin substrate 2184 connected to the lower substrate extension 2185. 57 200917017 Metal cover body 2178 is a metal pipe body, covering the foot substrate 2184 and the lower substrate. The metal cover body 2173 of the P 185 USB connector is filled on the metal cover body 2175 and the pin substrate 2184 on the side and the side. The gap between them. A mounting pin (m〇untingpin) 2182 can be formed on the metal cover 2178 to mount the USB slot to the PCB or chassis. Figure 21(C) shows the bottom surface of the pin substrate 2184 with the metal contact pins 2186 positioned thereon. The four pins are provided with different signals, power, and ground of the conventional USB, and are in contact with the metal contact pins 2188 of the USB connector located on the upper surface of the pin substrate 2170, as shown in Fig. 21(D). The USB contactor has five back metal contact pins 2172 on the bottom surface of the pin substrate 2170, as shown in Fig. 21(D). These pins 2172 are in contact with the expanded metal contact pins 2180 and are arranged on the lower substrate extension 2185 as shown in Fig. 21(C). These five expansion pins have an extended signal, such as a pCI Express signal. Figure 21(E) shows the USB connector plug with 9 pins plugged into the USB slot of 9 chats. When fully inserted, the end of the contact substrate 2170 is mounted between the pin substrate 2184 and the lower substrate extension 2185 of the USB slot. On the upper surface of the pin substrate 2170 of the connector, the metal contact pins 2188 are in contact with the four metal contact pins 2186 of the socket pin substrate 2184. The back metal contact pins 2172 located on the bottom surface of the pin substrate 2Π are in contact with the extended metal contact pins 2810 on the upper surface of the lower substrate extension 2185. Because the back metal contact pin 2172 is recessed and does not come into contact with the 58 200917017 metal cover 2138 of the conventional USB slot. The 21st 11135-± brother ZUF) shows the schematic diagram of the connector of the standard 4-pin connector and the expanded 9 before the USB slot is inserted. When fully inserted, as shown in Fig. 21 (8), the end of the connector interposer substrate 2134 is inserted below the slot contact substrate 2134. At the upper surface of the connector pin substrate 2134, the metal contact pins 2132 are in contact with the four metal contact pins 2186 of the socket pin substrate 2184. Since the standard 4-pin USB connector has only four pins 2132', the contact pins on the upper surface of the socket pin substrate 2185 are not in electrical contact with the _ connector. The 22(A)-22(I) diagram shows a schematic view of a second embodiment of the USB connector and the socket having one of the metal contact pins on the surface of the contact substrate. Figure 22(a) shows an extended 9-pin USB connector plug with four metal pins and five extended metal pins on the upper surface of the pin substrate. In Fig. 22(A), the connector has a plastic housing 2196 for the user to hold when inserting the connector plug into the slot. The pin substrate 2190 is provided with metal contact pins 220 〇, 22 〇 1 on its upper surface ‘where the substrate 219 〇 V is an insulating material such as ceramic, plastic or other material. A metal lead or wire may be passed through the pin substrate 2190 to connect the metal contact pins 2200, 2201 to the wires in the plastic housing 2196 for connecting the peripheral devices. The length of the pin substrate 2190 is longer than the length L2 of the pin substrate 2134. The increased length can be 2-5 mm. The end metal pin 22〇1 is mostly in the L-extension region exceeding l2. The metal cover 2193 is a rectangular tube body that surrounds the pin substrate 2190 and has an open end. 59 200917017 Figure 22(B) shows an expansion slot with four metal contact pins and five expansion metal contact pins on one of the surface of the pin substrate. The pin substrate 2204 has metal contact pins 2206, 2207 formed on a surface facing the recess for insertion of the pin substrate 2190 of the connector. The pin substrate 2204 does not require a lower substrate extension of the 21st (B) diagram, but may have an L shape as shown. The metal cover 2198 is a metal tube that covers the pin substrate 22〇4 and has an opening located below. The metal cover 2193 of the USB connector is inserted into the gap between the metal cover 2198 and the upper side and the side of the pin substrate 2204. Mounting pins 22A2 may be formed on the metal cover 2198 to mount the USB extension slot to the PCB or chassis. Figure 22(C) shows the insertion of a 9-pin USB connector plug into the 9-pin slot. The metal contact pins 22A and 2206 formed on the bottom surface of the pin substrate 2204 of the socket are in contact with the metal pins 2201 and 2202 of the pin substrate 2190, respectively. Fig. 22(D) shows the bottom surface of the socket pin substrate 22〇4 on which the metal contact pins 2206, 2207 are placed. The main metal contact pins are (10) tied to the five pins in the first row, the most sinful near the slot opening. The secondary metal contact pins 22A7 are attached to the four pins of the second row. The metal contact pin 2207, which is the farthest from the slot opening, includes four USB pins. The primary metal contact pins 2206 include expansion pins for supporting other interface specifications, such as PCI-Express. When the USB connector is fully inserted into the USB slot, the end of the pin substrate 2i9 is inserted into the recess below the contact substrate of the button. At the upper surface of the connector pin substrate (10), the metal contact pin 2200 contacts the six main 200917017 metal contact pins 2206 of the socket pin substrate 22〇4, and the metal at the end of the upper surface of the pin substrate 2190 Contact pin 2201 is in contact with secondary expanded metal contact pin 2207 located on the lower surface of pin substrate 2204. Figure 22(F) shows a schematic of an extended 9-pin connector before it is inserted into a standard 4-pin USB slot. When fully inserted, as shown in Fig. 22(G), the end of the pin substrate 2190 is inserted below the socket pin substrate 2142. On the upper surface of the connector pin board 2190, the first, third, fourth ' - sixth of the end metal contact pins 2201 are in contact with the four USB metal contact pins 2144 of the socket pin substrate 2142. The metal pins 2200 of the last row on the upper surface of the pin substrate 2190 are not in contact with the socket metal cover 2138 or any of the metal contact pins because they are located too far behind the connector pin substrate 2190. Therefore, only four standard usb pins (metal contact pins 2144, 2201) can be electrically contacted. Figure 22(H) shows a schematic diagram of a standard 4-pin USB connector in front of an extended 9-pin USB slot. When fully inserted, as shown in Fig. 22, the end of the connector U pin substrate 2134 is inserted below the socket pin substrate 2204. The metal contact pins 2132 on the upper surface of the connector pin substrate 2134 are in contact with the first, third, fourth, and sixth main metal contact pins 22〇6 of the socket pin substrate 22〇4. . The secondary metal contact pins 2207 on the substrate 2204 are not in contact with the contactor metal cover 2133 because the depth of the expanded USB slot is greater than the length of the prior art uSB connector. Therefore, only four standard USB pins (metal contact pins 2132, 22〇6) can be electrically contacted. As shown in Figure 22(F)-22(I), the extended 9-pin usb connection 61 200917017 plug, slot and standard 4 pin USB socket, USB connector plug electrical connection and mechanical aspects Match. Although the present invention has been described in terms of certain embodiments, it will be apparent to those skilled in the art that It should still be covered by the patent of the present invention. For example, the systems and methods described herein are specific to USB devices, but the spirit and method of the present invention are used to cover different interface sink types, and may include one or more PCI Express 'SD (Secure Digital)' MSs. (Memory Stick), CF (Compact Flash), IDE and SATA. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1(A) is a block diagram showing an electronic data flash card and a host system in accordance with an embodiment of the present invention. Fig. 1(B) is a block diagram showing an electronic data flash card and a host system in accordance with another embodiment of the present invention. Fig. 1(C) is a block diagram showing an electronic data flash card and a host system according to another embodiment of the present invention. Fig. 1(D) is a block diagram showing an electronic data flash card and a host system according to another embodiment of the present invention. 2 is a flow chart showing a method of high capacity manufacturing of a USB device in accordance with an embodiment of the present invention. Fig. 3(A) is a view showing a panel for displaying a surface mount technology according to an embodiment of the present invention. Fig. 0 62 200917017 Fig. 3(8) is a plan view showing the plane of the printed circuit board device separated from the panel of Fig. 3(A). Fig. 3(C) is a plan view showing the printed circuit board device of Fig. 3(8) after the package of the present invention. Figures 4(4) and 4(8) are simplified perspective views showing the test host used in accordance with another embodiment of the present invention. Figures 5(A) and 5(B) are simplified flow diagrams showing conventional and innovative test and format foot devices, respectively. Figure 6 is a flow diagram showing a simplified method of displaying which device to test and format in accordance with an embodiment of the present invention. The 6(A), 6(B), 6(C), 6(D), and 6(E) diagrams are flowcharts, further showing the 6th graph test and formatting method. Figure 7 is a schematic diagram showing the generated coffee maker in accordance with an embodiment of the present invention. Figure 8 is a simplified block diagram showing the different address structures and divisions of a flash memory device for use in a guest device in accordance with an embodiment of the present invention. Figure 9 is a diagram showing the structure of a bad block list of a flash memory device stored in a coffee maker in accordance with an embodiment of the present invention. Figure 10(A) is a flow chart showing the manufacturing software for performing a test or formatting process in accordance with another embodiment of the present invention. Fig. 10(B) is a flow chart showing the manufacturing software for performing the calculation of the device according to another embodiment of the present invention. 63 200917017 FIG. 11 is a flow chart showing the entire operation of the USB device in accordance with an embodiment of the present invention. Sections 12(A) and 12(B) are simplified flow diagrams showing the operation of a dual-line and single-route defective flash wafer, respectively, in accordance with another embodiment of the present invention. The 13th (4) and _ diagrams are block diagrams depicting the flash memory configuration for the dual- and single-route defect flash wafer operations of Figures 12(4) and 12(8), respectively. The diagram is a block diagram showing information stored in different memory regions of each device in accordance with an embodiment of the present invention. Figure 15 is a diagram showing the voltage sensing of a memory single (four) multi-layer cell in accordance with an embodiment of the present invention. Figure 16 is a diagram showing a programmable series of reference generators and comparators in accordance with an embodiment of the present invention. The figure is a flowchart for degrading a write or erase operation in accordance with an embodiment of the present invention. Figure 18 is a flow diagram for reading error correction using ECC bytes and adjusting the reference voltage in accordance with an embodiment of the present invention. 19(A) 19(C) is a block diagram showing the structure of the apparatus according to the embodiment of the present invention. The '〇(A) 20(C) diagram is a block diagram showing which device structure is extended in accordance with an embodiment of the present invention. 21(A)-21(G) is a schematic view showing the structure of the expansion connector 64 200917017 and the slot according to the embodiment of the present invention. 22(A)-22(I) is a schematic view showing the structure of a display and a socket according to an embodiment of the present invention. ΜConnector [Main component symbol description] 1 card body 2 processing unit 3 flash memory device 4 fingerprint sensor 5 input / output interface circuit 6 display unit 7 power supply 8 functional button group 9 computer 10 electronic data flash card 13 interface bus 2 Α processing unit 3A flash memory device 4 Α fingerprint sensor 5A input / output interface circuit 2 Β processing unit 3B flash memory device 5 Β input / output interface circuit 6B display unit 8 Β functional button group 9B computer 22 Power conditioner 23 reset circuit 10 Β USB device 201 monitor 202 test host 203 USB slot 204 composite card reader 205 probe fixture 206 probe 2 0 7 SMT probe test host 208 collection cable 211 panel 212 PCB shock 65 200917017 214 flash card controller 215 flash memory device 215-1 flash memory chip set 215-1A flash memory chip set 215-1B flash memory chip set 215-2 flash memory chip set 217 USB pin 413 bad block data 415A control select bit 415B control firmware 420 entry point register 421 non-volatile register 450 microprocessor 451 control end point register 4 52 address decoder 453 static ROM 453A RAM buffer 453B fast flash fetch time register 454 read only memory 454A jump start firmware 454B descriptor 456 only large transfer instruction decoder 470 input / output interface circuit 470A physical layer USB Transceiver 470B Continuous Interface Engine 470C Data Buffer 9 4 Good Block 95 Raw Bad Block 96 Generates Bad Block 97 Prepared Area 1030-1040 Comparator 1041-1051 Reference - Current Generator 1052 Control Engine 1054 Flash Memory Unit 1056 bit line 1060 interpretation logic 1101-1111 resistor 1181-1191 grounding resistor 1161-1171 amplifier 66 200917017 1120 voltage reference generator 1122 calibration register 1300 USB expansion plug 1303 housing 1304 USB connector substrate 1305 metal finger 1306 spring 1307 contact pin 1311 PCB substrate 1312 upper surface 1313 bottom surface 1314 memory controller 1315 memory device 1316 on-board chip package 1317 contact finger 1400 USB expansion plug 1403 housing 1404 USB connector substrate 1405 contact finger 1406 spring 1407 contact Pin 2132 contact pin 2134 pin substrate 2138 metal cover 2170 Substrate 2172 contact pin 2173 metal cover 2176 plastic case 2178 metal cover 2180 contact pin 2184 pin substrate 2185 substrate extension 2186 contact pin 2188 contact pin 2190 pin substrate 2193 metal cover 2196 plastic case 2198 Metal cover 2200, 2201, 2202 contact pin 67 200917017 2204 pin substrate 2206, 2207 contact pin

Claims (1)

200917017 X. Application for Patent Park: 1. A method for formatting/testing a universal serial bus () device, which utilizes a test host containing a computing system, the method comprising: transferring a complex number to a paste test host Each of the (four) devices includes a controller and one or more flash memory devices, wherein each of the devices includes an extended lake connector plug furnace-printed circuit board device for receiving an on-board chip (chip 〇 n board, C0B)' has one or more flash memory devices and a flash controller, wherein the expansion USB connector plug comprises: an expansion pin substrate 'having an extended length, which is greater than or equal to a standard USB The standard length of the pin substrate of the connector plug; the standard metal contact pin of the plurality of plugs is located on the pin substrate, and the standard pin substrate of the extended USB connector plug is inserted into one of the slots of the standard USB slot 'Standard metal contact pins are in substantial electrical contact with the standard metal contact pins of the plugs; and a plurality of plug expansion metal contact pins are located on the expansion pin substrate, the extended USB connection The expansion pin substrate of the plug is inserted into one of the recesses of the expansion USB slot. 'The plug expansion metal contact pin located on the expansion pin substrate is in contact with the slot expansion metal located on the expansion USB slot. The pin is substantially in electrical contact; reading at least one controller endpoint descriptor value from each of the USB devices, verifying that the controller endpoint descriptor value of each of the USB devices is a descriptor stored in the test host Value matching; and formatting/testing each of the USB devices having a valid endpoint descriptor value, 69 200917017 by writing the predetermined data into the flash memory device in a pipeline manner, and then from the flash a The predetermined data is read in the memory device, and the predetermined data to be read is compared with a known good data value existing in the test host. 2. The method of formatting/testing a universal serial bus device according to claim 1 of the patent application, further comprising installing a USB driver to the test host to indicate that the computer system blocks the standard once the USB device is detected. USB registration process. 3. The method of formatting/testing a universal serial busbar device as described in claim 1, further comprising fabricating the USB devices to connect the USB devices to a panel. 4. The method of formatting/testing a universal serial bus device as described in claim 3, wherein the USB device is further singulated to the panel before being connected to the panel. 5. The method of formatting/testing a universal serial busbar device as described in claim 4, wherein the step of coupling all of the USB devices to the panel comprises inserting each of the devices into a The card reader is connected to the test host, and the card reader is connected to the test host by a -_a serial bus transmission cable (USB cable). ν ; 6 · 彳 彳 第 第 第 第 第 第 第 第 第 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化 格式化7. The method for formatting/testing a universal serial busbar device according to item 6 of the scope of the patent application of the SN patent, wherein, in the step of connecting all the USB devices to the panel, the installation includes a probe fixture (pr Futurebe future) On the panel, the pins of each of the (four) devices are brought into contact by the corresponding probes of the probe. 8. If you apply for the method of formatting/testing the ordering of the full-time 丨 丨 , 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 读取 读取 读取 读取The endpoint descriptor value is less than one configuration descriptor value, a large storage category code value, and a value of 0. 9. The method of formatting the _通_汇流_ as described in the patent application _1, including the display-phase A corresponding colored flag is placed on the monitor of the host to verify that the controller endpoint descriptor value present in each of the devices is matched to the stored descriptor value. A method of formatting/testing a universal serial bus device as described in claim i of the patent application, wherein in the formatting/testing step, the scanning includes the presence of defective block data of the flash memory device. And verify that the reserve storage capacity of each flash memory device is equal to a fixed size. , the method of applying the special (4) 1 format to the job queue, wherein the formatting/testing step includes writing a copy of at least two bad area data to the flash memory device. In the predetermined block, the bad area data identifies the bad block on the flash memory device. 12. The method of formatting/provisioning a shipboard device according to Item 1, wherein the flash memory device comprises a plurality of non-volatile memory units, which may be a one-hour unit (Single level cell, SLC) type or a multi-layer unit (Mc-ieveI) ("MLC) type). The method of formatting/testing a universal serial busbar device as described in claim 12, wherein A single layer unit type memory unit includes at least one cell block single layer unit (Small Block SLC), a large block single layer unit (Large Block SLC) or both 71 200917017 combined with 'and the multi-cell unit type memory unit includes Cell block multi-level cell (Smal丨B1〇ck MLC) and large block multi-level cell (Large Block MIX). 14. The method of formatting/testing a universal serial bus device according to claim 13, wherein the cell block includes 512+16 bytes per page, and the large block includes 2048+64 bits per page. A group in which a 16-byte of the cell block corresponds to a 64-byte of a large block. 15. The method of formatting/testing a universal serial bus device according to claim 14, wherein the data writing speed of the large block is greater than a corresponding one of the corresponding blocks due to a difference in page size Four times faster. 16. The method of formatting/testing a universal serial bus device as set forth in claim 15 wherein the multi-unit memory unit has a data write time four times greater than a single-layer unit memory unit. 17. The method of formatting/testing a universal serial bus device as claimed in claim 12, wherein the single-layer cell memory unit comprises a memory cell of each page type, and a memory cell of 4 cells per page type memory cell. . ' 18. If you apply for a patent range! The method of formatting/testing a universal serial bus arrangement, wherein the test/formatting comprises writing at least a control code data and activation code data into a predetermined block of the shutter memory device. 19. The method of formatting/testing a universal serial bus device according to claim 18, wherein the step of writing to the flash memory device comprises transmitting a predetermined number of times from the test host to - the -USB a first-buffer of the device, wherein the first device writes the predetermined data from the first buffer to the flash memory device of the first USB device, and the test master pays the pre-72 200917017 The data is forwarded to a second buffer of one of the second USB devices. 20. The method of formatting/testing a universal serial bus device according to claim 1, wherein the five-dimensional continuous test/formatting process comprises writing data provided by the user to the flash memory device. In the predetermined block. 21. The method of formatting/testing a universal serial bus device as described in claim 1, wherein the continuous test/formatting process includes writing an update sequence number, a time code, and a product version blocking value to the flash A predetermined write-protect portion of the memory device. 73