708twf.doc/p 200916923 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晝素陣列結構及其製造方法，且 特別是有關於一種具有高顯示開口率的晝素陣列結構及其 製造方法。 【先前技術】 由於顯示器的需求與日遽增，加上近年來綠色環保概 念的興起，具有高晝質、空間利用效率佳、低消耗功率、 無幸S射專優越特性之薄膜電晶體液晶顯示器（thin film transistor liquid crystal display，TFT-LCD)已逐漸成為顯示 器市場之主流。為了滿足使用者的需求，薄膜電晶體液晶 顯示器的性能不斷朝向高對比(high contrast ratio)、無灰階 反轉(no gray scale inversion)、色偏小(littie c〇i〇r shift)、亮 度高(high luminance)、高色彩豐富度、高色飽和度、快速 反應、顯示晝面穩定與廣視角等特性發展。 般而&，薄膜電晶體液晶顯示器主要由分別配置有 晝素陣列與彩色濾鱗㈣兩基板以及配置於此兩基板間 的^晶層所組成1繪示為習知之晝素陣列結構的局部 不思圖。晝素陣列結構1〇〇包括多條掃描、線搬、多條資 ^線ι〇4以及與這些掃描線1〇2、資料線1〇4電性連接的 :^::、°構110。掃描線1〇2與資料線104相交而圍成 僅緣示—個)，且晝素結構ιι〇配置於 m、: |素結構⑽包括絲元件112與書素電極 ⑽主動元件U2電性連接其中一條掃描線1〇2與其t 200916923 7〇8twf.doc/p 條資料線104,而晝素電極u 另外，晝素陣列結構1〇〇 電性連接主動元件112。 其與晝素電極114構成儲存^有轉電容下電極120 ’ 影像之穩定。這些儲存電容^令以維持晝素結構110顯示 屬線所組成，而可能影響極120大多由大面積的金 此，儲存電容下電極配的顯示開口率。因 實際上，儲存電容下 '二素區p周邊。 相同膜層製作，所以般會與掃描線102以 間必須维持足约_5=2^20與掃描線如之 ，光源的發光效能以維必； 無法有效地節省能源的耗費。為了維“ 素構11G齡晝面的穩定性又要能夠兼顧良好的顯上 口“，甚至進一步降低能源的耗費，必須金二 列結構100進行改良。 I素陣 【發明内容】 本發明是提供一種晝素陣列結構，以提昇晝素 構的顯示開口率。 、、'σ 本發明另提供一種晝素陣列結構的製造方法，以提高 晝素陣列結構的製程良率並使畫素陣列結構具有高顯示= H7 :夸 〇 本發明提出一種畫素陣列、结構，包括多條掃描線、多 200916923 7〇8twf.doc/p ^料線以及多個晝素結構 ΪΪ辛性連接所對應的== 容。儲錢訂電触健存電 重4以構成健存電容。错存;==與畫素電極部分 至少一楚一# m 仔冤谷下電極包括鄰近資料線的 線段與第= :為不嶋而第二線段與鄰近之=鄰 列步= = = =:製造方法’包括下 ΠΠΓ描線與多個第， 一閑絕緣層ΐπ：=τ接著，於基板上依序形成 =安然後’移除部份閘絕緣層以及部份半導體二=屬 圖案化半導體相及多個翻t ^ 7成 $成-弟-金屬層。第二金屬層包括鄰近 = -線段、鄰近第-線段之多條資料線、連接資 二極以及多個汲極。資料線與掃描線相交多： =第一線段以形成多個儲存電容下電極 下電極位於晝素區周邊。 、省存电合 200916923 708twf.d〇c/p 本發明採用不同膜層製作 段，並且儲存電容下電極的各谷鄰下=的不同線 的情形。換言之，與鄰近的線路發生短路 有較高的良率。另外，本;及其製造方法具 防止短路的發生而使儲存電陣列結構中不需為了 維持較大的距離%極與赫近導體線路間 的顯示開口率。斤M本發明之晝素陣列結構具有較高 為讓树日狀均和其他目的、雜和優 明如下y文鱗健實施例，並配合所關式^詳細說 【實施方式】 請參叙示意圖。 ;，《及多個====:多條 204相交，並圍出多個佥抑p /描線2G2與貧料線 晝素區p中。各個書二二1Q = 素結構21G則配置於 電拖2U以及儲存G包括主動元件212、畫素 及資料線204電性^12與對應的掃描線202 件212。 叫接’而晝素電極214電性連接主動元 當晝素結構训j r部分重疊以構成錯存電容。 進仃顯示時，儲存電容有助於維持晝素電 8 200916923 708twf.doc/p 極以4的顯示電屢n顯量 顯示态所顯示的影像較為穩定，也就s⑤、σ構200的液晶 生殘影或是閃燦的現象。然而，影像甲不會發 透光的金屬材質製成，所以儲存電容下電極216由不 能會影響晝素結構2i〇的顯㈣二電麵216的配置可 本發明在此提出以不同膜層^段製作上述問題， 216会使得儲存電容下電極抓與鄰近的線路t電容下電極 現象。如此-來，可縮短儲存電容下^不易發生短路 路間的距離以提高顯示開口率，二^ 與鄰近的線 構200的製程良率。 乂提焉晝素陣列結 具體來說，f赫電容τ電極 與第二線段216Β。第—線段216α段2麻 同膜層所組成。第一線段216近細由不 楚—括。Ί W近貝料線2〇4 gp署，品 弟-射又216B鄰近掃描線2〇2配置。 ，置而708 twf.doc/p 200916923 IX. Description of the Invention: [Technical Field] The present invention relates to a halogen array structure and a method of fabricating the same, and more particularly to a halogen array structure having a high display aperture ratio and Its manufacturing method. [Prior Art] Due to the increasing demand for displays and the rise of the concept of green environmental protection in recent years, thin-film transistor liquid crystal displays with high quality, good space utilization efficiency, low power consumption, and unfortunate S-special characteristics (Thin film transistor liquid crystal display, TFT-LCD) has gradually become the mainstream of the display market. In order to meet the needs of users, the performance of thin film transistor liquid crystal displays is constantly facing high contrast ratio, no gray scale inversion, littie c〇i〇r shift, brightness. Features such as high luminance, high color richness, high color saturation, fast response, stable kneading surface and wide viewing angle. Generally, a thin film transistor liquid crystal display is mainly composed of a substrate composed of a halogen element array and a color filter scale (4), and a crystal layer disposed between the two substrates, and is shown as a part of a conventional halogen matrix structure. Do not think about it. The pixel array structure 1 includes a plurality of scans, line shifts, a plurality of lines ι〇4, and a ^::, ° structure 110 electrically connected to the scan lines 1 and 2 and the data lines 1〇4. The scanning line 1〇2 intersects with the data line 104 and is surrounded by only the edge, and the halogen structure ιι〇 is disposed at m, and the element structure (10) includes the wire element 112 electrically connected to the active element U2 of the pixel electrode (10). One of the scanning lines 1〇2 and its t 200916923 7〇8twf.doc/p data lines 104, and the halogen element u, in addition, the halogen array structure 1 is electrically connected to the active element 112. It is stable with the halogen electrode 114 to store the image of the lower electrode 120'. These storage capacitors are configured to maintain the display line of the halogen structure 110, and may affect the majority of the poles 120 by a large area of gold, and the display capacitors have a display aperture ratio. Because in fact, the storage capacitor is under the 'different area p'. The same film layer is formed, so that it is necessary to maintain a sufficient distance of about _5=2^20 and the scanning line between the scanning lines 102, and the light-emitting efficiency of the light source is indispensable; the energy consumption cannot be effectively saved. In order to maintain the stability of the 11G-old surface, it is necessary to take into account the good visibility. Even if the energy consumption is further reduced, the gold two-column structure 100 must be improved. I. Array of the Invention The present invention provides a halogen array structure for improving the display aperture ratio of a halogen structure. The invention further provides a method for fabricating a halogen matrix structure, which improves the process yield of the pixel array structure and has a high display of the pixel array structure = H7: The present invention proposes a pixel array and structure. It includes multiple scan lines, multiple 200916923 7〇8twf.doc/p^feed lines, and == capacitance corresponding to multiple prime structures. The money storage subscription power saves the weight 4 to form the storage capacitor.错存; == at least one of the pixel parts of the pixel electrode. The m electrode of the lower valley includes the line segment adjacent to the data line and the =: is not the second line segment and the adjacent line = adjacent column step == = =: The manufacturing method includes a lower drawing line and a plurality of first, a dummy insulating layer ΐ π:= τ, then sequentially formed on the substrate = amp then removes part of the gate insulating layer and a part of the semiconductor NAND patterned semiconductor phase And multiple turns t ^ 7 into $ into - brother - metal layer. The second metal layer includes a plurality of data lines adjacent to the - - line segment, adjacent to the first line segment, a connection pole, and a plurality of drains. The data line intersects the scan line: = the first line segment forms a plurality of storage capacitors. The lower electrode is located around the halogen region. Saving and storing electricity 200916923 708twf.d〇c/p The present invention uses different film layers to form segments, and stores the different lines of the lower electrodes of the lower electrodes of the capacitors. In other words, short-circuiting with adjacent lines has a higher yield. Further, the present invention and the method of manufacturing the same prevent the occurrence of a short circuit so that the storage aperture ratio between the % pole and the Hertz conductor line is not required to be maintained in the storage array structure.斤M The invention has a higher alizanic array structure for the purpose of letting the tree shape and other purposes, impurities and advantages as follows. . ;, and multiple ====: multiple 204 intersect, and enclose multiple deficient p / trace 2G2 and poor material line in the alizarin region p. Each book 22 2 = 1Q = element structure 21G is disposed on the electric tow 2U and the storage G includes an active element 212, a pixel and data line 204 electrical ^ 12 and a corresponding scan line 202 212. The battery element 214 is electrically connected to the active element. When the element structure j r is partially overlapped to form a faulty capacitor. When entering the display, the storage capacitor helps to maintain the battery. 2009 200923923 708twf.doc/p The image displayed by the display of 4 times is more stable, that is, the LCD of s5, σ structure 200 Afterimage or flashing phenomenon. However, the image A is not made of a light-transmissive metal material, so the storage capacitor lower electrode 216 is configured by a display (four) two-electrode surface 216 which cannot affect the halogen structure 2i〇. The segment makes the above problem, and 216 causes the storage capacitor lower electrode to grasp the adjacent circuit t capacitor lower electrode phenomenon. In this way, the storage capacitor can be shortened to avoid the distance between the short-circuit paths to increase the display aperture ratio, and the process yield of the adjacent fabric 200. In particular, the f-heap capacitor τ electrode and the second line segment 216 Β. The first line segment 216α segment 2 is composed of the same film layer. The first line segment 216 is nearly fine. Ί W near the shell line 2〇4 gp, the brother-shot and 216B are adjacent to the scan line 2〇2 configuration. Set
與其鄰近的資料線綱為不 而弟—線& 216A 其鄰近的掃描線2〇2為不同的膜二κι細與 存電容下電極Μ之外形例如為;型， 別斑此j 而第二線段2_的兩端分 Ϊ包6A交疊。此外，晝素結構_中 觸窗218,且第—_” 、弟一線& 16]8又®處的接 218電性連接。 A與第二線段216B藉由接觸窗 外形其存電容下電極216並不限定於Π型 只*例中，儲存電容下電極216例如不與主 708twf.doc/p 200916923 動元件212相交或重疊而構成接近c字型圖案，圍达於查 素區p周邊大部分輯，例而言，儲存電容下電ς = Ρ _周’且具有―對應主動元件212 的開口部位。 圖3緣示為圖2之晝素結構21〇的上視示意圖。請表 照圖2與圖3’在晝素結構21()中，第二線段2ΐ6β與掃描 線搬由不同膜層製作而成。由上視圖觀之，即使縮短第 二線段膽與掃描線2〇2間的距離d，第二線段鳩盘 掃描線202間仍不易發生短路的問題。因此，相較於= 的晝素結、構11。而言，儲存電容下電極216的第二線段 216B #刀可以更罪近掃描線2〇2，因而有助於增加晝素社 ί 3 2 Γσ率。此外’第—線段216A與資料線二 亦f不同膜層，·也有助於提昇晝素結構21()的顯 口率0 據實際測試結果發現’與習知畫素結構比較， 本實施例之畫素結構21G有較高的顯示開口率（依晝素钟 至少大叫所以在相同的光源條件 =。=冓210之液晶顯示面板也具有較高的光線穿透 $桌，^ί素結構21G的設計可以提升背光源的光線使 … 助於降低为光源的能源耗費。換言之，應用 的液晶顯示器不需搭配高亮度的背光模：或 疋Φ貝的日频就可以達到足夠的顯示亮度，以進 省成本。 圖4A〜®1 4D繪示為圖2之晝素陣列結構沿剖線ΑΑ, 708twf.doc/p 200916923 的製作方法剖面圖。請先同時參照圖2與圖4A，在一基板 400上形成一第一金屬層410。第一金屬層410包括—閘極 212A、一掃描線202以及一第一線段216A。閘極212A與 掃描線202連接，而第一線段216A遠離掃描線202。實際 上，第一線段216A與掃描線202互不接觸或重疊，且第 一線段216A的延伸方向與掃描線2〇2的延伸方向相交。 對應於各晝素區P中，第一線段216A例如會與相鄰晝素 區P的第一線段216A連接。 —' 接著，請同時參照圖2與 fThe data line adjacent to it is not the same - line & 216A its adjacent scan line 2〇2 is different from the film κι fine and the capacitor is lower than the electrode 例如, for example, type, do not spot this j and second Both ends of the line segment 2_ overlap the packet 6A. In addition, the germanium structure _ middle touch window 218, and the first _", the first line & 16] 8 and 218 at the electrical connection 218. A and the second line segment 216B through the contact window shape of the capacitor bottom electrode 216 is not limited to the Π type only example. The storage capacitor lower electrode 216 does not overlap or overlap with the main 708 twf.doc/p 200916923 moving element 212 to form a c-shaped pattern, and is surrounded by a large area around the check area p. For a partial series, for example, the storage capacitor is powered down Ρ _ _ 周 ' and has an opening corresponding to the active element 212. Figure 3 is a top view of the pixel structure 21 图 of Figure 2. 2 and FIG. 3' in the halogen structure 21 (), the second line segment 2 ΐ 6β and the scanning line are made of different film layers. From the top view, even if the second line segment bile and the scanning line 2 〇 2 are shortened The distance d, the second line segment is still less prone to short circuit between the scanning lines 202. Therefore, compared with the 昼 结 结 结 结 结 结, the second line segment 216B of the storage capacitor lower electrode 216 can be more The crime is close to the scan line 2〇2, which helps to increase the rate of 昼 3 Γ 。 σ. In addition, the 'line segment 216A and capital Line 2 also has different film layers, and also helps to improve the aspect ratio of the halogen structure 21 (). According to actual test results, 'the pixel structure 21G of this embodiment has a higher comparison with the conventional pixel structure. Display aperture ratio (at least the yelling clock, so in the same light source condition =. = 冓 210 liquid crystal display panel also has a higher light penetration $ table, the structure of the 21G design can improve the light of the backlight To help reduce the energy consumption of the light source. In other words, the application of the liquid crystal display does not need to be matched with a high-brightness backlight mode: or 日 Φ 的 daily frequency can achieve sufficient display brightness to save costs. Figure 4A ~ 1 4D is a cross-sectional view of the fabrication method of the cell array structure of FIG. 2 along the line ΑΑ, 708 twf.doc/p 200916923. Please first simultaneously refer to FIG. 2 and FIG. 4A to form a first metal layer on a substrate 400. 410. The first metal layer 410 includes a gate 212A, a scan line 202, and a first line segment 216A. The gate 212A is connected to the scan line 202, and the first line segment 216A is away from the scan line 202. In fact, the first Line segment 216A and scan line 202 do not touch or overlap each other And the extending direction of the first line segment 216A intersects with the extending direction of the scanning line 2〇2. Corresponding to each of the pixel regions P, the first line segment 216A is connected to the first line segment 216A of the adjacent pixel region P, for example. — — Next, please refer to both Figure 2 and f
…… 心丞微斗υυ上依月 形成一閘絕緣層420以及一圖案化半導體層43〇，且閘與 緣層420覆蓋閘極212Α。此外，閘絕緣層420上具有一名 觸窗218。圖案化半導體層430位於閘極212Α上方，而名 觸窗218暴露出第一線段216Α之末端。 斤然後，請同時參照圖2與圖4C，於基板400上形启 -第二金屬層440。第二金屬層44〇包括鄰近掃描線加 之一第二線段216Β、鄰近第一線段216Α之一資料線2〇4 連接資料線2G4之-源極212Β以及—祕2l2c。源和 212B與，極212c位於閘極贏上方之圖案化半導體^ 430上。弟二線段216B藉由接觸窗218電性 ; 存電容下電極216，其中儲存電容下= 216位於晝素區p周邊。 镇-目鄰近的掃描線观與第二線段2166分· 弟至屬層410與第二金屬層44〇，其 與第二金屬層_之間至少配置有閘絕緣層此 11 200916923 .708twf.doc/p ，描線202與鄰近的第二線段216B不容易發生短路的現 ，使旦素陣列結構200具有較高的製程良率。择描線 搬，、鄰近的第二線段216B之間的距離可以較f知晝素 了構110之叹计更為縮短，以增加畫素陣列結構細的顯 不開口率。此外，資料線204與相鄰近的第一線段216a 也是不同的姻層，所以也具有上述之優點。 再者’請同時參照圖2與圖4D，於基板彻上形成 ^保護層450以覆蓋第二金屬層44〇 ’並於保護層45〇上 开/成夕個晝素電極2M。晝素電極別 且㈣電極叫之邊緣與儲存電訂電極216實質上部^ f豐’以構成儲存電容。如此，晝素陣列結構2〇〇即製作 完成。 l 曰在本實施例中，接觸窗218與圖案化半導體層43〇例 用圖5所不之半透光罩進行钱刻製程而形成的。請 同時麥照圖4D與參照圖5,半透光罩5〇〇具有多個不同透 光度的透光區T。對應於單—晝素區p中，透光區τι對岸 於接觸窗別上方，透光區T2對應於圖案化半導體層430 上方’而透光區Τ3則位於其他區域中。詳細而言，形成 =化半導體層430以及接觸窗218之方法如圖6α〜圖6£ 所繪示。 * 先二參照圖6Α，於基板_上依序形成閘絕緣 層420、半¥體層432以及光阻材料層（未綠示）。同時，使 =透光罩50G將光阻材料層（树示）圖案化，而形成一 圖木化光阻層610。間絕緣層42〇與半導體層纽覆蓋第 12 200916923 ：70Btwf.doc/p 一金屬層410。在本實施例中， 非晶矽層434以及摻雜非晶矽層436。;參雜非准 :成方式例如是進行換雜製程以_接:;= 另外’半透光罩5〇〇具有不同透光 3應，域之光阻材料層齡)接收二二 ^線。因此，_化_層_在不域中呈有不= ，爲以本實施例而言，對應於單—晝素區 “ 具有至少一開，、—第一區域614 = /域614與開口 612之外的一第二區域61 _此/卜、’圖案化光阻層610在第—區域6Μ 予度大於在弟一區域616的厚度。 請參照圖6Β，移除開口612所暴露出來之半 ^=32以及閉絕緣層42〇，而形成接觸窗218。此步驟 進仃^刻製程以將開σ 612所暴露出來的半導體 ^ 3^以及開絕緣層移除。此時，第一區域614以及 ^ = 616關_雜層61〇可以保護其下方之半導 體層43yx及閘絕緣層以避免被钱刻。 接著，請參照圖6C，移除第二區域616之部分圖案 =光=層⑽’此步驟例如是進行—灰化(A—)製程。由 ;，红區域616之部分圖案化光阻層⑽具有較薄的厚 =而弟-區域6M之部分圖案化光阻層61〇具有較厚的 尽度。所以’第二區域616之部分圖案化光阻層61〇在灰 13 200916923 708twf.doc/p 化製程中被完全移除時，第—區域6i4之部 Ik之，岣芩照圖6D與圖6Ε，利用第— =Γ【Γ0為罩幕，移除部份半導心心 圖案：體層二的圖=::510移除，即可完成 。弟—區域616中 此步驟中被移除，而僅留下位於_2以二二在 半體層430。在本實施例中，不需以不同的光案ί ==同，刻製程’因此有助於節省購口 的==:製程設計之下，本發明並 218^圖案化半導體層·。AM刀別形成接觸窗 儲存電容制之畫素陣顺财其製造方法中， 層。所以，儲存:= 曼與鄰近的金屬線路為不同金屬 線或資料線 之晝素陣㈣構路的現象。也就是說，本發明 外，儲存泰~ /、製以方法具有較高的製程良率。另 因：C鄰近的金屬線路間不易發生短路 可以縮&料㈣織4射4紅間的轉 本發明提^t助於提高晝素結構的顯示開Π率。簡言之， 其製造方法良率與高齡開口率的晝素陣列結構及 限定;以較佳實施例揭露如上，然其並非用以 任何所屬技術領域中具有通常知識者，在不 14 200916923 708twf.doc/p 脫離本發明之精神和範圍内，當可作些許之更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 【圖式簡單說明】 圖1繪示為習知之晝素陣列結構的局部示意圖。 圖2為本發明之一實施例之晝素陣列結構之示意圖。 圖3繪示為圖2之畫素結構的上視示意圖。 圖4A〜圖4D繪示為圖2之晝素陣列結構沿剖線AA’ ( 的製作方法剖面圖。 圖5繪示為本發明之一實施例之半透光罩的示意圖。 圖6A〜圖6E繪示圖2之晝素陣列結構的圖案化半導 體層以及接觸窗之製造方法。 【主要元件符號說明】 100、200 :晝素陣列結構 102、202 :掃描線 104、204 :資料線 I 110、210 :晝素結構 ’ 112、212 :主動元件 114、214 :畫素電極 120、216 :儲存電容下電極 212A :閘極 212B :源極 212C :汲極 216A :第一線段 15 >708twf.doc/p 200916923 216B:第二線段 218 :接觸窗 400 :基板 410 :第一金屬層 420 :閘絕緣層 430 :圖案化半導體層 432 :半導體層 434 :未摻雜非晶矽層 436 :摻雜非晶矽層 440 :第二金屬層 450 :保護層 500 :半透光罩 610 :圖案化光阻層 612:開口 614 :第一區域 616 :第二區域 A-A’ ：剖線 P :晝素區 T、T卜T2、T3 :透光區 16...... The enamel micro-bucket is formed on the moon to form a gate insulating layer 420 and a patterned semiconductor layer 43A, and the gate and edge layer 420 covers the gate 212Α. In addition, the gate insulating layer 420 has a contact window 218 thereon. The patterned semiconductor layer 430 is over the gate 212A and the named window 218 exposes the end of the first line segment 216A. Then, please refer to FIG. 2 and FIG. 4C simultaneously to form a second metal layer 440 on the substrate 400. The second metal layer 44 includes a second line segment 216 邻近 adjacent to the scan line, a source line 2 〇 4 adjacent to the first line segment 216 连接, a source 212 Β connected to the data line 2G4, and a secret 21 2 c. The source and 212B and the pole 212c are located on the patterned semiconductor ^ 430 above the gate. The second line segment 216B is electrically connected by the contact window 218; the capacitor lower electrode 216 is stored, wherein the storage capacitor = 216 is located around the pixel region p. The scanning line view adjacent to the town-head and the second line segment 2166 are connected to the second metal layer 44, and at least the gate insulating layer is disposed between the second metal layer and the second metal layer_11 200916923 .708twf.doc /p, the line 202 and the adjacent second line segment 216B are not prone to short circuit, so that the denier array structure 200 has a higher process yield. By selecting the line to move, the distance between the adjacent second line segments 216B can be shortened more than the sigh of the structure 110 to increase the fine aperture ratio of the pixel array structure. In addition, the data line 204 and the adjacent first line segment 216a are also different layers of marriage, and therefore have the above advantages. Further, please refer to Fig. 2 and Fig. 4D at the same time, a protective layer 450 is formed on the substrate to cover the second metal layer 44A' and is opened on the protective layer 45A. The halogen electrode and (4) the electrode is called the edge and the storage electrode 216 is substantially fused to form a storage capacitor. Thus, the halogen array structure 2 is completed. In the present embodiment, the contact window 218 and the patterned semiconductor layer 43 are formed by using a semi-transparent cover as shown in FIG. At the same time, as shown in Fig. 4D and Fig. 5, the translucent cover 5 has a plurality of transparent regions T of different transmittances. Corresponding to the mono-halogen region p, the light-transmitting region τ1 is opposite to the contact window, the light-transmitting region T2 corresponds to the upper portion of the patterned semiconductor layer 430, and the light-transmitting region Τ3 is located in other regions. In detail, the method of forming the semiconductor layer 430 and the contact window 218 is as shown in FIGS. 6α to 6 . * Referring to Figure 6A, the gate insulating layer 420, the half body layer 432, and the photoresist layer (not shown in green) are sequentially formed on the substrate_. At the same time, the light transmissive cover layer (tree) is patterned by the light transmissive cover 50G to form a patterned photoresist layer 610. The interlayer insulating layer 42 and the semiconductor layer are covered with a metal layer 410 of 12 200916923:70Btwf.doc/p. In the present embodiment, an amorphous germanium layer 434 and an amorphous germanium layer 436 are doped. Miscellaneous: The method of forming is, for example, performing a change-making process to _:: = the other 'half-transparent cover 5' has a different light transmission 3, the domain of the photoresist material layer age) receives the two-two line. Therefore, the _ _ layer _ is not = in the non-domain, and in the present embodiment, corresponds to the uni-quartel region "having at least one open, - the first region 614 = / domain 614 and the opening 612 A second region 61 other than the first, the patterned photoresist layer 610 is greater in the first region than the thickness of the region 616. Referring to Figure 6A, the exposed half of the opening 612 is removed. ^=32 and the insulating layer 42〇 are closed to form the contact window 218. This step is performed to remove the semiconductor and the insulating layer exposed by the opening 612. At this time, the first region 614 And ^ = 616 off - the impurity layer 61 〇 can protect the underlying semiconductor layer 43yx and the gate insulating layer to avoid being engraved. Next, please refer to FIG. 6C, remove the partial pattern of the second region 616 = light = layer (10)' This step is, for example, an ashing (A-) process. A portion of the patterned photoresist layer (10) of the red region 616 has a thinner thickness = and a portion of the patterned photoresist layer 61 of the region-region 6M has a higher thickness. Thickness of the end. So the 'patterned photoresist layer 61 of the second region 616 is 〇 in the gray 13 200916923 708twf.doc/p process When completely removed, the part Ii of the first region 6i4, as shown in Fig. 6D and Fig. 6Ε, using the first ==Γ[Γ0 as a mask, removes part of the semiconducting core pattern: the picture of the body layer 2::: The 510 is removed, and the completion is completed. In the step 616, the step is removed, and only the second layer 430 is located at _2. In this embodiment, it is not necessary to use a different optical case. = the same, engraving process 'so it helps to save the purchase of the ==: process design, the invention and 218 ^ patterned semiconductor layer · AM knife to form a contact window storage capacitor system of the pixel array In the method, the layer. Therefore, the storage: = Man and the adjacent metal line are the phenomenon of the different metal wires or the data lines of the elementary array (4). That is to say, in addition to the present invention, the method of storing the Thai ~ /, has Higher process yield. Another reason: C is not prone to short circuit between adjacent metal lines. It can be used to improve the display opening ratio of the structure of the alizarin. Briefly, the structure and definition of the pixel array of the manufacturing method yield and the age of the aperture ratio; the above is disclosed in the preferred embodiment. It is not intended to be used in any way in the art, and it is within the spirit and scope of the invention, and the scope of protection of the present invention is BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1 is a partial schematic view showing a structure of a conventional halogen array. Fig. 2 is a schematic view showing a structure of a halogen array according to an embodiment of the present invention. 3 is a top view of the pixel structure of FIG. 2. FIG. 4A to FIG. 4D are cross-sectional views showing the manufacturing method of the pixel array structure of FIG. 2 along the line AA′. FIG. 5 is a schematic view of a translucent cover according to an embodiment of the present invention. 6A-6E illustrate a patterned semiconductor layer of the pixel array structure of FIG. 2 and a method of fabricating the contact window. [Description of main component symbols] 100, 200: halogen array structure 102, 202: scanning lines 104, 204: data lines I 110, 210: halogen structure '112, 212: active elements 114, 214: pixel electrodes 120, 216: storage capacitor lower electrode 212A: gate 212B: source 212C: drain 216A: first line segment 15 > 708 twf. doc / p 200916923 216B: second line segment 218: contact window 400: substrate 410: first metal Layer 420: gate insulating layer 430: patterned semiconductor layer 432: semiconductor layer 434: undoped amorphous germanium layer 436: doped amorphous germanium layer 440: second metal layer 450: protective layer 500: semi-transmissive cover 610 : patterned photoresist layer 612: opening 614: first region 616: second region A-A': line P: halogen region T, T Bu T2, T3: light transmissive region 16