200915558 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種影像感測器，影像感測器係為一種用以將 光影像轉化為電信號的半導體裝置，影像感測器粗略可分類為一 電荷耦合元件（Charge Coupled Device，CCD)影像感測器或一互 補金氧半導體(Complementary Metal Oxide Semiconductor，CMOS > 影像感測器（CIS)。 【先前技術】 在一影像感測器中，使用離子注入一光電二極體形成於具有 讀出電路的一基板中。由於為了增加晝素數目而不增加晶片尺寸 之目的，光電二極體的尺寸越來越減少，因此光線接收部份的區 域減少，致使產生影像質量的降低。 而且，由於堆疊尚度的減少沒有光線接收部份區域的減少那 麼大，因此，入射於光線接收部份的電子數目由於稱作艾瑞盤 disk)的光衍射也減少。 作為消除此限綱-種選擇’嘗試使用非晶娜成_光電二 極體，或者在-祕板巾形成—讀出電路且使用—例如晶片對晶 片結合方法在讀出電路上形成一光電二極體⑽作—三維（如,, 影像感測器）。光電二極體通過—金屬線與讀出電路相連接。 d而對於一維（3D)影像感測器而言，當光電二極體形 成於具有讀出電關基板上時，在光電二極_面與基板之 200915558 頂表面之間產生-高度差。特別地，由於形成於晶片的邊緣區域 中的-些誠二麵之細被祕，因此不舰的光線可入射於 此側面且可減少光線敏感度。 同時，根據習知技術，當光電二極體的表面電麼透過入射光 線降低時’ 感測部份的表面賴也同時降低。之後，當打開 -轉換電晶體Τχ且賴_時’龍電晶咖雜及汲極電堡變 為彼此相等，並且汲極的電位差通過—驅動電晶體被放大。根據 習知技術4於轉換電晶體的源極及汲極均高度摻雜有Ν型雜 質，因此可產生電荷共用現象。當產生電荷共用現象時，輸出影 像的敏感度可減少且可產生一影像錯誤。 而且，根據f知技術，因為光電荷不在光電二極體與讀出電 路之間錄地軸，因此產生黑奴或減錢和纽敏感度。 【發明内容】 ，因此，胁上蝴題，本發賴财—種影佩測器及其製 把方法’本發明之影像感·形成有—頂部線路，用以阻擔入射 =晝素部份之邊緣區域中的光電二極體之側面的光線，由此可提 高光線敏感度。 、j發贿供有i影像感·及其製造方法，本發明之影像 感測裔包含有-光電二極體上的透明電極及—外_份，透明電 極與一頂部線路電連接，用轉電壓施加於光電二極體及周圍電 路。 200915558 在本發明之一實施例中，—種影像感測器可包含有：一第〆 基板，第-基板包含有—晝素部份及—相部份；—形成於责幸 部份上的項出電路，一失層介電層，係形成於 圍部份上晴個底部線路，係 ^‘及外 ==份上;一透明電極，係形成於形成二 體的夾層,,電層上，透明電極與光 :_妾，·-第，，係形成二 =有-料，峨树_電婦卜晴广 線路相對應之-部份；以及一頂部線路 ^ 部份上，1中頂㈣饮目士 t 帥成於溝道中的外圍 相同之表蝴她㈣—献層之頂表面 上冑撕，丨輸侧树素部纷 上。^弟一純化層可形成於透明電極及外圍部份的夾層介電展 露查去，層可包含有一暴露外圍部份中的底部線路之溝道曰 思素部份之邊緣區域的透明電 | 於這兩個溝道中，用以溝道。頂部線路可形成 工極體之細雜__目連接且遮擋光電 下步ί據ΐΓΓΙΓιΓ彡細㈣造方法包含以 外園部份；形成基缺射—畫素部份及〜 成α買出電路於畫素部份上；形成一夹層介電層於 200915558 具有晝素部份及外_份之第—基板上；形成與讀出電路及外圍 部份相連接之底部線路於夾層介電層中；準備具有一結晶半導體 層的第H形成—光電二極體於結日日日半導體層n 基板及第二基板，以使得第-基板之底部線路與光電二極體電連 trr二基板用以暴露光電二極體；去除光電二極體與外圍 子應之部份’以使得光電二極體僅保留於晝素部份上，用 +路外1U[^上之底部線路；形成—透明電極層於夾層介電層 ^其中絲物上形她電二《，贿編電摩 =4體及_份中的底亀树接；形成—第一純❹ 於=電败；軸—輸f—糊 部線路相對紅，㈣_ 2 部線路於外圍部份上且該頂部線路包含於溝道中。 頂 勺人月之另—實施例，本發明之影像感測器之製造方法 =Γ電極層於光電二極體上;形成第-鈍化層於透明電 =外圍部份之夾層介電層上;形成—第一溝道—^ 二二素部份之邊緣部份的透明電極層’並且形成 化層中’弟—溝道暴露外圍部份中之底部線 辨軸—卿線路於第—溝道及第二溝道巾且沿著光電二 =側面喊，了晴_輪糊樹的底部線路 圖式部份自以下的說明蚩 本發明之-個或多個實施例將結合 200915558 中進行詳細。本發明的其他魏職町的綱書及圖式部 伤以及本發明之保護範圍巾變得更加清楚。 【實施方式】 以下，將結合附轉細描述本剌實施例之感測器及i 製造方法。 /' 田在此使肖_L或’上方的詞語係指作層、區域、圖案 或結構時’可㈣解的是該層、區域、醜或結構能夠直接位於 另-層或結構上，或者可具有插入層、區域、圖案或結構。當各 在此使下方"的詞語係指作層、區域、圖案或結才: 時，可以理解的是該層、區域、圖案或結構能夠直接位於另一層 或結構之下，或者可具有插人層、區域、圖案或結構。 第10圖」係為本發明一實施例之影像感測器之橫截面圖。 請參閱「第10圖」，一影像感測器可包含有：一第一基板 100 ’第一基板1〇〇包含有一晝素部份Α及一外圍部份Β ; 一形成 於晝素部份A上的讀出電路120; —夾層介電層16〇，係形成於具 有晝素部份A及外圍部份B的第一基板100上；複數個底部線路 150及170 ’係穿過夾層介電層160用以分別與讀出電路12〇及外 圍部份B電連接；一光電二極體205，係形成於夾層介電層16〇 的與晝素部份A相對應之一部份之上；一夾層介電層16〇上的透 明電極230 ’其中夾層介電層160上形成有光電二極體2〇5，透明 電極230與光電二極體205及外圍部份β中的底部線路17〇相連 11 200915558 =’月電極230上的第一純化層罵，第—純化層包含有 -溝道24卜溝道241暴露透明電極23〇的與外圍部份b中的底 部線路no相對應的部份；以及溝道241中的頂部線路25〇，頂部 線路250具有與晝素部份八上的第一鈍化層24〇同樣的表面高度。 第-基板蘭的讀出電路12〇可具有一形成在第一基板⑽ 中的電接面區M0 ;以及—第一導電型連接區w，第一導電型連 接區147與電接面區14〇上的底部線路⑼相連接。 頂部線路250可形成於第一純化層之溝道241中，用以 與透明電極230電連接。而且，頂部線路謂可形成為與光電二 極體205上的第-鈍化層24〇具有同樣之高度。透過將頂部線路 形成為在光電二極體205之上一定之高度，頂部線路，可阻擔 入射於光電二極體205之側面的光線，用以提高影像特性。 第12圖」係為本發明之另一實施例之影像感測器之橫截面 圖，其中透明電極僅形成於光電二極體上。 請參閱「第12圖」，一透明電極235形成於第一基板1〇〇上 的光電二極體205之上，透明電極235用以與光電二極體2〇5電 連接。第一鈍化層240具有第一溝道243及第二溝道245，並且第 一鈍化層240形成於夾層介電層16〇之上，其中夾層介電層16〇 上形成有透明電極235。第一及第二溝道243及245分別暴露透明 電極235及底部線路170。 一頂部線路255配設於具有第一及第二溝道243及245的第 12 200915558 一鈍化層240上。頂部蟪敉 、、' 255可按照不遮蔽對應於單元晝素 光電二極體205之方或形士 万式形成。頂部線路255配設於第一及第二溝 道243及245之内部，用LV收.未 '用U將透明電極235與底部線路170相連 接。 而且，頂部線路255從第一溝道祀延伸至第二溝道泌，用 以遮蔽光電二極體2〇5之側面。因此，頂部線路255能夠遮蔽入 射於光電二極體205之側面的光線。 根據本發明之實施例，找二極體可形成於—結晶半導體層 中。由於光電二極體形成於結晶半導體層之内部，因此可抑制此 光電二極體之缺陷。 而且’頂縣路可用作將—地面龍施加域電二極體，頂 部線路形成為用以遮蔽光電二極體之側面且因此可用作一光線阻 擔層。因此，可提高光電二極體的光敏感度。 根據本發明之實施例’―裝置設計為可使得在賴電晶體Τχ 的源極與錄之間產生-電位差，致使光電二極體2()5的光電荷 可被充分地傾卸。因此，由於光電二極體2G5產生的光電荷可被 充分傾卸至-浮置擴散區，因此，可增加輸出影像的敏感度。 也就疋說，一電接面區14〇可形成於具有讀出電路12〇的第 一基板100中，用以允許在轉換電晶體Τχ121之源極及汲極之間 產生一電位差，以致可充分傾卸一光電荷。讀出電路12〇可包含 有一轉換電晶體Τχ121、一複位電晶體^123、一驅動電晶體 13 200915558200915558 IX. Description of the Invention: [Technical Field] The present invention relates to an image sensor, which is a semiconductor device for converting an optical image into an electrical signal, and the image sensor is roughly categorizable It is a Charge Coupled Device (CCD) image sensor or a Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS). [Prior Art] In an image sensor Using ion implantation, a photodiode is formed in a substrate having a readout circuit. Since the size of the photodiode is increasingly reduced for the purpose of increasing the number of pixels without increasing the size of the wafer, the light receiving portion is further reduced. The area is reduced, resulting in a reduction in image quality. Moreover, since the reduction in stacking is not as large as the reduction of the portion of the light receiving portion, the number of electrons incident on the light receiving portion is called the disk of the disk. Light diffraction is also reduced. As a way to eliminate this limitation, try to use amorphous nano-photodiode, or to form a readout circuit and use - for example, a wafer-to-wafer bonding method to form a photodiode on the readout circuit. The polar body (10) is made up of three-dimensional (eg, image sensor). The photodiode is connected to the readout circuit through a metal line. d For a one-dimensional (3D) image sensor, when the photodiode is formed on the substrate having the readout voltage, a height difference is generated between the photodiode surface and the top surface of the substrate 200915558. In particular, since the two sides of the wafer are formed in the edge region of the wafer, the light of the non-ship can be incident on the side and the light sensitivity can be reduced. At the same time, according to the prior art, when the surface of the photodiode is reduced by the incident light, the surface of the sensing portion is simultaneously lowered. Thereafter, when the -transistor transistor is turned on and the NMOS is turned on, the potential of the drain is amplified by the drive transistor. According to the prior art 4, the source and the drain of the conversion transistor are highly doped with erbium-type impurities, so that charge sharing can occur. When a charge sharing phenomenon occurs, the sensitivity of the output image can be reduced and an image error can be generated. Moreover, according to the technique of f, since the photocharge is not at the recording axis between the photodiode and the readout circuit, black slaves or money reduction and sensitivity are generated. [Summary of the Invention] Therefore, the threat is on the subject, and the method of the present invention is to form a top line for blocking the incidence of the pixel. Light rays on the side of the photodiode in the edge region, thereby improving light sensitivity. , j bribing for i-image and its manufacturing method, the image sensing of the present invention comprises a transparent electrode on the photodiode and an outer portion, the transparent electrode is electrically connected to a top line, and is rotated A voltage is applied to the photodiode and surrounding circuitry. In an embodiment of the present invention, an image sensor may include: a second substrate, the first substrate includes a halogen component and a phase portion; and is formed on the part of the responsibility The output circuit, a lost dielectric layer, is formed on the clear bottom line of the surrounding portion, and is formed on the outer layer and the outer portion; a transparent electrode is formed on the interlayer forming the two body, on the electrical layer , transparent electrode and light: _妾,·-,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The witnesses t handsomely formed in the same periphery of the channel. She (4) - the top surface of the layer was torn, and the side of the tree was smashed. The diver-purified layer can be formed on the interlayer of the transparent electrode and the peripheral portion of the interlayer, and the layer can include a transparent portion of the edge region of the channel of the bottom portion of the channel in the exposed peripheral portion. In these two channels, the channel is used. The top line can form a fine structure of the working body body and block the photoelectric lower step. According to the ΐΓΓΙΓιΓ彡 fine (4) method, the outer part is formed; the base defect is formed - the pixel part and the ? Forming a sandwich dielectric layer on the substrate substrate having a monolithic portion and an outer portion on 200915558; forming a bottom line connected to the readout circuit and the peripheral portion in the interlayer dielectric layer Preparing an H-th photo-photodiode having a crystalline semiconductor layer on the day-to-day semiconductor layer n substrate and the second substrate, such that the bottom line of the first substrate and the photodiode are electrically connected to the trr two substrate Exposing the photodiode; removing the portion of the photodiode and the peripheral sub-portion so that the photodiode remains only on the alizarin portion, using the +U 1^[the upper line; forming the transparent electrode The layer is formed on the interlayer dielectric layer ^the wire is shaped by her electric two, and the bribe is replaced by the bottom eucalyptus tree in the body and the _ part; the formation - the first pure 于 = = electric defeat; the shaft - the transmission f - The paste line is relatively red, (4) _ 2 lines are on the peripheral part and the top line is included in the groove In the middle. The other embodiment of the present invention is the method for manufacturing the image sensor of the present invention. The germanium electrode layer is formed on the photodiode; and the first passivation layer is formed on the interlayer dielectric layer of the transparent electric=peripheral portion; Forming a transparent electrode layer ′ at the edge portion of the first channel—the second portion of the bismuth portion and forming a bottom line in the exposed peripheral portion of the smear-channel in the formation layer And the second channel towel and along the photodiode = side, the bottom line pattern portion of the clearing tree from the following description - one or more embodiments of the present invention will be described in detail in conjunction with 200915558. The other articles and drawings of the Weishou-cho of the present invention and the protective cover of the present invention will become more apparent. [Embodiment] Hereinafter, a sensor and an i manufacturing method of the present embodiment will be described in conjunction with the accompanying drawings. /' The field here makes the word _L or 'above as a layer, region, pattern or structure'. (4) The solution is that the layer, region, ugly or structure can be directly on the other layer or structure, or There may be an intervening layer, region, pattern or structure. When the words "lower" are referred to herein as layers, regions, patterns, or knots, it is understood that the layer, region, pattern, or structure can be directly under another layer or structure, or can be inserted Human layer, area, pattern or structure. Figure 10 is a cross-sectional view of an image sensor in accordance with an embodiment of the present invention. Please refer to FIG. 10 , an image sensor can include: a first substrate 100 ′ the first substrate 1 includes a pixel portion and a peripheral portion Β ; The readout circuit 120 on A; the interlayer dielectric layer 16 is formed on the first substrate 100 having the halogen portion A and the peripheral portion B; the plurality of bottom lines 150 and 170' are passed through the interlayer The electrical layer 160 is electrically connected to the readout circuit 12A and the peripheral portion B, respectively; a photodiode 205 is formed on a portion of the interlayer dielectric layer 16A corresponding to the halogen portion A. a transparent electrode 230' on the interlayer dielectric layer 16', wherein the interlayer dielectric layer 160 is formed with a photodiode 2〇5, a transparent electrode 230 and a photodiode 205 and a bottom line in the peripheral portion β 17〇连接11 200915558 = 'The first purification layer 月 on the moon electrode 230, the first purification layer containing the -channel 24 channel 241 exposing the transparent electrode 23〇 corresponds to the bottom line no in the peripheral portion b And the top line 25〇 in the channel 241, the top line 250 has a first blunt with the altar component The layer 24 has the same surface height. The readout circuit 12 of the first substrate may have an electrical junction region M0 formed in the first substrate (10); and a first conductive type connection region w, a first conductive type connection region 147 and an electrical junction region 14 The bottom line (9) on the raft is connected. The top line 250 can be formed in the channel 241 of the first purification layer for electrical connection with the transparent electrode 230. Moreover, the top line can be formed to have the same height as the first passivation layer 24 on the photodiode 205. By forming the top line to a certain height above the photodiode 205, the top line can block light incident on the side of the photodiode 205 to improve image characteristics. Figure 12 is a cross-sectional view of an image sensor according to another embodiment of the present invention, in which a transparent electrode is formed only on a photodiode. Referring to Fig. 12, a transparent electrode 235 is formed on the photodiode 205 on the first substrate 1b, and the transparent electrode 235 is electrically connected to the photodiode 2〇5. The first passivation layer 240 has a first channel 243 and a second channel 245, and a first passivation layer 240 is formed over the interlayer dielectric layer 16A, wherein the interlayer dielectric layer 16A is formed with a transparent electrode 235. The first and second channels 243 and 245 expose the transparent electrode 235 and the bottom line 170, respectively. A top line 255 is disposed on the 12th 200915558 passivation layer 240 having the first and second channels 243 and 245. The top 、 , , ' 255 can be formed by not covering the square or the shape corresponding to the unit halogen photodiode 205. The top line 255 is disposed inside the first and second channels 243 and 245, and is connected by the LV. The transparent electrode 235 is connected to the bottom line 170 by U. Moreover, the top line 255 extends from the first trench 至 to the second trench bleed to shield the sides of the photodiode 2〇5. Therefore, the top line 255 can shield the light incident on the side of the photodiode 205. According to an embodiment of the present invention, a find diode can be formed in the crystalline semiconductor layer. Since the photodiode is formed inside the crystalline semiconductor layer, defects of the photodiode can be suppressed. Moreover, the 'Dingxian Road can be used as a ground-mounted dragon to apply a domain electric diode, and the top line is formed to shield the side of the photodiode and thus can be used as a light-shielding layer. Therefore, the light sensitivity of the photodiode can be improved. The device according to the embodiment of the present invention is designed such that a potential difference is generated between the source and the recording of the photo transistor, so that the photocharge of the photodiode 2 () 5 can be sufficiently dumped. Therefore, since the photocharge generated by the photodiode 2G5 can be sufficiently dumped to the - floating diffusion region, the sensitivity of the output image can be increased. In other words, an electrical junction region 14 〇 can be formed in the first substrate 100 having the readout circuit 12 , to allow a potential difference between the source and the drain of the conversion transistor Τχ 121 to be Fully dump a photocharge. The readout circuit 12A can include a conversion transistor Τχ121, a reset transistor ^123, and a drive transistor 13 200915558
Dxl25、以及一選擇電晶體Sxl27。 以下，將詳細描述本發明之—實施例之光電荷之傾卸結構。 電接面區140可包含有一第一導電型離子注入層143，第一導 電型離子注人層143形成於—第二導電型井141(或—第二導電型 外延層（圖未示））上，以及—第二導電型離子注人層145，第二 導電型離子注人層145形成於第—導電型離子注人層143之上。 舉例而言’電接面區14〇係可為一闕妾面或一 pNp接面，但是 並不限制於此。 與洋置擴散區FD131的-節點，即n+型接面不相同，pNp 型電接面區140在-預定電壓被央斷，其中施加於着型電接面 區H0的紐沒有被完全轉換。此預定電壓稱作—閉合電壓，閉 合電壓依賴於P0型第二導電型離子注人層145及N•型第一導電 型離子注入層143之摻雜濃度。 特別地，光電二極體2〇5產生的一電子移動至pNp型電接面 區140’並且轉移至浮置擴散區Fm31之節點且當轉換電晶體 Txl21打開時轉化為一電壓。 由於Ρ0/Ν-/Ρ-型電接面㊣14㈣一最大電壓值變化為一閉合 電壓’並且浮置擴散區FD131之節點的最大電壓值變為複位電晶 體Rxl23的-閥值電壓Vth，因此透過在轉換電晶體Τχ12ι之側 面之間施加一電位差，在晶片頂部中的光電二極體2〇5產生的一 電子可充分傾卸至浮置擴散區FD131的節點而不出現電荷共用。 14 200915558 也就是說，根據本發明之一實施例，p〇/N_/p_型井接面而非 N+/P-型井接面形成於第一基板中，用以在4_Tr活性晝素感測器 (Active Pixel Sensor，APS)複位作業期間，允許一正電壓施加至 Ρ0/Ν-/Ρ-型井接面的N_型第一導電型離子注入層ι43且一地面電 壓施加至P0型第二導電型離子注入層145及一 p_型第二導電型井 141，以使得在Ρ0/Ν-/Ρ-型井雙接面以預定的電壓或在雙接面電晶 體（Bipolar Juncti〇n Transist〇r BJT)結構中以更大的電壓一產生 夾斷。這電壓稱作閉合電壓。因此，一電位差在轉換電晶體Τχ121 之側面產生於源極於汲極之間，在轉換電晶體Τχ的打開/關閉作 業期間防止產生電荷共用現象。 因此’與習知技術的光電二極體與Ν+型接面（Ν+/Ρ-型井） 簡單連接的情況不同，本發明之實施例能夠消除飽和度及敏感度 減少的限制。 而且，根據本發明之一實施例，第一導電型連接區147形成 於光電二極體與讀出電路之間，用以提供一光電荷的快速移動路 徑，以使得最小化黑電流源，並且可防止飽和度減少及敏感度的 減少。 為達此目的，根據本發明之一實施例，用以歐姆接觸的第一 導電型連接區147可形成於Ρ0/Ν-/Ρ-型電接面區14〇之表面上。同 時，為了防止第一導電型連接區147變為一洩漏源，第一導電型 連接區147之寬度可最小化。這樣，可減少三維（3D)影像感測 15 200915558 器的黑電流。 在上述之實施例中，使用N型離 T僮在接觸形成區進行 且重摻雜之原因在於當最小化里作跋 勹4 在重摻雜全部轉換電晶體Tx之情況 战 還過一矽（Si)表面縣介 鍵結可增加黑信號。 心二 以下將結合「第1圖」至「第D2 」主弟U圖」描述本發明之Dxl25, and a selection transistor Sxl27. Hereinafter, the dumping structure of the photocharge of the embodiment of the present invention will be described in detail. The electrical junction region 140 may include a first conductivity type ion implantation layer 143 formed on the second conductivity type well 141 (or a second conductivity type epitaxial layer (not shown)) The second conductivity type ion implantation layer 145 is formed on the first conductivity type ion implantation layer 143. For example, the electrical junction region 14 can be a dome or a pNp junction, but is not limited thereto. Unlike the node of the oceanic diffusion region FD131, i.e., the n+ junction, the pNp-type electrical junction region 140 is interrupted at a predetermined voltage, and the neon applied to the patterned electrical junction region H0 is not completely converted. This predetermined voltage is referred to as a closing voltage, and the closing voltage is dependent on the doping concentration of the P0 type second conductivity type ion implantation layer 145 and the N• type first conductivity type ion implantation layer 143. Specifically, an electron generated by the photodiode 2〇5 is moved to the pNp-type electrical junction region 140' and transferred to the node of the floating diffusion region Fm31 and converted to a voltage when the switching transistor Txl21 is turned on. Since the Ρ0/Ν-/Ρ-type electrical junction positive 14 (four)-maximum voltage value changes to a closing voltage 'and the maximum voltage value of the node of the floating diffusion FD131 becomes the threshold voltage Vth of the reset transistor Rxl23, Therefore, by applying a potential difference between the sides of the switching transistor ,12, an electron generated in the photodiode 2〇5 in the top of the wafer can be sufficiently dumped to the node of the floating diffusion FD131 without charge sharing. 14 200915558 That is, according to an embodiment of the present invention, a p〇/N_/p_ type well junction, rather than an N+/P-type well junction, is formed in the first substrate for active sensation in 4_Tr During the reset operation of the Active Pixel Sensor (APS), a positive voltage is applied to the N_type first conductivity type ion implantation layer ι43 of the Ρ0/Ν-/Ρ-type well junction and a ground voltage is applied to the P0. a second conductivity type ion implantation layer 145 and a p_ type second conductivity type well 141 such that the Ρ0/Ν-/Ρ-type well double junction is at a predetermined voltage or in a double junction transistor (Bipolar Juncti) 〇n Transist〇r BJT) The structure produces a pinch-off with a larger voltage. This voltage is called the closing voltage. Therefore, a potential difference is generated between the source and the drain on the side of the switching transistor Τχ121, and the charge sharing phenomenon is prevented during the opening/closing operation of the switching transistor 。. Therefore, unlike the case where the photodiode of the prior art is simply connected to the Ν+-type junction (Ν+/Ρ-well), the embodiment of the present invention can eliminate the limitation of saturation and sensitivity reduction. Moreover, according to an embodiment of the present invention, a first conductive type connection region 147 is formed between the photodiode and the readout circuit for providing a fast moving path of photocharges so as to minimize the black current source, and It can prevent saturation reduction and sensitivity reduction. To this end, in accordance with an embodiment of the present invention, a first conductive type connection region 147 for ohmic contact may be formed on the surface of the Ρ0/Ν-/Ρ-type electrical junction region 14A. At the same time, in order to prevent the first conductive type connection region 147 from becoming a leak source, the width of the first conductive type connection region 147 can be minimized. In this way, the black current of the three-dimensional (3D) image sensing 15 200915558 can be reduced. In the above embodiments, the reason why the N-type T-child is used in the contact formation region and heavily doped is that when the minimization is performed, the 转换4 is over-doped in the case of heavily doping the entire conversion transistor Tx. Si) surface counts can increase the black signal. The following is a description of the present invention in conjunction with "Figure 1" to "D2".
之影像感測器之製造方法。 J 請參閱「第1圖」，讀出電路120形成於第-基板觸的晝素 部份A上。-裝置絕緣層m形成於第—基板⑽中且用以定義 一活性區及一場區。形成有一單亓金本 Μ早凡畫素的畫素部份入及用以處理 信號的外圍部份Β形成於第一其虹 取、弟基板100的活性區中。舉例而言， 在本發明之一實施例中，讀屮雷 、 買出電路120可包含有-轉換電晶體A method of manufacturing an image sensor. J. Referring to Fig. 1, the readout circuit 120 is formed on the pixel portion A of the first substrate. - A device insulating layer m is formed in the first substrate (10) and is used to define an active region and a field region. A portion of the pixel portion of the primordial element and the peripheral portion for processing the signal are formed in the active region of the first lithography substrate 100. For example, in one embodiment of the invention, the read thunder, buyout circuit 120 can include a transposed transistor
Txl2卜一複位電晶體取123、一驅動電晶體μ⑵、以及一選擇 電晶體SX127。可形成浮置擴散區F则及具有各個電晶體的源 極/汲極區033、135、137)之離子注人區⑽。當形成讀出電 路120時，外圍部份b的電晶體電路（圖未示）可同時形成。 第基板100上形成讀出電路120可包含在第一基板1〇〇中 形成-電接面區140且在電接面區14〇上形成一與底部線路15〇 相連接的第一導電型連接區147。 電接面區140可為但不限制於一 pN型電接面區14〇。舉例而 吕，電接面區140可包含有一形成於第二導電型井141 (或第二導 16 200915558 電型外延層）上的第—導電型離子注人層143，以及—形成於第一 ，電型離子注人層143上的第二導電麵子注人層145。舉例而 。电接面區H〇可為如「第！圖」所示之洲⑽)肌⑽化⑽） 接面。在本發明之一實施例中，第—基板繼可為一第二導電型 基板。 根據本發明之一實施例，電接面區刚可形成於第一基板刚 中，在電接面區！4G㈣出電路12G _為允許在轉換電晶體The Txl2-reset transistor takes 123, a driver transistor μ(2), and a selection transistor SX127. The floating diffusion region F and the ion implantation region (10) having the source/drain regions 033, 135, 137 of the respective transistors can be formed. When the readout circuit 120 is formed, a transistor circuit (not shown) of the peripheral portion b can be simultaneously formed. Forming the readout circuit 120 on the first substrate 100 may include forming an electrical junction region 140 in the first substrate 1 and forming a first conductivity type connection on the electrical junction region 14A connected to the bottom wiring 15? District 147. The electrical junction region 140 can be, but is not limited to, a pN type electrical junction region 14A. For example, the electrical junction region 140 may include a first conductivity type ion implantation layer 143 formed on the second conductivity type well 141 (or the second conductivity 16 200915558 electrical epitaxial layer), and - formed in the first The second conductive surface on the electrotype ion implantation layer 143 is implanted with a layer 145. For example. The electrical junction area H〇 can be a (10) (10) (10) joint of the continent (10) as shown in the "Fig. In an embodiment of the invention, the first substrate may be a second conductivity type substrate. According to an embodiment of the invention, the electrical junction region can be formed just in the first substrate, in the electrical junction region! 4G (four) out circuit 12G _ is allowed to convert the transistor
Txl21的源極與汲極之間產生—電位差，以使得可充分傾卸—光 電荷。 也就是說，根據本發明之-實施例，一裝置設計為致使在轉 換電晶體Tx的雜與汲極之間產生—電位差，以使得光電荷可充 :傾卸。舉例而言’透過Ν_型第—導電型離子注入層143的推雜 /辰度小於洋置擴散區rom的摻雜濃度’此裝置設計為致使在轉 換電晶體Τχ之源極與汲極之間產生一電位差。 接下來，根據本發明之一實施例，用以歐姆接觸的第一導電 型連接區147可形成於ρ__/Ρ_型電接聽14〇之表面上。舉例而 吕’用以歐姆接觸的Ν+型第一導電型連接區147可形成於Ρ瞻暴 型電接面區140之表面上’根據本發明之—實施例，N+型第一導 電型連接區147可形成為穿過PQ型第二導電獅子注人層145及 與N-型第一導電型離子注入層143相接觸。 同時，為了防止第一導電型連接區147變為茂漏源，第一導 17 200915558 電型連接區147之寬度可最小化。為達此目的，在侧第一金屬 接觸插塞151a的過孔之後’可執行—插塞插人。細，本發明之 實施例並稀繼此，舉例的，在本發明之另—實施例中，可 形成離子注入圖案（圖夫示彳 禾丁）且然後使用離子注入圖案作為一離 子注入光罩可形成第一導電型連接區147。 根據本發明之實關，第—導電型連接區147舰於光電二 極體與讀出電路120之間用以提供一光電荷的快速移動路徑，並 且因此最小化黑電絲且防止飽和度減少及_度減少。 一夾層介電層廳可形成於第—基板綱上，並且然後形成 底赠路底部祕1M)可包含雜靴微第—金屬接觸插 塞151a第金屬151 (mi)、一第二金屬152 (M2)、一第三 金屬153 (M3)、以及一第四金屬接觸插塞15如。 各们單元旦素的底部線路15〇形成為用以將光電二極體施 〔與讀出電路120相連接且傳送光電二極體2〇5的光電荷。當形成 與嗔出電路120相連接的底部線路15〇時，可同時形成與外圍部 ~ B相連接之底部線路17〇。底部線路⑼及携可由不同的導 電材料形成，這些材料包含有金屬、合金及石夕化物。 請參閱「第2圖」，可準傷一具有結晶半導體層2〇〇的第二基 板2〇。第二基板20可為一單晶或多晶石夕基板，並且可為一摻雜有 P型雜質或η型雜質的基板。結晶半導體層例如可通過一外延 成長形成於第二基板2〇上。 18 200915558 請參閱「第3圖丨，来雷-把μ 」九尾—極體205可形成於結晶半導體層200 之内部。光電二極體2〇5 J匕含有一第一摻雜區210及一第二摻 雜區220。 第摻雜區210可透過將η型雜質注入於結晶半導體層 之深區（即最#近於第：基板的區域）形成。第：摻雜區220 1 ^將ρ 31雜纽人於結晶半導體層之淺區（即靠近於結 晶導體層之表_區域）軸。㈣—雜請及第 二摻雜區22〇形成為彼此相接觸，由此光電二極請可形成為 -有ΡΝ接面結構。因此’自光電二極體挪產生的光電荷可通 過底部線路15〇傳送至讀出電路12〇。 雖然圖未示，可透過將高濃度的η型雜質注入於第一推雜區 210的表面中形成一歐姆接觸層。而且，透過例如將ρ型雜質注入 於各個單元晝素的各個光電二極體2〇5巾，一襄置絕緣層可形成 於結晶半導體層200之内部。 由於透過離子注入光電二極體2〇5形成於結晶半導體層· 之中，因此可防止光電二極體2G5内部之缺陷且可減少產生黑電 流。 «月參閱「第4圖」’具有底部線路⑼及17〇的第一基板励 與具有結晶半導縣2〇〇的第二基板2G彼此相結合。當第一基板 100與第二基板2〇彼此相結合時，作為底部線路ls〇的第四金屬 接觸插塞154a與光電二極體205的第—摻雜區21〇電連接。 19 200915558 請參閱「第5圖」’去除第二基板20以使得光電二極體205 保留於第一基板100上。舉例而言，第二基板20可使用一刀片去 除，以使得可暴露光電二極體205。 因此，由於具有光電二極體205的結晶半導體層200保留於 第一基板1〇〇上，因此第一基板100與光電二極體205可垂直地 整合。 請參閱「第6圖」，去除結合於第一基板1〇〇上的結晶半導體 層200之以部份’以使得形成暴露夾層介電層160的與外圍部份b 相對應部份及底部線路170之頂表面的區域115。在暴露區域115 之後’光電二極體205可僅僅保留於畫素部份a上。特別地，「第 6圖」所示之光電二極體205可為第一基板1〇〇之全部區域的晝素 部份A之邊緣晝素的光電二極體205。 由於光電一極體205的咼度，畫素部份a與外圍部份b具有 局度差。因此’暴露鄰近於外圍部份B的光電二極體205之側 壁。 請參閱「第7圖」’一透明電極230可形成於第一基板1〇〇上， 其中第一基板100上形成有光電二極體205。透明電極23〇可與光 電二極體205及外圍部份B中的底部線路丨7〇電連接。舉例而言， 透明電極230可由形成氧化銦錫（IndiumTm〇xide，IT〇)、氧化錦 錫（CadmiumTin Oxide，CTO)、或氧化鋅（Zn〇2)形成。 請參閱「第8圖」，第-鈍化層240可形成於第一基板1〇〇上， 20 200915558 ，、申第基板i〇〇上形成有透明電極mo。舉例而言，第—銘化層 24〇可為-戰化層或氮化層。透過制第一銳化層施，—溝道洲 可屯成於第i化層24G t，用以暴斜圍部份^上的透明電極 230之一都你。 明，閱第9圖」，—頂部線路250可形成於溝道24i _。頂 Μ路250可由—種透明材料，例如紹⑺）、銅（⑻、欽㈤ 與/或鎢㈤形成。頂部線路25()形成於具有溝道糾的第一 鈍化層240上，頂部線路25〇用以與透明電極现並且 部線路170電連接。 贱 透過沉積—金屬層（圖未示）且使用第-純化層240作為— 餘刻停止件的平坦化過程，頂部線路㈣可與晝素區域A中的第 一純化層240的頂表面具有同樣之高度。由於形成頂部線路挪， 2除晝素部份讀_份3之_度差，因此_單地 執行一隨後的彩色濾光過程。 由於頂部線路250可選擇地形成在對應於底部線路請的透 明電極230之一部份上，因此頂部線路25〇不阻擔入射於光電二 極體205之頂表面的光線，並且因此可儘可能地保證光電二極體 2〇5的光線接收區域。 請參閱「第U)圖」，-第二純化層勘可形成於第一純化層 上，其中第一鈍化層24〇之上形成有頂部線路攻。而且，在 一單元晝素中，彩色濾光層27G可形成於第二純化層⑽的盤的 21 200915558 光電二極體205相對應之部份上。 「第U圖」及「第12圖」係為本發明之_實施例的透明電 極僅形成於晝素部份上之示意圖。 請參閱「第11圖」，透過在具有光電二極體2〇5的第一基板 上形成-透極層（®未示），並且形成此透明電極之圖案以使 得透明電極僅保留於晝素部份A上，由此可形成透明電極235。 然後，第-純化層240可形成於具有透明電極况的第一基 板100上。第-鈍化層240形成於光電二極體2〇5及外圍部份b 中的夾層介電層160上用以保護且隔離光電二極體施與底部線 路170第，冓道243及第二溝道245可形成於第一鈍化層24〇 上。第一溝道243可選擇性地形成用以暴露光電二極體2〇5的一 刀，並且第二溝道245可暴露外圍部份B中的底部線路17〇。 請參閱「第12圖」，頂部線路255形成於第一溝道243之内 部用以通過透明電極235與光電二極體2〇5電連接。而且，頂部 線路255從第一溝道243延伸至第二溝道245並且因此可與底部 線路170電連接。因此，一地面電壓可通過頂部線路255施加至 光電一極體205及底部線路170。而且，由於頂部線路255形成於 第一鈍化層240的與光電二極體205之側面相對應之一部份上， 因此頂部線路255能夠阻擋入射於光電二極體205之側面上的光 線。 「第13圖」係為本發明之另一實施例之影像感測器之橫截面 22 200915558A potential difference is generated between the source and the drain of Txl21 so that the photocharge can be fully dumped. That is, in accordance with an embodiment of the present invention, a device is designed to cause a potential difference between the impurity and the drain of the conversion transistor Tx such that the photocharge can be charged: dumped. For example, 'the doping/length of the Ν-type first conductivity type ion implantation layer 143 is smaller than the doping concentration of the ocean diffusion region rom'. This device is designed to cause the source and the drain of the conversion transistor. A potential difference is generated between them. Next, in accordance with an embodiment of the present invention, a first conductive type connection region 147 for ohmic contact may be formed on the surface of the ρ__/Ρ_ type electrical answering 14〇. For example, the Ν+-type first conductivity type connection region 147 for ohmic contact may be formed on the surface of the 暴-type electrical junction region 140. According to the present invention, the N+ type first conductivity type connection The region 147 may be formed to pass through the PQ-type second conductive lion injection layer 145 and to be in contact with the N-type first conductivity type ion implantation layer 143. Meanwhile, in order to prevent the first conductive type connection region 147 from becoming a source of leakage, the width of the first via 17 200915558 electrical connection region 147 can be minimized. To this end, the plug-in can be performed after the side first metal contacts the vias of the plug 151a. Fine, the embodiment of the present invention is inferior to this. For example, in another embodiment of the present invention, an ion implantation pattern (Toffin) is formed, and then an ion implantation pattern is used as an ion implantation mask. A first conductive type connection region 147 may be formed. According to the practice of the present invention, the first conductive type connection region 147 is driven between the photodiode and the readout circuit 120 to provide a fast moving path of photocharge, and thus minimizes the black wire and prevents saturation reduction. And _ degrees are reduced. An interlayer dielectric layer chamber may be formed on the first substrate, and then the bottom of the gift path bottom 1M) may include a miscellaneous shoe micro-metal contact plug 151a metal 151 (mi), a second metal 152 ( M2), a third metal 153 (M3), and a fourth metal contact plug 15 as. The bottom line 15 of each of the unit cells is formed to apply photodiode to the readout circuit 120 and to transfer the photocharge of the photodiode 2〇5. When the bottom line 15A connected to the extraction circuit 120 is formed, the bottom line 17A connected to the peripheral portion ~B can be simultaneously formed. The bottom line (9) and the carrier can be formed from different electrically conductive materials including metals, alloys and lithium. Please refer to "Fig. 2" to injure a second substrate 2 having a crystalline semiconductor layer 2〇〇. The second substrate 20 may be a single crystal or polycrystalline substrate, and may be a substrate doped with P-type impurities or n-type impurities. The crystalline semiconductor layer can be formed, for example, on the second substrate 2 by epitaxial growth. 18 200915558 Please refer to "Fig. 3, Ley-Pu". The nine-tailed body 205 can be formed inside the crystalline semiconductor layer 200. The photodiode 2〇5 J匕 contains a first doped region 210 and a second doped region 220. The first doping region 210 is formed by implanting an n-type impurity into a deep region of the crystalline semiconductor layer (i.e., a region closest to the first: substrate). First, the doping region 220 1 ^ ρ 31 is a person in the shallow region of the crystalline semiconductor layer (i.e., near the surface of the crystalline conductor layer) axis. (4) - The impurity and the second doping region 22 are formed in contact with each other, whereby the photodiode may be formed as a - gusset structure. Therefore, the photocharge generated by the photodiode can be transferred to the readout circuit 12A through the bottom line 15A. Although not shown, an ohmic contact layer can be formed by implanting a high concentration of n-type impurities into the surface of the first dummy pad 210. Further, an insulating layer can be formed inside the crystalline semiconductor layer 200 by, for example, injecting a p-type impurity into each of the photodiodes 2 〇 5 of each unit. Since the photodiode 2〇5 is formed in the crystalline semiconductor layer through the ion implantation, defects inside the photodiode 2G5 can be prevented and black current can be reduced. «Monthly, refer to "Fig. 4". The first substrate having the bottom lines (9) and 17 turns and the second substrate 2G having the crystalline semiconductors 2 are bonded to each other. When the first substrate 100 and the second substrate 2 are bonded to each other, the fourth metal contact plug 154a as the bottom line ls is electrically connected to the first doping region 21 of the photodiode 205. 19 200915558 Please refer to "Fig. 5" to remove the second substrate 20 so that the photodiode 205 remains on the first substrate 100. For example, the second substrate 20 can be removed using a blade such that the photodiode 205 can be exposed. Therefore, since the crystalline semiconductor layer 200 having the photodiode 205 remains on the first substrate 1 , the first substrate 100 and the photodiode 205 can be vertically integrated. Referring to FIG. 6, the portion of the crystalline semiconductor layer 200 bonded to the first substrate 1 is removed to form a portion corresponding to the peripheral portion b and the bottom portion of the exposed interlayer dielectric layer 160. The area 115 of the top surface of 170. After the exposed region 115, the photodiode 205 may remain only on the pixel portion a. In particular, the photodiode 205 shown in Fig. 6 may be the photodiode 205 of the edge element of the halogen portion A of the entire region of the first substrate. Due to the twist of the photodiode 205, the pixel portion a and the peripheral portion b have a difference in degree. Therefore, the side walls of the photodiode 205 adjacent to the peripheral portion B are exposed. Referring to FIG. 7 , a transparent electrode 230 may be formed on the first substrate 1 , wherein the photodiode 205 is formed on the first substrate 100 . The transparent electrode 23A can be electrically connected to the photodiode 205 and the bottom line 丨7〇 in the peripheral portion B. For example, the transparent electrode 230 may be formed of indium tin oxide (IT), cadmium Tin Oxide (CTO), or zinc oxide (Zn 〇 2). Referring to FIG. 8 , the first passivation layer 240 may be formed on the first substrate 1 , 20 200915558 , and the transparent substrate mo is formed on the substrate. For example, the first inscribed layer 24 can be a warfare layer or a nitride layer. By applying the first sharpening layer, the channel can be formed into the i-th layer 24G t, and one of the transparent electrodes 230 on the slanting portion is used. Ming, see Figure 9," the top line 250 can be formed in the channel 24i_. The top turn 250 may be formed of a transparent material such as shovel (7), copper (8), chin (5), and/or tungsten (five). The top line 25 () is formed on the first passivation layer 240 having channel correction, the top line 25 〇 is used to electrically connect with the transparent electrode and the line 170. 贱 Through the deposition-metal layer (not shown) and using the first-purification layer 240 as a planarization process of the residual stopper, the top line (four) can be combined with the halogen The top surface of the first purification layer 240 in the region A has the same height. Due to the formation of the top line shift, 2 the enthalpy fraction is read _ _ _ _ degree difference, so _ single execution of a subsequent color filter process Since the top line 250 is selectively formed on a portion of the transparent electrode 230 corresponding to the bottom line, the top line 25 does not block the light incident on the top surface of the photodiode 205, and thus can be exhausted It is possible to ensure the light receiving area of the photodiode 2〇5. Please refer to the “U” diagram, and the second purification layer may be formed on the first purification layer, wherein the first passivation layer 24 is formed thereon. Top line attack. Further, in a unit of the halogen, the color filter layer 27G may be formed on a portion of the 21 200915558 photodiode 205 of the disk of the second purification layer (10). "U-shaped diagram" and "12th diagram" are schematic diagrams in which the transparent electrode of the embodiment of the present invention is formed only on the halogen component. Please refer to FIG. 11 to form a transflective layer (® not shown) on the first substrate having the photodiode 2〇5, and form a pattern of the transparent electrode so that the transparent electrode remains only in the halogen. On the portion A, the transparent electrode 235 can be formed thereby. Then, the first purification layer 240 may be formed on the first substrate 100 having a transparent electrode condition. The first passivation layer 240 is formed on the interlayer dielectric layer 160 of the photodiode 2〇5 and the peripheral portion b for protecting and isolating the photodiode from the bottom line 170, the via 243 and the second trench. A track 245 can be formed on the first passivation layer 24A. The first channel 243 is selectively formed to expose a photodiode 2〇5, and the second channel 245 is exposed to the bottom line 17〇 in the peripheral portion B. Referring to Fig. 12, a top line 255 is formed inside the first trench 243 for electrically connecting to the photodiode 2〇5 through the transparent electrode 235. Moreover, the top line 255 extends from the first channel 243 to the second channel 245 and is thus electrically connectable to the bottom line 170. Therefore, a ground voltage can be applied to the photodiode 205 and the bottom line 170 through the top line 255. Moreover, since the top line 255 is formed on a portion of the first passivation layer 240 corresponding to the side of the photodiode 205, the top line 255 can block the light incident on the side of the photodiode 205. Figure 13 is a cross section of an image sensor according to another embodiment of the present invention 22 200915558
…請參閱「第13圖」，此影像感測器可包含有一第一基板謂， 第基板100中包合有一底部線路⑼及一讀出電路哪以及讀 出電路120上的光電二極體2〇5。一電接面區刚可形成於第一基 板100中且與底部線路150相連接之N+型連接區148可形成於電 接面區140的側面。 本實施例可採用「第1圖」至「第1·」之實施例的技術特 徵。 根據本發明之本實補，—裝置設計為使得在賴電晶體 之側面的源極與汲極之間產生—電位差，致使光電荷可被充分地 傾卸。因此，由於光電二極體產生的光電荷可被充分傾卸至浮置 擴散區FD131 ’因此，可增加輸出影像的敏感度。 而且，一電荷連接區形成於光電二極體與讀出電路之間，用 以提供-光f荷的快速軸路徑’峨得最小化—黑f流源，並 且可防止飽和度的減少及敏感度的減少。 與「第1圖」之實施例之不同的地方在於，N+型連接區148 形成於電接面區140之側面。 根據本實施例，用作歐姆接觸的N+型連接區148可形成於 Ρ0/Ν-/Ρ-型電接面區14〇之側面。在這一方面，因為裝置使用與 Ρ0/Ν-/Ρ-型電接面區14〇反向之偏壓而作業且因此可在矽（別）表 面產生一電場EF，因此形成N+型連接區148及M1C第一金屬接 23 200915558 觸插塞151a之過程可產生，漏源。這是因為在電場中形成接觸 期間，產生的晶體缺陷可用作洩漏源。 因此，根據本實施例，在N+型連接區148形成於p〇/N_/p_s 電接面區140之表面上的情況下，可由於讲胸型接面i48/⑷ 增添一電場，此電場也可用作一洩漏源。 因此，一第一金屬接觸插塞151a可形成於沒有與ρ〇區一起 摻雜但是包含有N+型連接區148的活性區上。然後，第—金屬接 觸插塞151a通過N+型連接區148與N_型第一導電型離子注入層 143電連接。 因此’在本實施财’树表面不產生電場，這有助於減少 三維（3D)結合的互補金氧半導體影像感測器（cis)的黑電流。 本„兒明書所提及之// 一實施例夕、r/示例性實施例具體 實施’等表示與本實施例相關之具體的特徵、結構或特性包含 於本發明之至少—實施例中。在本說明書中不同位置出現的此= 詞語並不-定表示同—實施例。而且，具體的特徵、結構或 特性描述為與任何實關_時，本領域之技術人員應當意識到 這些特彳玫、結構或特性可與其他實施例相關。 雖然本發明之實關財例性之實施觸露如上，然而本領 域之技術人員應當意識到在不脫離本發明所附之申請專利範圍所 揭不之本判之精神和範_情況下，所作之更動與㈣，均 本兔明之專利保護麵之内。制是可在本說明書、圖式部份及 24 200915558 申請專利範圍中進行構成部份與麟方式的不同變化 及修改。除了構成雜與合方式_化及修改外，本^ 之技術人員也應當意铜構成部份與/或組合方柄交替使用。 【圖式簡單說明】 第1圖至第I2圖係為本發明一實施例之影像感測器之製造過 程之橫截面圖；以及 第13圖係為本發明另一實施例之影像感測器之局部乔意圜。 【主要元件符號說明】 20 苐二基板 100 第一基板 110 裂置絕緣層 115 區域 120 讀出電路 121 轉換電晶體Tx 123 複位電晶體Rx 125 驅動電晶體Dx 127 選擇電晶體Sx 130 離子注入區 131 浮置擴散區FD 133 、 135 、 137 源極/没極區 140 電接面區 25 200915558 141 第二導電型井 143 第一導電型離子注入層 145 第二導電型離子注入層 147 第一導電型連接區 148 N+型連接區 150 、 170 底部線路 151 ' Ml 第一金屬 151a 第一金屬接觸插塞 152 > M2 第二金屬 153、M3 第三金屬 154a 第四金屬接觸插塞 160 夾層介電層 200 結晶半導體層 205 光電二極體 210 第一摻雜區 220 第二摻雜區 230 ' 235 透明電極 240 第一鈍化層 241 溝道 243 第一溝道 245 第二溝道 26 200915558 250 ' 255 頂部線路 260 第二鈍化層 270 彩色濾光層 A 晝素部份 B 外圍部份 27...refer to FIG. 13 , the image sensor may include a first substrate. The substrate 100 includes a bottom line (9) and a readout circuit, and the photodiode 2 on the readout circuit 120. 〇 5. An N+-type connection region 148, which may be formed in the first substrate 100 and is connected to the bottom wiring 150, may be formed on the side of the electrical interface region 140. This embodiment can adopt the technical features of the embodiments of "1st" to "1st". According to the present invention, the device is designed such that a potential difference is generated between the source and the drain of the side of the photovoltaic cell, so that the photocharge can be sufficiently dumped. Therefore, since the photocharge generated by the photodiode can be sufficiently dumped to the floating diffusion region FD131', the sensitivity of the output image can be increased. Moreover, a charge connection region is formed between the photodiode and the readout circuit for providing a fast axis path of the -photof charge to minimize the black f flow source, and to prevent saturation reduction and sensitivity. Degree reduction. The difference from the embodiment of "Fig. 1" is that the N+ type connection region 148 is formed on the side of the electrical junction region 140. According to the present embodiment, the N + -type connection region 148 serving as an ohmic contact can be formed on the side of the Ρ0/Ν-/Ρ-type electrical junction region 14A. In this respect, since the device operates using a bias voltage that is opposite to the Ρ0/Ν-/Ρ-type electrical junction region 14〇 and thus an electric field EF can be generated on the surface of the 矽 (other), an N+ type connection region is formed. 148 and M1C first metal connection 23 200915558 The process of touching plug 151a can generate, leak source. This is because crystal defects generated during the formation of contact in the electric field can be used as a source of leakage. Therefore, according to the present embodiment, in the case where the N+ type connection region 148 is formed on the surface of the p〇/N_/p_s electrical junction region 140, an electric field can be added due to the chest type junction i48/(4), and the electric field is also Can be used as a source of leakage. Therefore, a first metal contact plug 151a can be formed on the active region which is not doped with the ρ 〇 region but which contains the N + -type connection region 148. Then, the first metal contact plug 151a is electrically connected to the N-type first conductivity type ion implantation layer 143 through the N+ type connection region 148. Therefore, no electric field is generated on the surface of the present implementation tree, which contributes to reducing the black current of the three-dimensional (3D) bonded complementary MOS image sensor (cis). The specific features, structures, or characteristics associated with the present embodiment are included in at least the embodiments of the present invention, as referred to in the present specification, in the embodiment, the r/exemplary embodiment, and the like. The appearances of the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The present invention may be related to other embodiments. While the actual implementation of the present invention is disclosed above, those skilled in the art will recognize that the invention is not disclosed in the scope of the appended claims. In the case of the spirit and scope of the judgment, the changes and (4) are all within the patent protection of the rabbit. The system can be constructed in the scope of this specification, the schema and the application scope of 24 200915558. Different changes and modifications of the lining method. In addition to the composition and modification of the hybrid mode, the technicians of this technology should also use the copper component and/or the combination of the square handles alternately. 1 to 12 are cross-sectional views showing a manufacturing process of an image sensor according to an embodiment of the present invention; and FIG. 13 is a partial image of an image sensor according to another embodiment of the present invention.主要 [Main component symbol description] 20 基板 two substrate 100 first substrate 110 cleavage insulation layer 115 region 120 readout circuit 121 conversion transistor Tx 123 reset transistor Rx 125 drive transistor Dx 127 select transistor Sx 130 ion Injection region 131 Floating diffusion region FD 133 , 135 , 137 Source/polarization region 140 Electrical junction region 25 200915558 141 Second conductivity type well 143 First conductivity type ion implantation layer 145 Second conductivity type ion implantation layer 147 One conductive type connection region 148 N+ type connection region 150, 170 bottom line 151 'Ml first metal 151a first metal contact plug 152 > M2 second metal 153, M3 third metal 154a fourth metal contact plug 160 interlayer Dielectric layer 200 crystalline semiconductor layer 205 photodiode 210 first doped region 220 second doped region 230' 235 transparent electrode 240 first passivation layer 241 channel 243 first channel 245 Second channel 26 200915558 250 ' 255 Top line 260 Second passivation layer 270 Color filter layer A Alizarin part B Peripheral part 27