TW200915072A - Managing housekeeping operations in flash memory - Google Patents

Abstract

A flash re-programmable, non-volatile memory system is operated to disable foreground execution of housekeeping operations, such as wear leveling and data scrub, in the when operation of the host would be excessively slowed as a result. One or more characteristics of patterns of activity of the host are monitored by the memory system in order to determine when housekeeping operations may be performed without significantly degrading the performance of the memory system, particularly during writing of data from the host into the memory.

Description

200915072 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to the operation of non-volatile flash memory systems, and more particularly to routine operations (such as wear and tear) in such memory systems. The technique of leveling and data removal). [Prior Art] There are many commercially successful non-volatile memory products in use today (especially in the form of removable cards or embedded modules of smaller form factor), the use of which is formed in one or more Fast lightning on an integrated circuit chip can erase an array of programmable read only memory (EEPR0M) cells. A memory controller (usually (but not necessarily) located on a separate integrated circuit chip) is included in the memory system to interface with a host to which the system is coupled and to control the memory array within the card operating. The controller typically includes a microprocessor, a non-volatile read-only memory (ROM), a volatile random access memory (RAM), and one or more dedicated circuits (such as when the data is in the data) A special circuit for calculating an error correction code (ECC) from the data when stylizing and reading through the controller. Other memory cards and embedded modules do not include this controller, but the host to which it is connected includes software that provides controller functionality. The memory system in the form of a card includes a connector that mates with a receptacle external to the host. On the other hand, it is not intended to remove the memory system embedded in the host. Some commercially available memory cards, including controllers, are sold under the following trademarks: CompactFlash(CF) > MultiMedia(MMC) 'Secure Digital(SD)^ MmiSD, Mlcr〇SD and TransFlash. Does not include the memory system of the controller 131567.doc 200915072 One example is a SmartMedia card. All such cards are available from SanDisk Corporation (the transferee). Each of these cards has a mechanical and electrical interface with the host device to which it is removably connected. Another type of small, handheld flash memory device includes a flash drive that interfaces to a host via a standard universal serial bus (USB) connector. Corporation provides such equipment under its Cruzer trademark. Hosts for memory cards include personal computers, notebook computers, personal digital assistants (PE>A), various data communication devices, digital cameras, cellular phones, portable audio players, car audio systems, and similar types of equipment. . The flash drive works with any host that has a USB jack, such as a personal computer and a notebook. Two general purpose memory cell array architectures (reverse (N〇R) and inverse (NAND)) have commercial applications. In a typical N〇R array, the memory cell is connected between the adjacent bit line source diffusion region and the drain diffusion region extending in the row direction, wherein the control gate is connected to the word line extending along the column of cells . A memory cell includes at least one storage element positioned on at least a portion of the cell channel region between the source and the drain. The stylized levels of the charge on the memory elements thus control the operational characteristics of the cells, which can then be read by applying an appropriate voltage to the addressed memory cells. Examples of such units, which are in a memory system, are given in U.S. Patent Nos. 5,070,032, 5,095,344, 5,313,421, 5,315,541, 5,343, 〇63, 5,661, 053, and 6,222,762. Use and its manufacturing method. The NAND array utilizes a series string having two or more memory cells (such as 16 or 131567.doc 200915072 32), and the memory cells and one or more selection transistors are connected to the individual bit lines and one The reference potentials form a row of cells, and the lines extend across a large number of cells within the rows. During the stylization, the individual orders in the order are read and verified by causing the remaining cells of the string to be stably turned on so that the current flowing through the string is read according to the level of the charge in the single S of the storage address. . U.S. Patent Nos. 5,57,315, 5,774,397, 6,046,935, 6,373,746, 6,456,528,

Examples of architectural arrays and their operation as part of a memory system are found in 6'522, 580, 6, 771, 536, and 6,781, 877. As discussed in the prior referenced patent, the charge storage element of the flash front EEpR(R) M array is the most commonly used conductive floating gate, which is typically formed of a conductively doped smectite material. The 6-replica unit of the #代型 type that can be used in the flashing eepr〇m system uses a non-conductive dielectric material instead of the conductive floating gate to store the charge in a non-volatile manner...from oxidized oxide, nitrogen The three-layer dielectric formed by cutting and oxygen cutting is sandwiched between a conductive control gate and a surface of the semiconductive substrate located above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitrogen (tetra) (the electrons are trapped in the nitride and stored in a finite region) and is erased by injecting a thermoelectric hole into the nitride. Several specific element structures and arrays using dielectric storage elements are described in U.S. Patent No. 6,925,0G7. For example, in all integrated circuit applications, the fast EEPROM memory array also has the pressure to reduce the area of the substrate required to implement the function of the integrated body. Continued need to increase the storage area that can be stored in a given area of 16 substrates.

The amount of digital data is used to increase the storage capacity or increase the capacity and size of memory cards of other sizes and other types of packages. One way to increase the storage density of the data is to store more than one poor bit per memory unit and/or per storage unit or component. This is achieved by dividing the storage element charge level voltage range window into two or more states. Using four of these states allows two data bits to be stored per unit, one state allows three data bits to be stored per storage element, and so on. U.S. Patent No. 5, pp. 43, 9 and 5, 172, 338 describes a multi-state flash EEPR 〇M structure for operation of a feed gate and its operation, and the above-mentioned U.S. Patent No. M25 The structure using a dielectric floating interpole is described in G()7. A multi-state memory can also be operated in two states (binary) in the manner described in U.S. Patent Nos. 5,93,167 and M56,528 for various reasons: Selected portions of the cell array . The memory cell of a typical flash EEPR0M array is divided into discrete blocks of the same erased cell. That is, the block is the smallest number of units that can be erased at the same time. Each block is usually stored—or multiple pages. The page is the smallest unit of stylization and reading, but can be programmed or read more than one page in parallel in the same subarray or plane. Each page - or multiple data sections, where the size of the section is defined by the host system. - The instance section includes 512 user data bytes (following the standards established by the disk drive) plus a certain number of additional information bytes for the user's material and/or the block in which it is stored. These memories typically have 16, 32 or more pages in each block, and each page stores one or only a few host data segments. 131567.doc 200915072 To increase the degree of parallelism during the programming of user data into and from the memory array, the array is typically divided into sub-arrays (often referred to as planes), which The subarray contains its own data register and other circuitry to allow parallel operation such that several data sections can be simultaneously programmed into each of several or all planes or from each of several or all planes simultaneously Read several data areas 1. One of the array entities on a single integrated circuit can be divided into planes, or each plane can be formed by one or more integrated circuit wafers. An example of the implementation of this memory is described in U.S. Patent Nos. 5,798,968 and 5,890,192. To further efficiently manage memory, blocks can be linked together to form a virtual block or a metablock. That is, each metablock is defined to include one block from each plane. The use of metablocks is described in U.S. Patent No. 6,763,424. The physical address of the unary block is determined as a destination for stylizing and reading data by translation from a logical block address. Similarly, all blocks of a unitary block can be erased together. The controller in the memory system operated by such large blocks and/or metablocks performs a number of functions, including a logical block address (LBA) received from the host and a physical area within the memory cell array. Translation between block numbers (PBn). Individual pages within a block are typically identified by an offset within the block address. Address translation typically involves the use of logical block numbers (LBNs) and logical page inter-term terms. Operating a large block or metablock system while maintaining some extra blocks is common in the erased block set. When updating "or multiple pages" that are smaller than the capacity of a block, the typical practice is to write the updated page to __ 131567.doc 200915072 from the erased block of the pool, and then from the original The block copy does not change the data of the page to erase the block. Variations of this technique are described in U.S. Patent No. 6,763,424, incorporated herein by reference. Over time, as the host profile is rewritten and updated, many of the blocks may eventually have a relatively small number of pages containing valid data and the remaining pages containing material that is no longer current. In order to be able to effectively use the data storage capacity of the array, the logically relevant pages of valid data are from time to time in segments of multiple blocks.

Gather together' and are merged together into a smaller number of blocks. This process is often referred to as "waste collection". When a significant amount of data in a single block or metablock becomes obsolete, the data within the block can also be compressed. This involves copying the remaining valid data of the block into a blank erased block and then erasing the original block. The copy block contains valid data from the original block plus the erased storage capacity previously occupied by the obsolete data. It is also common to arrange valid data in the logical block in a logical order, thereby making data reading easier. Control data for the operation of the memory system is typically stored in one or more reserved blocks or metablocks t. Such control information includes operational stylization and erase voltage, file directory information and block configuration information). As much information as is required to have the controller operate the memory system at a given time is also stored in RAM and then written back to (4) memory during the update.

body. Frequent updates of control data result in frequent compression and/or waste collection of ant retention & If there are multiple reserved blocks, then the melon (1) Μ triggers the scrap collection of two or more reserved blocks. Α _ 杲 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免 避免Such preemptive data relocation techniques are described in U.S. Patent Application Publication No. 2005/0144365 A1. It can also be executed when the user data update block becomes almost full and waits until its change is fully loaded and triggered. It must be immediately before the data provided by the host can be written to the memory. Expanded waste collection operations. & In some memory systems, 'physical memory cells are also grouped into two or more regions. A region may be any partitioned subset of physical memory or memory system to which the specified range of logical block addresses is mapped. For example, a memory system capable of storing 64 megabytes of data can be divided into two regions, each of which stores (four) bytes of data. The range of logical block addresses is then also divided into four groups, one group being assigned to the physical block of each of the four areas. In a typical implementation, limiting the logic block bits

The address is such that each of the data is not written to the outside of the single physical area to which the logical block address is mapped. In a memory cell array divided into planes (sub-arrays), each of which has its own addressing, stylization and reading circuitry, each zone preferably includes blocks from multiple planes. Includes the same number of blocks from each of the planes). The area is primarily used to simplify address management (such as logical-to-entity translation), resulting in smaller translation tables, less ram memory required to hold these tables, and faster storage of the current active area of the addressed memory. Taking time, <den because of its restrictive nature' can result in less than optimal wear leveling. The individual fast EEPROM cells store a certain amount of charge representing one or more data bits in a charge store (four) or cell. The storage element is electrically 13I567.doc 200915072 The level control is 愔 _ _ The hidden voltage of the hidden body (4)* is used as the base for reading the single state: as: ;^ The threshold voltage window is divided into the eve Plus _ 将 often use one or two ranges for each of the storage units of the memory unit to protect the two units. These ranges are protected by the sensational sensation The storage of the element is straight... '立>. These storage levels are shifted due to charge disturbing stylized erase operations performed in adjacent or 2 mesh delta memory cells, pages or blocks. Therefore, the controller f is used to calculate the error correction code, which is stored together with the host data. The host data is read by the program 1 in the reading _ heart Wei (four) pure line difficulty i (if necessary). 快 flash memory The responsiveness of a unit typically changes over time based on the number of times the unit is erased and reprogrammed. This is considered to be a small amount of charge trapped in a storage element layer during each wipe: and/or reprogramming operation. The result 'this charge accumulates over time. This Usually, the memory cell becomes less reliable, and as the memory cell ages, a higher voltage can be used for erasing and programming. The programmable memory state can also be used to limit the voltage window. This is the case, as described in National Patent No. 5, 26M7G. The result is a memory unit: a limited effective service life; that is, the 'memory unit block is only subjected to the pre-set before being mapped-system The number of erase and reprogramming cycles. First, the number of cycles that the flash memory block needs to undergo depends on the memory cell = structure, the amount of threshold window used to store the state, usually with increasing every morning The number of storage states is increased by the range of the threshold window. Depending on the factors such as 131567.doc -12- 200915072, the number of life cycles can be as low as 100,000 or even up to 100,000 or even Hundreds of thousands. f

L. If it is deemed necessary to track the number of cycles experienced by the memory cells of an individual block, it may be incremented each time the block is erased for each block or for each of a block group The counts are as described in U.S. Patent No. 5,268,87, the disclosure of which is incorporated herein by reference. Material (4) may be stored in each block (as described elsewhere), or this count may be stored in a separate block along with other additional information, as described in U.S. Patent No. 6,426,893. In addition to its use to map a block out of the system when it reaches a maximum lifetime cycle count, the count can be used earlier to control erasure and stylization as the memory block ages. parameter. And U.S. Patent No. 6,345,0 (the number describes the technique of updating the number of cycles in the occurrence of random or pseudo-random events - the technique of compressing counts) rather than the exact previous number of cycles: the description describes several options to be The block of data readout and the block of data to be copied beforehand to make the adjustable block block (I can be based on the number of erased materials (4) or can be only random or decisive. ...) to select. Another periodic routine operation is to read h except for the description, which is composed of the assets that are scanned in the normal host command and are not read during the binding period, and there is a possibility. The wind of data degradation cannot be corrected by the ECC algorithm method. The risk cannot be detected before / or the degree of reading. / No (four) limit [invention content] Usually need to rely on a certain schedule to benefit Necessary - or multiple routine operation tables: ::: 1 line specific commands are not maintained - the flash memory system has 131567.doc 200915072 effective operation to accurately store and retrieve data during a longer life. Examples of line operations include wear leveling, capital Renew (clear), waste collection, and nurturing. It is better to do this in the background (ie, when predicting 2 or the known host will be in sufficient time for the interval). When the host sends a two-set command This situation can be known, and this situation can be foreseen when the host has been inactive for a duration of time, such as one millisecond. In the background, the execution system will only partially complete the routine, or in the memory system, In the case of receiving a command from the host before completing the background operation, 2 needs to abort the routine operation. It will take a while to terminate the ongoing routine operation' and thus delay the execution of the new host command. Performing a sufficient number of routine operations sufficiently frequently to maintain proper operation of the m system, then proceeding to the routine in the foreground, that is, although the host can prepare to send a command but the memory system tells the host that it is busy until 6 > , and the main operation of the master is executed.) When the receipt of a command and/or the execution of the fly is delayed in this way, the effect of the memory system is therefore adversely affected. Recall that the system has slowed down the data and transferred the data to the rate at which it was transferred from the S. In many commands & - 实例, the instance host command includes writing data to the memory, self-reporting < § § reading the back of the 5 - Bu - \ 胄 抹 and erasing the memory unit block. During the operation of the hall and the subscription, the memory system will interrupt the operation of this command, and the 1 -& 7 I reception will be performed. A small delay in the foreground center to terminate or postpone the operation can prevent the host from sending this command until & into the operation or at least & & C C C 。 。 4 completion will be postponed without having to start again 131567.doc -14- 200915072 To minimize these adverse effects, the memory system preferably monitors the host's mode of stay to determine whether it is in the background or in the foreground Execution of routine operations. If the host is in the process of quickly transferring a large amount of continuous data through the memory (such as blocking the streaming data of the audio or video data to write or read the illusion, then it can defer or postpone a certain routine operation. Similarly If the main f# is sent with a very short time delay gap to send a command or data, then the display host is using _ fast mode to indicate that it needs to push or go to any determined routine operation. Late 'will enable the routine operation when the data is non-continuous or in a smaller amount when the data is transferred or when the host delay gap increases. 乂 This way, allows the system to transfer data at a high rate or In addition: fast mode operation (when the user expects to do so). = avoid interruption caused by - routine operation. Because of the small: material transfer operation is more demanding for execution - some routine operations, so in ! Two: Two data transfer is not allowed during these routine operations, there is a small penalty (penalty). When the host mode allows, first enable the routine to perform in the f scene ί 不 不 ^) ' because This is usually effective for the system Can have minimal adverse effects. In the context of the limitations discussed above, the fall is completed quickly enough: read, then at the front desk under similar restrictions = 乍. This in turn provides a competitive advantage (that is, the need to perform a routine operation to write and read - some data) - the consideration factor is the amount of available power. In systems or applications that save power, for this reason, significant restrictions or even I31567.doc 200915072 are not allowed to perform routine operations. The following description: Additional grievances, advantages, and characteristics are included in the field of its illustrative examples, which should be understood in conjunction with the accompanying drawings. All patents, patents, patents, papers, books, etc., which are referenced in the specification, are incorporated herein by reference in its entirety for all purposes. The definition or use of the terms is incorporated Any inconsistency between the disclosure, the literature, etc. and the text of this document f. %

• The extent to which the dog is born or washed. The definition or use of this term in this document should prevail. [Embodiment] Memory Architecture and Operation First, referring to Fig. 1A, a flash memory includes a memory cell array and a controller. In the illustrated example, two integrated circuit devices (wafer and 13 include a memory cell array 15 and various logic circuits 17. The logic circuit 17 is coupled to the controller 1 on a separate wafer via data, command and status circuits. 9 interface, and also provides addressing, data transfer and sensing, and other support to the array 13. The number of memory array chips can range from one wafer to many wafers depending on the storage capacity provided. Alternatively, the controller And a portion or the entire array is combined onto a single integrated circuit die, but this is not currently an economical alternative. A flash memory device that relies on the host to provide controller functionality contains only memory volume circuit devices 11 and 13. A typical controller 19 includes a microprocessor 21, a read only memory (ROM) 23 for storing a memory, and a main memory for temporarily storing writes to the memory chips 11 and 13 or from the memory chip 11. And 13 read the user data 131567.doc -16 - 200915072 buffer memory (RAM) 25. The circuit 27 is interfaced with the (etc.) memory array chip, and the circuit 29 is connected 31. Interfacing with the host. In this example, the integrity of the 2 families is determined by computing the code using circuit 33 dedicated to calculating the ECC. When the user data is transferred from the host to the flash memory array When storing, the circuit calculates Ecc from the data and stores the code in the money body. When the user data is read from the memory later, it is again passed through the circuit 33 'the circuit 33 by the same algorithm Calculate the coffee, and compare the code to the code calculated and stored with the data. If the phase is 2, the integrity of the data is confirmed. If it is different, it can be identified by the specific ECC algorithm used. And correct their error bits (up to the number supported by the algorithm). The connection 31 of the memory of Figure 1A is coordinated with the host system (the connection of the real (4) is given in Figure ib. The host of Figure 1A The transfer of data to and from the memory is performed via interface circuitry 35. A typical host also includes a microprocessor 37, a ROM 39 for storing the Lexon code, and its circuitry and subsystem 43 are typically Host system and including a high Capacity magnetic data storage disk drive, interface circuit for keyboard, a monitor and the like. Some examples of such hosts include desktop computers, laptop computers, handheld computers, palmtop computers, personal computers. Digital Assistant (PDA), MP3 and other audio players, digital cameras, video cameras, electronic game consoles, wireless and wired telephone devices, answering machines, voice recorders, network routers and others. Memory of Figure 1A The implementation of the helmet 3 & _ ' is a 131567.doc 200915072 wide-type closed memory card or flash drive containing the controller and all of its memory array circuit devices in a form removably connectable to the host of FIG. 1B . That is, with the connections 31 and 31, the card is allowed to be disconnected and moved to another host, or by connecting another card to the host. Alternatively, the memory array device u and (4) can be closed in a separate card that can be electrically connected and mechanically connected to the controller and the connection 31. As another alternative, the memory of the figure can be embedded in the figure. In the host of m, the connections 31 and 31 are permanently formed. In this case, the memory is usually contained in the casing of the host together with other components. The inventive concept can be implemented in a system having various specific configurations. Techniques, examples of which are given in Figures 2 to 6. Figure 2 illustrates a σ Ρ 记忆 of a memory array in which 5 hex elements are grouped into blocks, and the cells in each block can be used as a single erase operation. The parts are usually erased together at the same time. The block is the minimum erase unit. The size of the individual memory unit blocks of Figure 2 can vary, but a commercial practice form includes a single data section in individual blocks. Explain that this material Q #又之谷. User data 5 1 is usually 5 12 bytes. The additional information except the user data 5 1 includes the ECC 53 from the user data. And section data and/or stylized in it The block-related parameters 55 of the segment and an ECC 57 calculated from parameter 55 and any other additional information that may be included. Alternatively, a single ECC may be calculated from all user data 5 and parameter 55. Including an amount associated with the number of stylized/erase cycles experienced by the block 'this amount is updated after each cycle or a certain number of cycles. When this amount of experience is used in a wear leveling algorithm, Logical block addresses are regularly remapped to different physical location addresses to equalize the use (wear) of all blocks 131567.doc -18- 200915072. Another use of this experience is based on experience by different segments The number of cycles to change the voltage and other parameters of stylization, reading, and/or erasing. Parameter 55 may also include an indication of one of the bit values assigned to each of the storage states of the memory unit (usually called For this, there is also a beneficial effect in the wear leveling. The parameter 55 can also include - or a plurality of indication states «. It can also be used for stylized and / or erased areas Block voltage level The indication is stored in parameter 55, which is updated as the number of cycles experienced by the block and other factors change. Other examples of parameter 55 include identification of any defective cells within the block, mapping to the physical block The logical address of the block in the middle and the address of any alternative block in the case where the main block is defective. The specific combination of parameters 55 used in the any-memory system will: vary according to design. Some or all of the additional data may be stored in a block dedicated to this function, rather than being stored in a block containing user data or additional data associated with it. The multi-section block of Figure 4 is different from Figure 2 The single data sector block. An instance block 59 (still the minimum erase unit) has four pages, and each of the pages (2) is the smallest stylized unit. One or more host data segments are typically stored in each page along with additional material including at least the ECC calculated from the segment data, and may be in the form of a data segment of FIG. Rewriting the entire block usually involves programming the new data into the erased block of the erased block pool. Then the original block is erased and placed in the erased set. When updating - less than all pages of the block, the updated data is usually stored in the erased area from the erased block I31567.doc 19 200915072

In the page of the block' and copy the data from the remaining unchanged pages from the original block to the new block. Then erase the original block. Alternatively, new material can be written to the update block associated with the > updated block and the update block kept open for as long as possible to receive any further updates to the block. When the update block has to be closed, the valid data located in the update block and the original block is copied into a single copy block in a garbage collection operation. Such large block management techniques typically involve writing updated data to pages of another block without moving data from the original block or erasing the block. This results in multiple data pages having the same logical address. The most recent material page can be identified by some convenient technique, such as stylized time recorded as a field or page attachment in a section.圑3甲 illustrates another more ~. w m m body unit array entity is divided into two or more planes (where four planes 说明 3 are illustrated) one sub-array of each plane memory unit, which has its own The data registers, sense amplifiers, address decoders, and the like are not capable of operating largely independently of other planes. All planes k can be supplied to an earlier integrated circuit device or to multiple devices. Each block in the example system of Figure 5 contains 16 pages p〇_pi5, each page having -: or more than two host data segments and some additional resources;;: 〇, the planes Formed on a single integrated circuit:: on the wafer. If formed on a plurality of wafers, the core SC is formed on one wafer and the other two planes are formed on the other or the memory cells on one wafer can be recalled in the plane of the body... Wait for the day and day. ~等记 131567.doc -20- 200915072 Another memory unit configuration is illustrated in FIG. Each plane contains a large number of unit blocks. To increase the degree of parallelism of operations, blocks in different planes are logically linked to form metablocks. One of the metablocks is illustrated in Fig. 6 as being formed by block 3 of plane 0, block 1 of plane 1, block 1 of plane 2, and block 2 of plane 3. Each metablock is logically addressable, and the memory control 1 § assigns and tracks blocks that form individual metablocks. Preferably, the host system interfaces with the memory system in units of data equal to the capacity of the individual metablocks. The logical data block 61 of Fig. 6 is identified, for example, by a logical block address a) which is mapped by the controller to the physical block code (PBN) of the block constituting the metablock. All blocks of the metablock can be erased together, and at the same time, the pages from each block are preferably programmed and read. There are many different memory array architectures, configurations, and specific cell structures that can be used to implement the memory described above with respect to Figures 2-6. A block of a NAND type memory array is shown in FIG. A plurality of row-oriented strings having serially connected memory cells are connected between a common source of voltage vss "with one of = element lines BL0-BLN, which in turn is decoded with address bits" A circuit 67 of a driver, driver, sense sense amplifier, and the like is coupled. Specifically, one such string contains charge storage cells connected in series between select transistors 77 and 79 at opposite ends of the strings. The crystals are 7〇, 71·.... 72 and 74. In this example, each string contains 16_ storage days, but other numbers are possible. The word line wlq_wli5 extends across one of each string. The crystal is coupled to a circuit 81 having a voltage source driver for the address decoder and the line. The voltages on lines 83 and 84 together control all of the strings in the control block via the transistor to the voltage source 65 and/or 131567. Doc 200915072 Line blo-bln connection. The data and address are from the memory controller. Each column of the charge storage transistor (memory unit) of the block contains one or one page, and the data of each page is programmed together. And read. Apply an appropriate 4 to the word line ( WL) is used to program or read the memory cells along the word line. Appropriate voltage is also applied to the bit lines (BL) connected to the cell of interest. The circuit of Figure 7 shows along a column. All units are programmed and read together, but are programmed as a unit along a column to program and read each of the other units. In this case, two sets of selection transistors (not shown) are used simultaneously and each One other unit is operatively coupled, and each of the other units forms a page. The voltage applied to the remaining word lines is selected such that their respective storage transistors are electrically conductive. In the stylized or read memory cells of a column During the process, the previously stored charge level on the unselected column can be disturbed because the voltage applied to the bit line can affect all cells in the string connected thereto. A specific type of memory system described above The architecture and its operation are generally illustrated in Figure 8. A memory cell array 213 (which is greatly simplified for ease of explanation) contains a block or metablock (PBN) pi _Pm depending on the architecture. It will be received by the memory system from the host. The logical addresses of the material are grouped together into a logical group or block Li-Ln having an individual logical block address (LBA). That is, the entire contiguous logical address space of the memory system is divided into a number of address groups. The amount of material addressed by each of the logical groups L1-Ln is the same as the storage capacity of each physical block or metablock. The memory system controller includes a function 215 that will group Li-Ln The logical address of each of them is mapped to one of the different physical blocks P1 - Pm. 131567.doc -22- 200915072 (

It may include more physical blocks than the logical group present in the memory system address (4). In the example of Figure 8, there are four such additional physical blocks. For the purpose of this simplified description provided to illustrate the application of the present invention, 'in the data' (4), both of the additional blocks are used as data update blocks, and the other two additional blocks constitute an erase block. A cluster. Usually, other extra blocks may be included for various purposes. In the case where a block becomes defective, an extra block is used as a redundant block. The state uses one or more other blocks. The memory is used by the memory system controller to manipulate the control data of the memory. Usually no specific block is specified for any particular purpose. In fact, the mapping 215 regularly changes the individual logical group between any of the blocks P1_Pm. The physical blocks to which the group's data are mapped. The physical blocks that serve as the update and erase block blocks are also migrated throughout the physical block Pl-pm during the operation of the memory system. Currently specified as update and erase sets The identification code of the physical blocks of the block is maintained by the controller. The writing of the new data represented by Figure 8 into the memory system will now be described. It is assumed that the data of the logical group L4 is mapped to the physical block p (m_2) ). Also Block P2 is designated as an update block and is completely erased and freely usable. In this case, when the host command writes data to the logical address or multiple consecutive logical addresses in the group " And writing the data to the update block p2. Thereafter, the poor material stored in the block P(m_2) having the same logical address as the new data is obsolete, and is newly stored in the update block L4. The data is replaced. At a later time, the data can be merged (waste collected) from the P(m_2) and ?2 blocks into a single physical block. This will be from the block p(m_131567). .doc •23· 200915072 2) The remaining valid data and the new data from the update block p2 are written to another block in the erased block set & (such as block P5). In addition to the block P(m-2) and P2, it is thereafter used to update or erase the block. Alternatively, the remaining valid data in the original block P(m_2) can be written into the block P2 along with the new data. (if this is possible), and then erase block P(m-2). To minimize the need for a given data storage capacity The size of the memory array keeps the number of extra blocks to a minimum. Memory system controllers typically allow for a limited number of (in this example, two) update blocks to exist simultaneously. Collecting the data from an update block with the remaining valid data from the original physical block, because the new data can be written by the host to the physical block associated with the update block. The same update block Additional data is then received. Since the waste collection takes time and the delay in other operations can adversely affect the performance of the memory system, waste collection is not performed each time waste collection can be performed. It takes a significant amount of time for a block to be copied into another block, especially when the data storage of individual blocks is very large (this trend). Therefore, when a host command writes data, it usually happens that there are no free or blank update blocks available to receive it. The existing update block is then garbage collected (required for the write command and executed for it) so that new data can be received from the host thereafter. In this case, the limit to how long the waste collection can be delayed has been reached. Routine Operations 131567.doc -24- 200915072 Most of the operation of the memory system is the direct result of executing the commands it receives from the system to which it is connected. The write command received by the host computer (for example) contains some instructions, including the read command received by the m machine after the ^7 heartbeak will be written to the address address (10)8. The logical address of the data that the system will read and send to the host. In addition, there is a typical host sent to the other, and many other fate of the system, which is present in the operation of the flash memory system. In order to be able to perform various kinds of receiving from the host The instructions or in order to be able to effectively suffice the instructions 'memory system to perform other functions including routine operations; the second example is to directly respond to a specific host command and execute the second command. One instance responds to the data write. The command does not have an insufficient number of garbage collection operations in the -= pool to store the erase block of the data to be written in response to the command. No other is required for the IL-command. Routine operation 'but often perform this equivalent = to maintain a good memory system without data errors' month b ° Examples of routine operations of this type include wear leveling, data re-sampling = preemptive waste collection Merging with data. When utilized = often at regular time intervals, at random time intervals or at time intervals to level the use of blocks of memory cells to avoid _ _ η 1 Some or most of the blocks of the block reached the end of life: a termination of the life of this extended life having its full storage capacity of the data memory 5 has the body.

In the case of the Uber material removal operation, the memory is usually scanned (a certain number of blocks are evaluated by a certain row of shoes) to read and check from their respective areas 131567.doc -25- 200915072 The quality of the data read by the block. If the quality of the information in the block is not t, then the data of the Guardian of the block is rewritten to another block from the erased area. . Also I found that the data was needed during the normal host command data. The new 'its Xin noticed that the number of errors in the read data f was high. In the need to execute a host write command ^ ^ M / v, the month of the first to perform a waste collection into a merger and merger operations. For example, the number is reduced to less than the number of _ _ erased block or data merge operation = to the need for waste collection operations to - or multiple erased blocks: = collection or data merge usually in the background and And 丄" , in the execution - specific host command some time - when idle, in the back ::: memory system is likely to occur in subsequent hits from the host to receive these routine operations 'but but instead executed The execution of the host command == is then aborted in the background to perform the routine operation; the command 'can be reduced by the chance of the interrupt. The routine can be performed by the memory system to the host. And "Taiwan sends any other commands to make 'e, '= g (four) is removed before the sender can be sent to read, read,,, this station operation therefore makes the host remember the performance of the system': therefore s and other The execution delay of the command affects the execution of the routine operation in the scene, except when the host is not ready to send the command, it becomes idle for the rest of the time to do this: ^When or if the host will be in the line for the execution - from the host this Cloth special command in the foreground enforcement of the terms frequently does not require the routine 131567.doc -26- 200915072 routine operations in order to ensure the implementation of these operations frequently enough. Sometimes, it is also necessary to perform this routine operation as quickly as possible, such as by performing a regular clear read scan of the data stored in the block or by reading a bad quality when executing the host read command. Information on the condition of the presence of information on poor quality. Since the data of the bad quality can be downgraded due to the continued operation of the ticker system, it is not an option to wait for the re-sale of the information of the bad quality in the background. The use of individual memory cell blocks is described in 纟© Patent Nos. 6,230,233, 6,985,992, L,973,531, 帛7, 〇35,967, 帛7, 〇96,313, and 7,120'729. Several different wear leveling techniques for cycle counting. The main advantage of wear leveling is to prevent some blocks from reaching their maximum cycle count when other blocks are almost unused and thus have to be mapped out of the system. By reasonably evenly spreading the number of cycles throughout all blocks of the system, good performance characteristics can be maintained throughout the extended period of memory. The wear leveling can also be performed without maintaining the memory block circulation and the number of juices, as described in U.S. Patent Application Publication No. 2004/J1, 697, A1. In another method for wear leveling, the boundary between the physical regions of the block is gradually migrated across the array of memory cells by incrementing the logical-to-physical block address by one or more blocks. This is described in U.S. Patent No. 7,120,729. The main reason that some blocks of memory cells are subjected to a much larger number of erase and reprogramming cycles than other blocks of the memory system is that the host continuously rewrites the data sectors in relatively few logical block addresses. This can happen in many applications of memory system I31567.doc -27- 200915072, where the host continuously updates the instance data stored in memory A & some logical sections (such as the slot configuration table (four) D) and Analogs) The specific use of the host can also cause some of the logical blocks to be rewritten much more frequently than other logical blocks with user data. In response to receiving from the host - a command to write the data to the specified logical block address, the data is written to one of the blocks of the erase block set. That is, the logical block address is remapped into one of the erase block chunks instead of rewriting the data to the same physical block in which the original data of the same logical block address resides. The block containing the original and now invalid material is then erased immediately or as part of a later garbage collection operation and then placed in the erase block pool. When only the data in some logical block addresses are updated much more frequently than the other blocks, the result is that relatively few physical blocks of the system cycle at a higher rate. For the reasons given above, it is of course necessary to provide within the memory system the ability to equalize wear on the physical block in the event of this very non-uniform logical block access. When Tian Zi's data unit read by the hidden body contains some errors, the error can usually be corrected by using the ECC carried by the data unit. However, the level of charge stored in the data unit has been removed from the state it was originally programmed to. Therefore, it is necessary to clear or renew the data by rewriting the correction data to other places in the memory system. The data can therefore be overwritten with its charge level positioned near the middle of the discrete charge level range defined by its storage state. 'When the data is read during the execution of the host read command, and usually scanned by 131567.doc -28- 200915072 in some memory blocks (clear scan) (especially relative to Other data and not read by the host during the long period of time ^ their data), can be said to detect such bad quality information. It can also be executed as follows: 于, 扫% 贞 所 所 所 所 所 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The charge level of the bit can be restored back to the center of its state range from time to time before the charge-interference operation of the step causes the ί 八 to move out of its defined range and thus cause the reading of the erroneous data. In March, 2007 U.S. Patent Nos. 5,532,962, 1 '1/69^49, and 2,835, the disclosures of which are incorporated by reference in the U.S. Patent No. 4, and No. 11/692,829. Process. _ = Scheduling in a way that minimizes the impact on the performance of the I system does not require prior routine operations for the order. In US Patent t;::7 006/0161724 A1^^^〇〇6/ 〇 161728 Am some = row host command period scheduling control of a pair of enabling routine operations of the operations that will be performed. Because routine operations in the background or foreground can affect the performance of data transfer, such execution is Its very large amount of system performance: in the case of L, the number of files in the s The number of consecutive top ten 枓 写 写 写 非常 非常 ! ! ! ! ! ! ! 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆Is the video or audio "tf wants or expects high performance). It is not necessary to perform a routine operation that is not required for the memory to perform the current write or read command in the memory system. This causes the host to interrupt the transfer during this process. In the case of a delay, the longer the delay of the resource buffer may be exceeded and the data from the stream may be lost, the longer the data buffer needs to be configured to provide a lossless transfer of the data stream ( Even the average read or write rate is sufficient, ,). Video or audio data streams should not be interrupted in particular when they are in progress, which can interrupt the human user's appreciation of the video or audio content. Referring to Figure 9, an illustrative method of operating a memory system to avoid such interruptions and performing such routine operations as appropriate is shown. (3) The section will be executed; the annotation of the routine operation begins the process. This routine operation can be, for example, abrading, leveling, skimming, &&<>, preemptive bedding waste collection or merging - 5 of these operations - above, _ ^ ^ ^ The order is both necessary and beneficial. The determination of routine operations can be noted by ^ 〃 for any particular host. For example, the ancient was triggered, since the last execution of wear leveling. 17 4 ‘It system spontaneous wear leveling operation. Similarly, the :== block is erased and the scan is taken. Then, in response to the clearing of the data below the level of the read data clearing & to an acceptable me, except for the read scan or the normal start of the new data. Or, when triggered, can be two = all of these routine operations, 1 in the ^ column

The middle and the ancient process picker performs the routine operation of taking the horse priority in the queue at 221... How to trigger or determine the routine operation is not heavy or light, the specific algorithm of operation determines The system is used by the individual routines 131567.doc -30· 200915072 ~ at 223^4 ' to determine whether the host command is being executed at this time. The process of Figure 9 = 221 should be performed in the foreground (during the execution of the host command) or in the background (when the system command is not executed or no host command at all): other routine operations. Whether or not the actual execution of the stipulation after being enabled will generally depend on the algorithm used for the routine operation and is part of the enabling process described with respect to FIG. ί

U = the child is currently executing the host command, then it is determined at 225 whether there is a specific mode that causes the determined (d) operation to be de-energized or deferred (root rib 7) instead of the host (four) according to 235). In general, the execution of the routine operation required to execute the current host command will not be granted in the foreground (subscribing to this may adversely affect the execution of the command, such as causing the transfer of Erliang data to or from the host) . Before the routine operation, the effect of this mode depends on the characteristics of the host activity mode. In the preferred embodiment, the three parameters of the host activity mode are used to make a decision at 225. The first criterion is the length of the data read from the memory or from the memory when the command is executed. Many host h headers include the length of the data that is transferred by the command ::: Compare this number to a preset threshold. If it is higher than the threshold:: =:! The data is long, and may be video and, or two: branch. In this case, no routine operation is allowed. If the order is concurrent: it: long data, in the receiving data section or other data unit to count the number of them to see if the total exceeds (four) threshold in the data section of the host can be transferred by a single command —... Set the preset threshold to this number or to a number greater than (for example) this = two 131567.doc 200915072. = The second standard that makes the decision at 225 of Figure 9 is the current command order A initial LBA and the pre-order command (which is usually the same type of d-material write, data read, etc. If there is no gap between the two LBAs specified in the paragraph, this indicates that the two commands are transferring a single long stream or a large file. In the case of the case, the month is not assigned.执行 Execution of the operation. Even when there is a certain gap between the two LBAs: this can indicate that there is a continuous long data stream with a positive transition. In 225, the gap between the two LBAs is determined. Whether it is less than the pre-numbered LB A. If it is less than, it can defer or postpone the routine operation. If it is not less than ', it can be routinely operated. - Usually operated by two or more update blocks Memory system, data from two or more separate standards or data streams are written to the two or more update blocks. Data to two or more more: zone: write Into the usual interlaced. In this case, in the same file or ^ / IL write command The Lba is compared between commands used to write data of different files to different update blocks. The third standard for use at 225 relates to the operating speed of the host. This can be done in one or more ways (4). One parameter related to speed is the time delay between when the memory system fails its busy state signal and when the host begins to send another command or data unit. If the delay is long, this indicates that the host is performing some kind of slowing down Handling of operations. A row operation can be enabled in this situation 'because its execution will not slow down the operation of the host, or at least will only slow down the operation of the host to a minimum. However, if this delay is short, this indicates the main 131567 .doc •32. 200915072 Machine & speed and should be able to defer or postpone any pending routine operations. Therefore, a time threshold can be set. If the actual time delay is less than the threshold, no power is applied. Line operation. “The other speed-related parameter is the data transfer rate selected by the host. Not all hosts operate at different data transfer rates. However, they are transferred to different data. For a host operating at a rate, when the data transfer rate is higher than the preset threshold, the routine operation is not enabled because it indicates that the host is operating quickly. Any delay of the host time or data transfer speed can be imposed. The value is set somewhere between the Iraqi poles can be operated). ...and the extreme & (the host decides that the routine operation can be enabled at these extremes, and then considers the additional operation with higher priority in the addition. For example, the old one may: execute the execution In the current situation, one of the additional operations required by the current order is merged. Under this circumstance, it will be able to delay or at least postpone the operation of 3 hai, until the completion of the 牯w loss adjustment my other instance has been determined to grind " However, it is necessary to copy the data according to the read-and-clear scan or other data read. When the read-and-removal (renew) is performed, the wear leveling operation will be deferred or delayed. If the shirt is judged at 233 In the host command currently being executed, then: the characteristics of the host activity 'to determine whether the determined routine operation can be performed between the = host commands in the background may be different, but it is similar to the above... Section 2, except that the criteria are applied to the most recent execution of the host command currently being executed (because no) the rightmost command (for example) indicates a forward rotation 131567.doc • 33- 200915072 Move continuous data stream or host positive - The place should not be assigned at the time::::= mode operation, then the effect of 225 on the foreground operation. The other - the second two = in its similarity to the individual sister, the thousand does not exist at 223 ) Early in the morning - other host mode standard rabbits) = amount of inactivity to make a decision. For example, operate unless the host was just operating in extreme fast mode.

In addition to being able to or delay the routine operations in the foreground at 237: Ground = the determined operation to unfold the burden on the system. For example, during the two-line data write command, all or part of the operation can be enabled after each cluster or other resource is written to the memory system. This can be determined as part of the 225 process. For example, the host can be responsive to the time delay of the memory system's negative state of its busy state signal to determine the amount of routine operation that should be simultaneously enabled for execution. This execution typically involves transferring multiple data pages from one memory unit block to another or exchanging pages between two blocks, so that less than all pages of the pages can be transferred in a continuous time. Until all pages are transferred. As the latency of the host decreases, some of the routine operations that are enabled to perform simultaneously are reduced until the point at which the operation is not energized at all is reached. Examples of specific techniques for deferring or de-determining routine operations at 237 are primarily related to Figures 14A, 14B and 14C of the above-referenced U.S. Patent Application Publication No. 2006/0161724 A1 and above. The descriptions of Figures 13A, 13B and 13C of U.S. Patent Application Publication No. 2006/016 1728 A1 are incorporated herein by reference. 131567.doc -34· 200915072 Illustrated in Figure 9 - Defining the execution of the operation Example 赋 The empowerment at 235 does not overly affect the memory (4). When it is possible to perform a routine operation in a non-process, the execution of the routine operation, ":: interval. During these periods, the assignment is performed on the routine operation == which operation will be performed. In addition, when the identified:::: will be called for a specific time period. !例 例 识别 识别 识别 识别 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: No other criteria are considered. The sample guide I makes the shirt by viewing only the current command or the immediately preceding command, or only the gap between the start of the previous command and the last command. "It is preferred to make a decision using either or both of the criteria described above. In this case, if the two or two of the above criteria are approved, the indication in the host operation is not It should be better to make the routine operation de-energized or postponed. Figure 10 shows an example of the decision to use multiple criteria for making 225. At 241, the above text In the manner described, the last LBA of the first previous command of the current command is compared. If the comparison shows that the two lifespans are consecutive, the process proceeds to 237 of Figure 9, where the determination can be made or delayed. Routine operation. However, if the right does not determine that the data is continuous at 24 1 , then the measurement responds to the length of the data transferred by the host command and compares it with a threshold N. At 243 in Figure 1, the length of the data read from the host command is 131567.doc • 35· 200915072 degrees, and this length is compared with the threshold N at 247. If the length exceeds two, the indication is long or continuous. The transfer of data, so can go or delay the routine operation (237 of Figure 9). If the order does not identify the length of the data, then the transferred data unit is counted at 245 until the threshold data length N is reached. Under this condition, the routine operation can be deferred or postponed. Determined by 243, 245, and 247 as N or less 'Execute - Third Test' as indicated at 249 of Figure 1(). Check host at 249

The delay or the - or multiple aspects of the operating speed are compared to - or a plurality of respective thresholds, as described above. If the host is operating at a high rate, then the process proceeds to 237 (Fig. 9 χ 能 推 推 推 推 推 确定 ' ' 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但 但Execution of the operation. The two figures shown in Figure 10 are shown in Figure 4, but the use of a test type 5 is 'but the test can be eliminated' and still provides good system management. In addition, you can add Extra = In particular, at 249, you can independently check two or more host time parameters to see if ^ 疋 no and you want to "delay the routine operation. If the temple parameter is any of the parameters p ^ # know the host to a possible range of speeds can go or delay the routine operation. "When mentioned in the above discussion;: the characteristics of the command, can be carried out - similar process to Figure 231 The decision was made to use the characteristics of the command to use the kidney pull to match the command in the face. Figure 11 and Figure 12 show the host and the operation of the host system. The sequence diagram is shown in Fig. β,. From the host connection diagram> The money received by the brother one command 259, the base* / the receiver that is received and written to the host is the two data units in the alpha body. % 1 131567.doc -36 - 200915072 And 263. determining a memory busy state signal 265 at times t4 and t7 immediately after receiving each of the data units, and maintaining the signal 265 until the data is available during times 267 and 269, respectively. Each of the cells is written to the non-volatile memory. When determining the busy state signal, the host does not transmit any data or commands. Immediately after the data write 267, the busy state signal 265 is denied at time t5. Enabling the host to transfer more data or another command to the memory system. The routine operation is enabled for use at time 271 (in this illustrative example, the time 271 is immediately after the data write period 269) Execution in the foreground' therefore does not negate the memory busy status signal 265 before time t9. Figure 2's curve 2 7 3 indicates when it has been determined to de-energize or postpone (low curve) the enabling of a row operation (237 of Figure 9) ) or empowerment Line) This operation (235 of Figure 9). In this case, when the memory system receives a command from the host, the routine operation is shown as being enabled at time 1. If it is applicable earlier for this command If it is applicable to make the criteria for the selection, then this will be the case. If the order contains the data accompanying the length of the command' and only two data units of this instance fall below the set threshold, then the test ( Figure 241) causes the operation to be disabled or delayed. It is also possible to compare the starting lba with the last LBa of the previous data write command before this time in order to apply the standard (Fig. 10, 243). , 245 and 247). However, time t1 is too early to cause any delay in the response of the host when executing command 259 (249 of Figure 1). Thus, in this example of Figure u, the host timing criteria are not used. The decision to make a row operation has been made from the standard of Fig. 10 and the standard of 243/245/247. 131567.doc -37- 200915072 When reading the data length from the command itself at 243 of Figure 10, for some hosts there is a possibility that the command can be aborted before the length of the data is transferred. This possibility can be considered by examining the actual length of the data transferred at the end of the execution of the command. If a row operation has been deferred or delayed due to the length of the particular command, the added check may cause the decision to be revoked if an earlier termination of the command is detected. The routine operation can then be enabled instead of completing the execution of the host command. County 状况 状况 状况 主机 'host send - has - expandable or very time 2 = degree command, and then later when all data has been transferred standard, because it can not = can not use the length of the data - The ancient + sin 5 Ge' can delay the routine operation, and until the stop command is received, the actual amount of the ^ ^ ^ ^ ^ ^ ^ material is known as I if the data: by the order If the transferred poor right-shelled 罝 is less than the set threshold, this routine operation can be assigned so that it can be routinely operated on the host. The end of the execution is as follows: arbitrarily, although the execution of the routine operation is performed by H but until time. This is the system. Let 259 receive the last: ## but after receiving the new command 275/non-volatile memory, the operation will be performed by the current Si routine to the non-volatile memory. . However, it is alternatively possible to perform the second command operation after the host command write interval 267 is completed earlier. Also, the second routine operation can be permitted immediately following the performance requirement. Tight: operation (if the memory system is poorly connected in a memory write 131567.doc •38· 200915072 y, the implementation of the f column operation is usually the most effective, but this is not the main thing done by the operation technology described in one Boundary: Requirement. The timeline of the operation of this article is executable - the case is called by 'but manages the definition of the window: the operation itself or other system is determined. The details of the sequence are when the host is timed. Used as a standard (249 of Figure 1G) - "when measuring the day or more, deferred in Figure 11" and used to determine whether to go or ^ then 疋 赋 No enable routine operation - This time interval is ~ Negative province n ° 糸 The time interval between the host's busy state signal and the start of the transmission of the data unit 263 after the time t5 is short (below a certain threshold) , (4) Rate operation to transfer data to the record:, the machine will not perform routine operations in the -high interval. The transition period of the extension door ^ speed is longer than the threshold, then 1 = and Not working very fast, so there is no need to postpone or go to routine operations to the side The other time interval is the time interval team training. ~, the main: after the busy state signal 265 is denied at time t9, after the execution of the first command, the time taken to send another command. When the short end of the circumference (below a set threshold), the display host is operating in fast mode 'so no routine operation is performed. I use the other - the timing parameter is the data transfer rate selected by the host. The indication ^ should be enabled for routine operation as this would potentially slow down the data: shift. Any of these timing parameters can be used alone in process 249 of Figure 10 or two or more timing parameters can be analyzed independently. Figure 12 is a timing diagram showing the operation of different instances. In this case, I31567.doc -39- 200915072 wears a first host command 277 to perform or delay the execution of the routine operation in the foreground because the host The pattern satisfies the criteria for the routine operation of the milk of Figure 9. However, at time t7 (when the point is ab', ^ (several 277 commands) and time t9 (this)

After the preset time), the anchor X machine does not have a long delay (such as - milliseconds). One of the criteria in 231 of Figure 9 can be used to determine that a row operation can be enabled to Back" execution (even if the characteristics of the host activity used to execute command 277 can additionally determine that it should not be assigned to the 仃 唧 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The busy signal 285 that has been executed after the routine is dropped to 283 and returned to the non-active m% system is stored during the time period of the period 1 after the completion of the operation of ', ^ ^, ^ f 7 277. The memory system actually selects the enable = medium rather than the previous "execute routine operation. This is intended to be received from the host during the operation 283. The command does not terminate its execution so that the host command can be executed. Abridged Although the embodiment has been described and its possible variations, it is reasonable to understand that the present invention enjoys the right to attach an additional claim. A - The patent is protected within the complete material [Simplified illustration] 1A and Figure 1B are respectively - the system of the system _; (10) Emissive memory and host = description of the first embodiment of the memory array of FIG. 1A - example organization; record body I:: instance main W material section with additional data as stored in the hidden body array of FIG. 1A; .doc •40- 200915072 Figure 4 illustrates the memory array of the Figure ia - example organization, Figure 5 illustrates the memory array of the circle a - consistent example organization; Figure 6 shows the cage of the memory array of Figure 1 a = Extension of the second instance organization;

Figure 7 is a circuit diagram of a memory cell group of the array of Figure 1A in a particular configuration; Figure 8 illustrates an example organization and use of the memory array of Figure 1A, and Figure 9 is an operational flow diagram illustrating the prior The operation of the illustrated memory system, which will enable the execution of routine operations; Figure 10 is an operational flow diagram that provides an example of the processing within the steps of Figure 9; Figure 11 is the previous A timing diagram illustrating the first/example operation of the memory system, which illustrates the process of FIG. 9; and FIG. 12 is a timing diagram of a second example operation of the memory system previously described, illustrating the process of FIG. [Main component symbol description] 1 Memory chip/memory volume circuit device/memory array device 3 Memory chip/memory volume circuit device/memory array device 5 Memory cell array 7 Logic circuit 9 Controller 1 Micro processing Device 3 Read-only memory (ROM) 131567.doc -41 - 200915072 25 Buffer memory (RAM) 27 Circuit 29 Circuit 31 Connection 31' Connection 33 Circuit 35 Interface circuit 37 Microprocessor 39 ROM 41 RAM 43 Other circuits and sub- System 51 User Data 53 ECC 55 Parameter 57 ECC 59 Block 61 Logical Data Block 65 Common Source 67 Circuit 70 Charge Storage Silicone 71 Charge Storage Silicone 72 Charge Storage Silicone 74 Charge Storage Silicone 77 Selects the transistor 131567. Doc -42- 200915072 79 Select transistor 81 Circuit 83 Line 84 Line 213 Memory cell array 215 Function 259 First command 261 Data unit 263 Data unit 265 Memory busy status signal 267 Time 269 Time 271 Time 273 Curve 275 Command 277 One host command 283 routine operation 285 busy signal BLO -BLN Bit Line Ll-Ln Logical Group PO-Pm Physical Block P1-P15 Page WL0-WL15 Word Line 131567.doc -43 -

Claims (1)

200915072 X. Patent application scope · Method of non-volatile memory system, L operations - reprogrammable includes: The self-host receives commands and executes the received commands, at least with respect to the received commands To monitor the active mode of the host, and to identify a first host active mode, enable a row of execution The routine operation is a type that is not required for execution of one of the equals a received from the host, or 7 is not authorized to perform the routine operation when identifying - different from the second of the first mode In the active mode of the host, 2. The method of requesting the item 'is additionally included in response to the first-host activity nucleus being identified, performing at least a portion of the energized routine operation. 3. The method of claim 2, wherein performing the energized routine operation comprises reading a data block from a location of the memory system, and thereafter writing the read data to the memory system In another location. 4' as requested! The method of 'receiving a command from the host and executing the received command includes receiving and executing (1) a write command to write data received from the host by the command to be written by the host The logical address of the memory specified by the command; or (2) a read command to read the data from the logical address of the memory specified by the read command and send the read data To the host. 5. The method of claim 4, wherein the second host activity mode comprises a number of data units of 131567.doc 200915072 specified by one of the commands over a predetermined number of data units, and wherein The first host activity mode includes the number of such data units that are less than the preset number. 6. The method of claim 4, wherein the first host activity mode comprises starting logic at one of the data specified by one of the commands, and ending the logic with one of the data specified by a previous command One of the differences between the addresses is a range that exceeds a predetermined number of logical addresses, and wherein the second host active mode includes the difference less than the preset number. 7. The method of claim 1, wherein the first host activity mode includes a duration that is exceeded by the host after the memory system indicates to the host that the memory system is not busy, which exceeds a predetermined duration Time 'and wherein the second host activity mode includes the duration less than the preset duration. 8. The method of any one of clauses 7 to 7, wherein when a busy status message is " When the system is sent to the host, the first host activity mode or the second host activity mode is identified. 9. The method of any of clauses 1 to 7, wherein the first host activity mode or the second host activity mode is identified when no busy status message is sent to the host by the memory system. 1 〇 〆 〆 操作 操作 〆 . . . . . 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新 新Operation; determining at least one parameter of the activity of the host; and 131567.doc 200915072 Right violation determines that at least one parameter satisfies at least - the execution of the routine operation of the predetermined rule, but 〃 丨 does not enable if the Hungarian at least _ i slave / If the number satisfies the predetermined condition, it can be used for execution. This child 11 • If the request item is 0, the old time is „ , /, and the execution of the routine is performed when the routine operation is enabled. Line operation, at the same time the memory system only sends the message to the host, #,, k state △ such as the request item 1G "^" to perform the routine operation. In addition, when the routine operation of the assignment (4) is performed, the memory operation "does not ", such as the request item!", the execution of the routine operation in the At. The method of the member, wherein the routine operation This includes rewriting the data from the location in the memory to another location in the memory system. The side of the month length item 13, i: 'where the routine operation data is rewritten as' - wear leveling or clearing The method of claim 1 wherein: (4) at least one parameter of the activity of the host is included in one of the commands received by the memory system from the host Monitoring the at least one parameter. 16. The method of claiming, wherein the at least parameter is a logical unit of data transferred to or from the memory due to execution of a single host command. The number-count, the at least one predetermined condition includes a number of data sheets S, wherein the - parameter satisfies the condition when the count is less than the threshold number, and when the count is greater than the threshold number, One 17. The method of claim 10, wherein the method of claim 10, wherein the at least one parameter is in response to the command being received by the master 131567.doc 200915072, the one of the transferred data begins and is executed from the host Receiving a logical address difference between the end of one of the transferred data during the previous command, the at least one predetermined condition including a predetermined address difference, wherein when the logical address difference is greater than the predetermined address difference, the one The parameter satisfies the condition, and when the logical address difference is greater than the pre-event address difference, the parameter does not satisfy the condition. 18. The method of U item 15 wherein the at least one parameter is included in the memory system The host indicates that the memory system is not busy after being responded by the host to the duration - the duration - the at least - predetermined condition includes a pre-capture amount, wherein the duration is less than the predetermined time increment The parameter satisfies the predetermined condition of 5 hai, and when the duration is greater than the predetermined time increment, the parameter does not satisfy the predetermined condition. 19 · 士Μ求丨i The method, wherein the routine operation comprises wear leveling. 20. The method of claiming, wherein the routine operation comprises clearing. 21. The method of determining the item ,2, wherein the routine operation comprises a wear adjustment 22. The method of claim 12, wherein the routine operation comprises clearing. 23_ The method of claim 1, wherein the currently received command individually includes one of data reading and data writing One of the command groups. 24. The method of claim 23, wherein the command group additionally includes erasing the defined block of the memory. a system adapted to be removably coupled to a host system comprising: an array of reprogrammable non-volatile memory cells organized as memory a unit block in which the memory cells of the individual blocks such as 131567.doc 200915072 can be erased at the same time, including - a controller of the microprocessor, operating with: 5 unnecessary routine operations; Determining - for the execution-slave-host receiving command, there is no need to respect the commander. 4a a. Determine at least one parameter of the activity of the host; and right (four) set at least - the parameter satisfies at least - the predetermined condition, then the month b is 4 cases Execution of the row operation, but assigning the right side determines that at least one parameter does not satisfy the pre-routine operation for execution. The record (10) is in which the execution of the routine operation is performed and the other operation is performed to perform at least a part of the routine operation when the memory system is in a busy state == machine, thereby This routine operation is performed in the argument. At the time, the monthly (four) system, in which the execution of the routine operation is performed: the other % of the controller performs the routine operation when the memory system does not - busy state == to the host, thereby In the background, 4 cases were executed. 28.: = The memory system of item 25, wherein the routine operation comprises setting the data. Rewrite to another memory in the memory system: Γ7's memory system' where the routine operation data rewriting is performed as part of 3 gentlemen 2 or clear routine operations. A memory system of == 25, wherein determining at least the activity of the host comprises monitoring the at least one parameter during execution of the first command received by the memory system from the host. 3 1 · If you want to ask for the item 25, the system is pity, the system, where the at least - 夂 Zhao after - a single host command and 祜 14 heart rate system due to execution ^ break into the memory or from the memory A count of one of the numbers of the early logical errors of the data transferred from the body φ, a predetermined condition including the data set-^, so μ is at least, and + is 7 早, which is less than the threshold. When the number is greater than the threshold number, the one parameter does not satisfy the one condition. Number 32. The memory system of claim 25, wherein the at least the parameter is in response to the data transferred from the host receiving the command, begins with data transferred during execution of a previous command received from the host a logical address difference between one of the ends, the at least one condition includes a predetermined address difference, wherein the one parameter satisfies the condition when the logical address difference is greater than the 敎 address difference, and when When the logical address difference is greater than the predetermined address difference, the one parameter does not satisfy the one condition. 33. The memory system of claim 30, wherein the at least one parameter comprises a response to the one of the memory systems by the host after the memory system indicates to the host that the § memory system is not busy 'the at least one predetermined The condition includes a predetermined time increment, wherein the parameter satisfies the predetermined condition when the duration is less than the predetermined time increment, and the parameter does not satisfy the one when the duration is greater than the predetermined time increment Predetermined conditions. 34. The memory system of claim 26, wherein the routine operation comprises wear leveling. 3 5 • The memory system of claim 26 wherein the routine operation includes clearing. 3 6. The memory system of claim 27 wherein the routine operation comprises a wear level of 131567.doc 200915072. 3. The memory system of claim 27, wherein the routine operation comprises clearing. 38. The memory system of claim 25, wherein the currently received command individually comprises one of a group of command data read and data write commands. 39. The memory system of claim 38, wherein the group of commands additionally comprises erasing the defined block of the memory. f 131567.doc