200915065 九、發明說明： 【發明所屬之技術領域】 本發明係有關-種E]態硬碟（SSD)，特別是關於—種整合有單層單元 快閃記憶體（SLC，Single Level Cell)以及多層單元快閃記憶體⑽，200915065 IX. Description of the Invention: [Technical Field] The present invention relates to an E-state hard disk (SSD), and in particular to a single-layer unit (SLC) Multi-level cell flash memory (10),
Mum Level cell)二者優點之混合型快閃記憶體裝置及其操作方法。 【先前技術】 在能夠充分發揮經濟價值之前提下，提高記憶容量—直是記憶體 裝置所追求的目標’而在半導體技術的推陳出新過程中，細：化 製程的進步使得高容量的記憶體S件—直都有突破性的發展。 以目前應用廣泛的快閃記憶體而言，主要分為單層料以及多層單元 兩大技術。單層單秘閃記憶體架構之儲存方式係糊對浮動閘極的電荷 施加電壓，並且透過源極將所儲存的電荷消除，藉此達到表示Q則的狀 態來儲存資料，以達記憶胞（咖⑽1υ即可贿個資料位元， 並且能夠提㈣速的料編絲讀取。軸_枝會受祕财效率 ㈤_ efficiency)問題’導致成本較高，但是其效率表現以及可靠 性是相對佔優勢的。 另-種的多層單㈣閃記憶體則是在—個浮_極中—次儲存兩個位 讀資訊，透過記憶胞的寫人和感應的控制，單1晶體中可產生四層單 元。不過由於多層單元快閃記憶鮮_成對位元的處理，導致記憶胞閑 極的電荷敎速度較快，因此在電力雜方面較為嚴重且财只有約i 萬次的寫增’爾姐__航w應目前快閃記 _價格的競爭趨勢，也有許多產品制這類多層單元快閃記憶體。 200915065 有鑑於此，本發明係有效的結合上述二種快閃記憶體於同一記憶樹 置中’提出-種混合型快閃記憶縣置及其操作方法，以便將快閃記憶的 效能發揮到極致。 【發明内容】 本發明之轉目的係在提供—觀合型,_記憶縣置及其操作方 法’其係將單層單元快閃記憶體與多層單讀閃記紐二種不同架構快閃 記憶體同時整合至記髓裝置巾，赌合單層單元蝴記憶體之寫 入速度快、穩雜高、可靠度高且壽命長的優如衫料讀閃記憶體 之價格低廉且财容量密度高_，進⑽低生產成本，並發揮卿己 憶體最大之性能。 ° 本發明之另-目的係在提供一種混合型快閃記憶體裝置及其操作方 法’其係可平均單層單元快閃記髓财層單以綱記髓兩者快閃記悚 體的抹除與寫入次數’使二者之使用壽命達到一個損耗平衡，以發揮_ 記憶體更佳的效能。 本發明之再一目的係在提供一種混合型快閃記憶體裝置及其操作方 法’其係可根據產品雜錢客戶絲，來雜縦混合敎憶難置内 之皁層單元綱記憶體與歸單元,_記賴之齡容量_，並可據此 調整單層單元快閃記憶體與多層單元快閃記憶體的抹除與寫入次數。 為達到上述目的，本發明之—實施態樣係絲示—龍合型 體裝置，其係包括有至少一單岸隐 有乂早層皁7L快閃記憶體與至少一多層單元快閃記 體’刀存資料：並有—控制單元，其係連接單層單元快閃記情 體與多層單元快閃記憶體，並控制兩者之存取與儲存位址。 心 200915065 、本發明之另—實鱗樣健躲上舰合型網記憶縣置之操作方 法，其係在接收至少一筆資料之後，先選擇這筆資料要儲存單層單元快閃 。己隐體或疋夕層單讀閃記憶體；再選擇單層單元快閃記憶體或多層單元 快閃記憶體中用以存放該資料之資料健存單元位址；判斷此資料儲存單元 位址是否純行抹除齡’若㈣絲寫人此資·縣元他中，若是 則接續取得朗斷此轉齡單元紐執行之抹除齡缝衫大於一限 概’若否’則先執行抹除指令後直接將資料存至該資料儲存單元位址中， 若是:則重新搜尋新的資_存單元位址。本發餐勒記錄抹除次數來 調整交換财恤’吻奸鮮層單元___單元快閃記憶 體之使用哥命的損耗平衡。 底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發明 之目的、技_容、翻及其所達成之功效。 【實施方式】 由於單層單元快閃記憶體（SLC)係具有寫入速度快、穩定性高、可靠 妓且壽命長的無，但料有價格昂貴謂树量密度低之缺點；多層 單讀閃戏體（MLC)則具有價格低廉且儲存容量密度高的優點，但卻具 有寫入速度慢、敎性似壽命短之缺點。有鑑於此，本發鴨單層軍元 快閃記憶體與多層單元快閃記憶體兩種不同架構賴記憶體同時實現在同 裝置中S出-種兼具有兩種特性優點之混合型快閃記憶體裝置。 第圖為本心月之此合型此憶體裝置示意圖，如圖所示，在一混合型記 隐體裝置1G中，包含有複數個單層單元快閃記憶體⑽卜⑽）12，提 供儲存第貝料’複數個多層單元快閃記憶體14，提供儲存 200915065 第二資料’再者，單層單元快閃記億體i2與多層單元快閃記紐Μ之傳 存容置的比例可為任意數，亦可使用一個或是—個以上的單層或多層單元 _記觸目，m娜峨㈣，_機其儲存容 :比例。另有-控制單元16，其係電性連接單層單元快閃記憶體I〗與多層 早几快閃記憶體14，並控制這二種快閃記憶體12、14之存取與健存位址； 控制早几16柯控鮮層單域衫層__體14之 抹除次數並據此平衡調整之。 一、〔早層早讀閃6己憶體12之架構示意圖請同時參閱第二(3)圖所 不更包括有複數個第—資料儲存單元⑽⑵以及複數個第一 抹^十數表（ECT1〜ECTS) 122，骑—個第-_儲存單元⑵係分別對 Τ個第-抹除計數表122，該些第，儲存如Μ係儲存控制單元 =來之第’ ’且每—第存單元121 _具有複數個 儲存區㈣，例如圖中所示之S1〜，且該些第—抹除計數表122中之 母個_塊124 ’如圖中所私_，係記_之第，儲存單 兀121内每—咖塊123所執行過之抹除指令次數；換言之，儲存區塊 &係對應記錄區塊…儲存區塊①係對應記縣塊⑶.，以此類推。 _ \ h單决閃錢體14之架構示意圖則請同時參閱第二(的圖 更〇括有複數個第一資料儲存單元⑽卜服幻⑷以及複數個 表(·，)142，且每一個第 16所值、、，—抹除概142 ’這些第二資料儲存單元141係儲存控制單元 16所傳送來之第二資料，备—_ 第二-貝料儲存單元141係分別具有複數個 200915065 儲存區塊143，例如財所示之奶〜删 係與每一儲存區塊123相等；料第_ :子區塊143之儲存容量 ⑷，如圖中所示之™，係記^=2142:之每個記錄區塊 存區塊143所執行過之抹除 換^储存早凡141内每一儲 塊T卜儲存數換5之，儲存區塊Mi係對應記錄區 慰塊船係對應記錄區塊T2...，以此類推。 :中，當第-抹除計數表122或第二抹 料儲存單元121或 L己錄之第-# 抹时“數# …子早几141 _有任—儲存區塊123或143的 未數超過—限制值時，例如：單層單元快閃記憶體 值與多層早元快閃記憶體14 乐關 於該儲存d塊第—限制值’此時’控制單元16會將儲存 找储存£塊123或143内的第—資 動作，詳細咖龜崎_朗:軸存她進行交換的 許财朗元舞咖兩㈣構不同，允 多Mm㈣’她铜—裝置㈣峨人次數較少的 在喊在Γ叙使__束，___能力與 第-限制值與第二限制值之比㈣ 要因素來調整 信愈n k 早層早讀閃記紐之第一限制 Γ m咖之第：峨之_為啤料元峨觸 存谷直.辦多層單元快閃記憶體儲 俨夕蚀六―旦^夕 丹甲倘右早層單元快閃記憶 體之儲存㈣與4單域啦憶體,縣量相 於第二限制值，例如：第—限夕Μ 乐關值係大 i，咖。 限制值认佳值為1G，咖，且第二限制值為 200915065 下歹ςΓ ，本發明之操財法係包括 .钱，如步_㈣魏至m㈣_㈣ =ΙΓ元16根據該筆龍的類型選擇儲存_之_記__:如 2=Γ可贿"料核攸触⑽）12妓多層單元快 :，）14，例如__料可_存至單層單元快閃記憶 單右二般資_則可選擇多層單元快閃_14 至 Γ單ΓΓ記憶體12中’則接軌行步驟⑽卜反之，若選擇健存至多 層早7L快閃記憶體14中，難續進行步驟S5〇卜 —當控制單元16選擇單層單元快閃記憶體12時，請同時參閱第四圖所 -^ ^^S401 ^ 16 12 ^ 存放資腑_元121位址。再如步驟繼_，峨是否需 要先細_令：奸，則_s彻_人奴之第, 疋121中之儲存區塊123位址，並如步物4結束整個流程；蝴是需 要執行抹除齡’ _下—_舰；步義5魏_於第一抹除 樹酬對應位址之記錄區塊124中的抹除指令咖再如步侧 所示.，摘瞭抹除物122記_細旨令缝响超過第一限 制值.:¾•沒有超過，係如步驟挪_必+ ♦資瓣單元心==：令後，梅料寫入 存塊123位址中，並如步驟S4G8結束整個 流程’·反之，細該第-限制值，則進行下—步驟_， 新指定儲存之記憶體架構為多層單元快閃記憶體以。再如步驟測所示， 搜尋並取得娜元_咖4巾峨二娜咖財記錄區塊 10 200915065 ⑷為最小值之姆猶存馳143之紐。並如步驟S4u卿，將多層 單το快閃記憶體14中選定之該相對應儲存區塊143内之資料與該單層單元 快閃記憶體12中超過該第-限制值之儲存區塊123内之龍互滅換並^ 新寫入，然後即可如步驟S412所示結束整個操作方法。 k 另-方面，當控制單元16選擇多層單元快閃記憶體14時，請同時參 閱第五圖所示，如步驟_，控制單元16選擇多層單邮閃記憶體Μ中 可以用來存《料之第二資料儲存單元141_再如步驟·所示，判 斷是"要細t抹除齡：若^，貞,丨如步職3直接寫人指定之第二資 枓储存早το 141中之儲存區塊143位址，並如步驟獅4結束整個流程；相 反地’若在步驟_中判斷是需要執行抹除指令，則進行下一步驟咖5 . 步細5細寻記錄於第二抹輯數表142所對應位址之_㈣中 的抹除指令次數。再如步_6所示，判_二抹除計數表142記錄的 抹除指令次數是否有超過第二限制值：若沒有超過，係如步驟挪所示， 先執行抹除指令後，再將資料寫入至第二資料儲存單元⑷之儲存區塊⑷ 位对，並如步物8結束整個流程；反之，若超過第二限制值，則進行 下步驟S509’控制單元16重新指定儲存之記憶體架構為單層單元快閃記 憶體12。再如步驟咖所示，搜尋並取_單元快閃記憶㈣中該等 示十數表122巾記賴塊124為最小值之相對應儲存區塊⑵之位 ^並如步驟_所示，將單層單蝴記憶㈣中敎之該相對應健 ⑽123内之資料與該多層單元快閃記憶體财超過該第二限制值之儲 存區塊143内之f料互相交換並靖寫人，織即可如步驟挪所示結束 200915065 整個操作方法 特舉-實際範例說明之，同時參閱第—圖及第二(a)、⑹圖，當控制 早7G 16欲將資料健存至單層單元快閃記憶體12中第一資料儲存單元⑵ 之儲存區塊S1時，會先判斷儲存於第—抹除計數表122中之記錄區塊以 中記錄之抹除指令次數是否大於第—限制值，若是，則控制單元Μ再搜尋 到多層單·〗記《财第二:_縣元141巾林最錢除指令次 數之儲存區塊_時，將儲存區塊S1與儲存區塊m6内之資料互相交換， 並更新儲麵址，如此即可平畴個諸齡單觸抹除指令次數，避免 。崎貝料儲存單提早結束使用壽命。反之亦然，不再重複資述。 綜上所述，由於本發明將單層單元快閃記憶體與多層單元快閃記憶體 二種不同咖_細—着㈣，輯响單元快閃記 憶體之寫入繼、娜高、猶高谢長輸从多層單元快 ^>1口己隐體之價格低廉且儲存容量密度高的優點；再配合操作方法，以平均 單層單元快閃記憶體與多層單記憶體兩者關記憶體的抹除與寫入 ^數’使二者之使轉命達到—编耗平衡，以發揮_記憶體更佳的效 月b ’此為先前技術所無法比擬者。 /上所述之實施例鶴為綱本發明之技術思想及特點，其目的在使 2此項賴之人士能_解轉日仅邮麟以魏，當不能以之限定 飾乃…涵蓋在本發明之專利範圍内。 12 200915065 【圖式簡單說明】 二圖為本發㈣合型快閃記憶雜裝置的架縣意圏。 咖術咐铜示意圖。 弟-(_為本發明使用之多層單 坌-難士⑫ 、4δ己憶體的架構示意圖。 第二圖為本發明讀作方法m段流程圖。 第四圖為本翻·齡至單料元 . , ^ h己隐體之刼作流程示意圖。 第五圖為本發明選擇儲存至多層單元 【主要元件符號說明】 4體之_流程示意圖。 10混合型記憶體裝置 12單層單元快閃記憶體（SLC) 121第一資料儲存單元（DBT1〜DBTS) 122第一抹除計數表（ECT卜ECTS) 123儲存區塊 124記錄區塊 14多層單元快閃記憶體（MLC) 141第二資料儲存單元（DBTi〜DBTS) 142第二抹除計數表（ECT卜ECTS) 143儲存區塊 144記錄區塊 16控制單元 13Mum Level cell) A hybrid flash memory device and its operation method. [Prior Art] Before the economic value can be fully utilized, the memory capacity is improved—it is the goal pursued by the memory device'. In the process of the innovation of semiconductor technology, the progress of the process makes the high-capacity memory S Pieces - straight have a breakthrough development. In the current widely used flash memory, it is mainly divided into two layers of single layer materials and multi-layer units. The storage mode of the single-layer single-secret flash memory structure is that the paste applies a voltage to the charge of the floating gate, and the stored charge is removed through the source, thereby achieving the state of the Q state to store the data to reach the memory cell ( Coffee (10) 1 υ can bribe a data bit, and can mention (four) speed material woven wire reading. Axis _ stick will be affected by the secret efficiency (five) _ efficiency) resulting in higher cost, but its efficiency and reliability are relative Advantage. Another type of multi-layer single (four) flash memory stores two bits of read information in a floating _ pole. Through the control of the writing and sensing of the memory cell, a four-layer unit can be generated in a single crystal. However, due to the processing of the multi-cell flash memory, the charge of the memory cell is faster, so the power is more serious and the money is only about 10,000 times. Hangw should be flashing at the current _ price competition trend, there are many products to make such multi-level cell flash memory. In view of the above, the present invention effectively combines the above two types of flash memory in the same memory tree, and proposes a hybrid flash memory county and its operation method, so as to maximize the performance of flash memory. . SUMMARY OF THE INVENTION The object of the present invention is to provide a view-type, _ memory county and its operation method, which is a single-layer unit flash memory and a multi-layer single-read flash memory two different architecture flash memory At the same time, it is integrated into the pulping device towel, and the writing speed of the single-layer unit butterfly memory is fast, stable, high-reliability, high-reliability and long-life, and the price of the flash memory is low and the density of the product is high. Into (10) low production costs, and play the biggest performance of the Qingyi recall. Another object of the present invention is to provide a hybrid flash memory device and an operation method thereof, which are capable of averaging a single layer unit flash flash memory layer and a flash memory of the body. The number of writes 'to achieve a wear level balance between the two to achieve better performance of _ memory. A further object of the present invention is to provide a hybrid flash memory device and an operation method thereof, which can be based on a product of a miscellaneous customer, a miscellaneous mixed memory, and a soap layer unit memory and return. The unit, _ _ _ _ age capacity _, and can adjust the number of erasing and writing of the single-layer unit flash memory and the multi-level unit flash memory. In order to achieve the above object, an embodiment of the present invention is a silk-and-long type body device, which comprises at least one single-shore hidden early layer soap 7L flash memory and at least one multi-layer unit flash memory. 'Knife storage data: and there is - control unit, which is connected to the single-layer unit flash flash memory and multi-level cell flash memory, and control the access and storage addresses of both. Heart 200915065, the other method of the present invention is a method for operating the county. After receiving at least one piece of data, the system first selects the data to store the single layer unit flashing. a single-read flash memory; or a single-layer flash memory or a multi-level cell flash memory for storing the data of the data storage unit address; determining the data storage unit address Whether it is purely erasing the age of 'If the (four) silk writes this capital · County Yuan, if it is then succeeded to break the age of the unit to perform the erasing of the sewing shirt is greater than a limit of 'if no' then first wipe The data is directly stored in the data storage unit address after the instruction, and if so: the new resource location is re-searched. This meal is recorded in the number of erasures to adjust the exchange of money. The new layer of ___ unit flash memory uses the loss balance of the life. The details of the present invention, the capabilities, the versatility, and the effects achieved can be more readily understood by the detailed description of the embodiments and the accompanying drawings. [Embodiment] Since the single-layer unit flash memory (SLC) system has the advantages of high writing speed, high stability, reliability, and long life, it is disadvantageous in that it is expensive and has a low density of trees; The flash theater (MLC) has the advantages of low price and high storage capacity density, but has the disadvantages of slow writing speed and shortness of life. In view of this, the two-layered flash memory of the single-layer military flash memory and the multi-layer unit flash memory of the hair duck are simultaneously realized in the same device, and the hybrid type is fast in the same device. Flash memory device. The figure is a schematic diagram of the device of the present invention. As shown in the figure, in a hybrid type stealth device 1G, a plurality of single-layer unit flash memories (10) (10) 12 are provided. Store the first shell material 'multiple multi-level unit flash memory 14 to provide storage 200915065 second data'. In addition, the ratio of the single-layer unit flash flash and the multi-layer unit flash memory can be arbitrary. The number can also be used for one or more single or multi-layer units _ note the eye, m 峨 峨 (four), _ machine its storage capacity: ratio. In addition, the control unit 16 is electrically connected to the single-layer unit flash memory I and the multi-layer flash memory 14 and controls the access and storage locations of the two flash memories 12 and 14. Address; control the number of erases of the __ body 14 of the fresh layer of the first layer of the control layer and adjust the balance according to this. First, [early layer early reading flash 6 memory structure 12 schematic diagram please also refer to the second (3) map does not include a plurality of first - data storage unit (10) (2) and a plurality of first wipe ^ ten table (ECT1 ~ECTS) 122, riding - the first -_ storage unit (2) is respectively for the first - erasing count table 122, the first, the storage such as the system storage control unit = the first '' and each - storage unit 121_ has a plurality of storage areas (4), such as S1~ shown in the figure, and the parent_blocks 124' in the first-erasing count table 122 are as private as in the figure, and are stored as _, stored The number of erase instructions executed by each of the coffee blocks 123 in the single frame 121; in other words, the storage block & corresponds to the recorded block... the storage block 1 corresponds to the count block (3)., and so on. _ \ h The structure of the single-flash body 14 is also referred to the second (the figure further includes a plurality of first data storage units (10) Bu service (4) and a plurality of tables (·,) 142, and each The first value storage unit 141 is the second data transmitted by the control unit 16, and the second-bean material storage unit 141 has a plurality of 200915065 respectively. The storage block 143, for example, the milk-to-deletion is equal to each storage block 123; the storage capacity (4) of the _: sub-block 143, as shown in the figure, is ^=2142: Each of the recording block storage blocks 143 performs the erase and save storage, and the storage block is replaced by 5 for each storage block in the 141. The storage block Mi corresponds to the corresponding recording area of the storage area. Block T2..., and so on. : When the first-erase count table 122 or the second wiper storage unit 121 or the first-recorded -# wiper "number #... - When the number of storage blocks 123 or 143 exceeds the limit value, for example, the single layer unit flash memory value and the multi-layer early element flash memory 14 Store d block first - limit value 'At this time' control unit 16 will store the store to find the first block in the block 123 or 143 action, the detailed coffee Kameaki _ Lang: Axis save her exchange of Xu Cai Lang Yuan dance two (four) Different structure, allow more Mm (four) 'her copper - device (four) 峨 次数 在 在 在 在 Γ _ , , _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Nk Early reading early reading of the first limit of the flash 纽 Γ 咖 咖 咖 咖 咖 咖 咖 咖 咖 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为 为The storage of the flash memory in the early layer unit (4) and the 4 single-domain memory, the county quantity is in the second limit value, for example: the first-limit Μ Μ music value is large i, coffee. The limit value is 1G. , coffee, and the second limit value is 200915065 歹ςΓ, the invention of the financial law system includes. Money, such as step _ (four) Wei to m (four) _ (four) = ΙΓ yuan 16 according to the type of the pen to choose to store _ _ _ __ : Such as 2 = Γ Γ & quot 料 料 料 料 料 料 料 料 料 10 10 10 10 10 10 10 10 10 10 10 10 10 10 妓 10 10 妓 妓 妓 妓 妓 妓 妓 妓 妓 妓 妓 妓 妓 妓 妓 妓 妓The multi-level cell flashes _14 to Γ ΓΓ ΓΓ ΓΓ ΓΓ ΓΓ 则 则 则 则 则 则 ΓΓ ΓΓ ΓΓ ΓΓ ΓΓ 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之 反之When selecting single-layer flash memory 12, please refer to the fourth figure-^^^S401 ^ 16 12 ^ to store the resource_yuan 121 address. If the step is followed by _, do you need to first fine? , then _s _ _ slave slave, 疋 121 in the storage block 123 address, and the end of the entire process as step 4; butterfly is required to perform erasing age _ under - _ ship; step 5 Wei _ The erasing instruction in the recording block 124 of the first erasing tree corresponding address is shown on the step side. The wiping object 122 is removed. The stitching exceeds the first limit value.: 3⁄4 • No more than, such as step move _ must + ♦ 单元 单元 = = = =: After the order, the plum is written to the block 123 address, and the whole process is terminated as in step S4G8'. Then, proceed to the next step _, the newly specified memory structure is a multi-level cell flash memory. As shown in the step test, search for and obtain Nayuan _ 咖 4 峨 峨 娜 娜 娜 咖 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财And in step S4u, the data in the corresponding storage block 143 selected in the multi-layer single το flash memory 14 and the storage block 123 in the single-layer unit flash memory 12 exceeding the first-limit value. The inner dragons are replaced with each other and newly written, and then the entire operation method can be ended as shown in step S412. In another aspect, when the control unit 16 selects the multi-level cell flash memory 14, please refer to the fifth figure at the same time. As step _, the control unit 16 selects the multi-layer single-mail flash memory to be used for storing materials. The second data storage unit 141_, as shown in the step, is judged to be "to be finely erased: if ^, 贞, 步, for example, step 3 directly writes the second stipend designated by the person to store early το 141 The storage block 143 address, and the entire process is completed as in step lion 4; conversely, if it is judged in step _ that the erasing instruction needs to be executed, the next step is performed. 5. Step 5 is carefully recorded in the second The number of erase instructions in _(4) of the address corresponding to the number table 142 is erased. Further, as shown in step _6, it is determined whether the number of erase instructions recorded by the second erase count table 142 exceeds the second limit value: if not exceeded, the step is skipped, and then the erase command is executed first, and then The data is written to the storage block (4) bit pair of the second data storage unit (4), and the entire process is terminated as the step 8; otherwise, if the second limit value is exceeded, the next step S509' is performed to the control unit 16 to re-specify the stored memory. The body architecture is a single layer unit flash memory 12. And as shown in the step coffee, searching and taking the _ unit flash memory (4), the decimal table 122 is the lowest value of the corresponding storage block (2) and as shown in step _ The data in the corresponding layer (10) 123 of the single layer single butterfly memory (4) is exchanged with the material in the storage block 143 of the multi-layer unit flash memory currency exceeding the second limit value, and is woven. As shown in the step, the end of the 200915065 whole operation method is specified - the actual example is explained, and the first picture and the second (a), (6) picture are also referred to. When the control is early 7G 16 , the data is saved to the single layer unit flashing. When the storage block S1 of the first data storage unit (2) in the memory 12 is first, it is determined whether the number of erase instructions recorded in the record block stored in the first erase count table 122 is greater than the first limit value. Then, the control unit Μ searches for the multi-layer single · 〗 "Financial second: _ county yuan 141 towel forest most money in addition to the number of instructions storage block _, the storage block S1 and the storage block m6 data in each other Exchange, and update the storage address, so that you can single-level one-touch erase command To avoid. The scalloped material storage list ends the service life early. Vice versa, no longer repeat the account. In summary, since the present invention separates a single-layer unit flash memory from a multi-layer unit flash memory, the following is a summary of the flash memory of the unit flash memory, Naigao, and Judah. Xie Chang loses the advantages of low-cost and high storage capacity density from the multi-layer unit. 1. With the operation method, the average single-layer unit flash memory and multi-layer single memory are used to turn off the memory. The erasure and writing of the number 'to make the two to achieve the goal - to balance the consumption, to play a better memory month b 'this is unmatched by the prior art. The above-mentioned embodiment is a technical idea and characteristic of the invention, and the purpose of the invention is to enable the person who can rely on the _ to be transferred to the post only to the postal Wei Wei, when it is not possible to limit the decoration is covered in this Within the scope of the invention patent. 12 200915065 [Simple description of the diagram] The second picture is the intention of the county (4) combined flash memory device. A schematic diagram of copper in the café. Brother-(_ is a schematic diagram of the structure of the multi-layered single-dragon-dragon 12, 4δ-remembered body used in the present invention. The second figure is a flow chart of the m-section of the reading method of the present invention. The fourth figure is the turning-in age to the single material. Yuan. , ^ h has a schematic diagram of the process of stealth. The fifth figure is the storage of the invention to the multi-level unit [the main component symbol description] 4 body _ flow diagram. 10 hybrid memory device 12 single-layer unit flash Memory (SLC) 121 First Data Storage Unit (DBT1~DBTS) 122 First Erasing Counting Table (ECT BUTS) 123 Storage Block 124 Recording Block 14 Multi-Level Cell Flash Memory (MLC) 141 Second Data Storage unit (DBTi~DBTS) 142 second erasing counter table (ECT BUTS) 143 storage block 144 recording block 16 control unit 13