TW200912498A - Thin film transistor and manufacturing method thereof and liquid crystal display device using the same - Google Patents

Abstract

A thin film transistor, which includes a gate electrode, a gate insulation layer, a semiconductor layer and a source/drain metallization layer, a manufacturing method of the TFT and a liquid crystal display device using the same are provided. The gate electrode and the gate insulation layer covering the gate electrode are disposed on a substrate. The semiconductor layer is disposed on the gate insulation layer. The source/drain metallization layer is disposed at two sides of the semiconductor layer and includes a first, a second and a third conductive layer. These conductive layers are disposed on the semiconductor layer sequentially. The lower surface of the first conductive layer is fully contacted with the upper surface of the semiconductor layer, and the upper surface is partially exposed from the second conductive layer. The lower surface of the third conductive layer is fully contacted with the upper surface of the second conductive layer.

Description

200912498

Sanda number: TW3819PA IX, invention said: [the invention belongs to the field of technology] The invention uses the liquid crystal display of the source and the nucleus of the liquid crystal display panel of the liquid crystal display panel and the manufacturing method thereof $板' and especially relating to a thin film transistor having a multi-layer structured layer and a method for fabricating the same, and a liquid crystal display panel (LCD pa: e〇) : The rapid progress of the balance of technology and its advantages of light weight, small size, low power and low radiation make LCD panels widely used in personal digital assistants (PDAs). Pen 5 computer, digital camera, mobile phone, computer screen and flat-panel TV and other electronic products. In addition to the industry's active investment in research and development, such as the use of large-scale production equipment, the quality of liquid crystal display panels continue to improve ' And the grid continues to drop', thus making the application field of the liquid crystal display panel rapidly expand. The conventional liquid crystal display panel of the thin film transistor is made of five masks. First, a gate is formed on the glass substrate by using a first mask process. Then, a gate insulating layer, a germanium semiconductor layer, and an n+ doped germanium layer are formed on the gate by a second mask process. Secondly, The source region and the drain region are formed in the third mask process. Further, a fourth mask process is performed to form a protective layer overlying the n+ doping; the ε layer and the shixi semiconductor layer. Finally, the fifth step is performed. The reticle process forms a halogen electrode on the protective layer, 昼素200912498

Three violation number: TW3819PA • The electrode is electrically contacted with the non-polar region by the contact hole of the protective layer (C〇ntaCth〇le). Generally, in the process of forming the source region and the drain region, a metal layer of a single layer or a multilayer structure is deposited on the n + doped germanium layer, and the pattern of the photoresist layer is used by wet etching. The metal layer is wet etched, and then the semiconductor layer is etched out of the channel region by dry singulation, while the source region and the drain region are formed on both sides of the channel region. Please refer to the second drawing, which shows a cross-sectional view of the thin transistor f after etching the channel region according to the pattern of the photoresist layer in the conventional process. The thin film transistor 10 includes a gate 12, a gate insulating layer 13, a germanium semiconductor layer 14, an n+ doped germanium layer 15, and a metal layer 16. The gate 12 is disposed on and partially covered on the glass substrate n, and the gate insulating layer 13 is disposed on the glass substrate 11 and covers the gate 12. The Shixia semiconductor layer 14, the n+ doped germanium layer 15 and the metal layer 16 are sequentially disposed on the gate insulating layer 13. When the etching step is performed in the process, a photoresist layer PR is first formed on the metal layer 16, and the photoresist layer PR has an opening w having a width D?. In general, this width D0 is essentially the width of the channel to be obtained. However, since the wet etching is an isotropic etching method, an undercutting phenomenon easily occurs under the photoresist layer pR when the metal layer 16 is etched, so that the opening formed by the metal layer 16 is etched. The width D0 is greater than the width D0 of the opening dw of the photoresist layer PR, which further causes the channel region width distortion formed by the dry etching of the n+ doped germanium layer 15 and the germanium semiconductor layer 14. As shown in FIG. 1, the channel region is not engraved. The width D1 is larger than the width of the opening W of the photoresist layer PR. The wider channel region causes problems such as an increase in the leakage current value of the thin film transistor, a decrease in the on/off current ratio, and further reduces the switching response time 5 and the boosting port is displayed. Miscellaneous noise, overall 200912498

Three of this number: TW3819PA affects the quality of the LCD display panel. SUMMARY OF THE INVENTION In view of the above, the present invention provides a thin film transistor, a method for fabricating the same, and a liquid crystal display panel using the same, which etches the source and the drain metallization layer of the multilayer structure by different methods without significantly increasing Under the condition of cost, the channel width of the thin film transistor can be effectively controlled in the process, and the process quality of the thin film transistor can be further maintained, and the utility model has the advantages of no need to purchase process, and can be compatible with the traditional process. According to one aspect of the invention, a thin film transistor is provided comprising a gate, a gate insulating layer, a semiconductor layer, and a source and drain metallization layer. The gate is disposed on a substrate, and the gate insulating layer is disposed on the substrate and covers the gate. The semiconductor layer is disposed on the gate insulating layer and includes a germanium layer and a doped layer. The stone layer is located on the gate insulating layer, and the doped layer is located on both sides of the layer, and the lower surface of the doped layer is in contact with the layer. Located on both sides of the Shixi layer. The sides of the doped layer are opposite each other. The source and drain metallization layers are located on opposite sides of the semiconducting L' body layer and include a first conductor layer, a second conductor layer and a third conductor layer. The first conductor layer is disposed on the doped layer, and the lower surface of the first conductor layer is in complete contact with the upper surface of the doped layer without exposure. The second conductor layer is disposed on the first conductor layer, and the upper surface portion of the first conductor layer exposes the second conductor layer. The third conductor layer is disposed on the second conductor layer, and the lower surface of the third conductor layer is in complete contact with the upper surface of the second conductor layer without exposure. According to another aspect of the present invention, a method of manufacturing a thin film transistor is proposed. First, a gate and a gate insulating layer are sequentially formed on a substrate.

Sanda number: TW3819PA " On, the gate insulation layer covers the gate. Next, a semiconductor layer is formed overlying the gate insulating layer. Next, a source and a drain metallization layer having a three-layer structure are formed overlying the semiconductor layer. Then, some of the source and drain metallization layers are engraved according to a pattern wet pattern. Then, the remaining source and the electrodeless metallization layer and a portion of the semiconductor layer are dry etched in accordance with the pattern. According to still another aspect of the present invention, a liquid crystal display panel is provided, comprising a plurality of scanning lines, a plurality of data lines, and a plurality of thin film transistors arranged in an array. Each of the thin film transistors includes a gate, a gate insulating layer, a half conductor layer, and a source and a non-polar metallization layer. The idle electrode is disposed on the substrate and electrically connected to one of the broom wires, and the gate insulating layer is disposed on the substrate and covers the gate. The semiconductor layer is disposed on the gate insulating layer and includes a germanium layer and a doped layer. The germanium layer is on the gate insulating layer, the doped layer is on both sides of the germanium layer and the lower surface of the doped layer is in contact with the germanium layer. The sides of the doped layers on both sides of the tantalum layer are opposite each other. The source and the drain metallization layer on the side of the two sides of the semiconductor layer and the electrodeless metallization layer are electrically connected to one of the data lines. The source and drain metallization layers comprise a first, a second and a third conductor layer. The first conductor layer is disposed on the semiconductor layer, and the lower surface thereof is in complete contact with the upper surface of the doped layer without exposure. The second conductor layer is disposed on the first conductor layer, and an upper surface portion thereof exposes the second conductor layer. The third conductor layer is disposed on the second conductor layer and the lower surface thereof is in complete contact with the upper surface of the second conductor layer without exposure. In order to make the above description of the present invention more comprehensible, the preferred embodiment hereinafter will be described in detail with reference to the accompanying drawings: 200912498 Sanda number: TW381卯a [Embodiment] Please refer to FIG. A schematic view of a portion of a liquid crystal display panel in accordance with a preferred embodiment of the present invention is shown. The liquid crystal display panel 2 includes a substrate 110, a plurality of scan lines 130, a plurality of data lines mo, and a plurality of thin film transistors 1 arranged in an array. The scan lines 13A and the data lines 15A are disposed on the substrate 110, and the data lines 15〇 are substantially orthogonal to the sweep lines 130. Please also refer to Fig. 3, which shows a cross-sectional view of a thin family of transistors in Fig. 2. Each of the thin film transistors 1 includes a gate 17, a gate insulating layer 19, a semiconductor layer 2, and a source/drain metallization layer 30. The gate 17 is disposed on the substrate 110 and electrically connected to a scan line 130 (as shown in FIG. 2). The gate insulating layer 19 is disposed on the substrate 110 and covers the gate 17. The semiconductor layer 20 is disposed on the gate insulating layer 19 and has a channel region 实质上 substantially corresponding to the gate 17 above. The semiconductor layer 20 includes a silicon layer and a doped layer 24. The germanium layer 22 is on the gate insulating layer 19, and the doped layer 24 is located on both sides of the germanium layer 22. The lower surface of the doped layer 24 is in contact with the germanium layer 22, and the doped layer 24 on both sides of the germanium layer 22 is The sides are opposite each other. The source and drain metallization layers 3 are located on both sides of the semiconductor layer, and the source and drain metallization layers 3 on one side are electrically connected to a data line 150 (as shown in Fig. 2). The source and the metallization sound 30 includes a first conductor layer 32, a second conductor layer 34 and a third conductor layer 36. The first conductor layer 32 is disposed on the doped layer 24, the lower surface of the first conductor 32 is completely in contact with the upper surface of the doped layer 24, and the second conductor layer 34 is disposed on the first conductor layer 32, the first conductor Layer u 10 200912498

Sanda number: TW3819PA The upper surface portion partially exposes the second conductor layer 34. The third conductor layer % is disposed on the second conductor layer 34, and the lower surface of the third conductor layer 36 is in complete contact with the upper surface of the second conductor layer 34 without exposure. Further, each of the two adjacent scan lines 13A and each of the two adjacent data lines 150 form a halogen region p, and each of the thin film transistors (10) is located in the corresponding halogen region p. In addition, the liquid crystal display panel further includes a plurality of halogen elements 170' each of which is located in the corresponding pixel-. region P. The source and the drain metallization layer 30b on the other side of each of the thin film transistors 100 are electrically connected to the halogen electrode 170 in the same halogen region p. In the liquid crystal display panel 200, the scan lines 13 sequentially enable the thin film transistors 1 同一 in the same row, and thereby input the data voltages to the thin film transistors 100 for the data lines 15 The display. These thin film transistors 100 are formed in accordance with a method of manufacturing a thin film transistor of a preferred embodiment of the present invention. Hereinafter, a method of manufacturing a thin film transistor 100 will be described as an example, which is accompanied by Fig. 4 and Figs. 5A to 5F. 4 is a flow chart showing a method for fabricating a thin film transistor according to a preferred embodiment of the present invention; and FIG. 5A is a schematic view showing a gate and a gate insulating layer formed on a substrate; FIG. 5B is a schematic view A schematic diagram of the semiconductor layer formed on the gate insulating layer of FIG. 5A; FIG. 5C is a schematic view showing the source and drain metallization layers formed on the semiconductor layer of FIG. 5B; and FIG. 5D shows the formation of the photoresist layer. Schematic diagram of the source and drain metallization layers of FIG. 5C; FIG. 5E is a schematic view showing the source and drain metallization layers of the fifth etching diagram of the wet etching; FIG. 5F shows the fifth etching of the dry etching Schematic diagram of the source and drain metallization layers of the figure and the semiconductor layer. 200912498

Sanda No.: TW3819PA The manufacturing method of this embodiment first performs the steps of forming the gate 17 and the gate insulating layer 19. As shown in step 410 and FIG. 5A, the gate 17 and the gate insulating layer 19 are sequentially formed on the substrate 110, the gate electrode covers only a portion of the substrate 11 〇, and the gate insulating layer 19 covers the gate 17 on. The common material of the gate 17 is, for example, a single conductive metal structure such as ingot or copper. However, in the present embodiment, the gate 17 may also have a multilayer structure such as a multilayer metal structure of titanium/aluminum/titanium. Secondly, the common material of the gate insulating layer 19 is widely used as silicon nitride, and other conventional high dielectric constant materials.

V can be applied to this. Next, as shown in step 430, a semiconductor layer 20 is formed over the gate insulating layer 19. In this embodiment, the semiconductor layer 20 includes a germanium layer 22 and a doping layer 24 as shown in FIG. 5B. The stone layer 22 is, for example, an amorphous siiicon iayer and covers the gate insulating layer 19. The doping layer 24 is, for example, an n+ doped yttrium layer, the system of which covers the ruthenium layer. 22 on. Next, in step 450, a source and drain metallization layer 30 is formed overlying the semiconductor layer 20. In this embodiment, the step of forming the source and the electrodeless metallization layer further includes the following steps. First, the first conductor layer 32 is formed to cover the semiconductor layer 20. In the present embodiment, the first conductor layer 32 is particularly accumulated on the doped layer 24, and the thickness of the deposition is, for example, approximately gstrom. The material includes, for example, tantalum, titanium nitride or a crane. It is used to form a second conductor layer 34 on the first conductor layer 32 for good adhesion of the source electrode metallization layer 3Q to the semiconductor layer 2q. In the present embodiment, the thickness of the first conductor layer 34 is, for example, about μ(8)~5, and 12 200912498. The material of the material is, for example, copper or aluminum, and the thin film transistor 100 is lowered by the good electrical conductivity of the material. RC time delay. Then, a third conductor layer 36 is formed on the second conductor layer 34. In this embodiment, the thickness of the third conductor layer 36 is, for example, about 305 A, and the material thereof includes, for example, a key, so that the source and the drain metallization layer 30 form a good ohmic contact surface with the semiconductor material of the rear process (ohmic). Contact). In practical applications, the aforementioned source and drain metallization layers 30 are formed.

Thereafter, a photoresist layer PR having a pattern is formed on the source and drain metallization layers 30. As shown in Fig. 5D, the photoresist layer has an opening W substantially corresponding to the upper side of the gate 17. The method of manufacturing a thin film transistor according to this embodiment is followed by a step 470 of wet etching a portion of the source and the drain metallization layer 3 in accordance with the pattern of the photoresist layer PR. As shown in FIG. 5E, in the wet residual step of the embodiment, the first conductor layer 32 is pasted as an etching end point, and the third conductor layer 36 and the second conductor layer under the opening w are removed. 34. After the wet etching, the lower surface of the third conductor layer 36 is completely in contact with the upper surface of the second conductor layer 34 without exposure. After the step of engraving the last name, the step 490 is followed by a pattern of dry etching of the remaining source and drain metallization layers 3〇L and then dry etching of the portion of the semiconductor layer 20. As shown in Fig. 5F, in the dry silking step of the example, the doping corresponding to the first side at the opening w is mutually mutually === 13 200912498

Sanda number: TW3819PA The upper surface portion of layer 32 exposes the outside of second conductor layer 34, and the lower surface of first conductor layer 32 is in complete contact with the upper surface of doped layer 24 without exposure. In this embodiment, step 490 can be performed by using a conventional dry etching semiconductor layer 2's machine without the need for a new machine. Furthermore, since the first conductor layer = having the minimum thickness of the leads M 3 2, 3 4 and 36, the effect of the first conductor layer 32 on the semiconductor layer 2 etch rate can be reduced. After the two etching steps are performed, the doping layers 24a and 24b corresponding to the two sides of the opening W form the source region and the polar region of the thin film transistor 1 而, and correspond to the source sides of the π W sides. And the drain metallization layer and 3〇b form the source electrode layer and the drain electrode layer, respectively. Further, correspondingly, the (four) 22 between the doped layers 24a and 24b forms the channel region c. Since the first conductor layer 32 is not wetted! Insects, and its coverage on the doped layer% can prevent the length of the channel area C from being wet by the third and second conductor layers 36 and 34, due to the undercut phenomenon (Fu (10) (four) tons) The effect of the reduced accuracy is such that the width of the semiconductor layer 20 is substantially equal; the width of the opening '' ensures that the thin film transistor 100 has a predetermined channel region C length. In addition, in the embodiment, the third conductor layer 36 and the second conductor layer 34 are removed by wet etching, and the first conductor layer 32 is removed by dry etching. In another embodiment, the third conductor layer 36 is removed by wet etching, and the second conductor layer 34 and the first conductor layer 32 are removed by dry etching. The manner in which the plurality of material layers in the source and drain metallization layers 30 are etched by different etching methods is within the scope of the present invention. 14 200912498

Sanda number: TW38I9PA After the above step 490, the manufacturing method of the present embodiment further includes the step of the photoresist layer PR for performing the rear lightening step. After removing the photoresist layer PR, the thin film transistor 100 of the example shown in Fig. 3 is completed.住灵& Μ Μ 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳In one embodiment, the bulk layer of the photoresist layer is covered with one half, and the third and second wet etching are performed by wet etching. Such an undercut phenomenon can still ensure the degree of lateral etching when etching the second layer of the semiconductor, thereby improving the quality of the process. Secondly, the width of the precise channel region when zinc is formed into the channel region avoids the problem that the channel length is long: good quality control is controlled in the process. In addition, because this:: the introduction of a variety of transistor crystal money engraving steps can use the wet shaft and dry line in the original process towel 'do not need to add additional button engraving machine ^ 及 and dry remnant The machine does not need to change the process steps significantly, except that it does not increase the process film-forming transistor structure and process technology. It is also possible to be compatible with the original thin-practices, although the invention has not been used to limit the invention. The U embodiment of the present invention is disclosed above, and those skilled in the art can make improvements and refinements without departing from the technical field of the invention. Accordingly, the invention is to be construed as being limited by the scope of the various patents. , Fan Fanyuan deserves the attached application 200912498

Sanda number: TW3819PA ' [Simple description of the drawing] FIG. 1 is a cross-sectional view showing a thin film transistor in which a channel region is etched according to a pattern of a photoresist layer in a conventional process; FIG. 2 is a view showing a preferred embodiment of the present invention. FIG. 3 is a cross-sectional view of a thin film transistor in FIG. 2; FIG. 4 is a flow chart showing a method of manufacturing a thin film transistor according to a preferred embodiment of the present invention; 5A is a schematic view showing the gate and the gate insulating layer formed on the substrate, FIG. 5B is a schematic view showing the semiconductor layer formed on the gate insulating layer of FIG. 5A; FIG. 5C is a view showing the source and the drain metal FIG. 5D is a schematic view showing the photoresist layer formed on the source and drain metallization layers of FIG. 5C; FIG. 5E is a view showing wet etching. A schematic diagram of the source and drain metallization layers of the 5D pattern; and FIG. 5F illustrates the source and gate metallization layers of the dry etching 5E, and the semiconductor layer. 16 200912498

Sanda number: TW3819PA ' [Main component symbol description] 10, 100: thin film transistor 11: glass substrate 12, 17: gate 13, 19: gate insulating layer 14: germanium semiconductor layer 15: n + doped germanium layer 16 Metal layer 20: semiconductor layer 22: germanium layer 24: doped layer 24a: side doped layer 24b: doped layer 30 on the other side: source and drain metallization layer 30a: - source of side And the drain metallization layer 30b: the source and drain metallization layer 32 on the other side: the first conductor layer 34: the second conductor layer 36: the third conductor layer 100: the thin film transistor 110: the substrate 13 0. Cat Line 150: Data Line 170: Alizarin Electrode 17 200912498

Sanda number: TW3819PA 200. LCD display panel C: Channel area DO, D1: Width P: Alizarin area PR: Photoresist layer W: Opening

18

Claims (1)

200912498 Sanda number: TW3819PA X. Patent application scope: 1. A thin film transistor comprising: a gate disposed on a substrate; a gate insulating layer disposed on the substrate and covering the gate; a semiconductor a layer disposed on the gate insulating layer, the semiconductor layer comprising: a silicon layer on the gate insulating layer; and a doped layer on both sides of the layer, wherein the holding a surface below the impurity layer is in contact with the ruthenium layer, and sides of the doped layer on both sides of the ruthenium layer are opposite to each other; and a source and a drain metallization layer are located on both sides of the semiconductor layer, and include a first conductor layer disposed on the doped layer, the lower surface of the first conductor layer is in complete contact with the upper surface of the doped layer without exposure; a second conductor layer is disposed on the first conductor layer The upper surface of the first conductor layer partially exposes the second conductor layer; and a third conductor layer is disposed on the second conductor layer, the lower surface of the third conductor layer and the second conductor layer Complete contact without exposure . 2. The thin film transistor of claim 1, wherein the thickness of the second conductor layer and the thickness of the third conductor layer are both greater than the thickness of the first conductor layer. 3. The thin film transistor of claim 2, wherein the first conductor layer has a thickness of about 250 A (angstrom). The thin film transistor of the second aspect of the invention, wherein the second conductor layer has a thickness of about 1500 5,000 to 5,000 Å. 5. The thin film transistor of claim 2, wherein the third conductor layer has a thickness of about 350. 6. The thin film transistor according to claim 1, wherein the material of the first conductor layer comprises titanium, titanium nitride or tungsten, and the material of the second conductor layer Including aluminum or copper, the material of the third conductor layer comprises a molybdenum. 7. A method for manufacturing a thin film transistor, comprising: sequentially forming a gate and a gate insulating layer. On the substrate, the gate insulating layer covers the gate; forming a semiconductor layer overlying the gate insulating layer; forming a source and a drain metallization layer overlying the semiconductor layer, the source and the gate The electrode metallization layer has a three-layer structure; partially etching the source and drain metallization layers according to a pattern; and dry etching the remaining source and drain metallization layers and portions of the semiconductor layer according to the pattern. 8. The method of claim 7, wherein the step of forming the source and drain metallization layers further comprises: forming a first conductor layer on the semiconductor layer, the material of the first conductor layer Including titanium, titanium nitride or tungsten; forming a second conductor layer on the first conductor layer, the second conductor layer 20 200912498 Sanda number: TW38丨9PA material comprises copper or slag; and forming a second conductor The material layered on the second conductor layer comprises molybdenum. The method of manufacturing the semiconductor layer as described in the application of the layer (4) includes: forming a germanium layer over the gate insulating layer; and forming a doped layer overlying the germanium layer 2. In the step of the manufacturing method according to claim 9 of the patent application, the third layer is in accordance with the figure (10) and the dry-type engraving as described in claim 10. In the step, the first guiding layer is engraved according to the pattern, and the manufacturing layer is the same as the manufacturing method described in the ninth item of the patent. The method of manufacturing the third conductor layer according to the pattern, wherein the second conductor layer is engraved according to the pattern of the second conductor layer. ^为彳> The hetero layer and part of it; 5 eve layer. Forming the manufacturing method of the seventh item of the patent scope, wherein after the step of the source and the electrodeless metallization layer, the method further comprises: having a photoresist layer on the source and the metallization layer, the first resistance Layer I5. The method of manufacturing the dry-type money engraving as described in claim 14 of the patent application, the method further comprises: m, wherein in 200912498, this is edited: 1 " remove the photoresist layer. 16. A liquid crystal display panel comprising: a substrate; a plurality of sweeping cat wires' disposed on the substrate, a plurality of data lines disposed on the substrate and substantially orthogonal to the scan lines; and an array Aligning a plurality of thin film transistors, each of the thin film transistors includes: a gate disposed on the substrate and electrically connected to one of the scan lines; a gate insulating layer disposed on the substrate Covering the gate; a semiconductor layer disposed on the gate insulating layer, the semiconductor layer comprising: a germanium layer on the gate insulating layer; and a doped layer on both sides of the hair layer, The lower surface of the doped layer is in contact with the ruthenium layer, and the sides of the doped layer on both sides of the ruthenium layer are opposite to each other; and a source and a drain metallization layer are located on both sides of the semiconductor layer, The source and the drain metallization layer are electrically connected to one of the data lines, and the source and drain metallization layers comprise: a first conductor layer disposed on the doped layer, a lower surface of the first conductor layer and a surface above the doped layer Full contact without exposure; a second conductor layer disposed on the first conductor layer, the upper surface portion of the first conductor layer exposing the second conductor layer; and 22 200912498 Sanda number: TW3819PA #一一第The three conductor layer ' is disposed on the second conductor layer, and the lower surface of the third conductor layer is in complete contact with the upper surface of the second conductor layer without exposure. The liquid crystal display panel of claim 16, wherein the thickness of the second conductor layer and the thickness of the third conductor layer are both greater than the thickness of the first conductor layer. The liquid crystal display panel of claim 17, wherein the first conductor layer has a thickness of about 25 Å. // If the liquid crystal display panel described in claim 17 is applied, the thickness of the first conductor layer is about 1500~5000 Λ. Please refer to the liquid crystal panel according to item 17 of the patent scope, wherein the conductor layer has a thickness of about 350 A. The liquid (four) display panel according to Item 16 of the patent scope, wherein the material of the conductor layer comprises titanium, titanium nitride or Zhan material comprises material copper, and the material of the third conductor layer is packaged.