200910480 24317twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種封裝結構及其製作方法，且特別 是有關於一種晶圓級封裝結構及其製作方法。 【先前技術】 近幾年來’隨著攜帶式（portable)電子產品、手持式 通訊以及及消費性電子產品之成長性已凌駕於傳統個人電 腦（PC)產品之上，電子元件不斷地朝向高容量、窄線寬 的高密度化、高頻、低耗能、多功能整合方向發展。而在 積體電路（integrated circuit, 1C )封裝技術方面，為配合言 輸入/輸出（I/O)數、高散熱以及封裝尺寸縮小化的要^ 下，使得晶粒級封裝（chip scaiepackage, csp)、曰 封裝（wafer level package )等高階封裝技術需求不古、及 有別於傳統以單-晶片（die)為加卫標的的封 術’晶圓級封裳以晶圓（wafer)為封袭處理的對象，j ，目的在簡化晶片之封錢程，以節省時間及 ^曰 圓上之積財路製作完成以後，便可直接對整=^：_曰 ^裝製程，其後再進行晶圓切割（wafersaw)的二乍仃 =多個晶一製作完成之-封 焊墊裝體_板接合時’習知技術是在晶片之 塊舆載二導=填充於晶片封裝趙之凸 登之間然而，金屬凸塊之彈性較差，在凸 200910480 24317twf.doc/n 塊與接墊間之電性連接受到應力時，金 衝，因此容易造成凸塊與接塾間之電性連勺做為緩 塊與接墊間之連接的可靠度，ς而貝降二 封裝體與載板之間的電性連接的可靠度。 降低a曰片 【發明内容】 本發明另提出-種晶圓級封裝結構， 載板間之電性連接具有較高的可#度。，、θ、裝體與 本發明提供-種晶圓級封裝結構的製作方法 晶片封裝體與載板之間電性連接之可靠度。 回 轉決上制題，本發贿出―種^圓崎裝結構， 匕括-晶>1、多個球底金屬層以及多 具有多個焊塾以及一保護層’其中保護層具有二1 :以將烊祕露。球底金屬層覆蓋倾層縣露出之焊 丄聚=凸塊配置於球底金屬層上，其中各聚合物凸塊 j-聚合2層、至少-導電柱以及—接合層。聚合物層 貫孔’而導電柱配置於貫孔中，且接合層覆蓋 導電柱，並透過導電柱與對應之焊墊電性連接。 在本發明之-實施例中，上述聚合物凸塊之材質為聚 醯亞胺（Polyimide)或聚合物（p〇lymer)。 在本發明之-實施例中’上述導電柱之材質為鈦鶴合 金，銅，金。 曾在本發明之-實施例中，上述聚合物層之高度大於於 V電柱之尚度，而位於導電柱上方之接合層具有一凹陷。 200910480 m-Aw / ντνν/名· 24317twf.doc/n 在本發明之一實施例中，上述接合層之材質為金。 本發明另提供一種晶圓級封裝結構的製作方^ w勹 括下列步驟。首先，提供一包括多個晶片之晶圓，其^各 晶片具有多個焊墊以及一保護層，而保護層具有多j固 開口以將焊墊暴露。接下來，在各焊墊上形成一壤底金屬 層。之後，在各球底金屬層上形成一聚合物層，其$各取 合物層具有至少一貫孔。然後，在各貫孔中形成—導電柱= 接下來，在各聚合物層上形成一接合層，覆蓋導電柱，並 使各接合層透過導電柱與對應之焊墊電性連接。 亚 在本發明之一實施例中，上述聚合物凸塊之 醯亞胺或聚合物。 <貝马來 在本發明之一實施例中，上述形成一接合芦 括以下步驟。錢’在保護層以及聚合物層上ς成一^ 化罩幕二圖案化罩幕具有多個第二開口以暴露出貫孔。ς 下來’藉蝴案化罩幕魏導電柱以在各貫孔巾形成一導 電柱。之後，移除圖案化罩幕。然後，在導電柱上形成一 接合材料層，並使接合材料層透過導妹與焊墊電性連 接。接下來，圖案化接合材料層以形成接合層。 ηΐίΐΓ之—實施例中，上述圖案化接合材料層之方 法包括微影餘刻。 ★在f發明之—實施例中，上述聚合物層之厚度大於導 電柱之高度’而位於導電柱上方之接合層具有一凹陷。 在本發明之-實施例中，上述導電柱之材質為敛鶴合 200910480 /v^yjvz. 24317twf.doc/n 在本毛明之-實施例中，上述接合層之材f為金。 基於上述，本發明採用彈性較佳之聚合物凸塊取代習 知金屬凸塊，因此，在聚合物凸塊與載板之接㈣的電性 連接受到應力時’聚合物凸塊可產生形變㈣收應力。如 此’可減少聚合物凸塊與接塾間之電性連接所受到之 力，進而提高之可靠度。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 圖1A至圖1J為本發明一實施例之晶圓級封裝結構的 製作方法流《。請參關1A至圖1：Γ，本發明之晶圓級 封裝結構的製作方法包括下列倾。首先，請參照圖认， 提供一包括多個晶片100a(圖中僅繪示一晶片1〇〇a)之晶 圓100其中各曰曰片l〇〇a具有多個焊墊以及一保護 層120a，且保濩層i2〇a具有多個第一開口 122a，而第一 開口 122a暴露一部分的焊墊n〇a。 接下來，請參照圖1B，在各焊墊u〇a上形成一球底 金屬層130 (見圖η及圖⑴。上述形成球底金屬層13〇 之方法，可在晶圓100表面以電鑛之方式形成一全面覆蓋 之金屬層130，，而在後續步驟中再將金屬層13〇，圖案化以 形成球底金屬層130。 之後’請參照圖1C至圖1G，在各球底金屬層13〇(見 圖II及圖1J)上形成一聚合物凸塊14〇，其中各聚合物凸 200910480 / 24317twf*.doc/ii 塊140包括一聚合物層142、至少一導電柱144以及一接 合層146。 在本實施例中，形成聚合物凸塊140之方法可包括下 列步驟。首先’請參照圖1C，在焊墊ll〇a上方之金屬層 130’上形成一聚合物層142，其中各聚合物層142具有至 少一貫孔142a，而上述聚合物層142之材質為聚醢亞胺或 其他聚合物。 然後’請參照圖1D至圖1E，在各貫孔142a中形成 一導電柱144。形成導電柱144的方法例如包括下列步驟。 首先，請參照圖1D，在金屬層130,以及聚合物層142上 形成一圖案化罩幕50，而圖案化罩幕5〇具有多個第二開 口 52，以使貫孔142a由第二開口 52中暴露出來。之後， 請參照圖1E，藉由圖案化罩幕50電鍍貫孔142a以在各貫 孔142a中形成一導電柱144。在本實施例中，上述導電柱 144之材質例如為鈦鎢合金。 ,接下來，請參照圖1F至圖U，在各聚合物層142上 形成一接合層146’其中接合層146覆蓋導電柱144，並使 各接合層146透過導電柱144與對應之焊墊n〇a電性連 接。在本實施财，上述形成接合層146的方法可包括以 :步驟。首先，請參照圖1F ’利用圖案化罩幕5〇，在由 =開π 52中暴露丨來的導電柱144上形成-接合材料層 雷使接合材料層146,麵導餘144與焊塾110a 。然後’請參照圖1G，移除圖案化罩幕50。之 ^參照圖1H至圖…關化接合材料層146,以形成 200910480 ' v-twva 24317twf.doc/n 接合層146。 在本實施例中，可以一微影蝕刻製程將接合材料層 146’圖案化。詳細來說，圖案化接合材料層146，可包括下 列步驟。首先，請參照圖1H，在各貫孔142a上方之接合 材料層146’上形成一罩幕60。接下來，請參照圖u，對未 被罩幕60餘刻之部分接合材料層146’進行餘刻以形成接 合層146,並同時蝕刻金屬層13〇，，以形成球底金屬層 (， 130。之後，請參照圖1J，移除罩幕60。至此，大致完丄 晶圓級封裝結構200之製作。 請參照圖2 ’在完成上述步驟之後，可再對晶圓級封 裝結構200進行切割，以使晶圓級封裝結構2〇〇形成多個 晶片封裝體20〇a，並將晶片封裝體2〇〇a安裝至一載板 上，且在載板70之接墊72與聚合物凸塊丨4〇之間填入導 電膠80，使晶片封裝體2〇〇a與載板7〇電性連接。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a package structure and a method of fabricating the same, and more particularly to a wafer level package structure and a method of fabricating the same. [Prior Art] In recent years, as the growth of portable electronic products, handheld communication, and consumer electronics has surpassed traditional personal computer (PC) products, electronic components are constantly moving toward high capacity. The development of high-density, high-frequency, low-energy, and multi-functional integration of narrow line widths. In the integrated circuit (1C) packaging technology, in order to match the number of input/output (I/O), high heat dissipation, and package size reduction, the chip-level package (chip scaiepackage, csp) ), high-level packaging technology such as wafer level package is not demanding, and is different from the traditional one-chip (die) as the Guardian's seal. Wafer-level sealing is sealed by wafer. The object of the attack, j, aims to simplify the process of sealing the chip, in order to save time and after the completion of the production of the road, the process can be directly applied to the whole =^:_曰^, and then Wafersaws================================================================================================= However, the elasticity of the metal bumps is poor. When the electrical connection between the bumps of the 200910480 24317twf.doc/n block and the pads is stressed, Jin Chong, so it is easy to cause the electrical connection between the bumps and the joints. The reliability of the connection between the slow block and the pad, and the second package The reliability of the electrical connection between the carrier plate. The invention further proposes a wafer level package structure, wherein the electrical connection between the carriers has a high degree of latitude. , θ, package and the invention provide a method for fabricating a wafer level package structure. Reliability of electrical connection between the chip package and the carrier. Rotating on the title, this bribe out of the "type ^ rounded out structure, including - crystal" 1, a plurality of ball bottom metal layer and more with multiple soldering and a protective layer 'where the protective layer has two 1 : Take the secret to reveal. The bottom metal layer covers the exposed solder layer of the tilting layer. The bump = bump is disposed on the bottom metal layer, wherein each polymer bump j-polymerizes 2 layers, at least - a conductive pillar and a bonding layer. The polymer layer is formed in the through hole, and the conductive layer is disposed in the through hole, and the bonding layer covers the conductive column and is electrically connected to the corresponding pad through the conductive column. In an embodiment of the invention, the polymer bump is made of a polyimide or a polymer. In the embodiment of the present invention, the material of the above-mentioned conductive column is titanium crane alloy, copper, gold. In the embodiment of the invention, the height of the polymer layer is greater than the degree of the V-pillar, and the bonding layer above the conductive post has a depression. 200910480 m-Aw / ντνν/名·24317twf.doc/n In one embodiment of the invention, the material of the bonding layer is gold. The invention further provides a method for fabricating a wafer level package structure, comprising the following steps. First, a wafer comprising a plurality of wafers having a plurality of pads and a protective layer is provided, and the protective layer has a plurality of openings to expose the pads. Next, a ground metal layer is formed on each of the pads. Thereafter, a polymer layer is formed on each of the bottom metal layers, each of which has at least a uniform pore. Then, a conductive pillar is formed in each of the through holes. Next, a bonding layer is formed on each of the polymer layers to cover the conductive pillars, and the bonding layers are electrically connected to the corresponding pads through the conductive pillars. In one embodiment of the invention, the above polymer bump is a quinone imine or a polymer. <Bei Malai In an embodiment of the invention, the above-described formation of a joint refining step comprises the following steps. The money' is patterned on the protective layer and the polymer layer. The patterned mask has a plurality of second openings to expose the through holes. ςLet's use the butterfly to cover the Wei conductive column to form a conductive column in each of the perforations. After that, remove the patterned mask. Then, a bonding material layer is formed on the conductive pillar, and the bonding material layer is electrically connected to the bonding pad through the guiding electrode. Next, the bonding material layer is patterned to form a bonding layer. In the embodiment, the above method of patterning the bonding material layer includes lithography. In the embodiment of the invention, the thickness of the polymer layer is greater than the height of the conductive post and the bonding layer above the conductive pillar has a depression. In the embodiment of the present invention, the material of the conductive pillar is a stagnation crane 200910480 /v^yjvz. 24317 twf.doc/n In the embodiment of the present invention, the material f of the bonding layer is gold. Based on the above, the present invention replaces a conventional metal bump with a polymer bump which is preferably elastic. Therefore, when the electrical connection between the polymer bump and the carrier (4) is stressed, the polymer bump can be deformed (four). stress. Such a 'reducing the force of the electrical connection between the polymer bumps and the joints, thereby improving the reliability. The above described features and advantages of the present invention will be more apparent from the following description. [Embodiment] FIG. 1A to FIG. 1J are flowcharts showing a method of fabricating a wafer level package structure according to an embodiment of the present invention. Please refer to FIG. 1A to FIG. 1: Γ, the fabrication method of the wafer level package structure of the present invention includes the following tilting. First, please refer to the figure, a wafer 100 including a plurality of wafers 100a (only one wafer 1a is shown), wherein each of the dies 10a has a plurality of pads and a protective layer 120a And the protective layer i2〇a has a plurality of first openings 122a, and the first opening 122a exposes a portion of the pads n〇a. Next, referring to FIG. 1B, a ball metal layer 130 is formed on each of the pads u〇a (see FIG. η and FIG. 1). The above method of forming the ball bottom metal layer 13 can be performed on the surface of the wafer 100. The method of mineral formation forms a fully covered metal layer 130, and in a subsequent step, the metal layer 13 is further patterned to form a ball-bottom metal layer 130. Thereafter, please refer to FIG. 1C to FIG. 1G for each ball bottom metal. A polymer bump 14 is formed on layer 13A (see FIG. II and FIG. 1J), wherein each polymer bump 200910480 / 24317twf*.doc/ii block 140 includes a polymer layer 142, at least one conductive pillar 144, and a The bonding layer 146. In this embodiment, the method of forming the polymer bumps 140 may include the following steps. First, please refer to FIG. 1C, forming a polymer layer 142 on the metal layer 130' over the pad 〇a. Each of the polymer layers 142 has at least a uniform hole 142a, and the polymer layer 142 is made of a polyimide or other polymer. Then, referring to FIG. 1D to FIG. 1E, a conductive column is formed in each of the through holes 142a. 144. The method of forming the conductive pillars 144 includes, for example, the following steps. Referring to FIG. 1D, a patterned mask 50 is formed on the metal layer 130 and the polymer layer 142, and the patterned mask 5 has a plurality of second openings 52 to expose the through holes 142a from the second opening 52. Referring to FIG. 1E, a through hole 142a is formed by patterning the mask 50 to form a conductive pillar 144 in each of the through holes 142a. In the embodiment, the conductive pillar 144 is made of, for example, titanium tungsten alloy. Next, referring to FIG. 1F to FIG. U, a bonding layer 146' is formed on each polymer layer 142, wherein the bonding layer 146 covers the conductive pillars 144, and the bonding layers 146 are transmitted through the conductive pillars 144 and the corresponding pads. The method of forming the bonding layer 146 may include the following steps. First, please refer to FIG. 1F 'Using the patterned mask 5 〇 to expose the 丨 in the π 52 The conductive pillar 144 is formed with a bonding material layer of a bonding material layer 146, a surface defect 144 and a solder fillet 110a. Then, please refer to FIG. 1G to remove the patterned mask 50. Referring to FIG. 1H to FIG. Bonding material layer 146 to form 200910480 'v-twva 24317twf.doc/n bonding layer 146. In this embodiment, the bonding material layer 146' may be patterned by a lithography process. In detail, the patterned bonding material layer 146 may include the following steps. First, please refer to FIG. 1H, above the through holes 142a. A mask 60 is formed on the bonding material layer 146'. Next, referring to FIG. u, a portion of the bonding material layer 146' that is not left for the mask 60 is left to form the bonding layer 146, and the metal layer 13 is simultaneously etched. , to form a spherical metal layer (, 130. Thereafter, referring to FIG. 1J, the mask 60 is removed. So far, the fabrication of the wafer level package structure 200 has been substantially completed. Referring to FIG. 2 ' after the above steps are completed, the wafer level package structure 200 can be further cut so that the wafer level package structure 2 〇〇 forms a plurality of chip packages 20 〇 a, and the chip package 2 〇 〇a is mounted on a carrier board, and a conductive paste 80 is filled between the pads 72 of the carrier 70 and the polymer bumps 〇4〇 to electrically connect the chip package 2〇〇a and the carrier board 7 .
由於本發明使用聚合物凸塊14〇取代習知技術中之金 屬^塊，因此’在晶片封裝體雇a與載板7()間之電性連 接受到應力時’聚合物凸塊14〇可產生形變以吸收應力。 如此’聚合物凸塊140可作為晶片封裝體施之焊墊缝 墊72間的緩衝’進而提高晶片封裝體200a 與载板70之間電性連接的可靠度。 除此之外，在本實施例中，上述聚合物層_ ，導脉m之高度，⑽位於導電柱144上方之= 二146具有-凹陷。如此，聚合物凸塊⑽在與接塾η 接合時，可固定導電膠8〇中之導電粒子82，進一步提高Since the present invention uses the polymer bumps 14A to replace the metal blocks in the prior art, the 'polymer bumps 14' can be used when the electrical connection between the wafer package body a and the carrier board 7 () is stressed. Deformation is generated to absorb stress. Thus, the polymer bumps 140 can serve as a buffer between the pad pads 72 of the chip package, thereby improving the reliability of electrical connection between the chip package 200a and the carrier 70. In addition, in the present embodiment, the polymer layer _, the height of the vein m, (10) is located above the conductive pillar 144 = 146 has a depression. Thus, when the polymer bumps (10) are bonded to the interface η, the conductive particles 82 in the conductive paste 8 can be fixed, further improving
200910480 —---------------------- 片封裝體200a與載板7〇之間電性連接的可靠声 :綜上所述，本發明與f知技術相較之下“以下優 =由於本發明使㈣合物凸塊取代f知技術中之金 鬼，因此’在晶片封裝體與載板間之雍 力時，聚合物凸塊可產生形變以吸收應力。二= :塊可作為晶片之墊與载板之接墊間的‘ 晶片封裝體與載板之間電性連接的可#度。術進而^ 導雷U吏聚:Λ層之厚度大於導電柱之高度，而使位於 接有—^。如此，聚合物凸塊在與 接塾接合％，可固定導電膠中之導電粒子，進—步提古曰 片封裝體與載板之間電性連接的可靠度。 131曰曰 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者為 準。 【圖式簡單說明】 圖1A至圖1J為本發明一實施例之晶圓級封裝結構的 製作方法流程圖。 圖2為圖1J之實施例中晶片封裝體與載板連接示意 圖0 11 200910480 24317twf.doc/n 【主要元件符號說明】 50 圖案化罩幕 52 第二開口 60 罩幕 70 載板 72 接墊 80 導電膠 82 :導電粒子 100 .晶圓 100a :晶片 110a :焊墊 120a :保護層 122a :第一開口 130 :球底金屬層 130’ ：金屬層 140 :聚合物凸塊 142 :聚合物層 142a :貫孔 144 :導電柱 146 :接合層 146’ ：接合材料層 200 :晶圓級封裝結構 200a :晶片封裝體200910480 —---------------------- Reliable sound of electrical connection between the chip package 200a and the carrier 7〇: In summary, the present invention In contrast, the following advantages: "Because the present invention replaces the (four) compound bumps with the gold ghosts in the technique, the polymer bumps can be generated when the force between the chip package and the carrier is generated. Deformation to absorb stress. Two =: The block can be used as the electrical connection between the wafer package and the carrier between the pads of the wafer and the pads of the carrier. The thickness is greater than the height of the conductive post, so that it is located at -^. Thus, the polymer bump is bonded to the joint, and the conductive particles in the conductive paste can be fixed, and the chip and the carrier are further advanced. The reliability of the electrical connection between the two. The present invention has been disclosed in the above embodiments, but it is not intended to limit the invention, and any one of ordinary skill in the art without departing from the spirit and scope of the invention Within the scope of the invention, the scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1J are flowcharts showing a method of fabricating a wafer level package structure according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a connection between a chip package and a carrier board in the embodiment of FIG. 1J. 200910480 24317twf.doc/n [Main component symbol description] 50 patterned mask 52 second opening 60 mask 70 carrier 72 pad 80 conductive paste 82: conductive particles 100. wafer 100a: wafer 110a: pad 120a: Protective layer 122a: first opening 130: ball bottom metal layer 130': metal layer 140: polymer bump 142: polymer layer 142a: through hole 144: conductive pillar 146: bonding layer 146': bonding material layer 200: crystal Circular package structure 200a: chip package