TW200908266A

TW200908266A - Embedded type multifunctional integrated structure and method of manufacturing the same

Info

Publication number: TW200908266A
Application number: TW96129673A
Authority: TW
Inventors: jian-hao Huang; wen-zhi Li
Original assignee: Inpaq Technology Co Ltd
Priority date: 2007-08-10
Filing date: 2007-08-10
Publication date: 2009-02-16

Abstract

An embedded type multifunctional integrated structure and a method of manufacturing the same are disclosed. The present invention utilizes the concept of multi-layer design to integrate more than two passive components on a component structure that would be adhered to a substrate. Hence, the embedded type multifunctional integrated structure has an OCP (Over-Current Protection), an OVP (Over-Voltage Protection), an anti-EMI (Anti-Electromagnetic Interference), and an anti-ESD (Anti-Electrostatic Discharge) function at the same time. Therefore, the present invention effectively integrate two or more than one passive components in order to increase function. Moreover, the present invention effectively reduces size of the passive components on a PCB and reduce the number of solder joints.

Description

200908266 九、發明說明· 【發明所屬之技術領域】本發明係有關於—種多功能整合型結構及其製作方法，尤指一種内埋式之多功能整合型結構（embedded type multifunctional integrated structure )及其製作方法。【先前技術】未來的電子產品，將朝著具有輕、薄、短、小的功能，以使得電子產品能更趨於迷你化。而被動元件（passive component)在電子產品中所占的面積又是最龐大的，所以能夠有效地整合被動元件，將使得電子產品可以達到輕、薄、短、小的功能。然而，習知被動元件的設計，皆以單一功能為主。因此’當電子產品需要安裝不同功能的被動元件來保護電子產品時，習知僅能設置多數個單一功能之被動元件於電子產品内。因此習知的作法不僅耗費製造的成本，更是佔用電子產品整體的體積。緣是，本發明人有感上述缺失之可改善，且依據多年來從事此方面之相關經驗，悉心觀察且研究之，並配合學理之運用，而提出一種設計合理且有效改善上述缺失之本發明。【發明内容】本發明所要解決的技術手段，在於提供一種内埋式之 7 200908266 多功能整合型結構（embedded type multifunctional integrated structure)及其製作方法。本發明係利用電路板多層設計的概念，將超過兩種以上的被動元件整合於一元件結構上，而完成之成品將以面黏著的方式黏著於基板上。因此，本發明内埋式之多功能整合型結構係能夠同時具有過電流保護、過電壓的保護、以及含有抗電磁干擾及抗靜電的功能。所以，本發明可以有效地整合兩個或多個 / 以上之被動元件而增加其功能性，再者本發明能有效地降低電路板上被動元件所佔的積體，並且減少銲點的數目。為了解決上述技術手段，根據本發明之其中一種方案，提供一種内埋式之多功能整合型結構（embedded type multifunctional integrated structure)係包括：一上蓋絕緣層 (top cover insulating layer )、一過電流保護層（over-current protection layer)、一中間絕緣層（middle insulating layer)、一多功能保護層（multifunctional protection layer)、一下蓋絕緣層（bottom cover insulating layer )、及一側邊導電單元 l ( lateral conductive unit)。其中，該上蓋絕緣層係具有至少一第一電源輸入部 (first power input portion )。該過電流保護層係設置於該上蓋絕緣層的下端，並且該過電流保護層係具有一第二電源輸入部（second power input portion)及一第二電源輸出部 (second power output portion )。該中間絕緣層係設置於該過電流保護層的下端’並且該中間絕緣層係具有一開口 (opening)。該多功能保護層係設置於該中間絕緣層的下 8 200908266 端’並且該多功能保護層係具有一第三電源輸入部（third power input portion )、一第三電源輸出部（third p〇wer 〇utput portion)、及一電性連接於該第三電源輸入部及該第三電源輸出口P之間之夕功此晶片單元（mUltifuncti〇nal chip )，其中該多功能晶片單元係容置於該中間絕緣層之開口内。 §亥下蓋絕緣層係設置於該多功能保護層的下端，並且該下蓋絕緣層係具有一第四電源輸出部（f〇urth power output portion )及一苐五電源輸出部（行拙p〇wer 〇utpUt p〇rti〇n )。再者’該側邊導電單元係包括三層彼此絕緣之一第一側邊導電層（first lateral conductive layer )、一第二側邊導電層（second lateral conductive layer )、及一第三側邊導電層（third lateral conductive layer )，其中每一層側邊導電層係由上到下依序成形在該上蓋絕緣層、該過電流保護層、該中間絕緣層、該多功能保護層、及該下蓋絕緣層之側邊。因此’该第一電源輸入部與該第二電源輸入部係透過該第一側邊導電層以產生電性連接，該第二電源輸出部、該第二電源輸入部與該第四電源輸出部係透過該第二側邊導電層以產生電性連接，並且該第三電源輸出部與該第五電源輸出部係透過該第三側邊導電層以產生電性連接。為了解決上述技術手段，根據本發明之其中一種方案kt、種内埋式之多功能整合型結構（embedded type multifunctional integrated structure )之製作方法，其步驟包括首先 k供一上蓋絕緣層（top cover insulating layer), /、，、有至夕、弟一電源輸入部（first power input portion ); 200908266 提供一過電流保護層（over-current protection layer)，其具有一第二電源輸入部（second power input portion)及一第二電源輸出部（second power output portion );提供一中間絕緣層（middle insulating layer)’ 其具有一開口（〇pening) 及一導電通道（conductive passage);提供一多功能保護層 (multifunctional protection layer )，其具有一第三電源輸入部（third power input portum)、一第三電源輸出部（third power output portion)、及一電性連接於該第三電源輸入部及該第三電源輸出部之間之多功能晶片單元 (nmltifimctional chip imit)，其中該多功能晶片單元係用於容置於該中間絕緣層之開口内；以及，提供—下蓋絕緣層 (bottom cover i臟論g iayeO ’其具有〜第四電源輸出部 (fourth power output portion)及一第五恭、皂源輸出部（fifth power output portion)。緊接著，依序將該上舰緣層、該過電流保護層、該 i 中&該下i絕緣層堆疊地 (stackedly)組合在一起；最後’形成〜如丨皇、音+句/ 斤人側邊導電層（first lateral conductive layer)、一第二側邊導齋 ^ ’电嘴(second lateral conductive layer )、及〆弟三側邊導齋w / ^ 4 層（third lateral conductive layer)，其中母一層側邊導電層由上到下依序成形在s亥上盍絕緣層、該過電流保護層、讀中間絕、該多功能保護層、及該下蓋絕緣層之侧邊，因此該第二電源輸入部與該第二電源輸入部係透過該第〜侧°導彥' 生電性連接，該第二電源輸出部、該第三電源輸入；與該 10 200908266 第四電源輸出部係透過該第二側邊導電層以產生電性連接，並且該第三電源輸出部與該第五電源輸出部係透過該第三側邊導電層以產生電性連接。為了能更進一步暸解本發明為達成預定目的所採取之技術、手段及功效，請參閱以下有關本發明之詳細說明與附圖，相信本發明之目的、特徵與特點，當可由此得一深入且具體之瞭解’然而所附圖式僅提供參考與說明用，並非用來對本發明加以限制者。【實施方式】請參閱第一 A圖至第一 D圖所示，其分別為本發明内埋式之多功能整合型結構（embedded type multifimctionai integrated structure)的第一實施例之立體分解圖、本發明第一實施例之過電流保護層反面後之立體圖、本發明第一實施例之下蓋絕緣層反面後之立體圖、及本發明内埋式之多功能整合型結構（embedded type multifunctional integrated structure )的第一實施例之立體組合圖。由該等圖中可知，本發明所提供之一種内埋式之多功能整合型結構（embedded type multifunctional integrated structure)係包括：一上蓋絕緣層（top cover insulating layer ) 1、一過電流保護層（over-current protection layer) 2、一中間絕緣層（middle insulating layer) M、~多功能保護層 (lmiltifunctional protection layer) 3、一下蓋I邑、緣層（bottom cover insulating layer ) 4、及一侧邊導電單元（lateral 11 200908266 conductive unit) 5。其中，該上蓋絕緣層1、該過電流保護層2、該中間絕緣層Μ、該多功能保護層3、及該下蓋絕緣層4係依序堆疊在一起，並且該側邊導電單元5係包括二層彼此絕緣之一第一側邊導電層（first lateral conductive layer) 5 1、一第二側邊導電層（secondlateral conductive layer ) 5 2、及一第三側邊導電層（third lateral conductive layer) 5 3 其中，該上蓋絕緣層1之一側邊係具有一第一半穿孔 (first half hole) 1 ◦ a，並且該上蓋絕緣層丄之另一相反側邊係具有一弟二半穿孔（sec〇nd half hole ) 1 〇 b及一第三半穿孔（thirdhalfhole) 1 ◦ c。此外，該上蓋絕緣層1 係具有至少一電性連接於該第一側邊導電層5丄之第一電源輸入部（first power input portion) 1 1、至少一電性連接於該第二側邊導電層5 2之第一電源輸出部（firstpower output portion) 1 2、及至少一電性連接於該第三側邊導電層5 3之接地部（grounding p〇rti〇n) 1 3，並且該至少一第一電源輸入部11係成形於該上蓋絕緣層1之上表面的一侧端’該至少一第一電源輸出部1 2及該至少一接地部 13係分別成形於該上蓋絕緣層1之上表面的另一相反側端。再者’該過電流保護層2係設置於該上蓋絕緣層1的下端。該過電流保護層2之一側邊係具有一第一半穿孔 (firsthalfhole) 2 〇 a，並且該過電流保護層2之另一相反侧邊係具有—第二半穿孔（second half hole) 2 0 b及一 12 200908266 第三半穿孔（third halfhole) 2 0 c。另外，該過電流保護層 2 係由一第一電極層（first electrode layer) 2 A、一第二電極層（second electrode layer) 2 B、及一正溫度係數材料層（positive temperature coefficient material layer) 2 C 所組成’並且該正溫度係數材料層2 C係成形於該第一電極層2 A及該第二電極層2 B之間。其中，該正溫度係數材料層2 C係可為一高分子正溫度係數（p〇iymer positive Temperature Coefficient，PPTC)材料層、電阻材料層、電容材料層、或電感材料層。再者，請配合第一 B圖所示，該過電流保護層2係具有一弟二電源輸入部（second power input portion) 2 1 及一第二電源輸出部（second power output portion ) 2 2，其中該第二電源輸入部2 1係為該第二電極層2 B之一側端’該第二電源輸出部2 2係為該第一電極層2 A之一側端。此外，該第一電極層2 A係具有一用於與該第一側邊 $笔層5 1黾性隔絕之第一絕緣部（first insuiating p〇rti〇n ) S 1及一用於與該第三侧邊導電層5 3電性隔絕之第二絕200908266 IX. OBJECTS OF THE INVENTION · TECHNICAL FIELD The present invention relates to a multi-functional integrated structure and a manufacturing method thereof, and more particularly to an embedded type multifunctional integrated structure and Its production method. [Prior Art] Future electronic products will be light, thin, short, and small, so that electronic products can be more miniaturized. Passive components occupy the largest area in electronic products, so the effective integration of passive components will enable electronic products to achieve light, thin, short, and small functions. However, the design of conventional passive components is based on a single function. Therefore, when electronic products need to install passive components with different functions to protect electronic products, it is conventional to set only a plurality of passive components with a single function in the electronic product. Therefore, the conventional method not only consumes the cost of manufacturing, but also occupies the overall volume of the electronic product. The reason is that the inventors have felt that the above-mentioned defects can be improved, and based on the relevant experience in this field for many years, carefully observed and studied, and in conjunction with the application of the theory, a present invention which is reasonable in design and effective in improving the above-mentioned defects is proposed. . SUMMARY OF THE INVENTION The technical means to be solved by the present invention is to provide a buried type of 200908266 embedded type multifunctional integrated structure and a manufacturing method thereof. The present invention utilizes the concept of a multi-layer design of a circuit board to integrate more than two passive components into a single component structure, and the finished product is adhered to the substrate in a surface-adhesive manner. Therefore, the embedded multi-functional integrated structure of the present invention can simultaneously have overcurrent protection, overvoltage protection, and functions of anti-electromagnetic interference and antistatic. Therefore, the present invention can effectively integrate two or more/or more passive components to increase the functionality thereof, and the present invention can effectively reduce the accumulation of passive components on the circuit board and reduce the number of solder joints. In order to solve the above technical means, according to one aspect of the present invention, an embedded type multifunctional integrated structure includes: a top cover insulating layer, an overcurrent protection Over-current protection layer, a middle insulating layer, a multifunctional protection layer, a bottom cover insulating layer, and a side conductive unit 1 Conductive unit). The upper cover insulating layer has at least one first power input portion. The overcurrent protection layer is disposed at a lower end of the upper cover insulating layer, and the overcurrent protection layer has a second power input portion and a second power output portion. The intermediate insulating layer is disposed at a lower end of the overcurrent protective layer and the intermediate insulating layer has an opening. The multifunctional protection layer is disposed on the lower 8 200908266 end of the intermediate insulating layer and the multifunctional protection layer has a third power input portion and a third power output portion (third p〇wer And a device that is electrically connected between the third power input portion and the third power output port P, wherein the multi-function chip unit is placed The opening of the intermediate insulating layer. § The lower cover insulating layer is disposed at a lower end of the multifunctional protective layer, and the lower cover insulating layer has a fourth power output portion and a fifth power output portion (line 拙p 〇wer 〇utpUt p〇rti〇n ). Furthermore, the side conductive unit includes three first insulating layers, a second lateral conductive layer, and a third side conductive layer. a third lateral conductive layer, wherein each of the side conductive layers is sequentially formed from top to bottom on the upper cover insulating layer, the overcurrent protective layer, the intermediate insulating layer, the multifunctional protective layer, and the lower cover The side of the insulation. Therefore, the first power input portion and the second power input portion are electrically connected through the first side conductive layer, and the second power output portion, the second power input portion, and the fourth power output portion The electrical connection is made through the second side conductive layer, and the third power output portion and the fifth power output portion are electrically connected to the third side conductive layer. In order to solve the above technical means, according to one aspect of the present invention, a method for fabricating an embedded type multifunctional integrated structure, the steps include first providing an upper cover insulating layer (top cover insulating) Layer), /,,, has a first power input portion; 200908266 provides an over-current protection layer having a second power input And a second power output portion; providing a middle insulating layer having a opening and a conductive passage; providing a multifunctional protective layer a (multifunctional protection layer) having a third power input port, a third power output portion, and an electrical connection to the third power input portion and the third a multi-function chip unit (nmtifimetic chip imit) between the power output portions, of which The functional wafer unit is for accommodating the opening of the intermediate insulating layer; and providing a bottom cover insulating layer (the bottom cover i dirty theory) has a fourth power output portion and a a fifth power, a gas power output portion. Next, the upper ship edge layer, the overcurrent protection layer, the i middle & the lower i insulation layer are stackedly stacked in sequence Together; finally 'formation~ such as 丨皇, 音+句/斤的第一侧 conductive层, a second lateral conductive layer, a second lateral conductive layer, and three sides of the younger brother The third lateral conductive layer, wherein the side conductive layer of the mother layer is sequentially formed from top to bottom on the upper layer of the insulating layer, the overcurrent protective layer, the reading intermediate, and the multifunctional a protective layer and a side of the lower cover insulating layer, wherein the second power input portion and the second power input portion are electrically connected through the first side guide, the second power output unit, and the second power output unit Third power input; with the 10 200908266 Power output line through the second side edge portion conductive layer to produce electrical connections, and the third power output unit and the fifth unit power output line through the third side conductive layer to create electrical connection. In order to further understand the technology, the means and the effect of the present invention in order to achieve the intended purpose, refer to the following detailed description of the invention and the accompanying drawings. It is to be understood that the invention is not to be construed as limited. [Embodiment] Please refer to FIG. 1A to FIG. 1D, which are respectively an exploded perspective view of a first embodiment of an embedded type multifimctionai integrated structure of the present invention. A perspective view of the reverse side of the overcurrent protection layer of the first embodiment of the present invention, a perspective view of the reverse side of the cover insulating layer of the first embodiment of the present invention, and an embedded type multifunctional integrated structure of the present invention. A three-dimensional combination of the first embodiment. As can be seen from the figures, an embedded type multifunctional integrated structure provided by the present invention includes: a top cover insulating layer 1 and an overcurrent protection layer ( Over-current protection layer 2, a middle insulating layer M, a lmiltifunctional protection layer 3, a bottom cover insulating layer 4, and one side Conductive unit (lateral 11 200908266 conductive unit) 5. The upper cover insulating layer 1, the overcurrent protective layer 2, the intermediate insulating layer Μ, the multifunctional protective layer 3, and the lower cover insulating layer 4 are sequentially stacked together, and the side conductive unit 5 is The first lateral conductive layer 5 1 , a second lateral conductive layer 5 2 , and a third lateral conductive layer 5 3 wherein one side of the upper cover insulating layer 1 has a first half hole 1 ◦ a, and the other opposite side of the upper cover insulating layer has a second half hole ( Sec〇nd half hole ) 1 〇b and a third half-hole (thirdhalfhole) 1 ◦ c. In addition, the upper cover insulating layer 1 has at least one first power input portion 1 1 electrically connected to the first side conductive layer 5 , at least one electrically connected to the second side a first power output portion 1 2 of the conductive layer 52, and at least one grounding portion 13 3 electrically connected to the third side conductive layer 53 The at least one first power input portion 11 is formed on one end of the upper surface of the upper cover insulating layer 1. The at least one first power output portion 12 and the at least one ground portion 13 are respectively formed on the upper cover insulating layer 1 The other opposite side of the upper surface. Further, the overcurrent protection layer 2 is provided on the lower end of the overlying insulating layer 1. One side of the overcurrent protection layer 2 has a first half hole 2 〇a, and the other opposite side of the overcurrent protection layer 2 has a second half hole 2 0 b and a 12 200908266 third halfhole 2 0 c. In addition, the overcurrent protection layer 2 is composed of a first electrode layer 2 A, a second electrode layer 2 B, and a positive temperature coefficient material layer. The composition of 2 C is 'and the positive temperature coefficient material layer 2 C is formed between the first electrode layer 2 A and the second electrode layer 2 B. The positive temperature coefficient material layer 2 C may be a polymer positive temperature coefficient (PPTC) material layer, a resistive material layer, a capacitor material layer, or an inductor material layer. Furthermore, as shown in FIG. B, the overcurrent protection layer 2 has a second power input portion 2 1 and a second power output portion 2 2 . The second power input unit 2 1 is a side end of the second electrode layer 2 B. The second power output unit 2 2 is a side end of the first electrode layer 2 A . In addition, the first electrode layer 2 A has a first insulating portion (first insuiating p〇rti〇n ) S 1 and one for being isolated from the first side edge pen layer 5 1 The second side conductive layer 5 3 electrically isolated second

緣部（second insulating portion) S2，該第二電極層 2B 係具有一用於與該第二侧邊導電層5 2及該第三側邊導電層5 3電性隔絕之第三絕緣部（thirdinsulatingp〇rti〇n) s 3。因此，該第一電極層2 A及該第二電極層2 B係分別透過該第二絕緣部S 2及該第三絕緣部s 3以與該第三側邊導電層5 3電性隔絕。此外’該中間絕緣層Μ係設置於該過電流保護層2的 13 200908266 下、’並且e亥中間絕緣層Μ係具有一開口（ 0pening ) μ 1 0。並且，該中間絕緣層滅之一側邊係具有一第一半穿孔 Uifsthalfhole) Ma ’並且該中間絕緣層μ之另一相反側邊係具有一第一半穿孔（second half hole ) Mb及一第三半穿孔（third half hole) Me。再者’該多功能保護層3係設置於該中間絕緣層M的下端。該多功能保護層3之一側邊係具有一第一半穿孔 (first half hole) 30 a，並且該多功能保護層3之另一相反侧邊係具有一弟二半穿孔（sec〇nd half hole) 3 0 b及一第三半穿孔（third half hole) 3 0 c。此外，該多功能保護層3係具有一第三電源輸入部（third power input portion ) 3 1、一弟二電源輸出部（third power output portion) 3 2、及一電性連接於該第三電源輸入部3 1及該第三電源輸出部3 2之間之多功能晶片單元（multifunctional chip unit) 3 3° 其中’該多功能晶片單元3 3係容置於該中間絕緣層 Μ之開口Μ 1 〇内。在本實施例中，該第三電源輸入部3 1及該第三電源輸出部3 2皆成形於該多功能保護層3之上表面（top surface)。此外，該多功能晶片單元3 3係可為一功能晶片（functional chip)’並且該功能晶片係可為一過電壓保護（Over-Voltage Protection，0VP)晶片、一抗電磁干擾（Anti-Electromagnetic Interference，anti-EMI)晶片、或一抗靜電（Anti-Electrostatic Discharge ’ anti-ESD )晶片。此外，該下蓋絕緣層4係設置於該多功能保護層3的 14 200908266 下端。該下蓋絕緣層4之一側邊係具有一第一半穿孔（first half hole) 4 0 a，並且該下蓋絕緣層4之另一相反側邊係具有一第二半穿孔（second half hole) 40b及一第三半穿孔（third half hole ) 4 0 c。另外，請配合第一 C圖所示，该下盍絕緣層4係具有一第四電源輸出部（fourth power output portion )4 1 及一第五電源輸出部（fifth power output portion) 4 2 ’並且該第四電源輸出部4 1及該第五電源輸出部4 2皆成形於該下蓋絕緣層4之下表面。再者’請配合第一D圖所示，每一層侧邊導電層（5 1、5 2、5 3)係由上到下依序成形在該上蓋絕緣層1、該過電流保護層2、該中間絕緣層Μ、該多功能保護層3、及該下蓋絕緣層4之側邊。其中，該第一側邊導電層5 1 係為電源輸入端（power input side ) V in，該第二側邊導電層5 2係為電源輸出端（power output side) Vout，並且該苐二側邊導電層5 3係為接地端（grounding side ) G。此外，該上蓋絕緣層1之第一半穿孔l〇a、該過電流保護層2之第一半穿孔20 a、該中間絕緣層Μ之第一半穿孔M a、該多功能保護層3之第一半穿孔3〇a、及該下蓋絕緣層4之第一半穿孔4 0 a係疊合成一第一側邊貫穿槽（first lateral penetrating groove) 6 1 ;該上蓋絕緣層1之第二半穿孔1 〇b、該過電流保護層2之第二半穿孔2 0 b、該中間絕緣層μ之第二半穿孔μ b、該多功能保護層3之第二半穿孔3〇b、及該下蓋絕緣層4之第二半牙孔4 0 b係疊合成一弟二側邊貫穿槽（sec〇n(j iaterai 15 200908266 penetrating groove) 6 2 ;該上蓋絕緣層1之第三半穿孔1 0 c、該過電流保護層2之第三半穿孔2 〇 C、該中間絕緣層Μ之第二半穿孔Me、該多功能保護層3之第三半穿孔3 0 c、及該下蓋絕緣層4之第三半穿孔4 〇 c係叠合成一第三側邊貫穿槽（third lateral penetrating groove ) 6 3。因此，該第一側邊貫穿槽6 1係由複數個分別成形在 §玄上蓋絕緣層1、該過電流保護層2、該中間絕緣層μ、 3玄多功也保遵層3、及§亥下盘絕緣層4之一側之第·一半穿孔（10a、20a、Ma、30a、40a)所堆疊而成，該第二側邊貫穿槽6 2係由複數個分別成形在該上蓋絕緣層1、該過電流保護層2、該中間絕緣層μ、該多功能保護層3、及該下蓋絕緣層4之另一相反側邊之第二半牙孔（l〇b、20b、Mb、30b、40b)所堆疊而成]並且該第三側邊貫穿槽6 3係由複數個分別成形在 e玄上蓋絕緣層1、該過電流保護層2、該中間絕緣層Μ、 5亥夕功忐保濩層3、及该下蓋絕緣層4之該相反側邊之第二半穿孔（l〇c、20c、Me、30c、40c)所堆疊而成。再者，上述三道彼此分離之第一側邊貫穿槽6丄、第邊貫穿槽6 2及第三侧邊貫穿槽6 3係組合成一側邊貫穿槽單元（lateral penetrating groove Ullit) 6，並且該第一側邊導電層5 1係成形於該第一側邊貫穿槽6丄的内表面，忒第一側邊導電層5 2係成形於該第二側邊貫穿槽6 2的内表面，並且該第三側邊導電層5 3係成形於該第三 16 200908266 侧邊貫穿槽6 3的内表面。因此，該第一電源輪入部1 1盥 1係透過該第—側邊導電 =-電源輸入部2 電源輸出部2 2 電性連接，該第二出部侧過該第第四麵並且該第三電源輸出部3 ’ ‘ 二f電性連接’ 過該第三側邊導電層5^產、= 性五連^輸出部42係透請再-次參考第—义圖至第一箭頭代表電流的方向。雷、s。。亥寻圖中之至該下罢絕缝爲在層（從該上蓋絕緣層1 里、” M 4 )的主要流動路徑如下所述·· 第層（该上蓋絕緣層^ )··透過該第一側邊導電斧5工’ 電流從該上蓋絕緣層1之第-電源輸入^丄工流到該過電流保護層2之第二電源輪入部2工。層（该過電流保護層2 ):電流依序經過該第二電極層 2 B、該正溫度係數材料層2 c及該第—電極^ 2 A ’而從該第二電源輸入部2 i流到該第二^ 源輸出部2 2。因此，透過該正溫度係數材料】第 2 C的特殊材料特性，以使得本發明具有過電流保瘦（Over-Current Protection，OCP )的功能。層（該中間絕緣層M):透過該第二側邊導電層5 2，電流從該第二電源輪出部2 2流到該多功能保護層之第三電源輸入部3 1。第四層（該多功能保護層3 ):依據該多功能晶片單元3 3 之功能設定’以決定電流的流向。因此，正常的 200908266 電流可直接流向下一層；而不正常的電流則從該第三電源輸入部3 1經過該多功能晶片單元3 3 而流向該第三電源輸出部3 2。例如：該功能晶片單元3 3係為一過電壓保護（Over-Voltage Protection，0VP)晶片，並且假設該過電壓保護晶片所設定之負載為5伏特（volt)。因此，當電流少於5伏特時，則正常地輸出該電流；當電流大於5伏特時，則使得該電流流過該過電壓保護 / 1 晶片並傳送到接地端。第五層（該下蓋絕緣層4 ):透過該第二侧邊導電層5 2，以使得正常的電流從該第三電源輸入部3 1流到該下蓋絕緣層4之第四電源輸出部41;透過該第三側邊導電層5 3，以使得不正常的電流從該第三電源輸出部3 2流到該下蓋絕緣層4之第五電源輸出部4 2並傳送到接地端。請參閱第二A圖及第二B圖所示，其分別為本發明第 ϋ 二實施例之過電流保護層之立體圖、及本發明第二實施例之過電流保護層反面後之立體圖。由該等圖中可知，該第二電源輸入部2 1 >係為該第一電極層2 A >之一側端，該第二電源輸出部2 2 /係為該第二電極層2 B >之一側端，並且該第一電極層2 A / ' 係具有一用於與該第二侧邊導電層5 2 /及該第三侧邊導電層5 3 '電性隔絕之第三絕緣部（third insulating portion ) S 3 /，該第二電極層2 B /係具有一用於與該第一侧邊 18 200908266 導電層5 1 '電性隔絕之第一絕緣部（first insulating portion) S 1 >及一用於與該第三側邊導電層5 3 >電性隔絕之第二絕緣部（second insulating portion) S 2 '，因此該第一電極層2 A /及該第二電極層2 B >係分別透過該第三絕緣部S 3 —及該第二絕緣部S 2 /以與該第三侧邊導電層5 3 /電性隔絕。因此，第二實施例之第二層（該過電流保護層2 一）的電流路控係為·電流依序經過該弟一電極層2 A 、該正溫度係數材料層2 C 及該弟二電極層2 B ’而從該第二電源輸入部2 1 >流到該第二電源輸出部2 2 /。請參閱第三A圖及第三B圖所示，其分別為本發明第三實施例之多功能保護層之立體圖、及本發明第三實施例之下盖絕緣層之立體圖。由該等圖中可知’該第二電源輸入部3 1 /、該第三電源輸出部3 2 /與該多功能晶片單元3 3 /皆成形於該多功能保護層3 /之下表面（bottom surface )，並且該下蓋絕緣層4 /係具有一用於容置該多功能晶片單元3 3 >之開口 4 0 /。因此，本發明亦能結合第一實施例與第三實施例，而使得該第三電源輸入部3 1、該第三電源輸出部3 2與該多功能晶片單元3 3皆成形於一多功能保護層之上表面 (如第一實施例所示），並且同時使得該第三電源輸入部3 1 ―、該第三電源輸出部3 2 >與該多功能晶片單元3 3 >皆成形於該多功能保護層之下表面（如第三實施例所示）。換言之，該第三電源輸入部係可同時成形於該多功能 19 200908266 保濩層之上表面（top surface )與下表面（bottom surface )，並且該第三電源輸出部係可同時成形於該多功能保護層之上表面（top surface)與下表面（bottom surface)。請參考第四A圖所示，其係為本發明多功能晶片單元的第一種排列方式之立體圖。由圖中可知，該多功能晶片早元33A係由複數個功能晶片（33ai、33^2、3 3 a 3)所組成，並且該等功能晶片係分別為一過電壓保護 (Over-Voltage Protection ’ 0VP )晶片、一抗電磁干擾 (Anti-Electromagnetic Interference，anti-EMI)晶片、及一抗靜電（Anti-Electrostatic Discharge，anti-ESD)晶片。再者，該等功能晶片（333::338^3333)係並聯地（parallelly)電性連接於該第三電源輸入部3 1及該第三電源輸出部3 2之間。請參考第四B圖所示，其係為本發明多功能晶片單元的第二種排列方式之立體圖。由圖中可知，該多功能晶片單元3 3 B係由複數個功能晶片（3 3 b i、3 3 b 2)所組成’並且該等功能晶片係可為一過電壓保護 (Over-Voltage Protection，0VP )晶片、一抗電磁干擾 (Anti-Electromagneticlnterference，anti-EMI)晶片、及一抗靜電（Anti_Electrostatic Discharge，anti-ESD)晶片之任意選擇。再者，該等功能晶片（3 3 b i、3 3 b 2 )係串聯地（seriesly)電性連接於該第三電源輸入部3 1及該第三電源輸出部3 2之間。請參考第四C圖所示’其係為本發明多功能晶片單元 20 200908266 的第三種排列方式之立體圖。由圖中可如，該多功能晶片單元3 3 C係由複數個功能晶片（3 3 c !、3 3 c 2、3 3 c 3、3 3 c 4)所組成，並且該等功能晶片係可為一過電壓保護（Over-VoltageProtection，OVP)晶片、一抗電磁干擾（Anti_Electromagnetic Interference，anti-EMI)晶片、及一抗靜電（Anti-Electrostatic Discharge，anti-ESD)晶片之任意選擇。再者，該等功能晶片（3 3 c!、3 3 c 2、 3 3 c 3、3 3 c 4)係可同時並聯地（parallelly )及串聯地（serially)電性連接於該第三電源輸入部3 1及該第三電源輸出部3 2之間。請參閱第五圖所示，其係為本發明内埋式之多功能整合型結構（embedded type multifunctional integrated structure)之製作方法的流程圖。由流程圖中可知，本發明所提供之一種内埋式之多功能整合型結構（embedded type multifunctional integrated structure )之製作方法，其步驟包括：步驟S100 :提供一上蓋絕緣廣（top cover insulating layer)，其具有至少一第一電源輸入部（first power input portion)。步驟S102 :提供一過電流保護層（over-current protection layer)，其具有一第二電源輸入部（second power input portion)及一第二電源輸出部（second power output portion)。步驟SUM :提供一中間絕緣層（middle insulating 21 200908266 kyer )，其具有一開口（ gening )及一導電通道（conductive passage ) 〇乂驟S ^供—多功能保護層（multifunctional protection layer)’其具有一第三電源輸入部（也㈤ρ〇·Γ i零t portion )、一第三電源輸出部（論d ρ〇·Γ 〇_说 portion )、及-電性連接於該第三電源輸人部及該第三電源輸出部之間之多功能晶片單元（_tif霍ti觀Uhip unit)， f I..a second insulating portion S2, the second electrode layer 2B having a third insulating portion for electrically isolating the second side conductive layer 52 and the third side conductive layer 53 (thirdinsulatingp 〇rti〇n) s 3. Therefore, the first electrode layer 2 A and the second electrode layer 2 B are respectively electrically insulated from the third side conductive layer 53 by the second insulating portion S 2 and the third insulating portion s 3 . Further, the intermediate insulating layer is disposed under the 13 200908266 of the overcurrent protection layer 2, and the intermediate insulating layer has an opening (0pening) μ 1 0. And, the one side of the intermediate insulating layer has a first semi-perforated Uifsthalfhole) Ma ' and the other opposite side of the intermediate insulating layer μ has a first half hole Mb and a first Third half hole Me. Further, the multifunctional protective layer 3 is provided at the lower end of the intermediate insulating layer M. One side of the multifunctional protective layer 3 has a first half hole 30 a, and the other opposite side of the multifunctional protective layer 3 has a second half hole (sec〇nd half) Hole) 3 0 b and a third half hole 3 0 c. In addition, the multi-function protection layer 3 has a third power input portion 3 1 , a third power output portion 3 2 , and an electrical connection to the third power source. A multifunctional chip unit between the input portion 31 and the third power output portion 32 is 3 3°, wherein the multi-function wafer unit 3 3 is placed in the opening of the intermediate insulating layer Μ 1 Inside. In this embodiment, the third power input portion 31 and the third power output portion 32 are both formed on the top surface of the multifunctional protection layer 3. In addition, the multi-function chip unit 33 can be a functional chip and the functional chip can be an Over-Voltage Protection (0VP) chip and an anti-electromagnetic interference (Anti-Electromagnetic Interference). , anti-EMI) wafer, or an anti-electrostatic antistatic (anti-Electrostatic Discharge 'anti-ESD) wafer. In addition, the lower cover insulating layer 4 is disposed at the lower end of the 200908266 of the multifunctional protective layer 3. One side of the lower cover insulating layer 4 has a first half hole 40 a, and the other opposite side of the lower cover insulating layer 4 has a second half hole (second half hole) 40b and a third half hole 40 c. In addition, as shown in FIG. C, the lower insulating layer 4 has a fourth power output portion 4 1 and a fifth power output portion 4 2 'and The fourth power output portion 4 1 and the fifth power output portion 42 are both formed on the lower surface of the lower cover insulating layer 4. Furthermore, 'please match the first D diagram, each side of the conductive layer (5 1 , 5 2, 5 3) is sequentially formed from top to bottom on the upper cover insulating layer 1, the overcurrent protection layer 2 The intermediate insulating layer Μ, the multifunctional protective layer 3, and the side edges of the lower cover insulating layer 4. The first side conductive layer 51 is a power input side V in , and the second side conductive layer 52 is a power output side Vout, and the two sides of the power output side The edge conductive layer 53 is a grounding side G. In addition, the first semi-perforation l〇a of the upper cover insulating layer 1, the first semi-perforation 20a of the overcurrent protection layer 2, the first semi-perforation Ma of the intermediate insulating layer, and the multifunctional protective layer 3 The first half of the through hole 3〇a, and the first semi-perforation 40 a of the lower cover insulating layer 4 are laminated to form a first lateral penetrating groove 6 1 ; the second cover insulating layer 1 is second a semi-perforation 1 〇b, a second semi-perforation 20b of the overcurrent protection layer 2, a second semi-perforation μb of the intermediate insulating layer μ, a second semi-perforation 3〇b of the multifunctional protective layer 3, and The second half hole 4 0 b of the lower cover insulating layer 4 is laminated to form a second side through groove (secet n (j iaterai 15 200908266 penetrating groove) 6 2 ; the third semi-perforated of the upper cover insulating layer 1 1 0 c, a third semi-perforation 2 〇C of the overcurrent protection layer 2, a second semi-perforation Me of the intermediate insulation layer 、, a third semi-perforation 3 0 c of the multifunctional protection layer 3, and the lower cover The third semi-perforation 4 〇c of the insulating layer 4 is laminated to form a third lateral penetrating groove 63. Therefore, the first side is penetrated. 6 1 is formed by a plurality of layers respectively formed on the § upper cover insulating layer 1, the overcurrent protective layer 2, the intermediate insulating layer μ, 3 Xuan multi-function also adheres to the layer 3, and § the lower plate insulating layer 4 The first half of the through holes (10a, 20a, Ma, 30a, 40a) are stacked, and the second side through grooves 6 2 are formed by the plurality of the upper cover insulating layer 1 and the overcurrent protection layer 2, respectively. The intermediate insulating layer μ, the multifunctional protective layer 3, and the second half-holes (l〇b, 20b, Mb, 30b, 40b) of the opposite side of the lower cover insulating layer 4 are stacked] And the third side through slot 63 is formed by a plurality of respectively formed on the e-top cover insulating layer 1, the overcurrent protection layer 2, the intermediate insulating layer Μ, the 5 夕忐忐 layer 3, and the lower The second semi-perforations (10c, 20c, Me, 30c, 40c) of the opposite sides of the cover insulating layer 4 are stacked. Further, the three first sides of the cover are separated from each other by the slot 6丄, The first side through groove 6 2 and the third side through groove 6 3 are combined into a side penetrating groove Ullit 6, and the first side conductive layer 5 1 is Formed on the inner surface of the first side through groove 6丄, the first side conductive layer 52 is formed on the inner surface of the second side through groove 64, and the third side conductive layer 53 Formed on the inner surface of the third through hole 16 3 of the third 16 200908266. Therefore, the first power supply wheel 1 1盥1 transmits the first side conduction=-power input unit 2 power output unit 2 2 a second connection, the third power supply output portion 3'' The 42 series is re-referenced to the first - the first arrow to represent the direction of the current. Ray, s. . The main flow path in the layer (from the upper cover insulating layer 1, "M 4 ) is as follows: · The first layer (the upper cover insulating layer ^) ··················· One side of the conductive axe 'current' flows from the first power supply input of the upper cover insulating layer 1 to the second power supply wheel of the overcurrent protective layer 2. Layer (the overcurrent protection layer 2): The current flows through the second electrode layer 2 B, the positive temperature coefficient material layer 2 c and the first electrode ^ 2 A ' from the second power input portion 2 i to the second source output portion 2 2 . Therefore, through the positive temperature coefficient material, the special material characteristics of the second C, so that the present invention has the function of Over-Current Protection (OCP). Layer (the intermediate insulating layer M): through the first The two side conductive layers 52, the current flows from the second power supply wheel portion 2 2 to the third power input portion 31 of the multifunctional protection layer. The fourth layer (the multifunctional protection layer 3): according to the The functional chip unit 3 3 is set to 'determine the flow of current. Therefore, the normal 200908266 current can flow directly downward. a layer; an abnormal current flows from the third power input portion 31 through the multi-function chip unit 3 3 to the third power output portion 32. For example, the functional chip unit 3 3 is an overvoltage protection (Over-Voltage Protection, 0VP) wafer, and assumes that the load set by the overvoltage protection chip is 5 volts. Therefore, when the current is less than 5 volts, the current is normally output; when the current is greater than 5 volts When the current is passed through the overvoltage protection / 1 wafer and transferred to the ground. The fifth layer (the lower cover insulating layer 4): through the second side conductive layer 52, so that the normal current from The third power input portion 31 flows to the fourth power output portion 41 of the lower cover insulating layer 4; and passes through the third side conductive layer 53 such that an abnormal current flows from the third power output portion 3 2 The fifth power supply output portion 4 2 of the lower cover insulating layer 4 is transferred to the ground terminal. Please refer to the second A diagram and the second B diagram, which are respectively the overcurrent protection according to the second embodiment of the present invention. a perspective view of a layer, and an overcurrent protection of the second embodiment of the present invention A perspective view of the reverse side of the layer. As can be seen from the figures, the second power input unit 2 1 > is one side end of the first electrode layer 2 A > the second power output unit 2 2 / is One side of the second electrode layer 2 B >, and the first electrode layer 2 A / ' has a second side conductive layer 5 2 / and the third side conductive layer 5 3 'Electrically insulated third insulating portion S 3 /, the second electrode layer 2 B / has a first electrical isolation from the first side 18 200908266 conductive layer 5 1 ' a first insulating portion S 1 > and a second insulating portion S 2 ' for electrically isolating the third side conductive layer 5 3 > 2 A / and the second electrode layer 2 B > are electrically isolated from the third side conductive layer 5 3 / through the third insulating portion S 3 - and the second insulating portion S 2 / respectively. Therefore, the current path of the second layer (the overcurrent protection layer 2) of the second embodiment is that the current sequentially passes through the first electrode layer 2 A , the positive temperature coefficient material layer 2 C and the second The electrode layer 2 B ' flows from the second power input unit 2 1 > to the second power output unit 2 2 /. Referring to FIG. 3A and FIG. 3B, respectively, a perspective view of a multifunctional protective layer according to a third embodiment of the present invention, and a perspective view of a cover insulating layer of a third embodiment of the present invention. As can be seen from the figures, the second power input unit 3 1 /, the third power output unit 3 2 / and the multi-function wafer unit 3 3 are both formed on the multi-function protective layer 3 / lower surface (bottom The under cover insulating layer 4 / has an opening 4 0 / for accommodating the multi-function wafer unit 3 3 > Therefore, the present invention can also be combined with the first embodiment and the third embodiment, so that the third power input portion 31, the third power output portion 32, and the multi-function wafer unit 33 are both formed into a multi-function. The upper surface of the protective layer (as shown in the first embodiment), and at the same time, the third power input portion 3 1 -, the third power output portion 3 2 > and the multi-function wafer unit 3 3 > On the lower surface of the multifunctional protective layer (as shown in the third embodiment). In other words, the third power input portion can be simultaneously formed on the top surface and the bottom surface of the multi-function 19 200908266, and the third power output portion can be simultaneously formed on the bottom surface. Functional protection layer top surface and bottom surface. Please refer to FIG. 4A, which is a perspective view of the first arrangement of the multi-function wafer unit of the present invention. As can be seen from the figure, the multifunction wafer early 33A is composed of a plurality of functional chips (33ai, 33^2, 3 3 a 3), and the functional chips are respectively an over voltage protection (Over-Voltage Protection). '0VP' wafer, an anti-electromagnetic interference (anti-EMI) wafer, and an anti-electrostatic discharge (anti-ESD) wafer. Further, the functional chips (333::338^3333) are electrically connected in parallel between the third power input unit 31 and the third power output unit 3 2 . Please refer to FIG. 4B, which is a perspective view of a second arrangement of the multi-function wafer unit of the present invention. As can be seen from the figure, the multi-function chip unit 3 3 B is composed of a plurality of functional chips (3 3 bi, 3 3 b 2 ) and the functional chip systems can be an over-voltage protection (Over-Voltage Protection, 0VP) wafer, an anti-electromagnetic interference (anti-EMI) wafer, and an anti-electrostatic (Anti-Electrostatic Discharge, anti-ESD) wafer. Further, the functional chips (3 3 b i, 3 3 b 2 ) are electrically connected in series between the third power input unit 31 and the third power output unit 32. Please refer to the fourth C diagram, which is a perspective view of the third arrangement of the multi-function wafer unit 20 200908266 of the present invention. As can be seen from the figure, the multi-function chip unit 3 3 C is composed of a plurality of functional chips (3 3 c !, 3 3 c 2, 3 3 c 3 , 3 3 c 4), and the functional chip systems It can be any choice of an Over-Voltage Protection (OVP) chip, an Anti-Electromagnetic Interference (anti-EMI) chip, and an Anti-Electrostatic Discharge (anti-ESD) chip. Furthermore, the functional chips (3 3 c!, 3 3 c 2, 3 3 c 3 , 3 3 c 4) can be electrically connected to the third power supply in parallel and serially. The input unit 3 1 and the third power output unit 3 2 are interposed. Referring to FIG. 5, it is a flowchart of a method for fabricating an embedded type multifunctional integrated structure of the present invention. The method for fabricating an embedded type multifunctional integrated structure provided by the present invention includes the following steps: Step S100: providing a top cover insulating layer It has at least a first power input portion. Step S102: providing an over-current protection layer having a second power input portion and a second power output portion. Step SUM: providing an intermediate insulating layer (middle insulating 21 200908266 kyer ) having an opening and a conductive passage step S ^ for a multi-functional protection layer a third power input unit (also (five) 〇 Γ i zero t portion), a third power output unit (on d ρ〇·Γ 〇 _ said transportation), and - electrically connected to the third power input unit And a multi-function chip unit between the third power output unit (_tif 霍景 Uhip unit), f I..

其中《亥夕功1日0 >1單7〇係用於容置於該中間絕緣層之開口步驟S10 8 :提供一下絮^ . 、^ α . 峨、”邑緣層(bottom cover insulating layer ) ’其具有一第四電 6 .、泉幸則出部（fourth power output portion)及一弟五電源輪出 ·〈步驟s11〇:依序將該上^(職po丽0卿utpo_n)。該中間絕緣層、該多魏絕騎、制電流保護層、 (,,,X 〜\層、及該下盍絕緣層堆疊地 (stackedly)組合在一起。步驟S112 :形成一側请、e 、邊導電層（first lateral conductive layer )、一第二側邊導電 , . ^ ^ ( second lateral conductive 7 甘二第三側邊導電層（third lateral conductive 層側邊導電層由上到下依序成形在該上蓋嫌保護層、該中間絕緣層、該多功能保護層、及该下1絕緣層之侧邊门^ & -帝、、/S认遭’因此该第一電源輸入部與該弟一電源柄入部係透過該 . Ζ弟—側邊導電層以產生電性連接，邊弟二電源輸出部、t ^ 仏山如政、* 〜弟二電源輪入部與該第四電源 $㈣導電層以產生電性連接，並且該 22 200908266 第三電源輸出部與該第五電源輸出部係透過該第三侧邊導電層以產生電性連接。再者’在該步驟步驟S112之前，本發明之製作方法更進一步包括：形成一第一側邊貫穿槽（first lateral penetrating groove )、一第二側邊貫穿槽（second lateral penetrating groove )、及一第三側邊貫穿槽（third lateral penetratingWherein, "Hai Xigong 1 day 0 > 1 single 7 〇 is used to accommodate the opening of the intermediate insulating layer step S10 8 : provide a little buck ^ . , ^ α . 峨 , "bottom cover insulating layer ) 'It has a fourth power 6. The fourth power output portion and one of the five power supply turns out. <Step s11〇: The next step is ^(Poly 0 ut utpo_n). The intermediate insulating layer, the multi-week riding, the current-preserving protective layer, (,, X~\ layer, and the lower insulating layer are stackedly stacked together. Step S112: forming one side, e, side a first lateral conductive layer, a second side conductive layer, a second lateral conductive layer (the third lateral conductive layer of the third side conductive layer is sequentially formed from top to bottom) The top cover of the protective layer, the intermediate insulating layer, the multifunctional protective layer, and the side of the lower insulating layer ^ & - Emperor, / / S recognized 'so the first power input and the young one The shank is passed through the Ζ--side conductive layer to create an electrical connection, and the second power supply output, t ^ 仏山如政, * 弟二 power supply wheeling portion and the fourth power supply $ (four) conductive layer to make an electrical connection, and the 22 200908266 third power supply output portion and the fifth power output portion pass through the third side The conductive layer is electrically connected to each other. Further, before the step S112, the manufacturing method of the present invention further comprises: forming a first lateral penetrating groove and a second side through groove. Second lateral penetrating groove and a third lateral penetrating groove

groove) ’其中該等侧邊導通槽係藉由鑽孔或衝壓的方式依序貫穿該上蓋絕緣層、該過電流保護層、該中間絕緣層、該多功能保護層、及該下蓋絕緣層所形成，並且該第一侧邊導電層係成形於該第—側邊貫穿槽的内表面，該第二側邊導電層係成形於該第二侧邊貫穿槽㈣表面，並且該第三侧邊導電層係成形於”三側邊貫穿槽的内表面。人其係為本發明内埋式之多功能整。生…構（embedded type mu職ncti〇nai 如 r由二單顆前，立體圖。，圖中可知，。該上蓋絕緣層1雷STf (punching)的方式依序貫穿該多功能賴層3賴層2、射_緣層M、穿孔Η高，再將導；緣層4 ’以形成複數個貫緣層1、麵電流仵^層由上到下依序成形在該上蓋絕保護層3、及該下蓋該中間絕緣層Μ、該多功能最後再將單顆的内埋、象//之該等貫穿孔Η的内表面， (如第-D圖所示整合型結構Ρ切割下來完成多個㈣式之乡功At 明之製作方式—次可同時夕功忐整合型結構p。 23 200908266 惟，以上所述，僅為本發明最佳之一的具體實施例之詳細說明與圖式，惟本發明之特徵並不侷限於此，並非用以限制本發明，本發明之所有範圍應以下述之申請專利範圍為準，凡合於本發明申請專利範圍之精神與其類似變化之實施例，皆應包含於本發明之範疇中，任何熟悉該項技藝者在本發明之領域内，可輕易思及之變化或修飾皆可涵蓋在以下本案之專利範圍。【圖式簡單說明】第一 A圖係為本發明内埋式之多功能整合型結構的第一實施例之立體分解圖，第一 B圖係為本發明第一實施例之過電流保護層反面後之立體圖；第一 C圖係為本發明第一實施例之下蓋絕緣層反面後之立體圖；第一 D圖係為本發明内埋式之多功能整合型結構的第一實施例之立體組合圖；第二A圖係為本發明第二實施例之過電流保護層之立體圖第二B圖係為本發明第二實施例之過電流保護層反面後之立體圖；第三A圖係為本發明第三實施例之多功能保護層之立體圖第三B圖係為本發明第三實施例之下蓋絕緣層之立體圖； 24 200908266 第四A圖係為本發明多功能晶片單元的第一種排列方式之立體圖；第四B圖係為本發明多功能晶片單元的第二種排列方式之立體圖；弟四C圖係為本發明多功能晶片早元的第三種排列方式之立體圖；第五圖係為本發明内埋式之多功能整合型結構（embedded type multifunctional integrated structure )之製作方法的流程圖，以及第六圖係為本發明内埋式之多功能整合型結構（embedded type multifunctional integrated structure)被切割成單顆前之立體圖。【主要元件符號說明】Groove) 'where the side conduction grooves are sequentially penetrated through the upper cover insulating layer, the overcurrent protection layer, the intermediate insulating layer, the multifunctional protective layer, and the lower cover insulating layer by drilling or stamping Forming, and the first side conductive layer is formed on the inner surface of the first side through groove, the second side conductive layer is formed on the second side through groove (four) surface, and the third side The conductive layer is formed on the inner surface of the three-side through-groove. The human body is the multi-functional whole embedded in the invention. The embedded type mu ncti〇nai such as r from two single front, three-dimensional map As can be seen from the figure, the upper cover insulating layer 1 has a STf (punching) manner, which is sequentially penetrated through the multi-functional layer 3, the layer _ edge layer M, the perforation Η high, and then the edge layer 4 ' Forming a plurality of peripheral layer 1, surface current layer, sequentially forming the upper cover protective layer 3 from the top to the bottom, and the intermediate cover layer of the lower cover, the multi-function finally burying the single layer , such as / / these through the inner surface of the hole, (as shown in Figure -D figure integrated structure Ρ cut down The method of making a plurality of (four) styles is the same as that of the integrated structure p. 23 200908266 However, the above description is only a detailed description and drawing of the specific embodiment of the present invention. However, the present invention is not limited thereto, and is not intended to limit the scope of the invention, and the scope of the invention should be determined by the following claims. It is intended to be included in the scope of the present invention, and any variation or modification that can be easily conceived by those skilled in the art can be covered in the following patent scope of the present invention. Figure A is a perspective exploded view of the first embodiment of the multi-functional integrated structure of the present invention, and the first B is a perspective view of the reverse side of the overcurrent protection layer of the first embodiment of the present invention; 1 is a perspective view of the first embodiment of the present invention; 2 is a perspective view of an overcurrent protection layer according to a second embodiment of the present invention. FIG. 2B is a perspective view of the reverse side of the overcurrent protection layer according to the second embodiment of the present invention; 3B is a perspective view of a cover insulating layer of a third embodiment of the present invention; 24 200908266 The fourth A is a perspective view of the first arrangement of the multifunctional wafer unit of the present invention. The fourth B is a perspective view of the second arrangement of the multi-function wafer unit of the present invention; the fourth C diagram is a perspective view of the third arrangement of the multi-function wafer early element of the present invention; A flowchart of a method for fabricating an embedded type multifunctional integrated structure of the invention, and a sixth diagram for cutting an embedded type multifunctional integrated structure of the present invention A single front view. [Main component symbol description]

上蓋絕緣層 1 第一半穿孔 10a 第二半穿孔 10b 第三半穿孔 10c 第一電源輸入部 11 第一電源輸出部 1 2 接地部 13 過電流保護層 2 第一半穿孔 2 0a 第二半穿孔 2 0b 第三半穿孔 2 0c 第一電極層 2 A 25 200908266 過電流保護層 2 中間絕緣層 Μ 多功能保護層 3 第二電極層 2 Β 正溫度係數材料層2 C 第二電源輸入部 2 1 第二電源輸出部 2 2 第一絕緣部 S 1 第二絕緣部 S 2 第三絕緣部 S3 第一電極層 2 Α ^ 第二電極層 2 B ^ 正溫度係數材料層2 c / 弟 >—電源輸入部 2 r 弟二電源輸出部 22，第一絕緣部 s r 第二絕緣部 S 2 ^ 第三絕緣部 S 3 ^ 開口 Μ 1〇第一半穿孔 M a 第二半穿孔 Mb 第三半穿孔 Me 第一半穿孔 3 0 a 第二半穿孔 3 0b 第三半穿孔 3 0c 第三電源輸入部 3 1 弟二電源輸出部 3 2 26 200908266 多功能保護層 3 多功能晶片單元 33 第三電源輸入部 3 1 — 第三電源輸出部 3 2 / 多功能晶片單元 3 3 — 多功能晶片單元 3 3 A 功能晶片 3 3 a 1 下蓋絕緣層 4 下蓋絕緣層 4 側邊導電單元 5 功能晶片功能晶片多功能晶片單元功能晶片功能晶片多功能晶片單元功能晶片功能晶片功能晶片功能晶片第一半穿孔第二半穿孔第三半穿孔第四電源輸出部第五電源輸出部開口第一侧邊導電層第二侧邊導電層 3 3a2 3 3 a 3 3 3 B 3 3 b 1 3 3 b 2 3 3 C 3 3 c 1 3 3 c 2 3 3 c 3 3 3 c 4 4 0a 4 0b 4 0c 4 1 4 2 4 0 ^ 27 200908266 第三側邊導電層 53 第一側邊導電層 51 第二侧邊導電層 52 第三侧邊導電層 53 電源輸入端 V in 電源輸出端 V outUpper cover insulating layer 1 first half perforation 10a second semi-perforated 10b third semi-perforated 10c first power input portion 11 first power output portion 1 2 ground portion 13 overcurrent protection layer 2 first half perforation 2 0a second semi-perforated 2 0b Third semi-perforated 2 0c First electrode layer 2 A 25 200908266 Overcurrent protection layer 2 Intermediate insulation layer 多功能 Multi-function protective layer 3 Second electrode layer 2 Β Positive temperature coefficient material layer 2 C Second power input unit 2 1 Second power supply output portion 2 2 first insulating portion S 1 second insulating portion S 2 third insulating portion S3 first electrode layer 2 Α ^ second electrode layer 2 B ^ positive temperature coefficient material layer 2 c / brother > Power input unit 2 r second power supply output unit 22, first insulating portion sr second insulating portion S 2 ^ third insulating portion S 3 ^ opening Μ 1 〇 first semi-perforated M a second semi-perforated Mb third semi-perforated Me first half perforation 3 0 a second semi-perforated 3 0b third semi-perforated 3 0c third power input 3 1 second power supply output 3 2 26 200908266 multi-function protective layer 3 multi-function chip unit 33 third power input Department 3 1 - Section Power output unit 3 2 / Multi-function chip unit 3 3 - Multi-function chip unit 3 3 A Function chip 3 3 a 1 Lower cover insulating layer 4 Lower cover insulating layer 4 Side conductive unit 5 Functional wafer function wafer Multi-function wafer unit function Wafer function wafer multifunction wafer unit function wafer function wafer function wafer function wafer first half perforation second half perforation third half perforation fourth power supply output fifth power output opening first side conductive layer second side conductive layer 3 3a2 3 3 a 3 3 3 B 3 3 b 1 3 3 b 2 3 3 C 3 3 c 1 3 3 c 2 3 3 c 3 3 3 c 4 4 0a 4 0b 4 0c 4 1 4 2 4 0 ^ 27 200908266 Third side conductive layer 53 First side conductive layer 51 Second side conductive layer 52 Third side conductive layer 53 Power input terminal V in Power output terminal V out

接地端 G 側邊貫穿槽單元6 第一侧邊貫穿槽 61 第二側邊貫穿槽 62 第三侧邊貫穿槽 63Grounding end G side through groove unit 6 first side through groove 61 second side through groove 62 third side through groove 63

2828

Claims

200908266 X. Patent application scope: 1. An embedded type multifunctional integrated structure, comprising: a top cover insulating layer having at least one first power input portion (first power input portion); an over-current protection layer disposed at a lower end of the upper cover insulating layer, and the overcurrent protection layer has a second power input portion And a second power output portion; an intermediate insulating layer disposed at a lower end of the overcurrent protection layer, and the intermediate insulating layer has an opening D; a functional protection layer is disposed at a lower end of the intermediate insulating layer, and the multifunctional protective layer has a third power input portion and a third power output portion Output Portion), and an electrical connection to the third power input unit and the third power a multifunctional chip unit between the source output portions, wherein the multi-function chip unit is placed in an opening of the intermediate insulating layer; a bottom cover insulating layer is disposed on the a lower end of the multifunctional protective layer, and the lower cover insulating layer has a fourth power output portion and a fifth power output portion; 29 200908266 and a side conductive unit ( Lateral conc}uctive miit) comprising three layers of a first hteml conductive layer, a second lateral conductive layer, and a third side conductive layer a third conductive layer, wherein each of the side conductive layers is sequentially formed from top to bottom on the upper cover insulating layer, the overcurrent protective layer, the intermediate insulating layer, the multifunctional protective layer, and the lower cover insulating layer a side wall; wherein the first power input portion and the second power input portion pass through the first side conductive layer to generate an electrical connection, the first The power output unit, the third power input unit and the fourth power output unit are electrically connected to the second side conductive layer, and the third power output unit and the fifth power output unit transmit the first Three side conductive layers to create an electrical connection. 2. The embedded type multifunctional integrated structure according to claim 1, further comprising: a lateral penetrating groove unit, which includes three lanes Separating from each other, a first lateral penetrating groove, a second lateral penetrating groove, and a third lateral penetrating groove, wherein the first a side conductive layer is formed on the inner surface of the first side through groove. The second side conductive layer is formed on the second side of the inner surface of the 30200908266 groove, and the third side conductive layer is Formed on the inner surface of the third side through groove. The embedded type multifuncti〇nal imegrated structure according to the second aspect of the invention, wherein the first side through-groove is formed by a plurality of Forming an upper cover insulating layer, the overcurrent protective layer, the intermediate insulating layer, the multifunctional protective layer, and a first half hole on one side of the lower cover insulating layer, the second side The side through slot is formed by a plurality of second halves respectively formed on the upper cover insulating layer, the overcurrent protection layer, the intermediate insulating layer, the multifunctional protective layer, and the opposite side of the lower cover insulating layer a second half hole is stacked, and the third side through hole is formed by the plurality of upper cover insulating layers, the overcurrent protection layer, the intermediate insulating layer, and the And the third half-holes of the opposite sides of the underlying insulating layer are stacked. 4. The embedded type multifunctional integrated structure of claim 1, wherein the upper cover insulating layer has at least one electrically connected to the one side conductive layer a first power output portion and at least one grounding portion electrically connected to the third side conductive layer and the at least one first power input portion is formed on the upper cover insulating layer The one side end of the upper surface, the at least one first electric source output portion and the at least one ground portion are respectively formed on the opposite side end of the upper surface of the upper cover insulating layer. 31 200908266 5. The embedded type multifunctional integrated structure of the first aspect of the invention, wherein the overcurrent protection layer is composed of a first electrode layer, a second electrode layer and a positive temperature coefficient material layer are formed and the positive temperature coefficient material layer is formed between the first electrode layer and the second electrode layer . 6. The embedded type niultifuiictional integrated structure according to claim 5, wherein the positive temperature coefficient material layer is a polymer positive temperature coefficient (Polymer Positive Temperature Coefficient, PPTC) material layer, resistive material layer, capacitive material layer, or inductive material layer. 7. The embedded type multifuiictional integrated structure according to the fifth aspect of the invention, wherein the second power input portion is a side end of the second electrode layer, the first The second power supply output portion is a side end of the first electrode layer, and the first electrode layer has a first insulating portion and a first electrical insulating portion for electrically isolating the first side conductive layer a second insulating portion for electrically isolating the third side conductive layer, the second electrode layer having a second side conductive layer and the third side conductive layer The third insulating portion is electrically insulated, so that the first electrode layer and the second electrode layer respectively pass through the second insulating portion and the 32 200908266 third insulating portion to conduct electricity with the third side The layer is electrically isolated. 8. The embedded type multifunctional integrated structure according to the fifth aspect of the invention, wherein the second power input portion is a side end of the first electrode layer, the first The second power supply output portion is a side end of the second electrode layer, and the first electrode layer has a third insulation for electrically isolating the second side conductive layer and the third side conductive layer a second insulating portion, the second electrode layer having a first insulating portion for electrically isolating the first side conductive layer and a third side conductive layer The second insulating portion is electrically insulated, so that the first electrode layer and the second electrode layer respectively pass through the third insulating portion and the second insulating portion to electrically connect with the third side conductive layer Sexual isolation. 9. The embedded type multifunctional integrated structure of claim 1, wherein the third power input portion is formed on the upper surface of the multifunctional protective layer (top surface) And the third power output portion is formed on the upper surface of the multifunctional protective layer (t〇p surface ). The embedded type multifunctional integrated structure of the first aspect of the invention, wherein the third power input portion is formed under the multifunctional protection layer a bottom surface, and the third power output portion is formed on a lower surface of the multifunctional protective layer (b〇tt〇ni surface). The invention relates to an embedded type multifunctional integrated structure as described in claim 1, wherein the third power input portion is formed on the upper surface of the multifunctional protective layer. (top surface) and lower surface (b〇tt〇In surface)' and the third power output portion is formed on the top surface and the lower surface of the multifunctional protective layer (b〇tt〇rn surface) 1 2. The embedded type multifunctional integrated structure of the embedded type described in claim 1 wherein the multifunctional chip unit is a functional chip ° 1 3 The embedded type multifunctional integrated structure as described in claim 12, wherein the functional chip is an Over-Voltage Protection (OVP) chip, Anti-Electromagnetic Interference (anti-EMI) wafer, CJ or Anti-Electrostatic Discharge (anti-ESD) Wafer. The embedded type multifunctional integrated structure of claim 1, wherein the multifunctional wafer unit is composed of a plurality of functional chips. 1 . The embedded type multifunctional integrated 34 200908266 structure according to claim 14, wherein the functional chips are respectively an over voltage protection (Over-Voltage Protection) , OVP) wafer, an anti-electromagnetic interference (anti-Electromagnetic Interference) film, and an anti-electrostatic (Anti-Electrostatic Discharge, anti-ESD) wafer. 1. The embedded type multifunctional integrated structure of claim 14, wherein the functional chips are electrically connected in parallel to the third power source. Between the input unit and the third power output unit. 1. The embedded type multifunctional integrated structure of claim 14, wherein the functional chips are electrically connected to the second power supply in series (seriesiy) Between the input unit and the third power output unit. 18. The embedded type multifunctional integrated structure of claim 4, wherein the functional chips are simultaneously Parallelly and Serially powered. The connection is between the third power input unit and the third power output unit. The embedded type multifunctional integrated structure of the above-mentioned invention, wherein the fourth power output portion is formed on a lower surface of the lower cover insulating layer, and The fifth power supply wheel is formed on the lower surface of the lower 35 200908266 cover insulation layer. 2. The embedded type multifunctional integrated structure of the invention of claim 1, wherein the upper cover insulating layer, the overcurrent protective layer, the intermediate insulating layer, the multifunctional The protective layer and the underlying insulating layer are sequentially stacked together. 2 1. A method of fabricating an embedded type multifunctional integrated structure, the method comprising: providing a top cover insulating layer having at least a first power input portion ( Providing an over-current protection layer having a second power input portion and a second power output portion; a middle insulating layer having an opening and a conductive passage; providing a multifunctional protection layer having a third power input portion a third power output portion, and a multifunctional chip unit electrically connected between the third power input portion and the third power output portion, wherein the multi-chip unit Functional wafer unit 36 200908266 $ for striking the intermediate insulating layer Inside the opening; providing a bottom cover insulating layer, a fourth power output portion of the itch power output portion; '°H upper cover insulation layer, The overcurrent protection layer, the intermediate insulating layer 'read multi & At / ' force the protective layer, and the lower cover insulating layer stack (St. kiss) are combined together; and form a boring edge φ a / , ^ (first lateral conductive layer) ' - second spur s γ and - second lateral conductive layer, - lateral conductive layer (third lateral conductive laye〇, i 夂 sel ^, ^ The mother-layer side conductive layer is sequentially formed from top to bottom on the eve, the home layer, the overcurrent protection layer, the intermediate insulation layer, or the eve I force energy only #第一示5 a vine layer and a side of the lower cover insulating layer, so that the sleeve-passing wheel portion and the second power input portion pass through the first electrical layer to electrically connect, the second power output portion, Second / brother ~ power wheel and the fourth power supply Transmitted through the second line portion 2 :: ί guide layer to create electrical connection, and the third power supply input 4 and the fifth output line of the third side section via the conductive layer to produce electrical connection. 2, 2, the method for fabricating an embedded type multifunctional integrated structure according to the second aspect of the patent application scope, wherein the step of forming the side conductive layers further The method includes: forming a first lateral penetrating groove, a second lateral penetrating groove, and a third lateral penetrating groove, wherein the third lateral penetrating groove The side conduction channel is formed by drilling or stamping through the upper cover insulating layer, the overcurrent protection layer, the intermediate insulating layer, the multifunctional protective layer, and the lower cover insulating layer, and The first side conductive layer is formed on the inner surface of the first side through groove, the second side conductive layer is formed on the inner surface of the second side through groove, and the third side conductive layer is Formed on the inner surface of the third side through groove. The manufacturing method of the embedded type multifimctional integrated structure according to the second aspect of the invention, wherein the first side through-groove is formed by a plurality of a first half hole of the upper cover insulating layer, the overcurrent protective layer, the intermediate insulating layer, the multifunctional protective layer, and one side of the lower cover insulating layer are stacked, the second side The through-groove is composed of a plurality of second semi-perforations (sec) respectively formed on the upper cover insulating layer, the overcurrent protective layer, the intermediate insulating layer, the multifunctional protective layer, and the opposite side of the lower cover insulating layer 〇 nd half hole) and the second side through slot is formed by the plurality of upper cover insulating layers, the overcurrent protective layer, the intermediate insulating layer, the multifunctional protective layer, and the A third half hole of the opposite side of the lower cover insulating layer is stacked. The method for fabricating an embedded type multifunctional integrated structure according to the above-mentioned claim, wherein the upper cover insulating layer has at least 38 200908266 electrically connected to the a first power output portion of the second side conductive layer and at least one grounding portion electrically connected to the third side conductive layer, and the at least one first power input portion The at least one first power output portion and the at least one ground portion formed on the upper surface of the upper surface of the upper cover insulating layer are respectively formed on the opposite side ends of the upper surface of the upper cover insulating layer. The method of fabricating an embedded type multifunctional integrated structure according to claim 21, wherein the overcurrent protection layer is formed by a first electrode layer (first electrode layer) a second electrode layer and a positive temperature coefficient material layer, and the positive temperature coefficient material layer is formed on the first electrode layer and the first Between the two electrode layers. 2. The method of fabricating an embedded type multifunctional integrated structure according to claim 25, wherein the positive temperature coefficient material layer is a local positive molecular temperature coefficient ( Polymer p〇sitive Temperature Coefficient, PPTC) material layer, resistive material layer, capacitive material layer, or inductive material layer. The method of manufacturing the embedded type multifunctional integrated structure according to the second aspect of the patent application, wherein the second power input unit is the 39 200908266

a side end of the second electrode layer, the second power output portion is a side end of the first electrode layer, and the first electrode layer has a function for electrically isolating the first side conductive layer a first insulating portion and a second insulating portion for electrically isolating the third side conductive layer, the second electrode layer having a second side a third insulating portion electrically isolated from the conductive layer and the third conductive layer, wherein the first electrode layer and the second electrode layer respectively pass through the second insulating portion and the third insulating portion The portion is electrically isolated from the third side conductive layer. The method of fabricating an embedded type multifunctional Uitegra^ structure according to the second aspect of the invention, wherein the second power input portion is a first electrode layer One side end, the second power output portion is a side end of the electrode layer, and the first electrode layer has a second side conductive layer and the third side conductive layer electrical three insulating portion a second insulating portion, the second electric wood rate has a first insulating portion for electrically isolating the first side conductive layer, and a color is used for the first insulating portion a second insulating portion (second 1 conduction portion) electrically isolated from the buffer layer, so that the first electrode layer and the second electrode layer are separated from the third insulating portion and the second insulating portion to be associated with the third gamma The enamel layer is electrically isolated.

2 9. The method for manufacturing an embedded type multifunctional integrated structure according to the invention of claim 2, wherein the third power input unit is formed in 5 Bprotecting the upper surface (t〇p surface), and the third power output portion is formed on the upper surface of the multifunctional protective layer (t〇p surface ) ° 3 0, as in the second application of the patent scope The manufacturing method of the embedded type multifunctional integrated structure, wherein the third power input portion is formed on a bottom surface of the multifunctional protective layer, and the third The power output portion is formed on a bottom surface of the multifunctional protective layer. The method of manufacturing an embedded type multifunctional integrated structure according to the above-mentioned claim, wherein the third power wheel-in portion is formed in the multifunctional protective layer. a top surface and a bottom surface, and the third power output portion is formed on the top surface and the bottom surface of the multifunctional protective layer. The method of fabricating an embedded type multifunctional integrated structure according to the above aspect, wherein the multifunctional chip unit is a functional chip. 3) The method for fabricating an embedded type multifunctional integrated structure (200908266 structure) according to claim 32, wherein the functional chip is an overvoltage protection (Over-Voltage) Protection, OVP) wafer, Anti-Electromagnetic Interference (anti-EMI) wafer, or an anti-Eleclrostatic Discharge (anti-ESD) wafer. 3. The method of fabricating an embedded type multifunctional integrated structure according to claim 21, wherein the multifunctional chip unit is composed of a plurality of functional chips. Composed of. 3 . The method for fabricating an embedded type multifunctional integrated structure according to claim 34, wherein the functional chips are respectively an over voltage protection (Over-Voltage) Protection, OVP) wafers, anti-electromagnetic interference (anti-Electromagnetic Interference) anti-EMI wafers, and an anti-electrostatic electrostatic anti-ESD wafer. 3. The method of fabricating an embedded type multifimctional integrated structure according to claim 34, wherein the functional chips are electrically connected in parallel Between the third power input unit and the third power output unit. 3. The method of fabricating an embedded type multifunctional integrated structure according to claim 34, wherein the functional chips are electrically connected in series 42 200908266 (seriesly) Between the source outputs. a second power input unit and the third power device, and a method for fabricating an embedded type m_functional integmted structure according to the third aspect of the invention, wherein the functional chip The device is electrically connected in parallel and in series (seriaiiy) between the third power input unit and the third power output unit.

3. The method of fabricating an embedded type multifunctional integrated structure according to the above-mentioned claim, wherein the fourth power output portion is formed in the lower cover insulating layer. The lower surface 'and the fifth power supply wheel is formed on the lower surface of the lower cover insulating layer. 43