200908040 VIT07-0045 24237twf.doc/p 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種被動元件（passive eQmpQnent)， 且特别疋有關於-種電谷器-(capacit〇r)卩及具有此電容 器的電子組裝體（dectr〇nic assembly)。 【先前技術】 桌上型電腦的北橋或南橋晶片組（chipset)是一個電 r、孩裝體’其包括-線路載板、—安裝在線路載板上的晶 k >1及多個安裝在線路载板上的電容器，其巾電容器的功用 在於使電子訊號穩定以維持電子訊號的品質。 圖1A是習知一種電子組裝體的俯視示意圖。請參閱 圖1A，電子組裝體刚包括一線路載板ιι〇、一對電容器 120a與1鳥、-晶片13()以及多條金線14〇，其中電容器 12Gb、晶片13G*這些金線14G皆組裝於線路載板 .片13G透過這些金線⑽而電性連接至這些打線接 I 、，霞6 b〇ndmg pad) 114 ’ 而這對電容器 120a 及 l2〇b 亚列地¥接於線路载板11〇上，並位於相鄰二條走線 之間。 由於線路載板11Q朝向高佈線密度的趨勢發展，所以 ^電容器⑽及12%之間會十分靠近，以縮小這 120a及·所佔據的線路載板11〇之面積。如此， 、'’路載板110的佈線密度可以提高。 、 然而，當這對電容器⑽與咖彼此太過靠近時， 200908040 νιιυ/-υϋ45 /4237twf.d〇c/p 電容器120a或電容器12〇b 110上。 14地焊接於線路載板 圖1B是圖1A中的二電容 路載板的立體示意圖，而圖丨 :的情況下焊接於線 器在異常的情況下烊接於線路栽的其中一個電容 閱圖1B，電容器120&的二端 體不意圖。請先參 ο c 而電容器120b的二端分別具:有二外部電極l22a， 在正常的情況下，這些外:電極咖。 極122b會分別透過這些焊錫S1 l22a與這些外部電 板110上。詳言之，這些焊錫s/、、^錫S2連接於線路载 會將這些外部電極122a與這些外if回焊（refl⑽）後 載板110上。 ~ 〇兒極12沘連接至線路 的焊過It，焊錫S1容易與鄰近 器隱的情況下，原本連接复太靠近電容200908040 VIT07-0045 24237twf.doc/p IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a passive element (passive eQmpQnent), and particularly to a type of electric grid device - (capacit〇r And an electronic assembly having this capacitor (dectr〇nic assembly). [Prior Art] The north bridge or south bridge chipset of a desktop computer is an electric r, a child's body, which includes a line carrier board, a crystal k >1 and a plurality of installations mounted on the line carrier board. The function of the capacitor on the line carrier is to stabilize the electronic signal to maintain the quality of the electronic signal. 1A is a top plan view of a conventional electronic assembly. Referring to FIG. 1A, the electronic assembly includes a line carrier ιι, a pair of capacitors 120a and 1 bird, a wafer 13 (), and a plurality of gold wires 14 〇, wherein the capacitors 12Gb and 13G* are each of the gold wires 14G. Assembled on the line carrier board. The sheet 13G is electrically connected to the wire bonding wires I and the wires 6 through the gold wires (10), and the pair of capacitors 120a and l2〇b are connected to the line. The board 11 is on the top and is located between two adjacent lines. Since the line carrier 11Q is trending toward a high wiring density, the capacitors (10) and 12% are very close to each other to reduce the area of the line carrier 11 occupied by the 120a and the . Thus, the wiring density of the ''road carrier board 110' can be improved. However, when the pair of capacitors (10) and the coffee are too close to each other, 200908040 νιιυ/-υϋ45 / 4237 twf.d 〇 c / p capacitor 120a or capacitor 12 〇 b 110. 14 is welded to the line carrier board. FIG. 1B is a perspective view of the two-capacitance road carrier board of FIG. 1A, and in the case of the figure: in the case of an abnormality, the one of the capacitors is connected to the line. 1B, the two ends of the capacitors 120 & are not intended. Please refer to ο c first and the two ends of the capacitor 120b have: two external electrodes l22a, in the normal case, these: electrode coffee. The poles 122b pass through the solders S1 l22a and the external boards 110, respectively. In detail, these solders s/, tin S2 are connected to the line carrier and these external electrodes 122a are reflowed (refl(10)) to the rear carrier 110. ~ 〇儿极12沘 is connected to the line of soldered It, solder S1 is easy to be hidden with the adjacent device, the original connection is too close to the capacitor
:很容易被其鄰近的焊錫Sl;吸引=== 的-端會受到其連接的焊錫S 因此，電容器12〇 :==:11°上，如圖lc所示。 circuit)。 、轉载板UG之間形成斷路（broken 在目广二1A，為了避免這種斷路的情形發生’ 去且衣衣私中’電容器120&與電容器120b之間的 的制在500微米（μιη)以上。然而，這種間隔D 的限物木件部k成線路載板110的佈線密度很難進一步地 200908040 4237twf.doc/p 提高。 【發明内容】 本發明提供一種雷交哭*Α 線路載板。 °° 組裝於高佈線密度的 本發明提供一種雷早、 與線路載板斷路。 ^ 以避免電容器在回焊後 六^發明提供—種電容器，包括多個 Ο 構、-第二電容結構、_ :層、：第—電 電極、一第三外部電 •極、一第二外部 電層相互重疊。第 :勺:夕卜部電接，其中這些介 :第二内部電極，其中===内部電極與多 电極分別配置於這些介 邻私極與這些第二内部 電容結構包括多個第三=fa ’並且交錯地重疊。第二 工這些第三内部電極;這：第極:f個第四内部電極，其 ί電層之間’並且交錯:;c配置於這些 麵:=及2相鄰的第二 ，蝴這些第―:部的第四内部電極。第二； =這些第二内部電極的端端緣，而第二外部電極連 内部電極的端緣 外U卜部電極連接這也 的端緣。 第四外部電極連接這些第四内部;極 “本發明另提供—種電 結構、-第二電容、4，括多個介電層、-第-心極、-第三外部電搞二':-外部電極、—第二： 及—第四外部電極，其中免 200908040 VIXU/-UU^〇 ^4237twf.doc/p 介電層相互重疊。第一帝& 多個第二内部電極，構包括多個第一内部電極與 部電極分別配置於這些介電極與這些第二内 二電容結構包括多個第三“^二，交錯地重疊。第 其中這些第三内部電極 ^極向、夕個第四内部電極， ο 些介電層之間= H電極分別配置於這 些第二内部電極之一、與、此ς廷些弟一内部電極及這 =電極之—夾持這些介電：：：：：部電極及這些第四内 第一内部電極的端緣，二-第一外部電極連接這些 ^極的端緣。第三外部電極連接接這些第二内部 緣’而第四外部電極連 接足』弟三内部電極的端 —本發明另提供—種電子組裝:内=極的端緣。 二線路载板。線路载板包括多個接墊匕：上述之電容器與 接至第-外部電極、第二=塾’而這些接墊分別桿 四外部電極。 兒極、第三外部電椏以及第 由於本發明之電容哭 構在結構上藉岭齡電電^續_二電容結 ^容器在回厚後正常地組裝於_^_；因此本發明能使 :知技術而言，本發明的電容=上。此外，相較於 較小’因此本發明的電容器適合 $線路載板之面積 载板。 σ、、、裝於南佈線密度的線路 發明之上述特徵和優點 牛』，並配合所附 ，下文特 【貫施方式】 作评細說明如下。 200908040 V1IU/-UU4^ Z4237fwf.d〇c/p 意圖:請參=;===示 ;;及上至少-電容器，其中電容器組=線载=: 電…線^板:包括多條走線212與多個接墊214，而 3: 包括一第-外部電極310、-第二外部電極 弟三外部電極以及„第四外部電極34 接墊别^別焊接至第一外部電極310、第二外部電ς 弟一外部電極33〇以及第四外部電極34〇 =組裝於線路载板210上。電容器_配心 才目钟二條走線212之間。在本實施例中 t 鄰近電容器3〇0之處的分佈較為密隼。—走線212在 線(=:=包: ^ 」30而晶片220可藉由這此鍵人霉蟪 ，裝於線路载板21〇上，如圖2Α所示。因:鍵= 反〇可為打線封裝類型的晶片載板。 、' =至少-電容器3。。::=。== 與晶片咖組裝於線路載板2iq’上。300 216，、而晶m〗,01括多條走線212以及多個覆晶接墊 ⑽。因:(卿）方錢絲越覆晶接塾 圖从是心由〇可為覆晶封裝類型的晶片載板。 圖2A中的電容器的立體示意圖，而圖3B是 200908040 νηυ/-υυ4^ ^4237twf.doc/p 圖3A的電容器的立體透視圖。請同時參閱圖3A與圖3B， 電容器300包括一第一電容結構350以及一第二電容結構 360。 第一電容結構350包括多個第一内部電極352與多個 第二内部電極354，且這些第一内部電極352與這些第二 内部電極354交錯地重疊。第二電容結構360包括多個第 三内部電極362與多個第四内部電極364，且這些第三内 部電極362與這些第四内部電極364交錯地重疊。因此， 這些第一内部電極352與這些第二内部電極354部分重 疊，而這些第三内部電極362與這些第四内部電極364部 分重疊。 圖3C是圖3A沿線I-Ι的剖面示意圖，而圖3D是圖 3A沿線II-II的剖面示意圖。請同時參閱圖3C與圖3D， 電容器300還包括多個介電層370，而這些介電層370相 互重疊。此外，這些介電層370可以是由多片陶瓷生胚燒 結而成。 這些第·一内部電極352、這些第二内部電極354、這 些第三内部電極362與這些第四内部電極364分別配置於 這些介電層370之間，其中這些介電層370之一夾於這些 第一内部電極352之一及與其相鄰的第二内部電極354， 並夾於這些第三内部電極362之一及與其相鄰的第四内部 電極364。 在同一層介電層370中，這些第一内部電極352之一 與這些第三内部電極362之一同在此介電層370的一側， 10 200908040 VIT07-0045 24237twf.doc/p 而这些第一内部電極354之—與這些第四内部電極364之 -則同在此介電層370的另—側。其次，這些第一内部電 極352與這些第二内部電極362不相連，而這些第二内部 電極354與這些第四内部電極364不相連。此外，第一電 谷結構350與第二電容結構在結構上是藉由這些介電 層37〇而彼此連接。 第—外°卩電極310連接這些第一内部電極352的端: It is easy to be soldered by its neighboring solder Sl; the end of the attracting === will be subjected to the solder S connected thereto. Therefore, the capacitor 12 〇 :==: 11°, as shown in Figure lc. Circuit). Breaking between the transfer board UG (broken in the 2A, in order to avoid this kind of open circuit occurs, and the gap between the capacitor 120& and the capacitor 120b is made at 500 micrometers (μιη) However, the wiring density of the spacer wood member k of the interval D is difficult to be further improved by the 200908040 4237 twf.doc/p. [Invention] The present invention provides a lightning supply crying line. The invention is assembled in a high wiring density to provide a lightning early, open circuit board disconnection. ^ To avoid capacitors after reflow, the invention provides a capacitor, including a plurality of structures, a second capacitor structure. , _ : layer,: the first electric electrode, a third external electric pole, and a second outer electric layer overlap each other. The first spoon: the outer portion of the electrical connection, wherein these are: the second internal electrode, wherein === The internal electrode and the plurality of electrodes are respectively disposed on the neighboring private poles and the second internal capacitor structures include a plurality of third=fa' and are alternately overlapped. The second working third internal electrodes; this: the first pole: f Fourth internal electrode Between 'and staggered:; c is placed on these faces: = and 2 adjacent second, the fourth internal electrode of the ―: part. Second; = the end edge of these second internal electrodes, and the second The external electrode is connected to the end edge of the internal electrode, and the U-port electrode is connected to the end edge. The fourth external electrode is connected to the fourth inner portion; the pole "the invention further provides an electrical structure, a second capacitor, 4, and a plurality of Dielectric layer, - first-pole, - third external electric two -: - external electrode, - second: and - fourth external electrode, which is free from 200908040 VIXU / - UU ^ 〇 ^ 4237twf.doc / p The electric layers overlap each other. The first emperor and the plurality of second inner electrodes comprise a plurality of first inner electrodes and the partial electrodes respectively disposed on the dielectric electrodes, and the second inner two capacitor structures comprise a plurality of third “^ Interlaced with each other, wherein the third internal electrode is in the direction of the fourth internal electrode, and the dielectric layers are disposed between the second internal electrodes, and Brother an internal electrode and this = electrode - hold these dielectric ::::: part of the electrode and these The end edges of the first inner electrodes of the four inner electrodes are connected to the end edges of the electrodes. The third outer electrodes are connected to the second inner edges and the fourth outer electrodes are connected to the ends of the inner electrodes of the third - The invention further provides an electronic assembly: an inner=pole end edge. A two-line carrier board. The line carrier includes a plurality of pads: the capacitor is connected to the first-outer electrode, and the second=塾' The pads are respectively connected to the external electrodes of the rods. The poles, the third external electric cymbals, and the capacitors of the present invention are crying on the structure, and the cascading electric power is continued. The two capacitors are assembled in the _^ after being thickened. Therefore, the present invention enables, by known technology, the capacitance of the present invention to be upper. Moreover, the capacitor of the present invention is suitable for the area carrier of the line carrier as compared to the smaller one. σ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 200908040 V1IU/-UU4^ Z4237fwf.d〇c/p Intent: Please refer to =; === show;; and at least - capacitor, where capacitor group = line load =: electric ... line ^ board: including multiple traces 212 and a plurality of pads 214, and 3: including a first outer electrode 310, a second outer electrode three external electrodes, and a fourth fourth outer electrode 34 are soldered to the first outer electrode 310, second The external power source an external electrode 33A and the fourth external electrode 34〇 are assembled on the line carrier 210. The capacitor _ core is between the two traces 212. In this embodiment, t is adjacent to the capacitor 3〇0. The distribution of the place is relatively dense. The line 212 is online (=:=Pack: ^ ”30 and the wafer 220 can be mounted on the line carrier board 21 by the button, as shown in FIG. 2A. Because: key = 〇 can be the wafer carrier of the wire package type., ' = at least - capacitor 3 . . :: =. == and the chip coffee is assembled on the line carrier 2iq'. 300 216, and crystal m 〖, 01 includes a plurality of traces 212 and a plurality of flip-chip pads (10). Because: (Qing) Fang Qiansi more than the flip-chip connection diagram is from the heart of the chip can be a flip-chip package type wafer carrier. Figure 2A Electricity in 3B is a perspective view of the capacitor of FIG. 3A. Please refer to FIG. 3A and FIG. 3B simultaneously, the capacitor 300 includes a first capacitor structure 350 and a The second capacitor structure 360. The first capacitor structure 350 includes a plurality of first internal electrodes 352 and a plurality of second internal electrodes 354, and the first internal electrodes 352 are alternately overlapped with the second internal electrodes 354. The second capacitor structure 360 includes a plurality of third inner electrodes 362 and a plurality of fourth inner electrodes 364, and these third inner electrodes 362 are alternately overlapped with the fourth inner electrodes 364. Therefore, the first inner electrodes 352 and the second inner electrodes 354 partially overlaps, and these third internal electrodes 362 partially overlap with the fourth internal electrodes 364. Fig. 3C is a cross-sectional view taken along line I-Ι of Fig. 3A, and Fig. 3D is a cross-sectional view along line II-II of Fig. 3A. 3C and 3D, the capacitor 300 further includes a plurality of dielectric layers 370, and the dielectric layers 370 overlap each other. Further, the dielectric layers 370 may be sintered from a plurality of ceramic green sheets. The first inner electrode 352, the second inner electrode 354, the third inner electrode 362 and the fourth inner electrode 364 are respectively disposed between the dielectric layers 370, wherein one of the dielectric layers 370 is sandwiched between the first inner electrodes 362 One of the internal electrodes 352 and the second internal electrode 354 adjacent thereto are sandwiched between one of the third internal electrodes 362 and the fourth internal electrode 364 adjacent thereto. In the same dielectric layer 370, one of the first internal electrodes 352 is on the side of the dielectric layer 370 with one of the third internal electrodes 362, 10 200908040 VIT07-0045 24237 twf.doc/p and these first The internal electrodes 354 - and the fourth internal electrodes 364 - are on the other side of the dielectric layer 370. Second, the first internal electrodes 352 are not connected to the second internal electrodes 362, and the second internal electrodes 354 are not connected to the fourth internal electrodes 364. In addition, the first valley structure 350 and the second capacitor structure are structurally connected to each other by the dielectric layers 37A. The first-outer 卩 electrode 310 connects the ends of the first internal electrodes 352
C o 緣:：二::極：連接這些第二内部電極354的端 三内部電極3心端Γ而第/外部電極330連接這些第 四内部電極364 :^。而第四外部電極340連接這些第 請再次參閱圖3R，太士 ^ 與第三外部電極^ =貫施财’第一外部電極310 320與第四外部|存有—間距G1，而第二外部電極 極與第二外部電極間距㈤。第—外部電 部電㈣。與第”卜部==距：而第三外 由於第—電衮妹 0之間存有一間足巨G4。 藉由這些介電層37〇而 ^第二電容結構360在結構上 與電容器120b之間 ^接’因此，相較於電容器120a m〜間距G4四者的的而言（請參閱圖叫，間距 爾（1密爾等於〇 〇〇1英豆例如是等於或大於100密 能打破習知技術中圖1A的。因此，間距G1〜間距G4 器3〇〇能有效⑻、其佔據綠之限制條件，所以電容 參閱圖2A與圖2B)。如:路，板210或210,的面積（請 這些走線212的分佈密度得 200908040 vnu/-uu43 z4237twf.doc/p 以提高，故電容器300適合組裝於高佈線密度的線路載板 210。 為了不同的電路設計之考置’第·一電容結構350的電 容值可以等於第二電容結構360的電容值，或者是第一電 容結構350的電容值不等於第二電容結構360的電容值。 在第一電容結構350與第二電容結構360二者電容值不相 等的情況下，第一電容結構350的電容值可以大於O.lpF， 而第二電容結構360的電容值則在0至lpF之間。 值得一提的是，針對其他不同的電路設計，在電性結 構上，第一電容結構350可以與第二電容結構360串聯或 並聯。當第一電容結構350與第二電容結構360並聯時， 第一外部電極310可以連接第三外部電極330，而第二外 部電極320可以連接第四外部電極340。 圖4A是本發明另一實施例的一種電容器的立體示意 圖，而圖4B是圖4A的電容器的立體透視圖。請參閱圖 4A與圖4B，本實施例的電容器400包括一第一外部電極 410、一第二外部電極420、一第三外部電極430、一第四 外部電極440、一第一電容結構450以及一第二電容結構 460。 第一電容結構450包括多個第一内部電極452與多個 第二内部電極454，且這些第一内部電極452與這些第二 内部電極454交錯地重疊。第二電容結構460包括多個第 三内部電極462與多個第四内部電極464，且這些第三内 部電極462與這些第四内部電極464交錯地重疊。也就是 12 200908040 VI 107-004^ ^4237twf.doc/p 說，這些第一内部電極452與這些第二内部電極454部分 重疊，而這些第三内部電極462與這些第四内部電極464 部分重疊。 在本實施例中，這些第一内部電極452實質上可以與 這些第三内部電極462完全重疊，而這些第二内部電極454 實質上可以與這些第四内部電極464完全重疊。 圖4C是圖4A沿線III-III的剖面示意圖，而圖4D是 圖4A沿線IV-IV的剖面示意圖。請同時參閱圖4C與圖 (5 4D，電容器400還包括多個介電層470,而這些介電層470 相互重疊。 這些第一内部電極452、這些第二内部電極454、這 些第三内部電極462與這些第四内部電極464分別配置於 這些介電層470之間，其中這些第一内部電極452及這些 第二内部電極454之一、與這些第三内部電極462及這些 第四内部電極464之一夾持這些介電層470之一。 另外，第一外部電極410、第二外部電極420、第三 Q 外部電極430以及第四外部電極440分別連接這些第一内 部電極452的端緣、這些第二内部電極454的端緣、這些 第三内部電極462的端緣以及這些第四内部電極464的端 緣。此外，在本實施例中，相鄰二介電層470夾持這些第 一内部電極452、這些第二内部電極454、這些第三内部電 極462以及這些第四内部電極464其中之一。 由於第一電容結構450與第二電容結構460在結構上 藉由這些介電層470而彼此連接，因此，相較於電容器120a 13 200908040 VIT07-0U4i> 24237twf.doc/p 與電容器1施之間的間隔D而言（請參閱圖⑷，二带 容結構之間關距距離較短，例如是等於或大於購一= 爾。因此，電容器_能有效縮小其佔據線板: 训的面積（請參閱圖2A與圖2B )。如此，這些犯 = = g =高’故電容器4GG適合組襞於高佈線密 針對不同的電路設計，第—電容姓 «等於第二電容結構細的電容值5^5^，值可 =的電容值不等於第二電容結構賴 3結Π:ί二電容結構46°二者電容二 %合結構45〇的電容值可以大於0〗 —電容結構46G的電容值财G至⑽之、。· μ而第 另外，在電性結構上，第_ :的需求與第二電容結構46"聯或::5〇:視電路設 令，第-外部電極可以連 1、/。在本貫施例 極420可以連接第四外部; 笔谷^45〇與第二電容結構46〇並聯。_，以至於第一 ^ 、、不上所述，本發明之電容哭 ，結構在結構上藉由這些介容結構與第二電 =電容H在回桿之後正常地二接’因此本發明 毛各器發场起。如此，電線路餘上，以避免 焊接i'r載板，以防止斷路;情:1 卜部電極能確實地 與弟二電料構之間距小於以二^㈣—電容結構 罨奋窃之間距（其約 14 200908040 νηυ/-υυ43 ^4237twf.doc/p ::微米）。因此，本發明能縮小電容器在線路載 佔據之面積，故本發明的電容_合_於高佈線密 線路載板。由此可知，在相同電㈣之數量的條件 發明能提高線路載板的佈線密度。 本 雖然本發明已以這些實施例揭露如上，鋏 限定本發明，任何賴技術領域中具有通料識=，以 脫離本發明之精神和範圍内，當可作些 隹不 =本發明之保護範圍當視後附之巾請專利範者 【圖式簡單說明】 圖1A是習知一種電子組裝體的俯视示意圖。 圖1B是圖ία中的二電容哭在正堂从 ° 路载板的立體示意圖。 的、况下蟬接於線 圖1C是圖1A中的其中一個電容器在里 接於線路載板的立體示意圖。 ”的情況下焊 Ο 圖2A是本發明一實施例的一種電 意圖。 、、且裝體的俯視示 圖2B是本發明另—實施例的一種 示意圖。 电于、、且裴體的俯視 圖3A是圖2A中的電容器的立體示意圖。 圖3B是圖3A的電容器的立體透視圖。 Q 3C疋圖3A /告線ι_ι的剖面示意圖。 圖3D是圖3A沿線11_11的剖面示意圖。 圖4A是本發明另—實施例的一 包合态的立體示意 15 200908040 v 11 u /-wwh-j ^4237t\vf.doc/p 圖4B是圖4A的電容器的立體透視圖。 圖4C是圖4A沿線III-III的剖面不意圖。 圖4D是圖4A沿線IVJV的剖面示意圖。 【主要元件符號說明】 100、200、200’ ：電子組裝體 110、210、210’ ：線路載板 112、212 :走線 114 :打線接墊 120a、120b、300、400 :電容器 122a、122b :外部電極 130、220、220’ ：晶片 140 :金線 214 :接墊 216 :覆晶接墊 230 :鍵合導線 310、410 :第一外部電極 320、420 :第二外部電極 330、430 :第三外部電極 340、440 :第四外部電極 350、450 :第一電容結構 352、452 :第一内部電極 354、454 :第二内部電極 360、460 :第二電容結構 16 200908040 νιιυ/-υυ^3 z^237twf.doc/p 362、462 :第三内部電極 364、464 :第四内部電極 370、470 :介電層 SI' S2 :焊錫 D :間隔 G：l、G2、G3、G4 :間距C o edge:: two:: pole: the end of the second inner electrode 354 is connected. The inner electrode 3 is open at the center end and the outer/outer electrode 330 is connected to the fourth inner electrode 364 : . And the fourth external electrode 340 is connected to these. Please refer to FIG. 3R again, the squirrel ^ and the third external electrode ^ _ _ _ _ 'the first external electrode 310 320 and the fourth external | stored - the distance G1, and the second external The distance between the electrode pole and the second outer electrode (5). The first - external electricity (four). The first capacitor structure is electrically connected to the capacitor 120b by the dielectric layer 37. Therefore, compared to the capacitor 120a m ~ the spacing G4 (see the picture, the spacing (1 mil is equal to 英 1 ying, for example, equal to or greater than 100 mils can break the habit It is known in Fig. 1A. Therefore, the spacing G1 to the spacing G4 can be effective (8), which occupies the green limiting condition, so the capacitance is referred to FIG. 2A and FIG. 2B). For example, the area of the road, the plate 210 or 210, (The distribution density of these traces 212 is increased by 200908040 vnu/-uu43 z4237twf.doc/p, so the capacitor 300 is suitable for assembly on the line carrier 210 of high wiring density. For the different circuit design, the first one The capacitance value of the capacitor structure 350 may be equal to the capacitance value of the second capacitor structure 360, or the capacitance value of the first capacitor structure 350 is not equal to the capacitance value of the second capacitor structure 360. The first capacitor structure 350 and the second capacitor structure 360 When the capacitance values of the two are not equal, the first capacitor junction The capacitance value of 350 may be greater than O.lpF, and the capacitance value of the second capacitance structure 360 is between 0 and lpF. It is worth mentioning that, for other different circuit designs, the electrical structure, the first capacitance structure The 350 may be connected in series or in parallel with the second capacitor structure 360. When the first capacitor structure 350 is connected in parallel with the second capacitor structure 360, the first external electrode 310 may be connected to the third external electrode 330, and the second external electrode 320 may be connected to the fourth 4A is a perspective view of a capacitor according to another embodiment of the present invention, and FIG. 4B is a perspective perspective view of the capacitor of FIG. 4A. Referring to FIG. 4A and FIG. 4B, the capacitor 400 of the present embodiment includes a first embodiment. An external electrode 410, a second external electrode 420, a third external electrode 430, a fourth external electrode 440, a first capacitor structure 450, and a second capacitor structure 460. The first capacitor structure 450 includes a plurality of first The internal electrode 452 and the plurality of second internal electrodes 454, and the first internal electrodes 452 are alternately overlapped with the second internal electrodes 454. The second capacitive structure 460 includes a plurality of third internal electrodes 462 and a plurality of fourth internal electrodes 464, and these third internal electrodes 462 are alternately overlapped with the fourth internal electrodes 464. That is, 12 200908040 VI 107-004^^4237 twf.doc/p, these first internal electrodes 452 are The second inner electrodes 454 partially overlap, and the third inner electrodes 462 partially overlap the fourth inner electrodes 464. In the present embodiment, the first inner electrodes 452 may substantially overlap the third inner electrodes 462. And these second internal electrodes 454 may substantially completely overlap with the fourth internal electrodes 464. 4C is a cross-sectional view taken along line III-III of FIG. 4A, and FIG. 4D is a cross-sectional view taken along line IV-IV of FIG. 4A. 4C and FIG. 4D, the capacitor 400 further includes a plurality of dielectric layers 470, and the dielectric layers 470 overlap each other. The first internal electrodes 452, the second internal electrodes 454, and the third internal electrodes 462 and the fourth internal electrodes 464 are respectively disposed between the dielectric layers 470, wherein the first internal electrodes 452 and one of the second internal electrodes 454, and the third internal electrodes 462 and the fourth internal electrodes 464 One of the dielectric layers 470 is sandwiched. Further, the first external electrode 410, the second external electrode 420, the third Q external electrode 430, and the fourth external electrode 440 are respectively connected to the end edges of the first internal electrodes 452, The end edges of the second inner electrodes 454, the end edges of the third inner electrodes 462, and the end edges of the fourth inner electrodes 464. Further, in the present embodiment, the adjacent two dielectric layers 470 sandwich the first ones. One of the internal electrode 452, the second internal electrode 454, the third internal electrode 462, and the fourth internal electrode 464. Since the first capacitive structure 450 and the second capacitive structure 460 are structurally The dielectric layer 470 is connected to each other, and thus, compared with the interval D between the capacitor 120a 13 200908040 VIT07-0U4i> 24237 twf.doc/p and the capacitor 1 (see Fig. 4, the relationship between the two-capacitance structure) The distance is shorter, for example, equal to or greater than the purchase price. Therefore, the capacitor _ can effectively reduce its occupation of the board: the area of the training (see Figure 2A and Figure 2B). Thus, these crimes = = g = high ' Therefore, the capacitor 4GG is suitable for the combination of high wiring and different circuit design. The first capacitor name is equal to the capacitance value of the second capacitor structure is 5^5^, and the value of the capacitor can be equal to the second capacitor structure. Π: 二 two capacitor structure 46 ° both capacitors two% of the structure 45 〇 capacitance value can be greater than 0 〗 〖capacitor structure 46G capacitance value G to (10), · · · And in addition, in the electrical structure, The requirements of the first _: and the second capacitor structure 46" union or ::5 〇: depending on the circuit design, the first-external electrode can be connected to 1, /. In the present embodiment, the pole 420 can be connected to the fourth outer; 45〇 is connected in parallel with the second capacitor structure 46〇. _, so that the first ^, not described, the present invention The crying, the structure is structurally connected with the second electric=capacitor H after the returning rod. Therefore, the present invention starts from the field. Thus, the electric circuit is left to avoid welding i 'r carrier board to prevent open circuit; love: 1 Bu electrode can be surely separated from the second electric material structure by less than two ^ (four) - capacitor structure 罨 stealing distance (its about 14 200908040 νηυ / - υυ 43 ^ 4237twf. Doc/p::micron. Therefore, the present invention can reduce the area occupied by the capacitor in the line load, so the capacitor of the present invention is used for the high wiring dense line carrier. From this, it can be seen that the invention of the number of the same electric (four) can increase the wiring density of the wiring board. The present invention has been disclosed in the above embodiments, and the present invention is not limited to the scope of the invention, and may be deviated from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a top plan view of a conventional electronic assembly. Fig. 1B is a schematic perspective view of the two capacitors in Fig. ία crying in the hall. Figure 1C is a perspective view of one of the capacitors of Figure 1A being connected to the line carrier. FIG. 2A is a schematic view of an embodiment of the present invention, and FIG. 2B is a schematic view of another embodiment of the present invention. The top view of the body is shown in FIG. Figure 3B is a perspective view of the capacitor of Figure 3A. Figure 3D is a cross-sectional view of Figure 3A along line 11-11. Figure 4A is a schematic view of the capacitor of Figure 3A. EMBODIMENT OF THE INVENTION - A clad stereoscopic representation of an embodiment 15 200908040 v 11 u /-wwh-j ^4237t\vf.doc/p Figure 4B is a perspective perspective view of the capacitor of Figure 4A. Figure 4C is a line III of Figure 4A Fig. 4D is a schematic cross-sectional view taken along line IVJV of Fig. 4A. [Description of main components] 100, 200, 200': electronic assembly 110, 210, 210': line carrier 112, 212: routing 114: wire bonding pads 120a, 120b, 300, 400: capacitors 122a, 122b: external electrodes 130, 220, 220': wafer 140: gold wire 214: pads 216: flip chip pads 230: bonding wires 310, 410 : first external electrodes 320, 420: second external electrodes 330, 430: third external Pole 340, 440: fourth external electrode 350, 450: first capacitive structure 352, 452: first internal electrode 354, 454: second internal electrode 360, 460: second capacitive structure 16 200908040 νιιυ/-υυ^3 z ^237twf.doc/p 362, 462: third inner electrode 364, 464: fourth inner electrode 370, 470: dielectric layer SI' S2: solder D: interval G: l, G2, G3, G4: pitch
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