200905869 九、發明說明： 【發明所屬之技術領域】 本發明有關於一種半導體封裝技術，特別是有關於 一種適用於光電裝置之晶圓級晶片尺寸封裝（wafer-level chip scale package, WLCSP)結構。 【先前技術】 數位影像器件係廣泛運用於諸如數位相機、數位影 像記錄器、具有影像拍攝功能的手機、以及監視器。而 數位影像感測器通常包括一光電裝置晶片，例如電荷耦 合裝置（charge-coupled device, CCD)影像感測晶片及 CMOS影像感測晶片。數位影像感測器可將一部份的光 學影像轉換成電子信號。該電子信號用於在一顯示器上 重新產生該光學影像。 上述影像感測晶片可藉由一種稱作WLCSP之先進 封裝技術來完成封裝。在傳統的封裝技術中，係先將具 有如電子裝置、微機電裝置、或是光電裝置等微裝置的 晶圓切割成多個晶片之後，再將其封裝。而不同於傳統 的封裝方式，WLCSP技術中，微裝置的封裝係在晶圓切 割成多個晶片之前進行。WLCSP技術之所以可以製作影 像感測晶片是因為影像感測晶片的主動區位於影像感測 晶片接合至玻璃基板的一侧，而作為内連接的球栅陣列 (ball grid array，BGA )則設置於晶片的另一侧。 【發明内容】 0978-A32974TW/VISERA-2007-007/spin 6 200905869 本發明的目的在於改變支撐接 晶圓期間所產生的庫力 方式卜低切割 根據上述之二=0?而防止接墊發生剝離。 封裝結構，其包括：㈣於先4置之 妒晋曰η 卜逯明基板及一上透明基板、— 裝置日日片、锼數金屬線、及複數 透明基板鱼上读日日υ 衣置日日片位於下 介電層ϊί= ?’包括:-半導體基板及-接奸，“基板包裝置區及圍繞該裝置區的-DD "中接墊區包括複數凹口，苴分別、、儿菩$ f ^ 基板的邊緣排列。介電層位於半導體二 之間’且包括複數接墊形成於介電層内且 ： 凹口。金屬線設置於下透明基板的， 設置於金屬線的下方。才反勺下表面’而錫球分別 【實施方式】 太二兒明本發明之實施例。此說明之目的在於提供 X明=體概“並非用以侷限本發明的範圍。本發 日之保護Ιέ·®當視後附之中請專利範圍所界定者為準。χ 本發明係有關於一種用於光電裝置之封裝結構。。 圖^會示出具有複數光電裝置的半導體晶目_的平面 :意圖:在本實施例中，係利用WLCSp技術對晶圓⑽ 仃十裝H在完成光電裝置製作並沿著複數切割 kLl—及L2切割晶圓1〇〇以形成複光電裝置晶片忉如之 後’每-光電裝置晶片1QGa已封裝完畢。第Μ圖係繪 不出切割第1圖中晶圓之後用於光電裝置的封裝結構^ 0978-A32974TW/VISERA-2007-007/SP1. 7 200905869 局部平面示意圖。再者，第3 A及3B圖係分別繞示出沿 第2A圖中3A-3A’線及3B-3B’線的剖面示意圖。 请參照第3 A圖’封裝結構包括一下透明基板3 00、 一上透明基板310、以及位於下透明基板300與上透明基 板310之間的一光電裝置晶片1 〇〇a (如第2A圖所示）。 下透明基板300與上透明基板310可由玻璃、石英、或 其他透明材料所構成。 請參照第2B圖，光電裝置晶片l〇〇a (如第2A圖所 ( 示）包括一半導體基板200及形成於半導體基板200前 表面上的一介電層202。此處，”前表面”所指的是作為 主動區的表面（active surface )。在本實施例中，半導體 基板200可由矽或其他半導體材料所構成。半導體基板 200具有一裝置區200a，其中可具有不同元件’例如電 晶體、電阻、及其他習知的半導體元件。半導體基板200 亦可具有導電層、絕緣層或隔離結構。導電層通常為金 屬層，例如銅，常於半導體工業中使用於連接基板上或 基板内分離的裝置。為了簡化圖式，此處僅繪示出一平 整的半導體基板。 請參照第3A圖，半導體基板200上的介電層2〇2可 由氧化石夕或其他低介電常數（low k)材料所構成，例如 氟石夕玻璃（fluorinated silicate glass, FSG)、摻雜碳的乳 化物（carbon doped oxide )、含甲基的石夕酸鹽（methyl silsesquioxane, MSQ )、含氫的矽酸鹽（hydrogen silsesquioxane, HSQ )、或含氟的四乙基石夕燒（fluorine 0978-A32974TW/VISERA-2007-007/spin 8 200905869 tetra-ethyl-orthosilicate, FTEOS )。另外，在其他實施例 中，介電層202可由多重的介電層所構成。複數接墊204 嵌入於介電層202中。在本實施例中，每一接墊204可 由金屬所構成，例如銅或銘。再者，每一接墊204可具 有一延伸部204a，其電性連接至半導體基板200内部或 上方的裝置（未繪示）。通常接墊204係與形成於半導 體基板侧壁的部份的金屬線314作侧向接觸。然而，一 旦半導體基板200與金屬線314直接接觸的話，將會造 成短路。未了避免因半導體基板200與金屬線314直接 接觸所引發的短路情形，半導體基板200必須自介電層 202的邊緣往内縮，如第2B圖所示。 請參照第3A圖，半導體基板200經由一黏著材料 302而與下透明基板300接合。再者，黏著材料302進一 步填入由介電層202、内縮的半導體基板200及下透明基 板300所形成的空間。而填入上述空間的黏著材料3〇2 係作為半導體基板200與形成於半導體基板200側壁的 一部份的金屬線3 14之間的絕緣層，以避免裝置發生短 路0 一圍堰（dam) 304設置於介電層202與上透明基板 310之間，以在其間形成一空腔，而得以在空腔内對應於 裝置區200a的介電層202上設置一光電裝置206,例如 電荷耦合裝置（CCD)或CMOS影像感測陣列。圍堪3〇4 係經由黏著層306a及306b而分別與介電声202及上透 明基板310接合。 0978-A32974TW/VISERA-2007-007/spin 9 200905869 請參照第3A圖，複數緩衝層312設置於下透明基板 300的底表面且在其上對應覆蓋複數金屬線314。一保護 層316,例如一氮化矽層，係覆蓋金屬線314以及下透明 基板300的底表面。保護層3 16具有複數開口 316a對應 於緩衝層312而露出所對應的金屬線3 14。錫球318係對 應设置於保護層316的開口 316a内。 請參照第2A圖，在本實施例中，接墊2〇4自半導體 基板200邊緣突出，使接墊2〇4大體上由黏著材料3〇2 、 作為支樓，而非半導體基板2〇〇。通常黏著材料3〇2由低 機械強度的絕緣膠所構成。因此，當切割晶圓時，會產 生應力及振動，造成接墊204的剝離而降低裝置的可靠 度。 為了避免上述問題的產生，在此提供光電裝置的封 裝結構的另一實施例。第4A圖係繪示出一實施例之切割 第1圖中晶圓100之後用於光電裝置的封裝結構的局部 .平面示意圖。再者，第5A及5B圖係分別繪示出沿第4A 圖中5A-5A線及5B-5B’線的剖面示意圖。其中，第‘a、 5A及5B圖中與第2A、3A及3B圖中相同的部件係標示 相同的標號並省略其說明。在本實施例中，半導體^板 400包括一裝置區400a及圍繞裝置區4〇〇a的一接墊區 4〇〇b。特別的是接墊區400a具有複數凹口 4〇〇c，A分= 沿著半導體基板400的邊緣排列。請參照第5A圖了^數 的接墊204形成於介電層202 +且大體對準於各個凹口 400c。在半導體基板4〇〇與下透明基板3〇〇接合之後.， 0978-A32974TW/VISERA-2007-007/spin 1〇 200905869 黏著材料302填入於凹口 400c中，以作為半導體基板400 與形成於半導體基板400侧壁的一部份的金屬線314之 間的絕緣層，防止裝置發生短路。因此，形成於半導體 基板400側壁的金屬線314的寬度必須小於凹口 400c的 寬度。然而，在本實施例中，每一接墊204的寬度大體 大於凹口 400c，使接墊204不僅可利用黏著材料302作 為支撐，還可利用半導體基板400作為支撐。由於每一 凹口 400c兩侧的半導體基板400可提供優於低機械強度 的黏著材料302的支撐力，故可避免或改善切割晶圓100 期間發生接墊204剝離的情形。 根據本實施例之封裝結構，由於接墊204可同時以 黏著材料302及凹口 400c兩侧的半導體基板400作為支 撐，故可避免或改善接墊204發生剝離的情形，進而提 高裝置的可靠度。再者，填入於凹口 400c中的黏著材料 302可作為金屬線314與半導體基板400之間的絕緣層， 因此也可防止裝置發生短路的情形。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何所屬技術領域中具有通常知識者， 在不脫離本發明之精神和範圍内，當可作更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定 者為準。 0978-A32974TW/VISERA-2007-007/spin 11 200905869 【圖式簡單說明】 第1圖係繪示具有複數光電裝置的晶圓的平面示意 圖， 第2A圖係繪示出一實施例之切割第1圖中晶圓100 之後用於光電裝置的封裝結構的局部平面示意圖； 第2B圖係繪示出第2A圖中封裝結構中的半導體基 板的局部平面示意圖； 第3A圖係繪示出沿第2A圖中3A-3A’線的剖面示意 C 圖； 第3B圖係繪示出沿第2A圖中3B-3B’線的剖面示意 圖； 第4A圖係繪示出一實施例之切割第1圖中晶圓100 之後用於光電裝置的封裝結構的局部平面示意圖； 第4B圖係繪示出第4A圖中封裝結構中的半導體基 板的局部平面示意圖； 第5A圖係繪示出沿第4A圖中5A-5A’線的剖面示意 圖；以及 第5B圖係繪示出沿第4A圖中5B-5B’線的剖面示意 圖。 【主要元件符號說明】 100〜半導體晶圓； l〇〇a〜光電裝置晶片； 200、400〜半導體基板；200a、400a〜裝置區； 202〜介電層； 204〜接墊； 0978-A32974TWmSERA-2007-007/spin 12 200905869 204a〜延伸部； 300〜下透明基板； 304〜圍堰； 310〜上透明基板； 314〜金屬線； 316a〜開口； 400b〜接墊區； LI、L2〜切割道。 206〜光電裝置； 3 02〜黏者材料， 306a、306b〜黏著層 3 12〜緩衝層； 3 16〜保護層； 318〜錫球； 400c〜凹口； / k 0978-A32974TWmSERA-2007-007/spin 13BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package technology, and more particularly to a wafer-level chip scale package (WLCSP) structure suitable for an optoelectronic device. [Prior Art] Digital imaging devices are widely used in digital cameras, digital image recorders, mobile phones with image capture functions, and monitors. Digital image sensors typically include an optoelectronic device wafer, such as a charge-coupled device (CCD) image sensing chip and a CMOS image sensing wafer. The digital image sensor converts a portion of the optical image into an electrical signal. The electronic signal is used to reproduce the optical image on a display. The image sensing wafer described above can be packaged by an advanced packaging technique called WLCSP. In the conventional packaging technology, a wafer having a micro device such as an electronic device, a microelectromechanical device, or an optoelectronic device is first diced into a plurality of wafers, and then packaged. Unlike the traditional packaging method, in the WLCSP technology, the package of the micro device is performed before the wafer is cut into a plurality of wafers. The WLCSP technology can make an image sensing wafer because the active area of the image sensing wafer is located on the side of the image sensing wafer bonded to the glass substrate, and the ball grid array (BGA) as an inner connection is disposed on The other side of the wafer. SUMMARY OF THE INVENTION 0978-A32974TW/VISERA-2007-007/spin 6 200905869 The purpose of the present invention is to change the mode of the force generated during the support of the wafer. The low-cutting prevents the pads from being peeled off according to the above two=0. . The package structure includes: (4) the first 4 sets of the 妒 曰 曰 逯 逯 逯 基板 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 及 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板The film is located in the lower dielectric layer ϊί= ?' includes: - the semiconductor substrate and - the smuggling, "the substrate package device area and the -DD " middle pad area surrounding the device area includes a plurality of notches, 苴, 儿The edge of the substrate is arranged. The dielectric layer is located between the semiconductors and includes a plurality of pads formed in the dielectric layer and: a recess. The metal lines are disposed on the lower transparent substrate and disposed under the metal lines. The second surface of the present invention is the same as the embodiment of the present invention. The purpose of this description is to provide a definition of the present invention. The protection of this date is determined by the scope of the patent. χ The present invention relates to a package structure for an optoelectronic device. . The figure will show the plane of the semiconductor crystallite with a complex optoelectronic device: In this embodiment, the wafer (10) is mounted on the wafer by the WLCSp technique, and the fabrication of the photovoltaic device is completed and the kL1 is cut along the complex— L2 dicing the wafer 1 〇〇 to form a complex optoelectronic device wafer, for example, after the 'every-optoelectronic device wafer 1QGa has been packaged. The second drawing shows the package structure for the photovoltaic device after cutting the wafer in Fig. 1 ^ 0978-A32974TW/VISERA-2007-007/SP1. 7 200905869 Partial plan view. Further, the 3A and 3B drawings are respectively shown in cross-sectional views along the 3A-3A' line and the 3B-3B' line in Fig. 2A. Referring to FIG. 3A, the package structure includes a transparent substrate 300, an upper transparent substrate 310, and an optoelectronic device wafer 1 〇〇a between the lower transparent substrate 300 and the upper transparent substrate 310 (as shown in FIG. 2A). Show). The lower transparent substrate 300 and the upper transparent substrate 310 may be composed of glass, quartz, or other transparent material. Referring to FIG. 2B, the photovoltaic device wafer 10a (shown in FIG. 2A includes a semiconductor substrate 200 and a dielectric layer 202 formed on the front surface of the semiconductor substrate 200. Here, the "front surface" Referring to the active surface as the active region, in the present embodiment, the semiconductor substrate 200 may be composed of germanium or other semiconductor material. The semiconductor substrate 200 has a device region 200a in which different elements such as a transistor may be present. , a resistor, and other conventional semiconductor components. The semiconductor substrate 200 may also have a conductive layer, an insulating layer or an isolation structure. The conductive layer is usually a metal layer, such as copper, which is often used in the semiconductor industry for connection on a substrate or in a substrate. In order to simplify the drawing, only a flat semiconductor substrate is shown here. Referring to FIG. 3A, the dielectric layer 2〇2 on the semiconductor substrate 200 may be made of oxidized oxide or other low dielectric constant (low k) a material composed of, for example, fluorinated silicate glass (FSG), carbon doped oxide, methyl-containing sulphate (methyl) Silsesquioxane, MSQ), hydrogen silsesquioxane (HSQ), or fluorine-containing tetraethyl sulphate (fluorine 0978-A32974TW/VISERA-2007-007/spin 8 200905869 tetra-ethyl-orthosilicate, FTEOS ) In addition, in other embodiments, the dielectric layer 202 may be composed of multiple dielectric layers. The plurality of pads 204 are embedded in the dielectric layer 202. In this embodiment, each of the pads 204 may be made of metal. For example, each of the pads 204 may have an extension portion 204a electrically connected to a device (not shown) inside or above the semiconductor substrate 200. Typically, the pads 204 are formed on the side of the semiconductor substrate. The metal wire 314 of the portion of the wall is in lateral contact. However, once the semiconductor substrate 200 is in direct contact with the metal wire 314, a short circuit will occur. The short circuit caused by the direct contact of the semiconductor substrate 200 with the metal wire 314 is not avoided. The semiconductor substrate 200 must be retracted from the edge of the dielectric layer 202 as shown in Fig. 2B. Referring to Fig. 3A, the semiconductor substrate 200 is bonded to the lower transparent substrate 300 via an adhesive material 302. The adhesive material 302 is further filled in a space formed by the dielectric layer 202, the retracted semiconductor substrate 200, and the lower transparent substrate 300. The adhesive material 3〇2 filled in the space is formed as the semiconductor substrate 200 and formed on the semiconductor substrate 200. An insulating layer between a portion of the sidewalls of the metal lines 314 to prevent shorting of the device. A dam 304 is disposed between the dielectric layer 202 and the upper transparent substrate 310 to form a cavity therebetween. An optoelectronic device 206, such as a charge coupled device (CCD) or CMOS image sensing array, is disposed on the dielectric layer 202 corresponding to the device region 200a in the cavity. The squeegee is bonded to the dielectric sound 202 and the upper transparent substrate 310 via the adhesive layers 306a and 306b, respectively. 0978-A32974TW/VISERA-2007-007/spin 9 200905869 Referring to FIG. 3A, a plurality of buffer layers 312 are disposed on the bottom surface of the lower transparent substrate 300 and correspondingly cover the plurality of metal lines 314 thereon. A protective layer 316, such as a tantalum nitride layer, covers the metal lines 314 and the bottom surface of the lower transparent substrate 300. The protective layer 3 16 has a plurality of openings 316a corresponding to the buffer layer 312 to expose the corresponding metal lines 314. The solder balls 318 are disposed in the openings 316a of the protective layer 316. Referring to FIG. 2A, in the embodiment, the pads 2〇4 protrude from the edge of the semiconductor substrate 200, so that the pads 2〇4 are substantially composed of the adhesive material 3〇2 as a branch instead of the semiconductor substrate 2〇〇. . Usually, the adhesive material 3〇2 is composed of a low mechanical strength insulating paste. Therefore, when the wafer is diced, stress and vibration are generated, causing peeling of the pad 204 to lower the reliability of the device. In order to avoid the above problems, another embodiment of the package structure of the photovoltaic device is provided herein. Fig. 4A is a partial plan view showing the package structure for the photovoltaic device after the wafer 100 of Fig. 1 is cut. Further, the 5A and 5B drawings are schematic cross-sectional views taken along lines 5A-5A and 5B-5B' in Fig. 4A, respectively. Here, the same components as those in the drawings 2A, 3A, and 3B are denoted by the same reference numerals and the description thereof will be omitted. In the present embodiment, the semiconductor board 400 includes a device area 400a and a pad area 4〇〇b surrounding the device area 4〇〇a. In particular, the pad region 400a has a plurality of recesses 4〇〇c, which are arranged along the edge of the semiconductor substrate 400. Referring to Figure 5A, the pads 204 are formed on the dielectric layer 202+ and are generally aligned with the respective recesses 400c. After the semiconductor substrate 4 is bonded to the lower transparent substrate 3, 0978-A32974TW/VISERA-2007-007/spin 1〇200905869, the adhesive material 302 is filled in the recess 400c to be formed as the semiconductor substrate 400. An insulating layer between a portion of the metal lines 314 on the sidewalls of the semiconductor substrate 400 prevents shorting of the device. Therefore, the width of the metal line 314 formed on the side wall of the semiconductor substrate 400 must be smaller than the width of the recess 400c. However, in the present embodiment, the width of each of the pads 204 is substantially larger than the notches 400c, so that the pads 204 can be supported not only by the adhesive material 302 but also by the semiconductor substrate 400. Since the semiconductor substrate 400 on both sides of each of the notches 400c can provide a supporting force superior to the low mechanical strength of the adhesive material 302, the peeling of the pads 204 during the cutting of the wafer 100 can be avoided or improved. According to the package structure of the embodiment, since the pad 204 can be supported by the semiconductor substrate 400 on both sides of the adhesive material 302 and the recess 400c at the same time, the peeling of the pad 204 can be avoided or improved, thereby improving the reliability of the device. . Further, the adhesive material 302 filled in the recess 400c can serve as an insulating layer between the metal wire 314 and the semiconductor substrate 400, so that the device can be prevented from being short-circuited. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. 0978-A32974TW/VISERA-2007-007/spin 11 200905869 [Simplified Schematic] FIG. 1 is a plan view showing a wafer having a plurality of photovoltaic devices, and FIG. 2A is a view showing a first embodiment of cutting. FIG. 2B is a partial plan view showing the semiconductor substrate in the package structure in FIG. 2A; FIG. 3A is a partial plan view showing the semiconductor substrate in the package structure in FIG. 2A; 3A-3A' is a cross-sectional view showing a C-graph; FIG. 3B is a cross-sectional view taken along line 3B-3B' in FIG. 2A; and FIG. 4A is a cross-sectional view showing an embodiment of the cutting in FIG. A partial plan view of the package structure for the photovoltaic device after the wafer 100; FIG. 4B is a partial plan view showing the semiconductor substrate in the package structure of FIG. 4A; FIG. 5A is a view along line 4A A schematic cross-sectional view of the 5A-5A' line; and a 5B drawing is a cross-sectional view taken along line 5B-5B' of Fig. 4A. [Main component symbol description] 100~ semiconductor wafer; l〇〇a~ optoelectronic device wafer; 200, 400~ semiconductor substrate; 200a, 400a~ device area; 202~ dielectric layer; 204~ pad; 0978-A32974TWmSERA- 2007-007/spin 12 200905869 204a~ extension; 300~ lower transparent substrate; 304~ cofferdam; 310~ upper transparent substrate; 314~ metal wire; 316a~ opening; 400b~ pad area; LI, L2~ cutting path . 206~photoelectric device; 3 02~ adhesive material, 306a, 306b~ adhesive layer 3 12~buffer layer; 3 16~protective layer; 318~ solder ball; 400c~ notch; /k 0978-A32974TWmSERA-2007-007/ Spin 13