200905844 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種主動電路上方測試墊(probing 〇ver active area ’ POAA pad)之群組設置，尤指一種可用於多重 針測（multi-probe)之位於主動電路上方測試墊之群組設置。 【先前技術】 在半導體產業中，一積體電路(integratedcircuit，以下 簡稱為1C)產品的產生首先係經過電路佈局設計，之後進入 半導體廠進行半導體製程以及積體電路的製作，待完成晶 圓之製作後’則係利用-測試探針(testingpiObe)或探針卡 (probing card)接觸焊墊以進行多重針測（multi pr〇be)。惟測 試良好或經修復過之晶 >；會於切割後進行後續接線 (bonding)以及封裝（packaging)等步驟；而即使已完成封裝 的曰曰片最後仍須一最終測試(final testing)以確認、良品工c。 晶圓之測試乃是使用探針卡接觸焊墊進行電性測試，以 探測該焊墊及其内部電路。而為了提昇並確保晶片的整體 效此4等¥塾於晶片製作完成後會在經過多次測試。此 外為了禮保探針此快速並準確地接觸到焊塾觸塾，探針 也曰夕-人與;^塾進行接觸，使烊墊表面產生刮痕(p蝴％ mark)或者凹凸不平的凹洞(dem)等傷害，甚至於焊塾的表 面❿成破壞f生的抽壞’例如產生破洞。由於焊墊除用以作 200905844 =:式步驟的測試點外，更重要的是用以作為—晶片與其 件間連接的蠕點。而此已被損傷的焊墊將不利於後續 a (bu^iping)或打線b〇nding)等接線及封裝生產過 而=錢率下降。另外，在晶#封裝完畢進行最終測 I 針係可切墊已形錢線或6塊後使進行測試， θ況下探針尖端亦容亦造成凸塊損傷或刮痕，影響凸 塊的可靠度。 因此’熟$該項技藝者係提出許多解決方法，如第1圖 =之設置有測試墊之封裝結構之示意圖，該封裝結構係 ;曰曰片100上„又置有複數個焊塾1〇2，與一覆蓋焊塾撤 之保Π蔓層1〇4 ’每—焊塾102上方之保護層104係具有兩 個開口’其中一個開口用以形成凸塊106;而另一個開口 、】暴4出心焊墊1〇2並作為—單—測試塾1Q8。另外請 二閱第2圖’《2圖亦為一設置有測試墊之封裝結構之示 意圖。如第2圖所示’封裝結構係利用一自焊墊1〇2連接 出來的重置層（滅軸咖—，脈)11〇，並於重置層 則上分別設置凸塊i 〇 6與單一測試塾i 〇 8。因此進行測^式 步驟時，探針係可針對焊墊收m具有之測試墊⑽進行 測試’而具有實際電性連接功能之凸塊⑽則免於在測試 步驟時受到任何因探針所造成之損壞。 如前所述，測試塾108亦會經過多重針測，以確 1〇0的整體效能，然而此單—測試墊⑽之設置在如系統 200905844 晶片（system-on-chip，SOC)等需要更複雜、更多次的多重 針測中漸漸地不敷使用。另外值得注意的是，近年來伴隨 著高積集度0· 18微米以下的深次微米（deep sub-micro)半導 體製程的進步，銅雙鑲嵌(dual damascene)技術搭配低介電 常數(low-K)材料、超低介電常數(ultra low-K，ULK)、或多 孔性低介電常數(porous low-k)材料所構成的金屬層間介 電（inter metal dielectric ’以下簡稱為IMD)層已成為目前最 受矚目的金屬内連線技術。Low-K材料、ULK材料或多孔 性low-K材料係具有較為脆裂（fragiie)的特質，因此建構在 此IMD層上的焊墊與其相對的單一測試墊在經過多重測試 後，容易使下方IM D層因重複受到探針針壓而造成崩塌或 毀壞，影響1C的整體效能。200905844 IX. Description of the Invention: [Technical Field] The present invention relates to a group setting of a probing 〇ver active area 'POAA pad, especially one that can be used for multiple needle testing (multi- Probe) is a group setting of the test pads above the active circuit. [Prior Art] In the semiconductor industry, the production of an integrated circuit (hereinafter referred to as 1C) is first designed through circuit layout, and then enters the semiconductor factory for semiconductor process and integrated circuit fabrication. After fabrication, the test pads are probed with a test probe or a probing card for multi-needle testing. However, a well-tested or repaired crystal will perform subsequent bonding and packaging steps after cutting; even if the finished wafer is finally finalized, a final testing is required. Confirmation, good work c. Wafer testing is performed using a probe card contact pad for electrical testing to detect the pad and its internal circuitry. In order to improve and ensure the overall effect of the wafer, it will be tested several times after the wafer is completed. In addition, in order to quickly and accurately contact the soldering contact, the probe is also in contact with the person, and the surface of the mattress is scratched or scratched. Damage such as holes (dem), even the surface of the weld bead is destroyed by the destruction of the raw 'for example, creating a hole. Since the pad is used as a test point for the 200905844 =: step, it is more important to use it as a creep point for the connection between the wafer and its parts. The damaged pad will not be conducive to the subsequent a (bu^iping) or wire b〇nding) wiring and packaging production = the money rate is reduced. In addition, after the final packaging of the crystal #I can be tested, the needle can be cut into the shape of the money line or 6 pieces. The tip of the probe can also cause bump damage or scratches under the condition of θ, which affects the reliability of the bump. degree. Therefore, the skilled person proposed a number of solutions, such as the first figure = a schematic diagram of the package structure provided with the test pad, the package structure is; the cymbal 100 is placed with a plurality of solder plaques. 2, with a cover weld removed the protective layer 1 '4' each of the protective layer 104 above the soldering station 102 has two openings 'one opening to form the bump 106; and the other opening, the storm 4 Out of the core pad 1〇2 and as a - single - test 塾 1Q8. Please also read Figure 2 '2" is also a schematic diagram of a package structure with a test pad. As shown in Figure 2 'package structure The reset layer (off-axis coffee-, pulse) connected by a solder pad 1〇2 is 11〇, and the bump i 〇6 and the single test 塾i 〇8 are respectively disposed on the reset layer. In the test step, the probe can be tested for the test pad (10) of the pad, and the bump (10) having the actual electrical connection function is protected from any damage caused by the probe during the test step. As mentioned earlier, the test 塾108 will also undergo multiple needle tests to determine the overall performance of 1〇0, however this The single-test pad (10) is gradually inferior in multiple-needle tests such as system-on-chip (SOC), which requires more complicated and more times. It is also worth noting that in recent years Advances in deep sub-micro semiconductor processes with a high degree of integration below 0·18 microns, dual damascene technology with low dielectric constant (low-K) materials, ultra low dielectric constant ( Inter low-k, ULK or porous low-k material Line technology. Low-K material, ULK material or porous low-K material has a more fragile character, so the solder pad constructed on this IMD layer and its single test pad are subjected to multiple tests. It is easy to cause the lower IM D layer to collapse or be destroyed due to repeated probe pin pressure, affecting the overall performance of 1C.
因此，如何能提供一可承受多重測試並減輕其下方IMD 層所承受之針壓的焊塾與測試塾設置，係成為—值得關注 的議題。 【發明内容】 故本發明於此提供-種主動電路上方剛試塾㈣bing over active area，POAA pad)之群組設置 从提供一可承受 多重測試並減輕其下方金屬層間介電層所承受之針壓的列 試墊群組設置。 種主動電路上方 根據本發明之申請專利範圍，係提供〜 200905844 測試墊(POAA pad)之群組設置’該P〇AA測試塾之群組設 置包含有一晶片’該晶片上設置有一組焊墊(b〇nding pads)、至少一第一組測試墊以及一第二組測試塾，該第一 組測試墊與該第二組測試墊係分別電連接該組焊墊，且呈 對角線錯位設置。 根據本發明之申請專利範圍，另提供一種主動電路上方 之測試墊(POAApad)群組設置’該P0AA測試墊之群組設 置包含有一晶片，該晶片上設置有一組焊塾(b〇nding pads)、至少一第一組測試墊以及一第二組測試墊，該第一 組測試墊與該第二組測試墊係分別電連接該組焊墊，且呈 垂直或水平錯位設置。 本發明所提供之P〇AA測試墊之群組設置係藉由一分 組叹置之觀念來進行該第一組測試墊與該第二組測試墊之 、品別且4第-組測試墊與該第二組測試墊之設置係採水 平垂直、或對角線之錯位設置。因此每一焊墊具有至少 :組與其相對應的賴紐供制功能，故每個測試塾所 :承受之針測次數係可降低，而得以減輕其下方咖 承受之針壓。 【實施方式】 ^㈣第3 ®與第4圖’帛3圖係為本發明所提供之主 動电路上方職墊之群組Μ之—第—較佳實施例之示意 200905844 圖；而第4圖則為第3圖所示之POAA測試墊群組設置之 部分放大示意圖。如第3圖所示’本較佳實施例所提供之 主動電路上方測試墊(probing POAA pad)之群組設置，包含 有一晶片200 ’晶片200上設置有一組焊塾(bonding pads) 202 ’用以提供該晶片對外之電性連接。而此電性連接則可 藉由打線連接(wire bonding)或凸塊連接(bumping)所提 供。晶片200上另設置有至少一第一組測試墊204以及一 第二組測試墊206 ’用以提供針測功能。第一組測試塾204 之各焊墊與第二組測試墊206之各焊墊係分別電連接至一 相對應之焊墊202。如第4圖所示，第一組測試墊204a與 第二組測試塾206a係分別電連接至向對應之焊墊202a。同 理’第一組測試墊204b與第二組測試墊206b係分別電連 接至相對應之焊墊202b，以此類推。此外，第一組測試墊 204與第二組測試墊206係呈對角線錯位設置。如第4圖 所示，第一組測試墊204a與第二組測試墊206a係呈對角 線錯位設置，且與焊墊202a亦呈對角線設置。當然，焊墊 202a並不為第4圖所繪示者所限，即焊墊2〇2a之位置係可 獨立於第一組測試墊204a與第二組測試墊206b之對角線 錯位設置之外。 如第4圖所示’第一組測試墊204之組内各測試墊 204a、204b、204c等彼此之相對位置係同於第二組測試墊 206之組内各測試塾206a、206b、206c等彼此之相對位置， 200905844 亦即各組測試墊之組内各測試墊彼此之相對位置係相對應 於探針卡(probe card)之各測試探針(testing pr〇be)的相對位 置。根據此設置方式，第一組測試墊2〇4與第二組測試墊 2〇6所提供之針測功能係可利用—同一探針卡(pr〇be card) 進行；而此針測功能係可提供相同或不同功能之晶圓針測 (c/p test)。Therefore, how to provide a solder and test set that can withstand multiple tests and reduce the acupressure pressure underneath the IMD layer becomes a topic of concern. SUMMARY OF THE INVENTION Accordingly, the present invention provides a group arrangement of a bing over active area (POAA pad) provided above from the provision of a test capable of withstanding multiple tests and mitigating the pin of the dielectric layer between the underlying metal layers. Pressed column test pad group settings. Above the active circuit, according to the patent application scope of the present invention, a group setting of ~200905844 test pad (POAA pad) is provided. The group setting of the P〇AA test chip includes a wafer on which a set of pads are disposed ( The second set of test pads and the second set of test pads are electrically connected to the set of pads, respectively, and are diagonally offset. . According to the patent application scope of the present invention, there is further provided a test pad (POAApad) group setting above the active circuit. The group setting of the P0AA test pad includes a wafer on which a set of soldering pads (b〇nding pads) is disposed. At least a first set of test pads and a second set of test pads, the first set of test pads and the second set of test pads are electrically connected to the set of pads, respectively, and arranged in a vertical or horizontal offset. The group setting of the P〇AA test pad provided by the present invention performs the first set of test pads and the second set of test pads, and the 4th set of test pads and the set by the concept of grouping and staking The setting of the second set of test pads is set horizontally or diagonally. Therefore, each pad has at least a group corresponding to the function of the lining, so that each test : can reduce the number of needles that can be taken, and can reduce the needle pressure underneath. [Embodiment] ^ (4) The 3th and 4th drawings '3' are the group of the active circuit above the present invention provided by the present invention - the schematic diagram of the preferred embodiment of the structure of the structure of the second embodiment of the present invention; This is a partial enlarged view of the POAA test pad group setup shown in Figure 3. As shown in FIG. 3, the group arrangement of the probing POAA pads provided in the preferred embodiment includes a wafer 200. The wafer 200 is provided with a set of bonding pads 202'. To provide external electrical connection of the wafer. This electrical connection can be provided by wire bonding or bumping. The wafer 200 is further provided with at least one first set of test pads 204 and a second set of test pads 206' for providing a needle test function. Each of the pads of the first set of test pads 204 and the pads of the second set of test pads 206 are electrically coupled to a corresponding pad 202, respectively. As shown in Fig. 4, the first set of test pads 204a and the second set of test pads 206a are electrically connected to the corresponding pads 202a, respectively. Similarly, the first set of test pads 204b and the second set of test pads 206b are electrically connected to the corresponding pads 202b, respectively, and so on. In addition, the first set of test pads 204 and the second set of test pads 206 are diagonally offset. As shown in Fig. 4, the first set of test pads 204a and the second set of test pads 206a are diagonally offset and disposed diagonally with the pads 202a. Of course, the pad 202a is not limited to the one shown in FIG. 4, that is, the position of the pad 2〇2a can be set independently of the diagonal misalignment between the first set of test pads 204a and the second set of test pads 206b. outer. As shown in FIG. 4, the relative positions of the test pads 204a, 204b, 204c, etc. in the group of the first set of test pads 204 are the same as the test bars 206a, 206b, 206c, etc. in the group of the second set of test pads 206. Relative position to each other, 200905844, that is, the relative positions of the test pads in each group of test pads correspond to the relative positions of the test probes of the probe card. According to this arrangement, the needle testing functions provided by the first set of test pads 2〇4 and the second set of test pads 2〇6 can be performed using the same probe card (pr〇be card); Wafer needles (c/p test) with the same or different functions are available.
值侍庄思的疋，由於晶圓針測係進行於半導體製程中之 各階段，且為確保探針能快速並準確地接觸到測試墊，探 針也會多次與接觸墊進行接觸，使焊墊表面產生刮痕或者 凹凸不平的凹洞等傷害。所以，當第―組測試墊謝已進 行了多次的針測步驟，且考量到第一組測試墊2〇4下方的 金屬層間介電（inter metal dielectric，以下簡稱為IMD)層因 重複文到騎針壓而造成崩塌或毁壞，即可將該探針卡位 移-間距(pheh)，而於第二組測触繼續進行針測步 驟。也就是說，根據本較佳實施例所提供<p〇AA 之群組設置，係藉由此一分組錯位之設置方式，使每二焊 藝202可藉由第-組測試墊2〇4與第二組測試塾2〇6在使 用同-探針卡之前提下，進行不同功能或相功能之針測步 顿’以進行測試’故第—組測試塾204第二組測試塾2〇6 所需承受之針測次數係可降低’因而減輕其下方細層所 承受之針壓。 另外，由於近年來伴隨著高積集度Μ 8微米以下的深次 200905844 微米（deepsub-micro)半導體製程的進步，銅雙鑲嵌(dual damascene)技術搭配低介電常數〇〇w部才料、超低介電常 數(ULK)、或多孔性低介電常數材料所構成的細層已成 為目前最受矚目的金屬内連線技術。而該等介電材料係罝 有較為脆裂的特質’因此本第—較佳實施例所提供之' POAA測齡之群組設置，係可藉由分散賴墊所承受之 針測次數，降似m塾WIMD祕重毅到之探針針 壓’更可避免IMD層於針測步驟中造成崩塌。此外，隨著 半導體製程的進步，當晶片2⑼所需之針測步驟次數更加 增時，係可根據此一對角線錯位之設置方式，提供較單一 測試整多的測試空間；或可依此原則更另行設置其他組的 測試墊，以於保護測試墊下方IMD層之前提下，提供更多 的測試空間。 請參閱第5圖與第6圖’第5圖與第6圖係為本發明所 提供之主動電路上方測試墊之群組設置之一第二較佳實施 例之部分放大示意圖。如第5圖與第6圖所示，本較佳實 施例所提供之POAA測試墊之群組設置，包含有一晶片 200，晶片200上設置有一組焊墊2〇2 ,用以提供該晶片對 外之電性連接。而此電性連接則可藉由打線連接或凸塊連 接所提供。晶片200上另設置有至少一第一組測試墊2〇4 以及一第二組測試墊206，用以提供針測功能。第一組測 試墊204與第二組測試墊206係分別電連接至對應之焊墊 200905844 202。例如，第一組測試墊204a與第二組測試墊206a係電 連接至焊塾202a ;而第一組測試墊204b與第二組測試墊 206b係電連接至焊墊202b，以此類推。此外，如第5圖所 示’第一組測試墊204與第二組測試墊206係呈水平錯位 設置；而如第6圖所示’第一組測試墊204與第二組測試 墊206係呈垂直錯位設置。 凊繼續參閱第5圖與第6圖。第一組測試墊204之組内 各測试墊204a、2〇4b、204c等彼此之相對位置係同於第二 組測試墊206之組内各測試墊2〇6a、2〇6b、2〇6c等彼此之 相對位置。根據此設置方式，第一組測試墊2〇4與第二組 測試墊206所提供之針測功能係可利用一同一探針卡進 行；而此針測魏係可提供相同或不同功能之晶圓針測。 值知'主思的疋，由於晶圓針測係進行於半導體製程中之 各1^又’且為確保探針能快速並準確地接制測試墊，探 針也會多次與接觸墊進行接觸，使焊絲面產生舰或者 凹凸不平的凹洞等傷害。所以，當第-組測試墊204已進 订了多次的針測步驟’且考量到第一組測試墊綱下方的 二因重複受到探針針壓而造成崩塌或毀壞，即可將該 株針卡位移一間距， ;弟—組測試墊206繼續進行針測 歩驟。也就是說，根攄According to the value of Shi Zhuangsi, since the wafer inspection system is carried out in various stages in the semiconductor manufacturing process, and in order to ensure that the probe can quickly and accurately contact the test pad, the probe also contacts the contact pad multiple times, so that Scratches or bumps on the surface of the pad cause damage. Therefore, when the first group test pad has been subjected to multiple pin testing steps, and considering the inter-metal dielectric (hereinafter referred to as IMD) layer under the first group of test pads 2〇4, due to duplicate text The probe card can be displaced-pitched (pheh) by the pin pressure and collapsed or destroyed, and the second set of probes continues the needle testing step. That is to say, the group setting of <p〇AA provided according to the preferred embodiment is such that each of the two soldering techniques 202 can be used by the first group of test pads 2〇4 by means of the setting of the group misalignment. With the second set of tests 塾2〇6 before using the same-probe card, perform different functions or phase functions for the needle test 'to test', so the first group test 塾204 second group test 塾 2〇 6 The number of needle measurements required to be taken can be reduced to reduce the needle pressure on the underlying fine layer. In addition, due to the recent advancement of the deep sub-micron semiconductor process with high integration Μ 8 microns or less, the dual damascene technology is combined with the low dielectric constant 〇〇w. Thin layers composed of ultra-low dielectric constant (ULK) or porous low dielectric constant materials have become the most attractive metal interconnect technology. The dielectric materials are more fragile. Therefore, the group setting of the POAA age measurement provided in the first preferred embodiment can be reduced by the number of needles received by the dispersed mat. It is better to avoid the collapse of the IMD layer in the needle testing step. In addition, as the semiconductor process progresses, when the number of pinning steps required for the chip 2 (9) is further increased, the test space of the single diagonal line can be provided to provide a test space that is more than a single test; or The principle further sets up other sets of test pads to provide more test space before protecting the IMD layer below the test pad. Please refer to FIG. 5 and FIG. 6 'Fig. 5 and Fig. 6 are partial enlarged views of a second preferred embodiment of a group arrangement of test pads above the active circuit provided by the present invention. As shown in FIG. 5 and FIG. 6, the group arrangement of the POAA test pads provided by the preferred embodiment includes a wafer 200 on which a set of pads 2〇2 is disposed to provide the wafer. Electrical connection. This electrical connection can be provided by a wire connection or a bump connection. The wafer 200 is further provided with at least one first set of test pads 2〇4 and a second set of test pads 206 for providing a needle test function. The first set of test pads 204 and the second set of test pads 206 are electrically connected to corresponding pads 200905844 202, respectively. For example, the first set of test pads 204a and the second set of test pads 206a are electrically connected to the pad 202a; and the first set of test pads 204b and the second set of test pads 206b are electrically connected to the pads 202b, and so on. In addition, as shown in FIG. 5, 'the first set of test pads 204 and the second set of test pads 206 are horizontally offset; and as shown in FIG. 6 'the first set of test pads 204 and the second set of test pads 206 are Vertical offset setting.凊 Continue to see Figures 5 and 6. The relative positions of the test pads 204a, 2〇4b, 204c, etc. in the group of the first set of test pads 204 are the same as the test pads 2〇6a, 2〇6b, 2〇 in the group of the second set of test pads 206. 6c and so on relative to each other. According to this arrangement, the needle testing function provided by the first group of test pads 2〇4 and the second group of test pads 206 can be performed by using the same probe card; and the needle system can provide the same or different functions. Round needle test. The value is known as the main idea, because the wafer needle measurement system is performed in the semiconductor process and the probe is used to ensure that the probe can quickly and accurately connect the test pad. Contact, so that the wire surface produces damage to the ship or uneven cavities. Therefore, when the first set of test pads 204 has been ordered multiple times of the needle testing step' and the two of the first set of test pads are considered to be collapsed or destroyed due to the probe needle pressure, the strain can be The needle card is displaced by a distance, and the set of test pads 206 continues to perform the needle test step. In other words, roots
^ 康本第一車父佳實施例所提供之POAA 且設置，係藉由此-分組錯位之設置方式，使 可精由第一組測試塾204與第二組測試塾206 200905844 係τ利用同振針卡提供不同或相同的針測功能，以進行 測試。且測試墊2〇4、206所需承受之針測次數係可降低， 因而減輕其下方IMD層所承受之針壓。此外，隨著半導體 製程的進步，當晶片200所需之針測步驟次數更加增時， 係可根據此一水平或垂直錯位之設置方式，提供較單一測 ό式墊多的測試空間；或可依此原則更另行設置其他組的測 試墊，以於保護測試墊下方IMD層之前提下，提供更多的 測試空間。 接下來請參閱第7圖與第8圖，第7圖與第8圖係為第 4圖中沿208虛線之剖面示意圖。如第7圖所示，晶片2〇〇 上設置有一組焊墊202，用以提供晶片2〇〇對外之電性連 接’如本第-較佳實施例所提供，該電性連接係由一凸塊 連接所提供。晶片2 0 0上另設置有至少一第一組測試墊2 〇 4 以及一第二組測試墊206 ’用以提供針測功能。且第一組 測4墊204與第二組測試墊2〇6係暴露於一保護層2⑺ 中。值得注意的是，焊墊202、第一組測試墊2〇4與第二 組測試整206下方係設置有複數層励層212。如前所述， 由於近年來伴隨著高積集度〇18微米以下的深次微米 (deep sub-micro)半導體製程的進步，銅雙鑲嵌 damascene)技術搭配低介電常數〇〇w_K)材料、超低介電常 數(ULK)、或多孔性低介電常數材料所構成的漏層已成 為目前最受矚目的金屬内連線技術。而該等材料係具有較 13 200905844 為跪裂的特質’因此本發明提供之pQAA測試墊之群組設 置，係可藉由分散測試塾所承受之針測次數，降低測試整 下方IMD層所重複㈣之探針㈣，更可避免IMD層於 針測步驟中造成崩塌。 另外，本發明所提供之P〇AA測試墊之群組設置係可如 第8圖所示，藉由一導線，例如一重佈層（redistHbuted layer ’ RDL) 220電性連接焊墊2〇2、第一組測試墊2〇4、 以及第二組測試墊206,以調整焊墊2〇2、第一組測試墊 204、以及第二組測試墊206的位置，進而更提升元件的穩 定性。值得注意的是’根據第7圖與第8圖所示，第一組 測試墊204、第一組測試墊206係為藉由一圖案化之保護 層210暴露於一金屬墊214上之主動電路上方測試墊，因 此分組增設的測試墊並不會佔用晶片200的面積。 綜上所述，本發明所提供之ΡΟΑΛ測試墊之群組設置係 藉由一分組設置之觀念來進行該第一組測試墊與該第二組 測試墊之區別，且5亥第一組測試整與該第二组測試塾之設 置係採水爭、垂直、或對角線之錯位設置。因此每一焊墊 具有至少雨’组與其相對應的測試墊提供針測功能，除可提 升晶片針測次數外，每個測試墊所需承受之針測次數亦可 降低，而得以減輕其下方IMD層所承受之針壓。此外，藉 由此分組設置測5式墊之方法，當晶片所需之針測步驟次數 更加增時，係可根據此一錯位之設置方式，另行設置其他 14 200905844 組的測㈣’⑽倾觀墊下方細狀前提下，提供 更多的測4空間’而更符合未來半導體製程之要求。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利$&圍所做之均等變化與師，㈣屬本發明之涵蓋範 圍。 【圖式簡單說明】 第1圖與第2圖係為—設置有測試塾之封裝結構之示意圖。 第3圖係為本發明所提供之主動電路上方測試墊之群組設 置之一第一較佳實施例之示意圖。 第4圖為第3圖所示之p〇AA測試墊群組設置之部分放大 不意圖。 第5圖與第6圖係為本發明所提供之p〇AA測試墊之群組 δ又置之一第二較佳實施例之部分放大示意圖。 第7圖與第8圖係為第4圖中沿208虛線之剖面示意圖。 【主要元件符號說明】 1〇〇 晶片 102 焊墊 104 保護層 106 凸塊 108 測試墊 no 重置層 200 晶片 202、202a、202b、202c 焊墊 15 200905844 204、204a、204b、204c 206、206a、206b、206c 208 虛線 212 金屬層間介電層 220 重置層 第一組測試墊 第二組測試墊 210 保護層 214 金屬墊 16^ The POAA and the settings provided by the first embodiment of Kangben's first car are set by means of this - group misalignment, so that the fineness can be utilized by the first set of test 塾 204 and the second set of test 塾 206 200905844 τ The vibrating pin card provides different or the same pinning function for testing. Moreover, the number of needles required to be tested by the test pads 2〇4, 206 can be reduced, thereby reducing the acupressure pressure that the IMD layer underneath. In addition, as the semiconductor process progresses, when the number of pinning steps required for the wafer 200 is further increased, a test space of more than a single test pad can be provided according to the setting of the horizontal or vertical misalignment; According to this principle, other sets of test pads are additionally provided to provide more test space before protecting the IMD layer under the test pad. Next, please refer to Fig. 7 and Fig. 8. Fig. 7 and Fig. 8 are schematic cross-sectional views along the broken line 208 in Fig. 4. As shown in FIG. 7, the wafer 2 is provided with a set of pads 202 for providing external electrical connection between the wafers 2, as provided in the first preferred embodiment, the electrical connection being Provided by bump connections. At least one first set of test pads 2 〇 4 and a second set of test pads 206' are provided on the wafer 200 for providing a needle test function. And the first set of test pads 4 and the second set of test pads 2 〇 6 are exposed to a protective layer 2 (7). It should be noted that the pad 202, the first set of test pads 2〇4 and the second set of test blocks 206 are provided with a plurality of layers of layers 212. As mentioned earlier, due to advances in deep sub-micro semiconductor processes with high accumulations below 18 microns, copper dual damascene technology with low dielectric constant 〇〇w_K) materials The leakage layer composed of ultra-low dielectric constant (ULK) or porous low dielectric constant material has become the most popular metal interconnect technology. And these materials have the characteristics of splitting than 13 200905844'. Therefore, the group setting of the pQAA test pad provided by the present invention can reduce the number of needles under the test by reducing the number of needles subjected to the test. (4) The probe (4) can avoid the collapse of the IMD layer during the needle testing step. In addition, the group arrangement of the P〇AA test pads provided by the present invention can be electrically connected to the pads 2, 2 by a wire, for example, a redistHbuted layer 'RDL 220, as shown in FIG. The first set of test pads 2〇4, and the second set of test pads 206 are used to adjust the positions of the pads 2〇2, the first set of test pads 204, and the second set of test pads 206 to further enhance the stability of the components. It should be noted that, according to FIGS. 7 and 8, the first set of test pads 204 and the first set of test pads 206 are active circuits exposed to a metal pad 214 by a patterned protective layer 210. The upper test pad, therefore, the test pads added in groups do not occupy the area of the wafer 200. In summary, the group setting of the test pad provided by the present invention performs the difference between the first set of test pads and the second set of test pads by a group setting concept, and the first group test of 5 sets The setting of the second set of test 系 is set by the dislocation of the water, vertical, or diagonal. Therefore, each pad has at least a rain 'group and its corresponding test pad provides a needle test function. In addition to increasing the number of wafer pin counts, the number of pin tests required for each test pad can be reduced, and the lower one can be reduced. The needle pressure that the IMD layer is subjected to. In addition, by means of grouping and setting the 5 type pad, when the number of needle testing steps required for the wafer is further increased, the other 14 200905844 group tests can be set according to the setting of the dislocation (4) Under the premise of the fine under the pad, more room 4 is provided, which is more in line with the requirements of future semiconductor processes. The above description is only the preferred embodiment of the present invention, and the equivalent changes made by the applicant's patents and/or (4) are covered by the present invention. [Simple description of the drawings] Fig. 1 and Fig. 2 are schematic diagrams of a package structure in which a test cartridge is provided. Figure 3 is a schematic diagram of a first preferred embodiment of a group arrangement of test pads above the active circuit provided by the present invention. Fig. 4 is a partial enlarged view of the p〇AA test pad group setting shown in Fig. 3. Fig. 5 and Fig. 6 are partial enlarged views of a second preferred embodiment of the group δ of the p〇AA test pads provided by the present invention. Fig. 7 and Fig. 8 are schematic cross-sectional views taken along line 208 of Fig. 4; [Main component symbol description] 1 〇〇 wafer 102 pad 104 protective layer 106 bump 108 test pad no reset layer 200 wafer 202, 202a, 202b, 202c pad 15 200905844 204, 204a, 204b, 204c 206, 206a, 206b, 206c 208 dashed line 212 inter-metal dielectric layer 220 reset layer first set of test pads second set of test pads 210 protective layer 214 metal pad 16