200905796 UMCD-2006-0697 23499twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體製 種内連線製程。 ^且特別疋有關於、 【先前技術】 〜體技術的進步’元件的尺寸也不斷地縮小。 田積體电路的積集度增加，使得曰 的面積來製作所需的内連線時:I⑽元; =線需求，兩層以上的多層金屬内連=所Ϊ 成為超大^频電路(VLSI)技術所必須採用的方式。更 以目前形成金屬内連線的製程來 中先^出開口，再於開口内填入金屬以作為内連線^ 此-丰半導體製程中，由於銅金屬的蝕刻不易，因 夕屬鑲嵌製程取代傳統的製程來製作銅導線 形成一層以氮化鈦⑽)為 》 ::在金屬硬罩幕層上形成介電。::罩： 中:r 一次崎程，以將介電硬以 罩1承* 在第一反應室中以圖案化的介電硬罩幕層為 之後:次，ί程’以將金屬硬罩幕層圖案：: 幕來進行# ^㈣介1衫幕料及域料幕層為罩 來進仃_製程，以於介電層巾形成開σ。 此外，為了減少上述製程巾的㈣步驟，也可以在金 200905796 UMCD-2006-0697 23499twf.d〇c/n 屬硬罩幕層上形成一層氮氧化矽(Si〇N)層，然 反應室中以含有四氟化碳(CF4)的钱刻氣體與含有氯ϋ 的姓刻氣體來分職職氧切層與金屬硬罩幕層/、2) 成圖案化的氮氧切罩幕層以及圖案化的金屬硬i暮展 的氮氧化_以及圖案化的it更 罩幕層為罩幕來進行_製程，以於介電層中形成開=。 然而，由於在同—庙它vtrin* y. 。 刻氣體斑含有氯气心應中同含有四氟化碳的蝕 屬^ 刻氣體來分職刻氮氧化石夕層與金 盘含氣^物* Τ反應室中往往會同時產生含氣聚合物 f t 了㈣製程中的微粒表現加疏 ormance)降低，進而對後續的製程造 【發明内容】 曰 „目的就是在提供—種内 ㈣製程中的微粒表現。 少製的另一目的是在提供一種内連線製程，可以減 少反再Γ目的是在提供—種内連線製程，可以減 w 的微粒以及減少製程步驟。 基底重内連線製程，其是先提供-基底，此 於介電層上步成1*然後’於基底上形成介電層。接著， 後，於圖安溝渠開口的圖案化金屬硬罩幕層。而 並填入、、冓、击硬罩幕層上共形地形成介電硬罩幕層， 中部分介;二，圖案以移除溝渠開口 邛勿介電層，以於介電層中形成第 200905796 UMCD-2006-0697 23499twf.doc/n 幕K罩^ I隹，絲_ ° 金屬硬罩 的、F仃第—網製程，在贿化麵硬罩幕層 的溝木開口的範圍内，在介電層中形成溝渠與由第 第二開口’其中第二開口暴露出導電區。之後， 於溝渠與第二開口^形成導體層。 -依照本發明實施綱述之内魏製程，上 罩幕層的材料例如是氧化;g夕。 依照本發明實施例所述之⑽線製程，上述之圖案化 金屬硬罩^層的材料例如是氮化鈦、氮化城鈦鶴j。 依照本發明實施例所述之内連線製程， 例如是導線或電極。 4疋V電& 依照本發明實施例所述之内連線製程，上述之介電声 的材料例如是低介電常數材料。 曰 依照本發明實施例所述之内連線製 的材料例如是銅或鎢。 蛉體層 依照本發明實施例所述之内連線製程，上 :的例如是先於介電硬罩幕層形成圖案= t然後’以圖案化光阻層為罩幕，進行第二爛' ::分介電硬罩幕層與部分介電層。之後，移除圖案 依，本J明實施例所述之内連線製程，上述在 電層之前，更可以於基底上形成覆蓋層。 战1 依^本發明實施例所述之内連線製程，上述在 ΐ層之後以及形成圖案化金屬硬罩幕層之前，更可以^ 200905796 UMCD-2006-0697 23499twf.doc/n 電層上形成研磨終止層或黏著層。 依照本發明實施例所述之二連 的形成方法例如是先於基底導y 奴導體層 行平坦化製程，以移除溝渠與第二開口以後，進 此美麻Φ目fί ’連線製程’其是先提美麻 此基底中具有導電區。然後，於 故供基底， o 中部分介電硬罩幕層與部分介電層，：:：二渠:" 二’=口暴露出導電區。然後，移二J成： 。接下來，以圖案化二Ϊ ί後，移除保製程、’以於介電層中形成溝渠。 依照本於明^之w於溝渠與開口中形成導體層。 步成方私丨二/&例所奴内連線製程，上述之開口的 =====幕層上形成圖案化光阻層。 广邱八入ί層為罩幕’進行第二侧製程，以移 trr硬罩幕層與部分介電層，直到暴露出導電區 之後，移除圖案化光阻層。 ，照本發明實施例所述之内連線製程，上述之保護屛 =方法例如是先於基底上形成保護材料層。之後，i Ϊ (etching back)製程，以移除開口以外的保護材料 依照本發明實施例所述之内連線製程，上述之導體層 200905796 UMCD-2006-0697 23499twf.doc/n =成方相如是先於基底上形成導體材料層。之後，進 坦化製程，以移除溝渠與開口以外的導體材料層。 罝墓^發明在形成開口之前，先將形成於介電層上金屬硬 2圖案化，然後再於_化金屬硬罩幕層上共形地形 二電硬罩幕層’之後直接進行微影製程與侧製程來形 —^口 ’藉由省略將介電硬罩幕層圖案化的步驟以及因為 罩幕層可以取代氮氧切的制，避免針對氮氧化 π 力金屬硬罩幕層所使用含氟化物的侧氣體對金屬產生 反應，減少蝕刻反應室中同時產生的多種微粒，因此改善 了蝕刻製程的微粒表現。 為讓本發明之上述和其他目的、特徵和優點能更明顯 董，下文特舉較佳實施例，並配合所附圖式，作詳細 明如下。 【貫施方式】 、以下將先以雙重金屬鑲喪(dual damascene)製程為例 f 來說明本發明之内連線製程。 ‘ Q 1A至圖ιέ為依照本發明一實施例所繪示的雙重金 • 屬鑲肷製程之剖面示意圖。首先，請參照圖ία，提供其中 ^有導電區102的基底100。基底100例如是矽基底了導 电區102可以是電極或導線。然後，選擇性地於基底1〇〇 ^形成覆蓋層104。接著，於基底1〇〇上形成介電層1〇6。 W電層106的材料例如是低介電常數材料，形成方法例如 為化學氣相沈積法(chemical vapor deposition，CVD)。接下 來，選擇性地於介電層106上形成研磨終止層或黏著層 200905796 UMCD-2006-0697 23499twf.doc/n ⑽’形成研磨終止層絲著層⑽的材料可為 ί篡Π磨終止層108上形成金屬硬罩幕層no。金屬硬 成方法例如為化學氣相沈積法。此外，覆 =層：的材料以及形成方法為本領域中:有通常 者所热知，於此不再贅述。 铒 然後’請參照圖出，於金屬硬罩幕層11〇 二光阻層(未繪示）’並以圖案化級層為罩幕進行餘刻製 I:成具有溝渠開口的圖案化金屬硬罩幕層110a。圖 層彡地形成介電硬罩幕 如“開中。介電硬罩幕層112的材料例 法'太：或二氧化矽，形成方法例如是化學氣相沈積 乙氧it施例中，介電硬罩幕層112的材料例如是以四 的氧^石夕i rhyl orth罐cate，TE0S)為氣體源所形成 幕層112 =2石夕、。ί然，在其他實施例中，介電硬罩 其他合適的介;r ΐίι (Sic)、氮碳切(_或 if硬罩幕層隐在後續祕㈣程中，其巾的全= 等y _氣體反應產生不易揮發的副產物，如氟化欽⑽） 化光參照圖1C’於介電硬罩幕層112上形成圖案 區域。而\，以圖圖牵="阻層114暴露錢續形成開口的 圖案化光阻層114為罩幕，進行蝕刻製程， 10 200905796 UMCD-2006-0697 23499twf.doc/n 移除部分介電硬罩幕層112 106，以形成開口 11ό。 研磨q止層⑽以及介電層 而後，請參照圖1D，移除+ 以圖案化金屬硬罩幕層llQa^i'，且層114。隨後， 案化金；I硬罩幕層11Ga的溝⑽⑽刻製程’在圖 跳中形成溝渠m與由^ 下的範圍内，在介電層 •中開口 120暴露出導電區1〇2上方的=申令的開口 120,其 ° 於介電硬罩幕層⑴與介電層1〇6比=覆盘層104。由 二=r刻製程中，_匕金 a特別:提的是，本發明暴在^成=電導硬電== 刖，先將形成的金屬硬罩幕層ιι〇 曰112之 步驟。 、〃電硬罩幕層⑴圖案化的 •代，^要驟中’因為氮氧化石夕被氧化石夕取 體來將介電硬罩幕層的含氣和含氣之二種钱刻氣 避免反應室中同時產生夕綠沾硬罩幕層圖案化’因此可以 粒表現。 ^ 、微粒’改善了餘刻製程的微200905796 UMCD-2006-0697 23499twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor seed interconnection process. ^ And in particular, the [pre-technical] advancement of the body technology's dimensions are constantly shrinking. The accumulative degree of the field integrated circuit is increased, so that the area of the crucible is used to make the required interconnect: I(10) element; = line demand, two or more layers of multi-layer metal interconnect = Ϊ become a super large frequency circuit (VLSI) The way technology must be used. In the current process of forming a metal interconnect, the opening is first opened, and then the metal is filled in the opening to serve as an interconnect. In the process of the semiconductor, the etching of the copper metal is not easy, and the etching process is replaced by the Xicheng mosaic process. The traditional process is to make a copper wire to form a layer of titanium nitride (10) as a :: dielectric on the metal hard mask layer. :: Cover: Medium: r One time, it is necessary to make the dielectric hard to cover the cover 1 in the first reaction chamber with the patterned dielectric hard mask layer: then, ί程' to harden the metal Curtain pattern:: Curtain to carry out # ^ (4) 1 shirt screen and the domain material layer as a cover to enter the process _ process, in order to form the opening layer σ. In addition, in order to reduce the (four) steps of the above process towel, a layer of bismuth oxynitride (Si〇N) layer may be formed on the hard mask layer of gold 200905796 UMCD-2006-0697 23499twf.d〇c/n, in the reaction chamber. A gas-cutting gas containing carbon tetrafluoride (CF4) and a gas containing a chloranium to separate the oxygen-cut layer and the metal hard mask layer, and 2) a patterned oxynitride mask layer and pattern The oxidized metal _ _ and the patterned ITO layer are masked for the process to form an open = in the dielectric layer. However, due to the same - temple it vtrin* y. The gas spot contains chlorine gas and the gas containing carbon tetrafluoride is used to separate the oxynitride layer and the gold disk gas. The reaction chamber often produces a gas-containing polymer ft. (4) The particle expression in the process is reduced or less, and then the subsequent process is made. [The content of the invention] The purpose is to provide the particle performance in the in-process (four) process. Another purpose of the system is to provide a kind of The wiring process can be reduced to provide an in-line process that can reduce the number of particles and reduce the number of process steps. The substrate is internally connected to the substrate, which is provided first on the dielectric layer. Step into 1* and then 'form a dielectric layer on the substrate. Then, after patterning the metal hard mask layer on the opening of the Tuan ditch, and form a conformal formation on the hard mask layer. Dielectric hard mask layer, middle part; second, pattern to remove the trench opening, do not dielectric layer, to form the second layer in the dielectric layer UMCD-2006-0697 23499twf.doc/n screen K cover ^ I隹, silk _ ° metal hard cover, F仃 first-net process, in the bribery In the range of the trench opening of the mask layer, a trench is formed in the dielectric layer and a conductive region is exposed by the second opening 'the second opening. Thereafter, the conductive layer is formed in the trench and the second opening ^. In the internal process of the invention, the material of the upper mask layer is, for example, oxidized. According to the (10) line process described in the embodiment of the invention, the material of the patterned metal hard mask layer is, for example, titanium nitride. An internal interconnect process, such as a wire or an electrode, according to an embodiment of the invention. 4 疋 V 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电The material of the sound is, for example, a low dielectric constant material. The material of the interconnect according to the embodiment of the invention is, for example, copper or tungsten. The body layer is in accordance with the interconnect process described in the embodiment of the invention. For example, the pattern is formed before the dielectric hard mask layer = t and then the patterned photoresist layer is used as a mask to perform the second bad '::dielectric hard mask layer and part of the dielectric layer. Thereafter, remove The pattern is as described in the embodiment of the present invention, the above-mentioned Before the electrical layer, a cover layer can be formed on the substrate. Battle 1 According to the interconnect process described in the embodiment of the present invention, the above-mentioned after the germanium layer and before the formation of the patterned metal hard mask layer can be further 200905796 UMCD -2006-0697 23499twf.doc/n A polishing stop layer or an adhesive layer is formed on the electric layer. The method for forming the two-layer according to the embodiment of the present invention is, for example, a planarization process prior to the substrate guiding y slave conductor layer to move In addition to the ditch and the second opening, the melon Φ mesh fί 'connection process' is the first to mention the mesophyll has a conductive area in the substrate. Then, for the base, o part of the dielectric hard mask layer and part of Electrical layer, ::: two channels: " Two '= mouth exposed conductive area. Then, move two J into: Next, after the pattern is patterned, the protective process is removed to form a trench in the dielectric layer. A conductor layer is formed in the trench and the opening according to the present invention. Step into the private 2 /& example of the slave connection process, the above opening ===== the patterned photoresist layer is formed on the curtain layer. The Guangqiu eight-in layers are masked to perform a second side process to remove the trr hard mask layer and a portion of the dielectric layer until the conductive regions are exposed, and the patterned photoresist layer is removed. According to the interconnect process described in the embodiments of the present invention, the above protection method is, for example, forming a protective material layer on the substrate. Then, an etching back process to remove the protective material other than the opening according to the embodiment of the present invention, the conductor layer 200905796 UMCD-2006-0697 23499twf.doc/n = square phase If a layer of conductor material is formed prior to the substrate. Thereafter, the process is advanced to remove the layer of conductor material other than the trench and the opening.罝Tommology ^Invented before the formation of the opening, the metal hard 2 formed on the dielectric layer is patterned, and then the SiC metal hard mask layer conforms to the surface of the second electric hard mask layer' directly after the lithography process By the side process, the step of patterning the dielectric hard mask layer is omitted, and because the mask layer can replace the oxynitride system, the use of the hard mask layer for the nitrogen oxide is avoided. The side gas of the fluoride reacts with the metal to reduce the number of particles simultaneously generated in the etching reaction chamber, thereby improving the particle performance of the etching process. The above and other objects, features and advantages of the present invention will become more apparent from [Complex method] Hereinafter, the dual damascene process will be taken as an example to illustrate the interconnect process of the present invention. ‘Q 1A to έ έ are schematic cross-sectional views of a double gold enamel process according to an embodiment of the invention. First, referring to Fig., a substrate 100 in which a conductive region 102 is provided is provided. The substrate 100 is, for example, a germanium substrate. The conductive region 102 can be an electrode or a wire. Then, the cover layer 104 is selectively formed on the substrate 1 . Next, a dielectric layer 1〇6 is formed on the substrate 1〇〇. The material of the W electrical layer 106 is, for example, a low dielectric constant material, and the formation method is, for example, chemical vapor deposition (CVD). Next, a polishing stop layer or an adhesive layer is selectively formed on the dielectric layer 106. The structure of the wire layer (10) forming the polishing stop layer (10) may be a rubbing stop layer. A metal hard mask layer no is formed on 108. The metal hardening method is, for example, a chemical vapor deposition method. Further, the material of the layer and the formation method are in the art: they are generally known, and will not be described again.铒 Then, please refer to the figure, in the metal hard mask layer 11 〇 two photoresist layer (not shown) and use the patterned layer as a mask for the engraving process I: into a patterned metal hard with a trench opening Mask layer 110a. The layer is formed by a dielectric hard mask such as "opening. The dielectric hard mask layer 112 material example" too: or cerium oxide, the formation method is, for example, chemical vapor deposition ethoxylate example, dielectric The material of the hard mask layer 112 is, for example, a curtain layer 112 = 2 stone etched by a gas source of four oxygen crystals, θ, TE0S). In other embodiments, the dielectric is hard. Cover other suitable media; r ΐίι (Sic), nitrogen carbon cut (_ or if hard mask layer hidden in the follow-up secret (four) process, its towel full = y _ gas reaction produces non-volatile by-products, such as fluorine Huachin (10)) tempering forms a pattern region on the dielectric hard mask layer 112 with reference to FIG. 1C', and the patterned photoresist layer 114 is exposed as a mask. Curtain, etching process, 10 200905796 UMCD-2006-0697 23499twf.doc/n Remove part of the dielectric hard mask layer 112 106 to form the opening 11 ό. Grind the q stop layer (10) and the dielectric layer, then please refer to Figure 1D , remove + to pattern the metal hard mask layer llQa ^ i ', and layer 114. Subsequently, the gold; I hard mask layer 11Ga groove (10) (10) engraving process ' In the range of the trenches m and the lower surface, the opening 120 of the conductive layer 1 〇 2 is exposed in the dielectric layer • the opening 120, which is in the dielectric hard mask layer (1) Electrical layer 1〇6 ratio=covering plate layer 104. In the process of two=r engraving, _ 匕金a special: mentioning that the invention is in the form of ^==conducting hard electric== 刖, the metal will be formed first Step of masking layer ιι〇曰 112. 〃Electric hard mask layer (1) Patterned generation, ^ is to be in the middle of 'the oxynitride oxidized stone etched to contain the dielectric hard mask layer The two kinds of gas and gas contain gas to avoid the simultaneous formation of the green layer and the hard mask layer in the reaction chamber. Therefore, the particles can be expressed. ^, the particles improve the micro-process
之後，清參照圖IP 緣示）’並填滿溝渠118與^口形成導體材料層(未 如是銅或鎢。然後二 。¥體材料層的材料 例如使用化學機械研磨⑽emkai 11 200905796 UMCD-2006-0697 23499twf.doc/n 刪hanicalp〇lish’ CMp)法來進行平坦化製程，將溝渠川 與開口 120以外的導體材料層移除至研磨終止層1〇8，以 ^渠m與開口 120中形成導體層122，使得導體層122 可電區102電性連接而完成雙重金屬鑲叙的製作。 舌j 至圖2D為依照本發明另一實施例所緣示的雙 ^鑲嵌製程之剖面示意圖。首先，請參㈣2a，其為 芦11; 後所進仃的步驟。在® 2A中’於介電硬罩幕 化光阻層114。圖案化光阻層114暴露 ϋ形成開口的區域。而後，以圖案化光阻層m為罩 止声二’移除部分介電硬罩幕層112、研磨終 霜=3 6直到暴露出導電區102上的部分 覆盍層104,以形成開口 124。 請參照圖2B，移除圖案化光 ΪΪ 成保護材料層(未綠示)，刪^ 126的钱刻丁速率’以形成保護層126，其中保護層 接莫，往率頁小於或等於介電層106的_速率。 罩幕，進圖2C’以圖案化金属硬罩幕層―為 = 4:，製裎’以於介電層*。6中形成溝渠⑶。 電層刚=刻的烟速率小於或等於介 溝渠I28時，保^ =在移除部分介電層106以形成 12二圖2D’移除保護層126。之後，於溝渠 形成導體層122’以完成雙重金屬鑲嵌的 12 200905796 UMCD-2006-0697 23499twf.doc/n 製作。 值得一提的是，本發明的内連線製程除了可以應用在 上述的雙重金屬鑲嵌製程之外，當然也可以應用在單一金 屬鑲嵌(single damascene)製程。 r 圖3A至圖3D為依照本發明另一實施例所繪示的單 一金屬鑲嵌製程之剖面示意圖。首先，請參照圖3A，提供 其中具有導電區302的基底300。基底300例如是；ς夕基底。 導電區302可以是電極或導線。然後，選擇性地於基底3〇〇 上形成覆盍層304。接著，於基底3〇〇上形成介電層3〇6。 介電層306的材料例如是低介電常數材料，形成方法例如 為化學氣相沈積法。接下來，選擇性地於介電層3〇6上形 成研磨終止層308。之後，於研磨終止層删上形成金屬 ，罩幕層31〇。金屬硬罩幕層的材料例如是氮化欽、 亂化钽或鈦鎢合金，形成方法例如為化學氣相沈積法。同 樣地，覆蓋層3〇4與研磨終止層3〇8的材料以及形成方法 為本領域中具有通常知識者所熟知，於此不再賢述。 以圖3Β，將金屬硬罩幕層310圖案化， Ϊ的圖案化金屬硬罩幕層咖。圖案化 孟屬硬罩幕層3H)a暴露出後續形成開 圖案化金屬硬罩幕層遍上共形地形成介 312 ’並填入溝渠開口中。介電 ^ 氧化㈣二氧化秒，形成方法 本實施例中，介電硬罩幕層312的材料: 魏為氣體源所形成的氧化石夕或二氧化梦。當然，在其ς 200905796 UMCD-2006-0697 23499twf.doc/n 實施例中，介電硬罩幕層31 碳化石夕或其他合義介％材料。_也了以故切、氮 接著，請參照圖3C，以阁安人p 罩篡，谁杆钻釗制私 乂圖木化金屬硬罩幕層3l〇a為 =進祕n以於介電層遍中形 心日日 電2上方的部分覆蓋層綱。 祕開口 313所暴露出的覆蓋層304,以暴露出部 分導電區302。 fl 之後，請參照圖3D，於開口 313中形成導體層川， 使得導體層314可與導電區3〇2電性連接而完成單一金屬 鑲嵌的製作。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者為 準。 【圖式簡單說明】After that, refer to the figure IP edge) and fill the trench 118 to form a conductive material layer (not as copper or tungsten. Then two. The material of the bulk material layer is, for example, chemical mechanical polishing (10) emkai 11 200905796 UMCD-2006- 0697 23499twf.doc/n The hanicalp〇lish' CMp) method is used to perform the planarization process, and the trench material and the layer of the conductor material other than the opening 120 are removed to the polishing stop layer 1〇8 to form the channel m and the opening 120. The conductor layer 122 is such that the conductor layer 122 can be electrically connected to the electrical region 102 to complete the fabrication of the double metal inlay. Tongue j to Fig. 2D are schematic cross-sectional views of a dual damascene process according to another embodiment of the present invention. First of all, please refer to (4) 2a, which is the step of the reed 11; In the ® 2A, the photoresist layer 114 is cured by a dielectric hard mask. The patterned photoresist layer 114 exposes the regions where the turns form an opening. Then, the patterned photoresist layer m is used as a mask to remove the partial dielectric hard mask layer 112 and the final frosting layer = 3 6 until the partial coverage layer 104 on the conductive region 102 is exposed to form the opening 124. . Referring to FIG. 2B, the patterned photo-deposited protective material layer (not shown in green) is removed, and the memory layer 126 is formed to form a protective layer 126, wherein the protective layer is connected, and the rate page is less than or equal to the dielectric. The _ rate of layer 106. The mask, as shown in Fig. 2C', is patterned with a metal hard mask layer of -4: 裎' for the dielectric layer*. A ditch (3) is formed in 6. When the electric layer has a smoke rate less than or equal to that of the trench I28, the portion of the dielectric layer 106 is removed to form a second protective layer 126. Thereafter, the conductor layer 122' is formed in the trench to complete the double damascene 12 200905796 UMCD-2006-0697 23499twf.doc/n. It is worth mentioning that the interconnect process of the present invention can be applied not only to the above dual damascene process, but also to a single damascene process. FIG. 3A to FIG. 3D are schematic cross-sectional views showing a single damascene process according to another embodiment of the invention. First, referring to Fig. 3A, a substrate 300 having a conductive region 302 therein is provided. The substrate 300 is, for example, an enamel substrate. Conductive region 302 can be an electrode or a wire. Then, a capping layer 304 is selectively formed on the substrate 3A. Next, a dielectric layer 3〇6 is formed on the substrate 3〇〇. The material of the dielectric layer 306 is, for example, a low dielectric constant material, and the formation method is, for example, a chemical vapor deposition method. Next, a polish stop layer 308 is selectively formed on the dielectric layer 3?6. Thereafter, a metal is formed on the polishing stop layer, and the mask layer 31 is formed. The material of the metal hard mask layer is, for example, a nitrided, chaotic or titanium-tungsten alloy, and the formation method is, for example, a chemical vapor deposition method. Similarly, the materials of the cover layer 3〇4 and the polishing stop layer 3〇8 and the method of forming are well known to those of ordinary skill in the art and will not be described herein. 3, the metal hard mask layer 310 is patterned, and the patterned metal hard mask layer is patterned. The patterned montage hard mask layer 3H)a exposes the subsequent formation of the patterned metal hard mask layer over the conformal formation of the dielectric layer 312' and fills the trench opening. Dielectric ^ Oxidation (4) Dioxide Second, Forming Method In this embodiment, the material of the dielectric hard mask layer 312: Wei is a gas oxide formed by a gas source or a dream of oxidizing. Of course, in its embodiment 200905796 UMCD-2006-0697 23499 twf.doc/n, the dielectric hard mask layer 31 is carbonized or otherwise. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The layer covers the part of the overlay layer above the solar power 2 in the layer. The cover layer 304 exposed by the opening 313 exposes a portion of the conductive region 302. After fl, referring to FIG. 3D, a conductor layer is formed in the opening 313, so that the conductor layer 314 can be electrically connected to the conductive region 3〇2 to complete the fabrication of a single damascene. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. [Simple description of the map]
Cw* y f 圖1A至圖IE為依照本發明一實施例所繪示的雙重金 屬鑲後製程之剖面示意圖。 圖2A至圖2E)為依照本發明另一實施例所繪示的雙 重金屬鑲嵌製程之剖面示意圖。 圖3A至圖3D為依照本發明另一實施例所緣示的單 一金屬鑲嵌製程之剖面示意圖。 、 【主要元件符號說明】 100、300 :基底 14 200905796 UMCD-2006-0697 23499twf.doc/n 102、302 :導電區 104、304 :覆蓋層 106、306 :介電層 108、308 :研磨終止層/黏著層 110、310 :金屬硬罩幕層 110a、310a:圖案化金屬硬罩幕層 112、312 :介電硬罩幕層 114 :圖案化光阻層 116、120、124、313 :開口 118、128 :溝渠 122、314 :導體層 126 :保護層 15Cw* y f Figure 1A to Figure IE are schematic cross-sectional views of a dual metal inlay process in accordance with an embodiment of the present invention. 2A-2E are cross-sectional views of a dual damascene process in accordance with another embodiment of the present invention. 3A through 3D are schematic cross-sectional views showing a single damascene process in accordance with another embodiment of the present invention. [Main component symbol description] 100, 300: substrate 14 200905796 UMCD-2006-0697 23499twf.doc/n 102, 302: conductive region 104, 304: cover layer 106, 306: dielectric layer 108, 308: polishing stop layer / Adhesive layer 110, 310: metal hard mask layer 110a, 310a: patterned metal hard mask layer 112, 312: dielectric hard mask layer 114: patterned photoresist layer 116, 120, 124, 313: opening 118 , 128: trenches 122, 314: conductor layer 126: protective layer 15