200905436 九、發明說明： 【發明所屬之技術領域】 本發明係關於閘極驅動電路，特別是關於可箝制輸出 電壓位準的閘極驅動電路。 【先前技術】 閘極驅動電路若輸出過高準位的驅動訊號將使場效電 晶體的間極氧化層朋潰。因此，間極驅動電路的設計需考 慮被驅動元件之閘極氧化層之保護，避免使其崩潰，習知 技術以輸出電壓箝制電路來達到防護功能，例如：一般應 用一基納二極體（Zener Diode )或是一線性穩壓器（Linear Regulator)提供所需箝制電壓位準，以及所需電流。 第一圖為習知應用基納二極體12於驅動P型功率電晶 體13實現電壓箝制之電路示意圖。該電路10使得輸出電 壓位準V0UT與電源電壓VDD的差值限制於基納二極體 12崩潰電壓，達到輸出電壓箝制的效果；然而，由於該基 納二極體12操作於崩潰區，因此會在電壓箝制穩態時具有 直流電流，而具有較高的功率消耗。 第二圖為習知應用線性穩壓器22於驅動P型功率電晶 體24實現電壓箝制之電路圖。該電路20利用負回授使得 輸出電壓位準VOUT與電源電壓VDD的差值被鎖定在預 設的電壓位準，達到輸出電壓箝制的效果；然而，該線性 穩壓器22需提供一與電源電壓預設的壓降，因此需固定輸 出直流電流，此外，該線性穩壓器22亦需提供輸出閘極信 200905436 號電位轉換所需高速暫態電流，因此傳統作法上需要一大 面積穩壓電容23以穩定輸出電壓準位VOUT，如此造成大 幅耗費晶片面積及成本。 【發明内容】 有鑑於上述問題，本發明之目的是提出一主動式電壓 箝制閘極驅動電路，利用簡單的輸出檢測回授即可實現輸 出電壓箝制，以及低功率消耗的S的。 為達成上述目的，本發明提供一種主動式電壓箝制閘 極驅動電路。上述主動式電壓箝制閘極驅動電路包含一差 異比較電路及一閘極驅動電路。上述差異比較電路接收一 基準參考電壓，以及一輸出閘極控制信號，並據此輸出至 少一電壓比較信號。上述閘極驅動電路接收一資料輸入信 號以及前述電壓比較信號，並輸出至少一閘極驅動信號。 其中，當該輸出閘極控制信號與該基準參考電壓位準之差 大致（大於或小於）等同於一預定值時，該電壓比較信號 控制該閘極驅動電路關閉，藉以使得輸出閘極控制信號位 準被箝制於預設電壓位準。 本發明也提供另一種主動式電壓箝制閘極驅動電路。 上述主動式電壓箝制閘極驅動電路包含一差異比較電路及 一閘極驅動電路。上述差異比較電路接收一基準參考電 壓、一預設電壓位準以及一輸出閘極控制信號，並據此輸 出至少一電壓比較信號。上述閘極驅動電路接收一資料輸 入信號，以及前述電壓比較信號，並輸出至少一閘極驅動 200905436 信號。其中，當該輸出閘極控制信號與 :編致(大於或小於)等同於該C: 祕比較信號控制該閘極驅動電路關閉， ’該 極控制彳§號位準被箝制於預設電壓位準。 、輸出閘 【實施方式】 電壓 掛制閘極驅 r200905436 IX. Description of the Invention: [Technical Field] The present invention relates to a gate driving circuit, and more particularly to a gate driving circuit capable of clamping an output voltage level. [Prior Art] If the gate drive circuit outputs a drive signal with a high level, the interlayer oxide of the field effect transistor will collapse. Therefore, the design of the interpole drive circuit needs to consider the protection of the gate oxide layer of the driven component to avoid collapse. The prior art uses an output voltage clamp circuit to achieve the protection function, for example, a general application of a Zener diode ( Zener Diode) or a Linear Regulator provides the required clamping voltage level and the required current. The first figure is a schematic diagram of a conventional circuit for applying voltage-clamping by driving a P-type power transistor 13 by a Zener diode 12. The circuit 10 limits the difference between the output voltage level VOUT and the power supply voltage VDD to the breakdown voltage of the Zener diode 12 to achieve the effect of output voltage clamping; however, since the Zener diode 12 operates in a collapse region, It will have a DC current when the voltage is clamped to a steady state, but has a higher power consumption. The second figure is a circuit diagram of a conventional application of a linear regulator 22 for driving a P-type power transistor 24 to achieve voltage clamping. The circuit 20 utilizes negative feedback such that the difference between the output voltage level VOUT and the power supply voltage VDD is locked at a preset voltage level to achieve an output voltage clamping effect; however, the linear regulator 22 is required to provide a power supply. The voltage is preset to the voltage drop, so the output DC current needs to be fixed. In addition, the linear regulator 22 also needs to provide the high-speed transient current required for the potential conversion of the output gate signal 200905436, so the conventional method requires a large area of voltage regulation. Capacitor 23 stabilizes the output voltage level VOUT, which results in significant expense of wafer area and cost. SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an active voltage clamping gate driving circuit that can realize output voltage clamping and low power consumption S by simple output detection feedback. To achieve the above object, the present invention provides an active voltage clamp gate drive circuit. The active voltage clamping gate driving circuit comprises a differential comparison circuit and a gate driving circuit. The difference comparison circuit receives a reference reference voltage and an output gate control signal, and outputs at least one voltage comparison signal accordingly. The gate driving circuit receives a data input signal and the voltage comparison signal, and outputs at least one gate driving signal. Wherein, when the difference between the output gate control signal and the reference reference voltage level is substantially equal to or greater than a predetermined value, the voltage comparison signal controls the gate driving circuit to be turned off, thereby causing the output gate control signal The level is clamped to the preset voltage level. The present invention also provides another active voltage clamping gate drive circuit. The active voltage clamping gate driving circuit comprises a difference comparison circuit and a gate driving circuit. The difference comparison circuit receives a reference reference voltage, a predetermined voltage level, and an output gate control signal, and outputs at least one voltage comparison signal accordingly. The gate driving circuit receives a data input signal, and the voltage comparison signal, and outputs at least one gate driving 200905436 signal. Wherein, when the output gate control signal is equal to: the C (same or smaller) is equivalent to the C: the secret comparison signal controls the gate drive circuit to be turned off, 'the pole control 彳 § level is clamped to the preset voltage level quasi. Output gate [Embodiment] Voltage-mounted gate drive r
以下參考圖示詳細說明本發明主動式 動電路。 本發明之精神係㈣極驅動信號使被驅 狀態時，偵測閘極驅動信號是否達到一牛為導通 當閘極驅動信號達到-駄的輸出準位時，關準位。 電路’使閘極驅動信號被箱制在該預定輸出準^虽驅動 時無習知技術的箝制方式所造成的直流 此 低功率消耗之優點。 &亦達到降 第二圖為本發明主動式電壓箝制閘極驅動電路示土 。如謗圖所示，該主動式電壓箝制閘極驅動電路忍圖 閘極驅動電路31依據資料輸入信號vin來提供衿，用— 驅動信號VOUT’以驅動後級被驅動元件33,其^閘極 被驅動元件33應用之參考電壓位準為基準參考電屢，後級 ，同時利用一差異比較電路32依據一基準參考電髮 以及輪出閘極驅動信號νουτ產生閘極驅動電路3l Vi>〇T 信號vCTL;其甲，差異比較電路32由差異放大的辁制 2位準比較電路322所組成；差異放大電路321俺^321 參考電壓VP0T以及輸出閘極驅動信號ν〇υτ 暴準 1聲差 200905436 異信號VD，再經由位準比較電路322與預設參考位準 VREF作比較，產生鬧極驅動電路3 i的控制信號VCTL。 當電麼差異M VD與預設參寺位準VREF之差達到 定值時，即基準參考電壓VP0T和輪出閘極驅動信號ν〇υτ 之電壓差異達到預設參考位準VREF時，位準比較電路切 產生一控制信號VCTL以關閉閘極驅動電路31，此時閘極 驅動電路31因關閉而維持閘極驅動信號ν〇υτ的準位，如 此即達到箝制輸出閘極電壓信號VOUT電壓位準，以及無 穩態直流電流而低消耗功率的目的。 上述的基準參考電壓VPOT係用以判斷是否閘極驅動 信號VOUT是否低於（如：對p型電晶體或不同的基準參 考電壓VPOT時）、高於（如：對^^型電晶體或不同的基 準參考電壓VPOT時）或大致等於（如：以上述的比較或 邊緣觸發方式判斷時）一參考電壓位準，於上述條件達 時，差異比較電路32即輸出控制信號VCTX以關閉 動電路31。故基準參考電壓乂]?〇了除了可以是後級、亟驅 元件33應用之參考電壓位準’也可以是電源電壓v破驅動 電路共地VSS，或被驅動元件33的汲極電壓（咯、〇〇、 件為導通狀態時，相當於電源電壓VDD或接 ％ 極電壓（即電源電壓VDD或電路共地vss)。 整預設參考位準VREF即可達到上述本發明之目讀 第四圖顯示第三圖之閉極驅動電路31第〜你的。 電路示意圖，其依據資料輸人信號VIN反向輪 #號VOUT並用以驅動p型功率電晶體。電晶桃阳技趣_ &麻、/〜&____ u !髮 要鋼 4〇、 41 200905436 構成主要驅動級’依據資料輸入信號VIN反向輸出閘極驅 動信號VOUT ’電晶體42形成一控制級，依據控制信號 VCTL使該閘極驅動電路31作邏輯相乘（Logic and)。配 合參考第三圖’當資料輸入信號VIN為邏輯低態時，電晶 體41為導通狀態、電晶體40為截止狀態’故閘極驅動信 號VOUT為邏輯南態。此時差異放大電路321輸出的電壓 差異彳§號VD為低準位而小於預設參考位準vref，因此控 制信號VCTL為邏輯高態。當控制信號VCtl為邏輯高態 時’主要轉級正常動作，依據資料輸人錢vin反向輸 t問極驅動信號V〇UT。當資料輸人信號VIN為邏輯高態 %’電晶體41為截止狀態、電a曰辦仙炎、曾 極驅動信號卿Τ日體4G轉桃態，故間 VOUT低至H Γ ~低態。當間極驅動信號 VOUT低至小於基準參考電壓νρ〇 兩The active circuit of the present invention will be described in detail below with reference to the drawings. The spirit of the present invention is that the (4) pole drive signal causes the gate drive signal to reach a state when the drive state is driven. When the gate drive signal reaches the output level of -駄, the level is turned off. The circuit 'has the advantage that the gate drive signal is boxed at the predetermined output when the predetermined output is driven without the conventional technique of clamping. & also achieves the second diagram of the active voltage clamp gate drive circuit of the present invention. As shown in the figure, the active voltage clamping gate driving circuit forcing the gate driving circuit 31 provides the 依据 according to the data input signal vin, and drives the rear driven component 33 with the driving signal VOUT'. The reference voltage level applied by the driving component 33 is the reference reference power, and the latter stage is simultaneously generated by a difference comparison circuit 32 according to a reference reference power and the wheel gate driving signal νουτ to generate the gate driving circuit 3l Vi> The signal vCTL; a, the difference comparison circuit 32 is composed of a differentially amplified clamp 2-bit comparison circuit 322; the differential amplifier circuit 321 321 321 reference voltage VP0T and the output gate drive signal ν 〇υ τ 1 1 1 01 01 The different signal VD is further compared with the preset reference level VREF via the level comparison circuit 322 to generate the control signal VCTL of the alarm circuit 3 i. When the difference between the difference M VD and the preset reference level VREF reaches a fixed value, that is, when the voltage difference between the reference reference voltage VP0T and the turn-off gate drive signal ν〇υτ reaches the preset reference level VREF, the level The comparison circuit cuts a control signal VCTL to turn off the gate driving circuit 31. At this time, the gate driving circuit 31 maintains the level of the gate driving signal ν〇υτ due to the shutdown, so that the clamped output gate voltage signal VOUT voltage level is reached. Quasi, as well as the purpose of low steady state DC current and low power consumption. The above reference voltage VPOT is used to determine whether the gate drive signal VOUT is lower than (for a p-type transistor or a different reference voltage VPOT), higher than (eg, for a ^^ transistor or different) When the reference voltage reference voltage VPOT is substantially equal to (for example, when the above comparison or edge trigger mode is determined) a reference voltage level, when the above condition is reached, the difference comparison circuit 32 outputs the control signal VCTX to turn off the dynamic circuit 31. . Therefore, the reference voltage 乂] 〇 除了 除了 可以 可以 可以 可以 后 后 后 后 后 后 后 后 后 后 后 应用 应用 应用 应用 应用 应用 应用 应用 应用 应用 应用 应用 应用 应用 应用 应用 电源 电源 电源 电源 电源 电源 电源 电源 电源 电源 电源 电源 电源When the device is in the on state, it is equivalent to the power supply voltage VDD or the terminal voltage (ie, the power supply voltage VDD or the circuit common ground vss). The preset reference level VREF can reach the above-mentioned fourth reading of the present invention. The figure shows the closed-circuit driving circuit 31 of the third figure. Your circuit diagram, which is based on the data input signal VIN reverse wheel #VOUT and used to drive the p-type power transistor. The electric crystal Taoyang skill _ & Hemp, /~&____ u! hair steel 4〇, 41 200905436 constitutes the main drive stage 'based on the data input signal VIN reverse output gate drive signal VOUT 'transistor 42 forms a control level, according to the control signal VCTL The gate driving circuit 31 performs logic multiplication (Logic and). Referring to the third figure, when the data input signal VIN is in a logic low state, the transistor 41 is in an on state, and the transistor 40 is in an off state, so the gate driving signal is VOUT is a logical south state At this time, the voltage difference 彳§ VD outputted by the differential amplifying circuit 321 is a low level and less than the preset reference level vref, so the control signal VCTL is a logic high state. When the control signal VCtl is a logic high state, the main transition Normal action, according to the data input money vin reverse input t-polar drive signal V〇UT. When the data input signal VIN is logic high state%' transistor 41 is off state, electricity a 曰 仙 炎 、, Zengji drive The signal is Τ Τ 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
大於預設參考位準VREF時吏^差異㈣VD 態。如上述，當資料輸入传㈣VCTL轉為邏輯低 41 ± 儿m為邏輯高態時，電晶體 41為截止狀恝，此時控制信號 。了 電晶體42也為截止狀態， 孔麵輯低態時，使得 容作充放電動作。如此即可維元件的閘極寄生電 VOUT於-預定的驅動準位而避即柑制）閘極驅動信號 亦可減少習## % > 免被驅動元件33之崩潰， 錢辑出所造成之功率 弟立圖顯示第 電路示意圖，其依據資料輸入信號 信號VOUT並用以驅動p型功率^ 31第二實施例之 正向輸出閘極驅動 。電晶體510、511、 200905436 512、513、514構成前級驅動電路51，其中，電晶體510、 512、513為主要驅動级，電晶體511、514為控制級。電 晶體521、522構成後級驅動電路52。電晶體521係接收 前級驅動電路51所產生之驅動信號DRVP，電晶體522係 接收前級驅動電路51所產生之驅動信號DRVN。後級驅動 電路52的電晶體521、522根據驅動信號DRVP及驅動信 號DRVN而共同產生輸出閘極驅動信號VOUT。當資料輸 入信號VIN為邏輯高態時’疋向輪出邏輯高態之閘極驅動 信號VOUT使被驅動元件為截止狀態。此時控制信號VCTL 為代表「非關閉」的邏輯低態時，使閘極驅動電路31正常 動作。此時前級驅動電路51驅動信號DRVP以及DRVN 直接受資料輸入信號VIN控制，以驅動後級驅動電路52， 因此輸出閘極驅動信號νουτ依據資料輸入信號VIN正向 輸出。當資料輸入信號VIN為邏輯低態時，正向輸出邏輯 低態之閘極驅動信號VOUT使被驅動元件為導通狀態。當 間極驅動信號VOUT低於一預定範圍時，差異比較電路32 將輸出代表「關閉」邏輯高態之控制信號VCTL。控制信 號VCTL為邏輯高態，故前級驅動電路51驅動信號DRVN 因電b曰體511的導通而會固定輸出邏輯低態，而使後級驅 動電路52之電晶體522為戴止狀態，前級驅動電路51驅 動信號DRVP則因電晶體5丨4為截止狀態，而直接受資料 輸入信號VIN控制。此時資料輸入信號VIN為邏輯低態， 驅動信號DRVP為邏輯高態而使後級驅動電路52之曰" 591 , \电日曰體 也為截止狀態。由於後級驅動電路52的電晶體521 ' 200905436 522均為截止狀態，停止對被驅動元件的閘極寄生電容作 充放電動作。如此即可維持（即箝制）閘極驅動信號VOUT 於一預定的驅動準位。 當然，除了 P型功率電晶體會因閘極驅動信號VOUT 過低而有崩潰之虞，N型功率電晶體亦會因閘極驅動信號 VOUT過高而也有崩潰之虞。以下閘極驅動電路之實施例 係用以驅動N型功率電晶體，亦透過控制信號VCTL之控 制而可達到閘極驅動信號VOUT之電壓準位箝制之功能。 f ' 第六圖顯示第三圖之閘極驅動電路31第三實施例之 示意圖，其依據資料輸入信號VIN反向輸出閘極驅動信號 VOUT並用以驅動N型功率電晶體。電晶體60、61構成主 要驅動級，依據資料輸入信號VIN反向輸出閘極驅動信號 VOUT，電晶體62形成一控制級，依據控制信號VCTL使 該閘極驅動電路31作邏輯相乘（Logic AND)。當資料輸入 信號VIN為邏輯高態時，電晶體60為導通狀態、電晶體 (, 61為截止狀態，故閘極驅動信號VOUT為邏輯低態使被驅 動元件為截止狀態。此時被驅動元件無崩潰之虞，故控制 信號VCTL為代表「非關閉」之邏輯低態，閘極驅動電路 31正常動作。當資料輸入信號VIN為邏輯低態時，電晶體 61為導通狀態、電晶體60為截止狀態，故閘極驅動信號 VOUT轉為邏輯高態使被驅動元件開始導通。當閘極驅動 信號VOUT上升至高於一預定準位時，控制信號VCTL轉 為代表「關閉」之邏輯高態，使電晶體62為截止狀態，以 關閉閘極驅動電路31。如此，停止對被驅動元件的閘極寄 11 200905436 生電容作充放電動作而達到箝制功能。 第七圖顯示第三圖之閘極驅動電路31第四實施例之 示意圖，其依據資料輸入信號VIN正向輸出閘極驅動信號 VOUT並用以驅動N型功率電晶體。電晶體710、711、712、 713、714構成前級驅動電路71，其中，電晶體710、712、 714為主要驅動級，電晶體71卜713為控制級。電晶體721、 72 2構成後級驅動電路7 2 ,電晶體7 21係接收前級驅動電 路71驅動信號DRVP，電晶體722係接收前級驅動電路71 驅動信號DRVN，共同產生輸出閘極驅動信號VOUT。當 控制信號VCTL為邏輯高態時，閘極驅動電路31正常動作 ，前級驅動電路71驅動信號DRVP以及DRVN直接受資料 輸入信號VIN控制，用以驅動後級驅動電路72，因此輸出 閘極驅動信號VOUT依據資料輸入信號VIN正向輸出。當 控制信號VCTL為邏輯低態時，前級驅動電路71驅動信號 DRVP會固定輸出邏輯高態，使得後級驅動電路72電晶體 721為截止狀態，前級驅動電路71驅動信號DRVN則直接 受資料輸入信號VIN控制而為邏輯低態，後級驅動電路72 電晶體722亦為截止狀態，停止對後級被驅動元件對電路 共地VSS作充電。如此即可維持（即箝制）閘極驅動信號 VOUT於一預定的驅動準位。 接下來以實施例說明差異比較電路之運作。 第八圖顯示第三圖之差異比較電路32第一實施例之 不意圖’用以控制P型功率電晶體之驅動。電晶體81構成 一差異放大電路321，該電源電壓VDD為前述基準參考電 12 200905436 壓 VPOT。雷 Kn。。 νηη ^ ^ ^ 以及電流源86構成一參考於電源電壓 vdd-Λ電壓位^VREF，該參考電麗位準為：VREF = 1 R1。電晶體82，84構成電流鏡，與電晶體83， 以及电阻85 ’電流源86，纽參考電流源卿， 比較⑽構成位準比較電路322,其中，電壓比較器如 知之運算放大器實現。電晶體81依據輸出閘極驅動 :“νουτ構成一輸出電流源職。當輸出閘極驅動信 號v<^大於參考電壓位準VREF時，輸出電流源謂T 小於，考電流源IREF，使得類比信藏DET小於類比信號 NOR，此時電壓比較器8Q輸出控制信號Μ:為邏輯高態 。當輸出閘極驅動信號ν〇υτ小於參考電壓位準丽時， 輸出電流源IOUT大於表去★泣 一 翏考私流源IREF,使得類比信號 DET面於舰㈣MIR，此時電壓比㈣ 號VCTL為邏輯低態。在此竇 隹此貝施例中，控制信號VCTL為大于^ difference (4) VD state when it is greater than the preset reference level VREF. As described above, when the data input transmission (4) VCTL is turned to logic low 41 ± m is a logic high state, the transistor 41 is turned off, and the signal is controlled at this time. The transistor 42 is also in an off state, and when the hole surface is in a low state, it is allowed to perform a charge and discharge operation. In this way, the gate parasitic electric power VOUT of the dimension element can be avoided at a predetermined driving level, and the gate driving signal can also be reduced. ## % > The drive element 33 is not collapsed, and the money is produced. The power brother diagram shows a schematic circuit diagram based on the data input signal signal VOUT and used to drive the positive output gate drive of the p-type power transistor. The transistors 510, 511, 200905436 512, 513, 514 constitute the front stage drive circuit 51, wherein the transistors 510, 512, 513 are the main drive stages and the transistors 511, 514 are the control stages. The transistors 521, 522 constitute a rear stage drive circuit 52. The transistor 521 receives the drive signal DRVP generated by the pre-drive circuit 51, and the transistor 522 receives the drive signal DRVN generated by the pre-drive circuit 51. The transistors 521, 522 of the subsequent stage drive circuit 52 collectively generate an output gate drive signal VOUT based on the drive signal DRVP and the drive signal DRVN. When the data input signal VIN is in a logic high state, the gate drive signal VOUT is turned to a logic high state to turn off the driven component. At this time, when the control signal VCTL is in a logic low state representing "non-off", the gate driving circuit 31 is normally operated. At this time, the driving signals DRVP and DRVN of the preceding stage driving circuit 51 are directly controlled by the data input signal VIN to drive the subsequent stage driving circuit 52, so that the output gate driving signal νουτ is outputted in the forward direction according to the data input signal VIN. When the data input signal VIN is in a logic low state, the gate drive signal VOUT of the forward output logic low state causes the driven component to be in an on state. When the inter-level drive signal VOUT is below a predetermined range, the difference comparison circuit 32 will output a control signal VCTL representative of the "off" logic high state. The control signal VCTL is in a logic high state. Therefore, the driving signal DRVN of the pre-stage driving circuit 51 is fixed to output a logic low state due to the conduction of the battery block 511, and the transistor 522 of the subsequent stage driving circuit 52 is in a wearing state. The stage drive circuit 51 drive signal DRVP is directly controlled by the data input signal VIN because the transistor 5丨4 is in an off state. At this time, the data input signal VIN is in a logic low state, and the driving signal DRVP is in a logic high state, so that the rear stage driving circuit 52 is also "off". Since the transistors 521 ' 200905436 522 of the subsequent stage drive circuit 52 are both turned off, the charge and discharge operation of the gate parasitic capacitance of the driven element is stopped. Thus, the gate drive signal VOUT can be maintained (i.e., clamped) at a predetermined drive level. Of course, except that the P-type power transistor will collapse due to the gate drive signal VOUT being too low, the N-type power transistor will also collapse due to the gate drive signal VOUT being too high. The following embodiment of the gate driving circuit is used to drive the N-type power transistor, and the voltage level clamping function of the gate driving signal VOUT can also be achieved by the control of the control signal VCTL. f' Fig. 6 is a view showing a third embodiment of the gate driving circuit 31 of the third figure, which outputs the gate driving signal VOUT in reverse according to the data input signal VIN and is used to drive the N-type power transistor. The transistors 60, 61 constitute a main driving stage, and the gate driving signal VOUT is inverted according to the data input signal VIN. The transistor 62 forms a control stage for logically multiplying the gate driving circuit 31 according to the control signal VCTL (Logic AND ). When the data input signal VIN is in a logic high state, the transistor 60 is in an on state and a transistor (61 is an off state), so the gate driving signal VOUT is in a logic low state to turn off the driven component. There is no crash, so the control signal VCTL is a logic low state representing "non-off", and the gate driving circuit 31 operates normally. When the data input signal VIN is in a logic low state, the transistor 61 is in an on state, and the transistor 60 is in a state of In the off state, the gate drive signal VOUT transitions to a logic high state to cause the driven component to begin to conduct. When the gate drive signal VOUT rises above a predetermined level, the control signal VCTL transitions to a logic high state representing "off". The transistor 62 is turned off to turn off the gate driving circuit 31. Thus, the charging of the gate of the driven element is stopped and the charging function is performed to achieve the clamping function. The seventh figure shows the gate of the third figure. A schematic diagram of the fourth embodiment of the driving circuit 31, which outputs a gate driving signal VOUT according to the data input signal VIN and drives the N-type power transistor. The transistors 710 and 711 712, 713, and 714 constitute a front stage driving circuit 71, wherein the transistors 710, 712, and 714 are main driving stages, and the transistors 71 and 713 are control stages. The transistors 721 and 72 2 constitute a rear stage driving circuit 7 2 , and the electric The crystal 7 21 receives the drive signal DRVP of the front stage drive circuit 71, and the transistor 722 receives the drive signal DRVN of the front stage drive circuit 71 to jointly generate the output gate drive signal VOUT. When the control signal VCTL is logic high, the gate drive The circuit 31 operates normally, and the driving signals DRVP and DRVN of the pre-stage driving circuit 71 are directly controlled by the data input signal VIN for driving the subsequent-stage driving circuit 72, so that the output gate driving signal VOUT is forwardly output according to the data input signal VIN. When the signal VCTL is in a logic low state, the driving signal DRVP of the pre-stage driving circuit 71 is fixed to the output logic high state, so that the transistor 721 of the subsequent stage driving circuit 72 is turned off, and the driving signal DRVN of the pre-stage driving circuit 71 is directly subjected to the data input signal. The VIN control is in a logic low state, and the rear stage driving circuit 72 transistor 722 is also in an off state, and stops charging the circuit VSS to the circuit driven element of the subsequent stage. Thus, the gate driving signal VOUT can be maintained (ie, clamped) at a predetermined driving level. Next, the operation of the difference comparison circuit will be described by way of an embodiment. The eighth figure shows the difference comparison circuit 32 of the third figure. It is not intended to 'control the driving of the P-type power transistor. The transistor 81 constitutes a differential amplifying circuit 321, which is the reference reference voltage 12 200905436 VPOT. Thunder Kn. νηη ^ ^ ^ and current source 86 The reference is made to the power supply voltage vdd-Λ voltage bit ^VREF, and the reference battery level is: VREF = 1 R1. The transistors 82, 84 form a current mirror, and the transistor 83, and the resistor 85' current source 86, the reference current source, and (10) constitute a level comparison circuit 322, wherein the voltage comparator is implemented as an operational amplifier. The transistor 81 is driven according to the output gate: "νουτ constitutes an output current source. When the output gate drive signal v<^ is greater than the reference voltage level VREF, the output current source T is smaller than the current source IREF, so that the analog signal The hidden DET is smaller than the analog signal NOR, at which time the voltage comparator 8Q outputs the control signal Μ: is a logic high state. When the output gate drive signal ν 〇υ τ is less than the reference voltage level, the output current source IOUT is greater than the table. Referring to the private flow source IREF, the analog signal DET is in the ship (four) MIR, and the voltage is lower than the (IV) VCTL. In this case, the control signal VCTL is
邏輯咼恝，控制閘極驅動電路3 1 H ^ ^ 正吊動作，而當控制信號 VCTL為雜低悲，控制閘極驅動電路31關閉。 第九圖顯示第三圖之差異比較電路32第二實施例之 示意圖，用：控制ρ型功率電晶體之驅動。電晶體91構成 一差異放大電路321，該電源雪厭 壓礙。電阻95以及電 為前述基準參考電 久％机原96構成一參考 垂之參考電麼位準VREF， / W包源 VDD-I1*R〗。電晶體92，94構^ K位準為.VREF：=； 以及電阻95，電流源96，產生與電晶體％， 比較器90構成位準比較電路切考甘電流源卿，與電壓 z ’其中’電壓比較器90 13 200905436 可以習知之運算放大器實現。略曰 信號νουτ構成-輸出電^ 日_ 91依據輪出閘極驅動 號VOUT大於參考電壓位準ν 田翰出閘極驅動信 小於參考電流源IREF，使得麵t丄，輸出電流源IOUT MIR，此時電壓比較器9〇輪出 ，DET小於類比信號 。當輸出閘極驅動信號v〇uT ,制^ ?虎VCTL為邏輯低態 ，輸出電流源IOUT大於參考；/考包壓位準VREF時 DET高於類比信號MIR ,此IREF ’使得類比信號 號VCTL為邏輯高態。在此匕較器9〇輸出控制信 邏輯低態，控制閘極驅動電略二J控制信號％孔為 ML為邏輯高態，控糊1 =動作’ Μ控制信號 第十圖顯示第三圖之差==路31關閉。 干音岡異比較電路32第三實施例之 不忍圖，用以控制N型功率 成—差異放大雷路321，^ 驅動。電晶體102構 電壓v °xt路共地VSS為前述基準參考 ^:而。電阻⑽以及電流㈣6構成一參考於電路 考電壓位準VREF，該參考電壓位準為™F “卜電晶體101 ’ 103構成電流鏡，與電晶體1〇4，以 及電阻105 ’電流源1〇6，產生參考電流源〗REF，與電壓 ，較器1〇〇構成位準比較電路322，其中，電壓比較器1〇〇 可以習知之運算放大器實現。電晶體102依據輸出閘極驅 動^就νουτ構成一輸出電流源I0UT。當輸出閘極驅動 仏號VOUT小於參考壓降vREF時，輸出電流源IOUT小 於參考電流源IREF，使得類比信號DET大於類比信號MIR ，此時電壓比較器1〇〇輸出控制信號VCTX為邏輯低態。 14 200905436 當輸出閘極驅動信號νουτ大於參考—位準vref時， 輸出電流源IOUT大於參考電洁满iRpp 可包"11•源iKEF ’使得類比信號 DET低於類比信號MIR，此時電壓比较器⑽輸出控制信 號VCTL為邏輯高態。在此實施例巾，控制信號似[為 邏輯低態’控制閘極驅動電路31正當叙〜* VCTL為邏輯兩態，控制閘極驅動電路3丨關閉。 帛十-圖顯示第三圖之差異比較電路32第四實施例 f 之示意圖，用以控制Ν型功率電晶體之驅動。電曰體ιΐ2 構成-差異放大電路32卜該電路共地卿為^基準參 考電壓wot。電阻115以及電流源116才舞成一參考於電 路共地VSS之參考電壓位準VREF，該參考電壓位準為： VREF = I1*IU。電晶體lu，113構成電流鏡，與電晶體 114，以及電阻；115，電流调IK,姦斗办土 & 原116產生參考電流源IREF， 與電壓比較器110構成位準比較電路322，其中，電壓比 ,較器⑽可以習知之運算放大器實現。電晶體112依^ I 出閘極驅動信號VOUT構成一輸出電流源Ι〇υτ。當輸出 閘極驅動信號VOUT小於參考壓降VREF時，輸出電流源 IOUT小於參考電流源IREF，使得類比信號det大於類比 信號MIR，此時電壓比較器110輸出控制信號VCTL為邏 輯咼態。當輸出閘極驅動信號ν〇υτ大於參考電壓位^ VREF時，輸出電流源ι0υτ大於參考電流源汉，使得 類比信號DET低於類比信號MIR，此時電壓比較器輸 出控制信號VCTL為邏輯低態。在此實施例中，控°制信^ VCTL為邏輯高態，控制閘極驅動電路31正常動作，而當 15 200905436 控制信號VCTL為邏輯低態，控制閘極驅動電路31關閉。 弟十二圖為本發明主動式電壓粉制閘極驅動電路3 0 ’ 應用於驅動P型功率電晶體123實施例一之詳細電路圖。 閘極驅動電路121與第四圖相同，差異比較電路122與第 八圖相同。當資料輸入信號VIN為邏輯低態時，閘極驅動 電路121中，電晶體41為導通狀態，電晶體40為截止狀 態，使得輸出閘極驅動信號VOUT為邏輯高態，亦即對被 驅動元件123對電路共地作充電。輸出閘極驅動信號VOUT 電壓位準與電源電壓VDD相同，使得差異比較電路122 輸出控制信號VCTL為邏輯高態，電晶體42為導通狀態。 當資料輸入信號VIN轉態為邏輯高態時，閘極驅動電路121 中，電晶體41為截止狀態，電晶體40、42為導通狀態， 使得輸出閘極驅動信號VOUT轉態為邏輯低態，亦即對被 驅動元件123對電路共地作放電。而當輸出閘極驅動信號 VOUT電壓位準降低至參考電壓位準VREF時，差異比較 電路122輸出控制信號VCTL轉態為邏輯低態，使得閘極 驅動電路121中之電晶體42為截止狀態，此時閘極驅動電 路121停止對被驅動元件123對電路共地作放電，使得輸 出閘極驅動信號VOUT不再作變動，而達到箝制輸出閘極 驅動信號VOUT的目的，同時亦無箝制時之穩態直流電流 〇 第十三圖為本發明主動式電壓箝制閘極驅動電路3 0 ”， 應用於驅動P型功率電晶體133實施例二之詳細電路圖。 閘極驅動電路131與第五圖相同，差異比較電路132與第 16 200905436 九圖相同。當資料輸入4s说VIN轉悲為迷輯高態時，閘極 驅動電路131中，電晶體510、512、514、521為導通狀轉， 電晶體511、513、522為截止狀態，使得輪出閘極驅動信 號VOUT為邏輯高態，亦即對被驅動元件133對電路共地 作充電。輸出間極驅動#號νουτ電麗位準與電源電壓 VDD相同，使得差異比較電路132輸出控制信號vctl為 邏輯低態。當資料輸入信號VIN轉態為邏輯低態時，閘極 驅勤電路131中，電晶體513、514、522為導通狀態，電 晶體510、51卜512、521為截止狀態，使得輸出閘極驅動 信號νουτ轉態為邏輯低態，亦即對被驅動元件133對電 路共地作放電。而當輸出閘極驅動信號VOUT電壓位準降 低至低於參考電壓位準VREF㈠·，差異比較電路η]輸出 控制信號VCTL轉態為邏輯高態，使得閘極驅動電路131 中’電晶體514為截止狀態’電晶體511為導通狀態，使 得電晶體522也為截止狀態’此時閘極驅動電路13ι停止 對被驅動元件133對電路共地作放電，使得輸出閘極驅動 信號VOUT不再作變動，而達到箝制輸出閘極驅動信號 VOUT的目的，同時亦無箝制時之穩態直流電流。 第十四圖為本發明主動式電壓轉制閘極驅動電路3〇，，， ，應用於驅動N型功率電晶體143貧施例一之詳細電路圖 。閘極驅動電路141與第6圖相同’差異比較電路142與 第10圖相同。當資料輸入信號VIN為邏輯高態時，閘極 驅動電路141中’電晶體60為導通狀態，電晶體61為截 止狀態，使得輸出閘極驅動信號ν〇ϋτ為邏輯低態，亦即 17 200905436 共地作放電。輸出間極驅動信號 _==::Γ同’使得差異比較電路 離。者資料於”U 為抑低態，電晶體62為導通狀 ;二Γ!入信號VIN轉態為邏輯低態時，間極驅動電 卜晶體6〇為截止狀態，電晶體61、62為導通 /極驅動信號vou^態為邏輯高態，亦 動ΐΐ=Γ對電路共地作充電。而當輪出間極驅 t壓㈣提升至參考電壓位準vref時，差 輪出控制信號化几轉態為邏輯高態，使 …路141中’電晶體62為截止狀態。此時閘極 °動電路141停止對被驅動元件143對電路共地作充電， =得輸出閘極驅動信號ν〇υτ不再作變動，而達到箱制輸 流=驅動信號V0UT的目的，同時亦無籍制時之穩態直 第十五圖為本發明主動式電壓箝制閘極驅動電路3 〇，，，, η«用於驅動N型功率電晶體153實施例二之詳細電路圖 y雜驅動電路151與第7圖相同，差異比較電路152與 第十目相同。當資料輸人信號VIN轉態為邏輯低態時， 閘，驅動電路151中，電晶體711、712、714、722為導通 狀H日日體71〇、713、721為截止狀態，使得輸出間極 驅動信號VOUT為邏輯低態，亦即對被驅動元件153對電 路共地作放電。輪出閘極驅動信號VOUT電壓位準與電路 、也VSS相同，使得差異比較電路152輸出控制信號vctl 為邏輯高態。當資料輸入信號VIN轉態為遴輯高態時，閘 200905436 極驅動電路151中，電晶體710、711、721為導通狀態， 電晶體712、713、714、722為截止狀態，使得輸出閘極驅 動信號VOUT轉態為邏輯高態，亦即對被驅動元件153對 電路共地作充電。而當輸出閘極驅動信號VOUT電壓位準 提升至參考電壓位準VREF時，差異比較電路152輸出控 制信號VCTL轉態為邏輯低態，使得閘極驅動電路151中 ，電晶體711為截止狀態，電晶體713為導通狀態，而使 電晶體721為截止狀態。此時閘極驅動電路151停止對被 驅動元件153對電路共地作充電，使得輸出閘極驅動信號 VOUT不再作變動，而達到箝制輸出閘極驅動信號VOUT 的目的，同時亦無箝制時之穩態直流電流。 以上雖以實施例說明本發明，但並不因此限定本發明 之範圍，只要不脫離本發明之要旨，該行業者可進行各種 變形或變更。 【圖式簡單說明】 第一圖為習知應用基納二極體於驅動P型功率電晶體 實現電壓箝制之電路圖。 第二圖為習知應用線性穩壓器於驅動P型功率電晶體 實現電壓箝制之電路圖。 第三圖為本發明主動式電壓箝制閘極驅動電路。 第四圖顯示第三圖之閘極驅動電路31第一實施例之 示意圖。 第五圖顯示第三圖之閘極驅動電路31第二實施例之 19 200905436 示意圖。 第六圖顯示第三圖之閘極驅動電路31第三實施例之 示意圖。 第七圖顯示第三圖之閘極驅動電路31第四實施例之 示意圖。 第八圖顯示第三圖之差異比較電路32第一實施例之 示意圖。 第九圖顯示第三圖之差異比較電路32第二實施例之 示意圖。 第十圖顯示第三圖之差異比較電路32第三實施例之 示意圖。 第十一圖顯示第三圖之差異比較電路32第四實施例 之示意圖。 第十二圖為本發明主動式電壓箝制閘極驅動電路應用 於驅動P型功率電晶體實施例一之詳細電路圖。 第十三圖為本發明主動式電壓箝制閘極驅動電路應用 於驅動P型功率電晶體實施例二之詳細電路圖。 第十四圖為本發明主動式電壓箝制閘極驅動電路應用 於驅動N型功率電晶體實施例一之詳細電路圖。 第十五圖為本發明主動式電壓箝制閘極驅動電路應用 於驅動N型功率電晶體實施例二之詳細電路圖。 【主要元件符號說明】 10、20、30 主動式電壓箝制閘極驅動電路 20 200905436 11 > 21 > 31 閘極驅動電路 12 基納二極體 22 線性穩壓器 23 穩壓電容 32 差異比較電路 321 差異放大電路 322 位準比較電路 40、41 ' 42 電晶體 51 前級驅動電路 52 後級驅動電路 510 、 512 、 513 、 514 ' 521 ' 522 60 > 61 > 62 電晶體 71 前級驅動電路 72 後級驅動電路 710 、 712 、 713 、 714、721、722 80 電壓比較器 81 、 82 、 83 、 84 電晶體 85 參考電阻 86 參考電流源 90 電壓比較器 91 、 92 ' 93 ' 94 電晶體 95 參考電阻 96 參考電流源 100 電壓比較器 電晶體 電晶體 21 200905436 101 、 102 、 103 、 105 106 110 111 、 112 、 113 、 115 116 121 122 123 131 132 133 141 142 143 151 152 153 104電壓電晶體 參考電阻 參考電流源 電壓比較器 114電晶體 參考電阻 參考電流源 閘極驅動電路 差異比較電路 P型功率電晶體 閘極驅動電路 差異比較電路 P型功率電晶體 閘極驅動電路 差異比較電路 N型功率電晶體 閘極驅動電路 差異比較電路 N型功率電晶體 22Logic 咼恝, the gate drive circuit 3 1 H ^ ^ is hoisted, and when the control signal VCTL is low, the control gate drive circuit 31 is turned off. The ninth drawing shows a schematic view of the second embodiment of the difference comparison circuit 32 of the third figure for controlling the driving of the p-type power transistor. The transistor 91 constitutes a differential amplifying circuit 321, which is incapable of being impeded. The resistor 95 and the power supply form a reference for the reference reference voltage source 96, which is a reference reference voltage VREF, / W packet source VDD-I1*R. The transistors 92, 94 have a K-position of .VREF:=; and a resistor 95, a current source 96, which is generated with the transistor %, and a comparator 90 constitutes a level comparison circuit to cut the current source, and the voltage z' 'Voltage comparator 90 13 200905436 can be implemented by conventional operational amplifiers. Slightly 曰 signal νουτ constitutes - output electric ^ _ 91 according to the wheel drive drive number VOUT is greater than the reference voltage level ν Tian Han gate drive letter is less than the reference current source IREF, so that the surface t 丄, the output current source IOUT MIR, At this time, the voltage comparator 9 turns out, and the DET is smaller than the analog signal. When the output gate drive signal v〇uT, the system VCTL is logic low state, the output current source IOUT is greater than the reference; / the test packet pressure level VREF when the DET is higher than the analog signal MIR, this IREF ' makes the analog signal number VCTL It is a logic high state. In this case, the output control signal logic low state, the control gate drive power slightly J control signal % hole is ML is logic high state, control paste 1 = action ' Μ control signal tenth figure shows the third figure Poor == Road 31 is off. The third embodiment of the dry-tone analog comparison circuit 32 does not endure the picture, and is used to control the N-type power into a differential amplification radar 321 , ^ drive. The transistor 102 has a voltage v °xt path common to VSS as the aforementioned reference reference ^:. The resistor (10) and the current (4) 6 constitute a reference to the circuit test voltage level VREF, which is the TMF "the transistor 101' 103 constitutes a current mirror, and the transistor 1〇4, and the resistor 105' current source 1〇 6, the reference current source REF is generated, and the voltage comparator 〇〇 constitutes a level comparison circuit 322, wherein the voltage comparator 1 〇〇 can be implemented by a conventional operational amplifier. The transistor 102 is driven according to the output gate ^ νουτ Forming an output current source IOUT. When the output gate drive 仏VOUT is less than the reference voltage drop vREF, the output current source IOUT is smaller than the reference current source IREF, so that the analog signal DET is greater than the analog signal MIR, and the voltage comparator 1 〇〇 output The control signal VCTX is logic low. 14 200905436 When the output gate drive signal νουτ is greater than the reference-level vref, the output current source IOUT is greater than the reference power supply full iRpp can be packaged "11•source iKEF' makes the analog signal DET lower than Analog signal MIR, at this time the voltage comparator (10) outputs the control signal VCTL to a logic high state. In this embodiment, the control signal looks like [for logic low state] control gate drive The circuit 31 is justified as follows: * The VCTL is in a logic two state, and the control gate drive circuit 3 is turned off. The figure 10 shows a schematic diagram of the fourth embodiment f of the difference comparison circuit 32 of the third figure for controlling the 功率 type power transistor The driving of the electric body ιΐ2 constitutes a differential amplifying circuit 32. The circuit is a reference voltage wt. The resistor 115 and the current source 116 are danced to a reference voltage level VREF of the circuit common ground VSS. The voltage level is: VREF = I1*IU. The transistor lu, 113 constitutes the current mirror, and the transistor 114, and the resistor; 115, the current is adjusted to IK, the smuggling soil & the original 116 generates the reference current source IREF, and the voltage The comparator 110 constitutes a level comparison circuit 322, wherein the voltage ratio is implemented by a conventional operational amplifier (10). The transistor 112 forms an output current source Ι〇υτ according to the gate drive signal VOUT. When the driving signal VOUT is less than the reference voltage drop VREF, the output current source IOUT is smaller than the reference current source IREF, so that the analog signal det is greater than the analog signal MIR, and the voltage comparator 110 outputs the control signal VCTL to the logical state. When the gate drive signal ν〇υτ is greater than the reference voltage bit ^VREF, the output current source ι0υτ is greater than the reference current source, so that the analog signal DET is lower than the analog signal MIR, and the voltage comparator output control signal VCTL is logic low. In this embodiment, the control signal VC VC is in a logic high state, and the gate driving circuit 31 is controlled to operate normally. When the 15 200905436 control signal VCTL is in a logic low state, the control gate driving circuit 31 is turned off. 12 is a detailed circuit diagram of the first embodiment of the active voltage powder gate driving circuit 3 0 ' applied to drive the P-type power transistor 123. The gate driving circuit 121 is the same as the fourth figure, and the difference comparing circuit 122 is the same as that of the eighth drawing. When the data input signal VIN is in a logic low state, in the gate driving circuit 121, the transistor 41 is in an on state, and the transistor 40 is in an off state, so that the output gate driving signal VOUT is in a logic high state, that is, on the driven component. 123 pairs the circuit to charge. The output gate drive signal VOUT voltage level is the same as the power supply voltage VDD, so that the difference comparison circuit 122 outputs the control signal VCTL to a logic high state, and the transistor 42 is in an on state. When the data input signal VIN transitions to a logic high state, in the gate driving circuit 121, the transistor 41 is in an off state, and the transistors 40 and 42 are in an on state, so that the output gate driving signal VOUT is in a logic low state. That is, the driven element 123 is discharged to the circuit in common. When the output gate drive signal VOUT voltage level is lowered to the reference voltage level VREF, the difference comparison circuit 122 outputs the control signal VCTL to a logic low state, so that the transistor 42 in the gate drive circuit 121 is in an off state. At this time, the gate driving circuit 121 stops discharging the circuit to the driven component 123, so that the output gate driving signal VOUT is no longer changed, and the purpose of clamping the output gate driving signal VOUT is achieved, and there is no clamping time. The steady-state DC current 〇 thirteenth diagram is a detailed circuit diagram of the active voltage clamp gate drive circuit 3 0 ′′ of the present invention applied to drive the P-type power transistor 133. The gate drive circuit 131 is the same as the fifth diagram. The difference comparison circuit 132 is the same as the figure No. 16 200905436. When the data input 4s says that the VIN turns into a confusing high state, in the gate driving circuit 131, the transistors 510, 512, 514, and 521 are turned on, and the electricity is turned on. The crystals 511, 513, and 522 are in an off state, so that the turn-off gate drive signal VOUT is in a logic high state, that is, the drive element 133 is commonly charged to the circuit. The output interpole drive ##νο The τ 丽 位 level is the same as the power supply voltage VDD, so that the difference comparison circuit 132 outputs the control signal vctl to a logic low state. When the data input signal VIN transitions to a logic low state, the gate drive circuit 131, the transistor 513, 514, 522 are in an on state, and the transistors 510, 51, 512, and 521 are in an off state, so that the output gate drive signal νουτ is in a logic low state, that is, the driven element 133 is discharged to the circuit in common. The output gate drive signal VOUT voltage level is lowered to be lower than the reference voltage level VREF(1)·, and the difference comparison circuit η] outputs the control signal VCTL to a logic high state, so that the transistor 514 is turned off in the gate drive circuit 131. 'The transistor 511 is in an on state, so that the transistor 522 is also in an off state.' At this time, the gate driving circuit 13i stops discharging the circuit to the driven element 133, so that the output gate driving signal VOUT is no longer changed. The purpose of clamping the output gate drive signal VOUT is achieved, and there is no steady-state direct current at the time of clamping. The fourteenth embodiment is the active voltage-transfer gate drive circuit of the present invention. A detailed circuit diagram for driving the N-type power transistor 143. The gate driving circuit 141 is the same as the sixth drawing. The difference comparison circuit 142 is the same as the tenth figure. When the data input signal VIN is a logic high state In the gate driving circuit 141, the transistor 60 is in an on state, and the transistor 61 is in an off state, so that the output gate driving signal ν 〇ϋ τ is in a logic low state, that is, 17 200905436 is commonly discharged. The signal _==:: Γ the same 'make the difference comparison circuit away. The data is "U is the low state, the transistor 62 is conducting; the second Γ! input signal VIN transition to the logic low state, the interpole drive The transistor 6 is turned off, and the transistors 61 and 62 are in a logic high state for the on/off drive signal vou^ state, and the circuit is also charged to the circuit. When the wheel-to-pole voltage (4) is boosted to the reference voltage level vref, the differential wheeling control signal is turned into a logic high state, and the transistor 62 is turned off. At this time, the gate shifting circuit 141 stops charging the circuit to the driven component 143, and the output gate driving signal ν〇υτ is no longer changed, and the boxed current=drive signal VOUT is achieved. The fifteenth figure of the present invention is the active voltage clamped gate drive circuit 3 〇,,,, η« is used to drive the N-type power transistor 153. Circuit 151 is the same as Fig. 7, and difference comparison circuit 152 is the same as the tenth. When the data input signal VIN transitions to a logic low state, in the gate, the driving circuit 151, the transistors 711, 712, 714, and 722 are turned on, and the Japanese bodies 71, 713, and 721 are turned off, so that the output is between The pole drive signal VOUT is in a logic low state, that is, the drive element 153 is commonly discharged to the circuit. The turn-on gate drive signal VOUT voltage level is the same as the circuit, also VSS, such that the difference comparison circuit 152 outputs the control signal vctl to a logic high state. When the data input signal VIN transitions to the high state, in the gate 200905436 pole drive circuit 151, the transistors 710, 711, 721 are in an on state, and the transistors 712, 713, 714, 722 are in an off state, so that the output gate The drive signal VOUT transitions to a logic high state, that is, the drive element 153 charges the circuit in common. When the output gate drive signal VOUT voltage level is raised to the reference voltage level VREF, the difference comparison circuit 152 outputs the control signal VCTL to a logic low state, so that the transistor 711 is turned off in the gate drive circuit 151. The transistor 713 is in an on state, and the transistor 721 is in an off state. At this time, the gate driving circuit 151 stops charging the circuit to the driven component 153, so that the output gate driving signal VOUT is no longer changed, and the purpose of clamping the output gate driving signal VOUT is achieved, and there is no clamping time. Steady-state DC current. The present invention has been described above by way of examples, and the scope of the invention is not limited thereto, and various modifications and changes can be made by those skilled in the art without departing from the scope of the invention. [Simple description of the diagram] The first figure is a circuit diagram of a conventional application of a Kina diode to drive a P-type power transistor to achieve voltage clamping. The second figure is a circuit diagram of the conventional application of a linear regulator to drive a P-type power transistor to achieve voltage clamping. The third figure is the active voltage clamping gate driving circuit of the present invention. The fourth figure shows a schematic view of the first embodiment of the gate driving circuit 31 of the third figure. The fifth figure shows a schematic diagram of the second embodiment of the gate drive circuit 31 of the third figure, 19 200905436. Fig. 6 is a view showing a third embodiment of the gate driving circuit 31 of the third drawing. The seventh figure shows a schematic view of a fourth embodiment of the gate driving circuit 31 of the third figure. The eighth diagram shows a schematic view of the first embodiment of the difference comparison circuit 32 of the third figure. The ninth drawing shows a schematic view of a second embodiment of the difference comparison circuit 32 of the third figure. The tenth diagram shows a schematic view of a third embodiment of the difference comparison circuit 32 of the third figure. Fig. 11 is a view showing a fourth embodiment of the difference comparison circuit 32 of the third figure. Figure 12 is a detailed circuit diagram of the first embodiment of the present invention for driving a P-type power transistor according to the active voltage-clamping gate driving circuit of the present invention. Figure 13 is a detailed circuit diagram of the second embodiment of the active voltage clamping gate driving circuit of the present invention applied to drive a P-type power transistor. Figure 14 is a detailed circuit diagram of the first embodiment of the active voltage clamping gate driving circuit of the present invention applied to drive an N-type power transistor. The fifteenth figure is a detailed circuit diagram of the second embodiment of the active voltage clamping gate driving circuit of the present invention applied to the N-type power transistor. [Major component symbol description] 10, 20, 30 active voltage clamp gate drive circuit 20 200905436 11 > 21 > 31 gate drive circuit 12 kenna diode 22 linear regulator 23 voltage regulator capacitor 32 difference comparison Circuit 321 differential amplifier circuit 322 level comparison circuit 40, 41' 42 transistor 51 front stage drive circuit 52 rear stage drive circuit 510, 512, 513, 514 '521 '522 60 > 61 > 62 transistor 71 front stage Drive circuit 72 rear stage drive circuit 710, 712, 713, 714, 721, 722 80 voltage comparator 81, 82, 83, 84 transistor 85 reference resistor 86 reference current source 90 voltage comparator 91, 92 '93 ' 94 Crystal 95 Reference Resistor 96 Reference Current Source 100 Voltage Comparator Transistor Crystal 21 200905436 101 , 102 , 103 , 105 106 110 111 , 112 , 113 , 115 116 121 122 123 131 132 133 141 142 143 151 152 153 104 Voltage Crystal Reference Resistor Reference Current Source Voltage Comparator 114 Transistor Reference Resistor Reference Current Source Gate Drive Circuit Difference Comparison Circuit P-type Power Body gate driving circuit of comparison between P-type power circuit transistor gate driving circuit of comparison between the N-type power transistor circuit gate driving circuit of comparison between the N-type power transistor circuits 22