TW200904013A - Digital-to-analog converter and method thereof - Google Patents

Abstract

An integrated circuit may include an operation amplifier, a first capacitor, a plurality of second capacitors, and/or a switching circuit. The operational amplifier may have a first input terminal, a second input terminal, and/or an output terminal. The first capacitor may have a first terminal and a second terminal. The second terminal of the first capacitor may be connected to the first input terminal of the operational amplifier. The plurality of second capacitors may each have a first terminal and a second terminal. The second terminal of each of the second capacitors may be connected to the second input terminal of the operational amplifier. The switching circuit may include a plurality of switches configured to switch in response to a plurality of switching signals. The switching circuit may be configured to transmit a reference voltage to the first terminal of the first capacitor and the first terminals of the second capacitors and/or connect the first input terminal of the operational amplifier to the output terminal of the operational amplifier during a first period. The switching circuit maybe configured to isolate the first terminal of the first capacitor from the reference voltage, transmit a voltage selected from at least two selection voltages to the first terminals of the second capacitors, and/or connect the first terminal of the first capacitor to the output terminal of the operational amplifier during a second period.

Description

200904013 IX. Description of the Invention: TECHNICAL FIELD [0001] Example embodiments relate to digital to analog converters (DACs) and, for example, to DACs that drive source driver circuits of liquid crystal display (LCD) devices. This application is filed in Korea Patent Application No. 1〇_2〇07-005 2 798, filed on May 30, 2007 by the Korea Intellectual Property Office, and Korea filed on February 25, 2008. The benefit of the priority of the patent application, the entire disclosure of which is hereby incorporated by reference. [Prior Art] A digital to analog converter (DAC) is a core block that drives a source driver circuit of a liquid crystal display (LCD) device. Resistor-based Dac (r_ DAC) is commonly used in source driver circuits. Figure 1 illustrates a conventional R-DAC 100. The R-DAC 1 00 includes a resistor array 110, a decoder 12A, and an operational amplifier (〇p AMp) 13(). The resistor array 11 includes a plurality of resistors from a first R to a second R, which are connected in series to a first node receiving a first reference voltage Vref1 and a second receiving a second reference voltage Vref2 A plurality of voltages are generated between the nodes (where Vref2 < Vrefi). The decoder 1 selects a voltage from the plurality of voltages and outputs the selected voltage as a selection in response to a digit for displaying the full gray level 13⁄4. The voltage DECO. For example, the decoder 12 selects a voltage from the first line to the 2nth line (for example, metal) corresponding to the plurality of resistors, one R to the second. 131464.doc 200904013 It takes 28 (that is, 256) resistors and wires to convert 8-bit 7G digital data into 8-bit DAc of analog signal. Decoder 12〇 selects one from 256 voltages. The voltage is implemented by a 256-to-1 decoder. As the number of bits in the digital data increases, the number of resistors and voltage lines increases geometrically. For example, if the digital data is 1 unit, then 1G24 (ie '2, a resistor and voltage line to And give (5) solve the 'coder. Therefore, the size of the DAC increases. In order to reduce the size of the DAC', it is recommended to use the sampling and holding circuit of the switched capacitor as the DAC. The DAC using the switched capacitor can be divided into a linear DAC and a nonlinear DAC. The linear DAC has a linear output characteristic, so it is more difficult to properly represent the gamma curve of the LCD panel. Therefore, the nonlinear DAC is more suitable for representing the gamma curve of the LCD panel. To implement the switched capacitor DAC', the two reference voltages can be divided into plural a gray scale voltage, or a voltage applied to the capacitor can be converted based on a reference voltage, and the converted voltage can be output. However, the conventional switched capacitor 〇 DAC occupies a larger due to a more complicated structure of the capacitor and the switch. The area, and/or the conventional switched capacitor DAC, degrades the image quality due to the inter-channel deviation caused by the deviation of the reference voltage. SUMMARY OF THE INVENTION Example embodiments provide a digital to analog converter (DAC), and / Or including one of the digital to analog converter source driver and display device, the digital to analog converter occupies a smaller face Product, reduce inter-channel variation, and / / provide nonlinear characteristics of the gamma curve of a liquid crystal display (LCD) panel. ^ 131464.doc 200904013 According to the example embodiment - the integrated circuit can include - operational amplifier, - the first a capacitor, a plurality of second capacitors, and/or a switching circuit. The operational amplifier may have a -first input terminal, a second input terminal, and/or an output terminal. The first capacitor may have a first terminal And a second terminal of the first capacitor: the terminal of the first capacitor can be connected to the second terminal of the operational amplification, and the plurality of second capacitors can each have a first terminal and a second terminal. A second terminal of each of the second capacitors is connectable to a second input terminal of the passivation amplifier. The switching circuit can include a plurality of switches configured to switch in response to a plurality of switching signals. The switching circuit can be configured to transmit a reference voltage to a first terminal of the first capacitor and a second terminal of the second capacitor during a first time period and/or to input the operational amplifier The terminal is connected to the output terminal of the operational amplifier. The switching circuit can be configured to isolate a first terminal of the first capacitor from the reference (four) during a second time (four), and to transmit a voltage selected from the at least two selection voltages to the second capacitor

U $ a terminal and/or connecting the first terminal of the first capacitor to the output terminal of the operational amplifier. According to an example embodiment, the integrated circuit may comprise m and/or - a selection circuit. The divider can include an array of resistors coupled between the first node coupled to the -receive first reference and the second node receiving a second reference. The repeater can be configured to generate a plurality of divided electric houses by dividing a range between the second reference and the first reference. The selection circuit can be configured to select at least two powers from the plurality of divided electrical frequencies in response to the -digital signal and provide the selected electrical power 131464.doc -10.200904013 as the at least two Select the voltage. The first input terminal of the operational amplifier can be an inverting input terminal and the S input terminal of the operational amplifier can be a non-inverting input terminal. The digital signal can be part of the -n bit digital signal. According to an example embodiment, the reference voltage may be one of: the first reference voltage, the second reference voltage, an intermediate voltage between the first reference voltage and the second reference voltage, and / or one of the at least two selection voltages.

According to an example embodiment, the at least two selection voltages may include a first selection voltage and a second selection voltage lower than the first selection voltage. The switching circuit can include a first switch coupled between the first input terminal of the operational amplifier and an output terminal of the operational amplifier, and a second switch configured to selectively transmit the reference voltage a first terminal to the first electrical device; a third switch configured to selectively connect the first terminal of the first capacitor crying to an output terminal of the operational amplifier; and/or a plurality of a two-group switch configured to reference the reference voltage, first

The selection voltage and the second selection voltage are selectively transmitted to the capacitor. According to an example embodiment, the selection circuit can include at least two decoders. Each of the decoders is configurable to receive a portion of the divided electrical dust and to select a voltage from the divided voltage received in response to one of the first digital signals . The first selection voltage = the second selection voltage may be selected from the output signals of the at least two decoders. According to another example embodiment, a digital to analog conversion method J St includes: 131464.doc -11· 200904013 provides a reference power to a first input terminal connected to an operational amplifier during the -first period a capacitor and a plurality of second capacitors connected to the second input terminal of the operational amplifier, and the input terminal of the operational amplifier being connected to an output terminal of the operational amplifier. The method can include isolating the first capacitor from the reference voltage during a second time period, transmitting an electrical energy selected from the at least two selection voltages to each of the plurality of second capacitors, and The first terminal of the first capacitor is connected to the output terminal of the delta-half nasal amplifier. According to the example embodiment, the at least two selection voltages may be determined based on a first digit #, and the voltage transmitted to each of the plurality of second capacitors during the second period may be based on a The two-digit signal is fixed. According to an example embodiment, the first digit may consist of at least a south bit of the digit signal and the second digit signal may consist of at least one lower bit of the digit signal. The above and/or other aspects and advantages will become more apparent and easier to understand from the following detailed description of example embodiments. Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. However, the embodiment can be embodied in many different forms and should not be construed as being limited to the example embodiments described herein. Rather, these example embodiments are provided such that === will be comprehensive and complete and will convey the material to the skilled person. The thickness of the layer and the area may be exaggerated in the purpose of the "fourth type towel". 131464.doc •12· 200904013 It should be understood that when one component is referred to, on another component, "connected to" When coupled to another component, it may be directly on another component, connected to or coupled to another component, or an intervening component may exist. Conversely, when a component is referred to as "directly in another There is no intervening component when "," is directly connected to " or "directly coupled to " another component. As used herein, the term " and / or '' includes the associated items listed Any combination or combination of one or more of the items.

It will be understood that, although the terms "a", "the", "the", "the" Sections should not be limited by these terms. The terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer or section. Thus, a first element, component, layer, layer or section, which is discussed below, may be referred to as a second element 'component, region, layer or section without departing from the teachings of the example embodiments. For example, "below", ", under ".", "lower, .. above", ", upper, and the like" are used to describe one of the components illustrated in the figure or The relationship of another (or more) components or features of the feature disk. It should be understood that such spatial correlations are intended to cover different orientations in the use or operation other than those in the figure. In addition to the simplicity of the description of the heart 疋 π, can be used in this article (4) related surgery ff A " ΤΓ +丨丨丨丨丄y % 'above... The terminology used in this article is only a description The specific example embodiments are not intended to be limiting. As used herein, 7" and "the" are intended to include the 彳 彳 L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L When used, the term "includes" 131464.doc -13· 200904013 The handle: the characteristics, the whole, the steps 'operations, components and/or groups of children are 'but not excluded' or a number of other features, the whole , steps, work, 7L parts and / or components exist or add. ' "

(j Unless otherwise defined', all terms used in this document (including technology (4)) have the same meaning as commonly understood by the skilled artisans of the example embodiments. It should be further understood that the terms should be For example, the terms defined in the syllabus are interpreted as having meanings that are related to the meaning of the relevant technology, and should not be (iv) conceived or overly formal, _ unless Example embodiments are described herein with reference to the drawings, in which like reference numerals refer to the like, and the like, FIG. 2 illustrates a digital to analog converter (DAC) 2GG according to an example embodiment. An example timing diagram for a digital signal and a plurality of switching signals according to an example embodiment. Referring to Figures 2 and 4, a DAC 2 (which may be implemented in an integrated circuit) may include an amplifier (which may be It is called a switched capacitor amplifier p5 〇. Amplification > „250 can & a capacitor Csa, a second capacitor group, an operational amplifier (OP amp) 251, and/or a switching circuit 28 〇. dac 200 can It is called a resistor capacitor dac(rc-dac). OP AMP 251 can include a first input terminal (for example, an inverting (one) input terminal) and a second input terminal (for example, a non-inverting (+) input terminal). And an output terminal of the output "is number DACO. The first condenser piano Csa may be connected to the first (·) input terminal of the OP AMP 25 1 - the first terminal and a 131464.doc .14· 200904013 second The second capacitor bank 270 can include a plurality of second capacitors (eg, 'four second capacitors) Cs1, Cs2, Cs3, and Cs4 that can be coupled to the second (+) input terminal of the 〇p AMP 25 1 . Each of the second capacitors Cs1, Cs2, Cs3, and Cs4 may have a first terminal and a second terminal 'and each of the second capacitors Cs1, Cs2, Cs3, and Cs4. The second terminal can be connected to the second (+) input terminal of the OP AMP 251. The first capacitor Csa can have a capacitance equal to the sum of the capacitances of the second capacitors Cs1, Cs2, Cs3, and Cs4.

The switch circuit 280 can include: a first group of switches, each of which switches in response to a respective one of the first group of switch signals S11, S12, and S13, and a second group of switches, each of which is responsive to the second The group switching signals S2 1 S22, S23 and S24 are switched by corresponding signals. Switching circuit 280 can further include - initialization ON, which operates in response to - switching signal S10 to initialize the second (+) input terminal of OP AMP 251. The first group of switches and the second group of switches included in the switching circuit 280 can be transistors. For example, a first switch responsive to the switching signal S1 可 can be connected between the first (1) input terminal of the OP AMP 251 and the output terminal of the 〇p AMp 251. A second switch responsive to the switching signal S12 can selectively transmit a reference voltage VREF (eg, the -first reference voltage) to the first terminal of the first capacitor Csa and/or can be coupled to the first A first terminal of the capacitor Csa and a node receiving the reference voltage vref (eg, the first reference voltage VMIN) can selectively connect the first terminal of the first capacitor Csa to the OP in response to the switch signal SU Output terminal of AMP 251. 131464.doc -15- 200904013 Each of the second group of switches can reference voltage VRef (eg, first reference voltage VMIN), a first selection voltage VI, and a second selection voltage One of V2 is selectively transmitted to a first terminal of a respective second capacitor csi, Cs2, Cs3 or Cs4. For example, a fourth switch may be responsive to switch k number S21 during a first time period The reference voltage vref is transmitted to the corresponding electric grid device Cs1 and the first selection voltage VI or the second selection voltage V2 is transmitted to the corresponding capacitor csi during a period of time. Similarly, the fourth switch, the fifth switch, and the sixth Switch and seventh open The reference voltage VREF may be respectively transmitted to the respective capacitors Cs2, Cs3, and Cs4 during the first period and the first selection voltage V1 or the second selection voltage during the second period in response to the switching signals S22, S23, and S24, respectively. V2 is respectively transmitted to the corresponding capacitors Cs2, Cs3 and Cs4. The reference voltage VREF may be the first reference voltage vmin 'but is not limited thereto. For example, the reference voltage VREF may be the second reference voltage VMAX or the first reference voltage VMIN and the first An intermediate voltage between the two reference voltages VMAX, or the reference voltage VREF may be set to other values. If the DAC according to an example embodiment is used in a display device, the reference voltage vref may vary with the channel (or data line). The initialization switch may transmit the reference voltage VREF to the second (+) input terminal of the OP AMP 251 during the first period and/or during the initialization period in response to the switching signal Si 。. Cp can be between the first (one) input terminal of 〇p amp 251 and ground. The other capacitor can be connected to the first (one) input terminal and/or the second (+) input of 〇p Amp 251 Son to obtain the symmetrical parasitic capacitance between the terminals of the OP AMP 251 input 131464.doc •16·200904013. The DAC 200 may include a controller 260 to generate the switching signals S10, S11, S12, S13, S21, S22, S23 and S24. The timing of the switching signals S10, S11, S12, S13, S21, S22, S23, and S24 will be described later with reference to FIG. The DAC 200 can include a signal conversion block 21A. The signal conversion block 21A may include a voltage divider 220 and/or a selection circuit 230. The voltage divider 220 can be a resistor array including a plurality of resistors connected in series from a first scale to a 2nth R. For example, the voltage divider 22 can be connected between a first node receiving the first reference voltage VMIN and a second node receiving the second reference voltage VMAX (where VMAX>VMIN) to generate different bits. A resistor array that is divided by voltages VD1 through VDK (eg, K = lm or K-2 +1). The resistance value of each of the first R to the 2"R of the resistor included in the voltage divider 220 can be determined by a desired gamma curve or a predetermined gamma curve. In an example embodiment, "m" is an integer less than the number of bits in the digit signal DATA "n" The selection circuit 230 is responsive to a first digit signal DAT1 from the plurality of divided voltages VD1 to VDK Selecting at least two voltages and providing the selected voltages as the at least two selection voltages V1 & V2. The selection voltages may be two-bit voltages and are referred to as first selection voltages νι and second selection voltages as described above. V2, and V2 < V1. The first digital signal DAT 1 may be a signal consisting of a high order bit of the digital signal DATA (for example, a high "m"(<n) bit). The digital signal £) 八1 ^ can be an n-bit parallel video signal (where "n" is a natural number, for example, (7) or 131464.doc 17 200904013 12) and can be the first digit signal DAT1 and one (n_m) bit of the m-bit The second digit signal DAT2 is composed. The controller 260 can generate the second group of switching signals S2l, S22, S23, and S24 based on the (n_m) bits τ, the second digit signal DAT2, which is composed of the lower bits of the digital signal DATA. This operation will be described in more detail later. 3A and 3B illustrate the structure of the DAC 200 during the first period and the structure of the DAC 2〇〇 during the second period, respectively, according to an example embodiment. The operation of the DAC 200 during the first period and the second period will be described hereinafter with reference to Figs. 2 through 4. During the first period of phase 1, the switching circuit 28A can transmit the reference voltage VREF to the first terminal of the first electric valley Csa and the first terminal of the second capacitors csi to Cs4, and transmit the reference voltage vrEF to the op aMP 251 The second (+) input terminal 'and/or the first (one) input terminal of the OP AMP 251 is connected to the output terminal of the OP AMP 25 1 . During the first period of phase 1, the switching signals S10, S11 and S12 can be activated (for example, to "high level"). In response to the activated switching signals S10, S11 and S12, the initialization switch and the first switch and the second The switch can be closed. The switch signal s丨3 can be cancelled (for example, to the low level "), and the third switch can be turned off, and the second group of switch signals S21, S22, S23 and S24 can be in a first state ( For example, "ρ), and the second group of switches in response to signals S21 to S24 can respectively transmit the reference voltage VREF to the second capacitors Cs1 to Cs4. Therefore, during the first period of phase 1, the first of 〇p Amp 251 The voltage of the second (+) input terminal may be equal to the reference voltage VrEF, and if the deviation voltage between the first (1) input terminal and the second (+) input terminal of the 〇p amp 251 is v〇ff 131464.doc -18- 200904013 Ignoring or presuming to be "ο", the electric grind and output signal DACO of the second (+) input terminal of 〇P AMp 251 can be equal to the reference voltage VREF. During the second period of phase 2, the switching circuit 280 can make the _ The first terminal of the capacitor Csa is isolated from the reference voltage VREF Transmitting the first selection voltage π or the second selection voltage V2 to the first terminal of the second capacitor Cs1 to CM, and/or connecting the first terminal of the first capacitor Csa to the output tweezers k of the 〇p AMp25i s 10, s 11 and s 12 may be revoked (eg, to "low level") and the initialization switch and the first switch and the second switch may be interrupted in response to the unlocked switching signals S10, sn, and S12 On, while the switching signal S13 is activated (eg, 'to " high level") and the third switch is closed. The second group of switching signals S21, S22, S23, and S24 can be in a second or third state (eg, ' "2" or "3")' and the second group of switches responsive to signals S21 through S24 can respectively transmit the first selection voltage ... or the second selection power (four) to the respective second capacitors Cs1 to Cs4. The first selection voltage vi may be transmitted when the second group of switching signals (2) to S24 are in the second state (eg '"2") and in the third state (eg, 3) at the second group of switching signals (3) to S24 The second voltage V2 can be transmitted. Only the first time period and the second time period are illustrated in FIG. However, another operation can be provided, such as a 'pre-initialization period. For example, during the pre-initialization period before the first period, 'initial switch and off can be closed in response to signal S10' and initialization can be performed. Switch HS10 The signal to S13 and the switching signals S21 to S24 may not be synchronized in order to reduce switching noise. For the sake of clarity of description, the second capacitor will be referred to as the first, second, 131464.doc • 19-200904013 three and fourth interpolating capacitors Cs1, Cs2, Cs3, and Cs4, and will be applied during the second time period. The voltages to the first to fourth interpolating capacitors Cs1 to Cs4 are referred to as first, second, third, and fourth input voltages VII, VI2, VI3, and VI4. Each of the first input voltage VII to the fourth input voltage VI4 may be set to the first selection signal VI or the second selection signal V2 according to the second group switching signals S21 to S24. Therefore, during phase 2 of the second period, equation (1) is satisfied: 0 = Csl(Vx - VII) + Cs2(Vx - VI2) + Cs3(Vx - VI3) + Cs4(Vx - VI4), (1) Vx is the voltage at the second (+) input terminal of the OP AMP 251. If the capacitance of the first (-) input terminal of the OP AMP 251 is substantially the same as the capacitance of the second (+) input terminal of the OP AMP 251, the voltage Vx becomes the second (+) of the OP AMP 251 during the second period. The voltage of the input terminal and the output signal DAC0 of the OP AMP 251. Based on equation (1), the voltage Vx can be expressed by equation (2):

CslYIl + Cs2VI2 + Cs3VI3 + Cs4VI4 (2) X (Csl + Cs2 + Cs3^Cs4) ' ^ If the first interpolating capacitor Cs1 to the fourth interpolating capacitor Cs4 have the same capacitance, according to the first input voltage VI1 to the fourth input The voltage VI4 is used to determine the output signal DAC0 of the OP AMP 251, as shown in Table 1. Table 1 Case input voltage (vn, VI2, VI3, VI4) Output signal DAC0 1 VI Ύ1 ' VI ' VI VI 2 VI ' VI > VI > V2 (3Vl+V2)/4 3 V Bu VI, V2, V2 (2Vl+2V2)/4 4 V Bu V2, V2, V2 (Vl+3V2)/4 5 V2 ' V2 ' V2 ^ V2 V2 As shown in Equations 1 and 2 and Table 1, the output signal of 〇p AMP 251 131464.doc -20- 200904013 The DACO can be the result of interpolation between the first selection voltage V1 and the second selection voltage V2. The output signal DACO of the '〇P AMP 251 as described above may be independent of the reference voltage (e.g., the first reference voltage VMIN) and may be determined by the selection voltages V1 & V2. Therefore, the change of the reference voltage (e.g., the first reference voltage vmiN) (e.g., 'inter-channel deviation) does not need to affect the output signal DACO of the 〇p AMP 251. Because the interpolation value between the selection voltages ¥1 and ¥2 is reflected to 〇p

The output signal DAC of the AMP 251 is on (not inverted), so the selection circuit 230 can be implemented more easily. Figure 5 is a block diagram of the signal conversion block 21A illustrated in Figure 2. The signal conversion block 210 in Fig. 5 corresponds to an example in which the number of bits in the digital signal DATA is 10. However, example embodiments are not limited thereto, and the number of bits το in the digital signal DATA may be a different number than 1G, and the signal conversion block 210 may be configured to coordinate accordingly. > Looking at Figure 5, the tool 220 can include a resistor array of resistors connected in series from the first R to the 64th R (where "m" is 6 and 2〇1 = 64), and/or A 65-bit divided voltage VD1 to ν 〇 65 is generated. The selection circuit 230 may include first to third decoders 231, 232 and, for example, and/or - select 234. The first decoder 23 i may receive the divided voltage Up to one of the first group-divided voltages VD1, VD3, VD5, ..., VD61 and VD63, in response to the first signal Β[9··5] in the first digital signal dati from the first- The group is divided by the voltage ν〇ι to the side to select a voltage: and the selected divided voltage is output as - the - decoder output; ^ according to the example embodiment, including the first - digit signal dati ^ 131464.doc 21 The 200904013 bit signal DATA can be an ι〇 bit signal and is denoted as B[9:〇]. The second decoder 2 3 2 can receive the second group of divided voltages of the divided voltages v D 丨 to v D 6 5 VD2, VD4, VD6, ..., VD62 and VD64, in response to the first signal B[9.5] selecting a divided voltage from the second group of divided voltages ν〇2 to VD64, and dividing the selected The voltage output is the second decoder output signal OUT2. The third decoder 233 can receive the second group of divided voltages VD3, VD5, Vd63 and vD63 of the divided voltages 乂(1) to VD65, and respond (' to the first nickname B[9:5] selects the selected divided voltage from the third group divided voltages VD3 to VD65, and outputs the selected divided voltage to the third decoder output signal OUT3. The selector 234 can respond to a second Signal B[4] selects two signals from the first to second decoder output signals OUT1, OUT2 and OUT3, and outputs the selected two signals as the first selection voltage 乂丨 and the second selection voltage V2. The signal B[4] is the least significant bit (LSB) of the first digital signal DAT1, and the first signal B[9:5] is the remainder of the first digital signal DAT1 excluding the second signal B[4]. (J Figure 6 is a block diagram of an amplifier 250, according to an example embodiment. Referring to Figure 6, the amplifier 25 0' may include five second group capacitors Cs1 through Cs5. The amplifier 250' is somewhat similar to the amplifier illustrated in Figure 2. 25〇, and therefore, the redundant description will be omitted. For the sake of clarity of description, if 5 second groups are The devices Cs1 to Cs5 are referred to as the first interpolating electric grid device Cs1 to the fifth interpolating capacitor cS5. The amplifier 250 may further include a fifth interpolating capacitor Cs5 and an eighth switch as compared with the amplifier 250 illustrated in FIG. The eighth switch selectively transmits the reference voltage VREF or the second selection voltage V2 to the fifth inner 131464.doc 22·200904013 plug capacitor Cs5 in response to the signal s25. Therefore, the 'second group switching signals S21, S22, S23 and S24 can be generated based on the second digital signal DAT2 (e.g., four lower bits B[3: 〇] in the digital signal DATA). For example, the second group of switching signals S24 can be generated based on LSB B[0] in the digital signal DATA. SLSB B[0] is at a first level (for example, "high level"), then the first selection voltage V1 can be transmitted to the fourth interpolation capacitor Cs4, and if LSB B[0] is in the first The second level (for example, "low level") can transmit the second selection voltage V2 to the fourth interpolation

I capacitor Cs4. Similarly, the second group switching signal S23 can be generated based on the second LSB B[1] of the digital signal DATA, and the first selection voltage ¥1 or the second selection voltage V2 can be selectively transmitted to the third interpolation. Capacitor Cs3. Similarly, the second group of switching signals S22 and S21 may be generated based on the second LSB B[2] and the fourth LSB B[3] of the digital signal DATA, and may select the first selection voltage VI or the second selection voltage V2 It is selectively transmitted to the second interpolation capacitor Cs2 and the first interpolation capacitor Cs1. The eighth switch operative in response to signal S25 may transmit the reference voltage VREF to the fifth interpolation capacitor Cs5 during the first time period and/or transmit the second selection voltage V2 to the fifth interpolation capacitor during the second time period Cs5. The right first interpolating capacitor Cs1 to the fifth interpolating capacitor Cs5 respectively have 8/16, 4/16, 2/16' 1/16 and 1/16 capacitors of the capacitance C of the first electric valley l § Csa, and then the output The signal DACO may have one of values obtained by dividing a range between the first selection voltage V1 and the second selection voltage V2 into 16 segments. The output signal DACO can be obtained from equation (3):

Vx = V2 + B[k]2k'N-') X dV, 131464.doc (3) •23- 200904013 :,:dV ”2 ' B[k] is the bit in the second digit signal DAT2, and Ν is the number of bits in the second digit signal DAT2, that is, for example, 4) in the above example case, so 'if bit B is just and bit B[3] to ΒΠ] is "0,' The output signal DAC is represented by ^Vx=vi + i/2vd. For example, the turn-off signal DACO is a voltage corresponding to 1/2 between the second selection voltage V2 of the first selected power (four) disk. ^ Ο In the example embodiment illustrated in FIG. 5 and FIG. 6, if a bit (1/10 bit 数) digital signal is converted into an analog signal, one can include two resistors (where m<n, and The column is added as =6) instead of a resistor array of resistors to generate a plurality of divided voltages, and the range selected from the voltages of the plurality of divided voltages can be divided into a plurality of m levels, for example Interpolation can be performed between selected voltages such that the η-bit digital signal can be converted to one of the 2" level analog shifts. Therefore, 2" is used as compared to the read digital signal resistance Conventional DACs, DACs according to example embodiments may use fewer resistors and, or use fewer capacitors and switches. Thus, DAc according to example embodiments may be implemented in less complex cases. Occupying a smaller area and/or having a smaller size. According to an example embodiment, the resistance value of each of the resistors _like to 2m R included in the voltage divider 220 may be a desired gamma curve or a predetermined gamma curve decision. Depending on the number of second capacitors and their capacitance, interpolation between two voltages selected from the divided electric powers may be performed linearly or non-linearly. Appropriately set the resistance value of the first r to the second mth of the resistor, the number of the second capacitor, and/or its capacitance to obtain a nonlinear rotation of the pseudo-margin curve of the liquid crystal display (LCD) panel Characteristic 131464.doc -24- 200904013 Curve. Figure 7 illustrates a DAC 20CT according to another example embodiment. The DAC 200' can be similar to the DAC 200 illustrated in Figure 2, but compared to the DAC 200 illustrated in Figure 2, the DAC 200' may further include a buffer 240. DAC 20 (Γ The functions and operations of the other components are the same as those of the components in the DAC 200, and therefore, a description thereof will be omitted. The buffer 240 can receive and buffer one of the selection voltages VI and V2 and will buffer the voltage. The output is the reference voltage VREF. In the DAC 200 illustrated in FIG. 2, the reference voltage VREF is set to a desired value or a predetermined value (eg, the first reference voltage VMIN) regardless of the voltage of the output signal DACO. However, in the DAC 200' illustrated in FIG. 7, the reference voltage VREF may vary with the previous output signal DACO. For example, the reference voltage VREF can be set to one of the selection voltages VI and V2 generated by the previous output signal DACO. According to the example embodiment illustrated in FIG. 7, the buffer 240 may buffer and output the second selection voltage V2 as the reference voltage VREF. However, in another example embodiment, the buffer 240 may buffer and output the first selection voltage VI as the reference voltage VREF. Buffer 240 can be an analog amplifier having a unity gain (e.g., gain = 1) having an output terminal coupled to an inverting input terminal. 8 is an example timing diagram illustrating the operation of amplifier 250 included in DAC 200 or 20, according to an example embodiment. Referring to FIG. 8, one line time of amplifier 250 may include a first time period phase 1 and a second time period phase 2 During the first period of phase 1, capacitors Csa and Cs1 to Cs4 may be initialized to the reference voltage VREF such that the output signal DAC◦ is set to the reference voltage VREF. During the first period L & 2 during 131464.doc • 25- 200904013 Driving the output signal dac〇 to a gray scale voltage corresponding to the digital code DAT. In order to continuously generate the output signal row by row, the amplifier may need to generate the output signal DACO^d corresponding to the previous digit code and The capacitors Csa and Cs1 to Cs4 are initialized to the reference voltage VREF before the output signal DAC(T) corresponding to a current digital code is generated. In order to satisfactorily drive the output signal DAC〇 during the trip time, the initialization time can be reduced, during which the output of the amplifier 250 is changed from the previous output signal DAC〇(T_. to the reference voltage VREF. FIG. 9 is a diagram included in FIG. An example timing diagram for the initialization of the amplifier in the DAC 2〇〇 is illustrated. The worst case scenario may be that the difference between the voltage of the previous output signal dacoch of the amplifier 250 and the reference voltage vref^ has a maximum value. For example, if the output range of the amplifier 25〇 is a higher gamma from a first high gray scale voltage VH(0) to a first (Ν_υ high gray scale voltage VH(N_1) (where 1^ is 2η) , the reference voltage VREF is set to an intermediate voltage VREFp between the first high gray scale voltage VH(〇) and the first (Ν_η high gray scale voltage vh(ni), and if the output range of the amplifier 25〇 is one The lower gamma of the first low gray scale voltage VL(0) to a (N-1)th low gray scale electric dust VL(Nl) sets the reference voltage vREF to the first low gray scale voltage VL (0) to an intermediate voltage VREFn between the (N-1)th low gray scale voltage VL(N1). If the amplifier 250 outputs a higher gamma, the first gray scale voltage VH(0) and the The (N-1)th high gray scale voltage VH(N1) may correspond to the first reference voltage VMIN and the second reference voltage νΜΑχ, respectively. If the amplifier 250 outputs a lower gamma, the first low gray scale voltage is 匕(〇) and 131464.doc •26- 200904013 The first (ND low gray scale electric screams can correspond to the first reference voltage VMIN and the second reference voltage vmaX, respectively. In the worst case case above, even the reference electricity Vref is set to the middle of a gamma curve VREFp or VREFn, the electric dust of the output signal still needs to be changed, and the change is as much as 1/2 of the gamma curve. For example, if the previous output signal DACOfi) has The _high gray scale voltage VH(9) or the (Ν_ι) high gray scale voltage ^沁), the output signal may need to change and change as much as corresponding to the (N-1) high gray scale power yH (N_ 1) a voltage of 1/2 of the difference between the first high gray scale voltage VH(0) so as to be initialized to the reference power. If the previous output signal dac〇(t_υ has the first low gray scale voltage VL (0) or (Ν υ υ low gray scale voltage VL (Nl), then the output signal may need to be changed, such as corresponding to the (N-1) low gray scale voltage ν ΜΝ υ and the first low gray a voltage of 1/2 of the difference between the step voltages VL(〇) so as to be initialized to the reference voltage VREFn° so that the 'amplifier 250 can perform twisting and stabilization with respect to half of the voltage of the entire gamma voltage, which can be increased Initialization time. Or 'included in the DAC 200 illustrated in Figure 7, the amplifier 250 can use the previous output letter The voltage of DACO (Tl) is used to set an initialization voltage for the current output signal DACO (T). For example, one of the selection voltages VI and V2 for calculating the previous output signal DACO (Tl) can be set as the current wheel. The initialization voltage of the signal DACO(T), for example, the reference voltage VREF. Therefore, the amplifier 250 included in the dac 200 does not need to perform the twisting' but can perform only stabilization, thereby being phased with the amplifier 250 included in the DAC 200. Reduce initialization time and power consumption. 131464.doc • 27- 200904013 Figure 1 is a block diagram of a display device including a source driver 540 including the DAC 200 illustrated in FIG. Referring to FIG. 1 , a flat panel display device 500 (eg, a thin film transistor lcd (tft_lcd), a plasma display panel (PDP), or an organic light emitting diode) may include a display panel 51 , a control circuit 52〇, a gate driver 53〇 and/or a source driver 540 〇 display panel 510 may include a plurality of data lines 81 to 33 (where "s" is a natural number), and a plurality of gate lines G1 to Gg (where g" is a natural number, and g=s or g矣s), and/or a plurality of unit cells (including - unit cell 晶). Each of the cells may be connected between the data line 81 to a corresponding one of the ones and one of the gate lines (1) to Gg. The control circuit 520 can generate a plurality of control signals including a first control signal c〇N1 and a second control signal CON2. For example, control circuit 520 can generate first control signal CON1, second control signal CON2, and/or digital data DATA based on a horizontal sync signal and/or a vertical sync signal. The gate driver 530 can sequentially drive the gate lines G1 to Gg in response to the first control signal c〇N1. For example, the first control signal c〇N1 may be a signal indicating the start of scanning of the gate lines G1 to Gs. The source driver 540 can include a plurality of DAs (: 200 according to an example embodiment. It is also apparent that the source driver 5 4 can include each of the plurality of DACs 200, DACs 200 according to another example embodiment. For example, the output signal DACO of the dac 200 can be supplied to the data line S1. One includes the DAC 2〇〇 and the driver 131464.doc -28 - 200904013 A single data line driver is referred to as a channel driver, and the single data line is referred to as a channel. According to an example embodiment, even a reference voltage (eg, first reference voltage VMIN) used in DAC 200 is in the channel driver The difference between the output signal DACO of the DAC 200 is also not affected by the reference voltage, and therefore, the deviation between the channel drivers (for example, the deviation between the output signals of the channels) can be reduced. The source driver 540 can respond. The second control signal CON2 and the digital data DATA output from the control circuit 520 drive the source lines S1 to Ss. Although not shown, a source driver module according to an example embodiment may include A plurality of source drivers of the same structure as the source driver 540 illustrated in Fig. 10. The digital to analog conversion method according to an example embodiment may be performed by a DAC according to an example embodiment. In the digital to analog conversion method, Providing a reference voltage to a first capacitor connected to one of the first input terminals of _ 〇p Amp and/or providing a second connection to the 〇p AMP during a first day ττ #又期' a plurality of second capacitors of the input terminal. The first input terminal of the 〇p amp can be connected to the output terminal of the OP AMP. During a second period of time, the first capacitor can be isolated from the reference voltage, and one can be selected from A voltage of two selected voltages is transmitted to each of the second capacitors, and/or a first terminal of one of the first capacitors is connectable to an output terminal of the 〇p AMp. As described above, according to an example embodiment A DAC can occupy a small area (and/or have a smaller size) and provide a non-linear output characteristic curve of the approximation-LCD panel gamma curve 131464.doc • 29- 200904013. If the DAC is used for one In the display device, the deviation between the channel drivers, for example, the deviation between the output signals of the channels, can be reduced. Although the example embodiments have been shown and described in the specification and the drawings, those skilled in the art should It will be appreciated that the illustrated and/or described example embodiments may be modified without departing from the principles and spirit. [FIG. 1 illustrates a conventional digital-to-analog converter (DAC); FIG. 2 illustrates Figure 3A illustrates the structure of a dac during a first time period according to an example embodiment; Figure 3B illustrates the structure of the dac during a second time period according to an example embodiment; FIG. 5 is a block diagram of a signal conversion block illustrated in FIG. 2; FIG. 6 is a block diagram of an amplifier according to an example embodiment; FIG. 7 illustrates dAC according to another example embodiment; FIG. 8 is a timing diagram illustrating an operation of an amplifier according to an example embodiment; FIG. 9 is an illustration illustrating an amplifier included in the DAC illustrated in FIG. Examples of a timing chart; and FIG 1〇 block diagram including a display comprising a source apparatus illustrated in Figure 2 of the driver of the DAC. 131464.doc •30· 200904013 f

[Main component symbol description] 100 R-DAC 110 Resistor array 120 Decoder 130 Operational amplifier 200 Digital to analog converter 200' Digital to analog converter 210 Signal conversion block 220 Voltage divider 230 Selection circuit 231-233 Decoder 234 selector 250 amplifier 250' amplifier 251 operational amplifier 260 controller 270 second capacitor bank 280 switching circuit 500 flat panel display device 510 display panel 520 control circuit 530 gate driver 540 source driver B [4] second signal 131464.doc • 31 · 200904013 B[9:5] First signal CONI First control signal CON2 Second control signal Cp Parasitic capacitor Csl-Cs5 Second capacitor Csa First capacitor DACO Output signal DAT1 First digit signal DAT2 Second digit signal DATA Digital signal DECO Select voltage Gl-Gg Gate line OUT1 First decoder output signal OUT2 Second decoder output signal OUT3 Third decoder output signal S10-S13 Switch signal S21-S24 Second group switching signal Sl-Ss Data line VI first selection voltage V2 second selection voltage VD1 -VD65 divided voltage VD1-VDK divided voltage VH(0) first high gray scale voltage VH(Nl) (N-1) high gray scale voltage 131464.doc -32- 200904013 VL(0) first Low gray scale voltage VL(Nl) (Nl) low gray scale voltage VMAX second reference voltage VMIN first reference voltage Vrefl first reference voltage Vref2 second reference voltage VREF reference voltage VREFn intermediate voltage / reference voltage VREFp reference voltage / intermediate voltage

131464.doc -33-

Claims (1)

200904013 X. Patent application scope: 1. An integrated circuit comprising: a different operational amplifier having a first input terminal, a second input terminal, and an output terminal; a first capacitor having a first a terminal and a second terminal, the second terminal of the first capacitor is connected to the first input terminal of the operational amplifier; the plurality of second capacitors each having a first terminal and a second terminal, and the like a second terminal of each of the second capacitors is coupled to the second input terminal of the operational amplifier; and a switching circuit including a plurality of switches configured to switch in response to the plurality of switching signals, wherein The Tenghai switch circuit can pass and can transmit a reference voltage to the stem of the first capacitor during the first period... Keiko and the second capacitor to the operational amplifier Outputting a first input terminal connection: =_ configured to isolate the first capacitor from the reference voltage during a second time period, the voltage of the selected voltage being transmitted to the Up to two or two, and the first _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ , further comprising a voltage divider, comprising: - connecting to - 3 \ first point, receiving a first reference electronic calendar, a point and receiving a second reference electric second node Between the resistors, the voltage divider is configured to generate a plurality of divided voltages by dividing a range between the second reference voltage and the first reference voltage; and a selection circuit Configuring, in response to a first digital signal, selecting at least two voltages from the plurality of divided voltages and providing the selected voltages as the at least two selection voltages, the tenth of the different amplifiers An input terminal is an inverting input terminal 'and the second input terminal of the operational amplifier is a non-inverting input terminal' and the first digital signal is a portion of an n-bit digital signal. 3. The integrated circuit of claim 2, wherein the at least two selection voltages comprise a first selection voltage and a second selection voltage lower than the first selection voltage, and the switching circuit comprises: a U terminal and the operation Between the output terminals of the amplifier; (8) training a first switch configured to selectively transmit the reference voltage to the first terminal of the first capacitor; ☆ a second switch configured to The first & t of the first capacitor is selectively coupled to the output terminal of the operational amplifier; and: a plurality of second group switches configured to reference the voltage, the voltage, the voltage, and the voltage A second selection voltage is selectively transmitted to the plurality of the second capacitors. 4. The integrated circuit of claim 3, wherein: 131464.doc 200904013 = during the first time period, the first switch and the second switch are closed, the i-th switch is off, and the plurality of second groups are The switch transmits the reference voltage to the plurality of second capacitors; > during the second period, the first switch and the second switch are turned off, the third switch is closed, and the plurality of second group switches Transmitting one of the first selection voltage and the second selection voltage to the plurality of second capacitors based on a second digit signal; and r the second digit signal is the n-bit digit signal excluding the first digit 1 The remainder of the signal. 5. The integrated circuit of claim 4, wherein each of the plurality of second group switches is configured to respond to a corresponding one of the second digit signals during the second time period One of the first selection voltage and the second selection voltage is transmitted to a corresponding one of the plurality of second capacitors, the first digital signal being the highest &" bits in the 11-bit digital signal The Q element is composed, wherein m is smaller than η, and the melon is an integer, and the second digital sign is composed of a low (1) salty bit in the n-bit digital signal. 6. The integrated circuit of claim 3, wherein the selection circuit comprises at least two decoders, each of the decoders configured to receive the portion of the divided voltages and in response to the first a first signal of the digital signal and a voltage selected from the divided voltages received, and the first selection voltage and the second selection voltage are selected from the output of the at least two 131464.doc 200904013 decoders signal. 7. The integrated circuit of claim 3, wherein the selection circuit comprises: a first decoder configured to receive the first divided voltage of the divided voltages, responsive to the first digital signal One of the first-signals selects a voltage from the first group of divided voltages, and rotates the selected voltage as a first decoder output signal; jin-second decoding H, configured to receive the same Dividing the voltage - Γ :: group divided voltage 'in response to the first signal from the second group: knife voltage selection - voltage, and outputting the selected voltage as a -coder output signal; one solution one second decoding And configured to receive the divided voltages - the second group of divided voltages, in response to the first signal, select -voltage from the third group of calcium knives and rotate the selected voltage As a third coder output signal; and - a selection n ' is configured to respond to the _th: 乜 sign from the first decoder output signal to the third decoder The output signal selects two signals and outputs the selected two signals = Is a selection voltage and the second selection voltage, μ - wherein the second signal for the remaining part of the signal of one least significant bit of the first digital signal. 8. The integrated circuit of claim 7, wherein the electrical follower array comprises two resistors 131464.doc 200904013 connected in series, the divided voltages comprising (2m+i) level voltages, the first group The divided voltage includes an odd number of voltages out of the (2m+1) level voltage excluding the most extreme voltage, and the second group divided voltage includes an even number of the (2m+l) level voltages, The third group of divided voltages includes the odd voltages excluding a minimum voltage of the quasi-voltages, and the selector is configured to output a k number from the first decoder in response to the second signal The third decoder output signal selects two signals and outputs two selected signals, such as X, to the first selection voltage and the second selection voltage. [9] The integrated circuit of claim 8 is the plurality of a second capacitor package: a first-interpolating capacitor configured to have a capacitance corresponding to the first electrical power of 8/16, the first interpolating capacitor being grouped by two: during the first period - from one of the least significant bits of the n-bit digital signal a fourth bit selectively receiving one of the first selection voltage and the second selection voltage, the least significant bit being one of the first bits of the bit 7 digital signal; a second interpolating capacitor configured to have an electrical valley corresponding to _ 4/16 of the capacitance of the first capacitor, the second interpolating capacitor configured to be in the 笫-卩 main one, & And selectively receiving one of the first selection voltage and the second selection voltage based on a third bit from the least significant bit of the n-bit digital signal 131464.doc 200904013: a second interpolating capacitor configured to have a capacitance corresponding to 2/16 of each of the first = current °° Selecting one of the second voltage and the second selection voltage based on a second bit from the least significant bit of the n-bit digital signal during the second time period; a quad insert capacitor configured to have a power corresponding to 1/16 of the first: Capacity, the fourth interpolation capacitor is grouped And selectively receiving one of the first selection voltage and the selection voltage based on the least significant bit of the n-bit digital signal during the first time period; and -& fifth interpolation capacitor, group thereof The state has a capacitance corresponding to the capacitance of the first: container, and the fifth interpolation capacitor is grouped. The first selection voltage is received during the first period of time. I 0. The integrated circuit of claim 2, wherein the switch circuit further comprises a second stage configured to transmit the reference voltage to the amplifier during the period of the first ##π u In (5), the initialization switch of the input terminal. II. The integrated lightning-plating circuit of claim 2, wherein the reference voltage is selected from a first reference voltage, a flute Α, a μ first reference voltage, and the first reference voltage and the first-* reference Voltage simplification M | Between - the voltage of the group of intermediate voltages. 12. The integrated body of claim 2, owing a circuit, wherein the reference voltage is one of the at least selected voltages. ^1U It further comprises: 13. The integrated circuit of claim 12, wherein the buffer is configured to apply a voltage to the voltage and to output a buffered buffer selected from the at least two selected voltages as the reference voltage. 131464.doc 200904013 14. 15. The integrated circuit of claim 1 is a controller 'configured as the integrated circuit ratio converter of claim 1. It further comprises: outputting the plurality of switching signals. Where the integrated circuit is a digit to 16. A source driver for a display device, the source driver comprising the integrated circuit of claim 1. 17. A display device comprising: a plurality of data lines; a plurality of gate lines; a plurality of unit cells, each unit cell being coupled to a respective one of the plurality of data lines and the plurality of gate lines And a source driver of claim 16, wherein a voltage of the output terminal of the operational amplifier included in the integrated circuit is supplied to a corresponding one of the plurality of data lines . 1-8. A digital to analog conversion method, comprising: providing a reference voltage to a first capacitor connected to a first input terminal of an amplifier and connected to the operational amplifier during a first period of time a plurality of second capacitors of the second input terminal and the first input terminal of the operational amplifier being connected to the output terminal of the operational amplifier; and during a second period of time, the first capacitor and the reference voltage are Isolating, transmitting a voltage selected from the at least two selection voltages to each of the plurality of second capacitors' and connecting the first terminal of one of the first capacitors to the output terminal of the operational amplifier, 131464. Doc 200904013 wherein the at least two selection voltages are determined based on a first digital signal and the voltage transmitted to each of the plurality of second capacitors during the second time period is based on a second digital signal To judge. 1 9. The digit-to-analog conversion method of claim 18, wherein the first digital signal is composed of at least one high bit of a digital signal, and the second digital signal is composed of at least one low bit of the digital signal composition. 20. The method of claim 8, wherein the method further comprises: dividing a range between a first reference voltage and a second reference voltage and generating a plurality of divided voltages; and responding to the first The digital signal is selected from the plurality of divided voltages to the two voltages and provides the selected voltages as the at least two selection voltages. 21. The digital-to-analog conversion method of claim 18, further comprising: ϋ 胄 5 至少 5 at least two of the selected voltages and providing a buffered voltage as the reference voltage. 22. A method, comprising: applying a charge to a first wheel input and a second input of an operational amplifier based on a reference voltage during a first time period; applying a charge to the current period based on a feedback voltage during the first time period The first round of the amplifier; and applying a charge to the second input of the master amplifier based on a voltage selected from the at least two selection voltages during the slave period . 131464.doc 200904013 23. An integrated circuit comprising: applying a first input charge to the first circuit structure during a time period, configured to apply a charge to a first reference voltage to An operational amplifier and the first input of an operational amplifier based on a feedback voltage during a second period of time, and a second circuit architecture wherein the reference voltage is to be electrically applied and a charge is applied to the second period of time The second round of the operational amplifier is based on a voltage selected from the at least two selection voltages based on a load applied to one of the operational amplifiers during a period of time. 131464.doc