200901408 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體封裝件之組裝接合技術， 別係有關於一種避免基板翹曲引起之銲接缺陷之半 體封裝接合構造，可運用於高密度3D堆疊的架 (Package- 〇n_ package module，Pop)。 【先前技術】 奴著半導體封裝件的薄化發展趨勢，在經過表面 合之回銲處理之時，半導體封裝件之基板變得更易 曲，導致冷銲、空銲或假銲等銲接缺陷。特別是半導 封裝堆疊之接合構造（Package_〇n_Package devi< POP) ’銲接缺陷更是接合過程中一大問題。為了符合 進的微小化電子產品’複數個半導體封裝件可以縱 3 D堆疊以符合小型表面接合面積與高密度元件設置 要求，然而微間距的端子與端子之間的銲接關係更容 (J 受到基板翹曲而被破壞而產生電性斷路。 富士通（Fujitsu)公司於美國專利第 6476503 以 Tessera公司於美國專利公開第2006/0 1 3 8647號各提 一種可應用於封裝堆疊之微接觸架構。請參閱第1圖 示’一種習知半導體封裝接合構造100主要包含一第 半導體封裝件110、一第二半導體封裝件丨2〇以及銲 1 3 0，其中該第一半導體封裝件1 1 0係堆疊在該第二 導體封叢件120之上，並以銲料130連接兩半導體封 件110與120。該第一半導體封裝件11〇係具有一第 特 導 構 接 翹 體 'e, 先 向 之 易 及 出 所 料 半 裝 5 200901408 基板111、一設置於該第一基板111之一上表面 ΠΙΑ 之第一晶片112以及複數個形成於該基板ill之一下表 面1 11 B之凸塊1 1 3，例如銅凸塊或其它不可回銲之柱 狀凸塊，作為封裴堆疊之微接觸端子。並可利用複數個 第一銲線114通過該第一基板111之一第一槽孔111C， 以電性連接該第一晶片11 2之銲墊至該第一基板1 1 1， 並以一第一封膠體1 1 5密封該些第一銲線1 1 4。該第二 f 半導體封裝件1 20係作為一封裝載體，如同第一半導體 封裝件1 1 0 ’該第二半導體封裝件1 20係具有一第二基 板121、一設置於該第二基板121之一上表面121八之 第二晶片1 22以及複數個形成於該第二基板1 2丨之一下 表面1 2 1 B之凸塊1 23，作為對外端子。複數個第二銲 線1 2 4係通過該第二基板1 2 1之一第二槽孔1 2〗c，而 電性連接該第二晶片1 22至該第二基板1 2 1，並以一第 二封膠體1 2 5密封該些第二銲線1 2 4。習知在該第二半 〇 導體封裝件120之該第二基板121之上表面121八係1200901408 IX. Description of the Invention: [Technical Field] The present invention relates to an assembly and bonding technique for a semiconductor package, and relates to a half-package joint structure for avoiding soldering defects caused by substrate warpage, which can be applied to high Density 3D stacked rack (Package- 〇n_ package module, Pop). [Prior Art] With the trend toward thinning of semiconductor packages, the substrate of the semiconductor package becomes more flexible when subjected to surface reflow processing, resulting in soldering defects such as cold soldering, void soldering or dummy soldering. In particular, the joint construction of the semi-conductor package stack (Package_〇n_Package devi< POP)' soldering defects is a major problem in the bonding process. In order to meet the miniaturized electronic products, a plurality of semiconductor packages can be stacked vertically to meet the requirements of small surface bonding area and high-density component setting, but the soldering relationship between the terminals of the micro-pitch and the terminals is more suitable (J is the substrate A micro-contact structure that can be applied to a package stack is provided by Fujitsu, Inc., in U.S. Patent No. 6,476,503, issued to the U.S. Patent No. 2006/0 1 3 647, the entire disclosure of which is incorporated by reference. Referring to FIG. 1 , a conventional semiconductor package bonding structure 100 mainly includes a first semiconductor package 110 , a second semiconductor package 丨 2 〇 , and a solder 1 30 , wherein the first semiconductor package 1 1 0 is stacked. On the second conductor cover member 120, and connecting the two semiconductor packages 110 and 120 with solder 130. The first semiconductor package 11 has a first conductive structure, and the first semiconductor package 11e And a half-mount 5 200901408 substrate 111, a first wafer 112 disposed on one surface of the first substrate 111, and a plurality of first wafers ill formed under the substrate ill a bump 1 1 3 of the surface 1 11 B, such as a copper bump or other non-returnable stud bump, as a micro-contact terminal of the package stack, and the first substrate can be passed through the first substrate 114 One of the first slots 111C is electrically connected to the pads of the first wafer 11 2 to the first substrate 1 1 1 , and the first bonding wires 1 1 are sealed by a first sealing body 1 15 4. The second f semiconductor package 120 is used as a package carrier, like the first semiconductor package 110. The second semiconductor package 120 has a second substrate 121 and a second substrate. a second wafer 1 22 having an upper surface 121 and a plurality of bumps 1 23 formed on a lower surface 1 2 1 B of the second substrate 1 2 as an external terminal. The plurality of second bonding wires 1 2 4 is electrically connected to the second wafer 1 22 to the second substrate 1 2 1 through a second slot 1 2 c of the second substrate 1 2 1 and a second encapsulant 1 2 5 Sealing the second bonding wires 1 2 4 . It is known that the upper surface 121 of the second substrate 121 of the second semiconductor package 120 is octagonal 1
有複數個平墊狀之連接墊121D，藉由回銲上述銲料13〇 以接合該第一半導體封裝件1 1 〇之該些凸塊丨丨3至該第 二半導體封裝件120之對應連接墊121D，藉以達到微 接觸之型態’該些半導體封裝件丨i 0與丨2 0堆A 且呀係以 該些凸塊1 1 3作為微小化接觸點’可增加訊號接腳數 (high pin count)並可增加走線面積，更可以縮小封裝堆 疊間隙（small POP stacking standoff)。然而此 _ 加城 w 木構對 於基板翹曲度的可承受程度將變得更低。銲料 200901408 銲過程與堆疊接合之後，該第—基板ηι會遭受重覆的 熱循環溫度變化，故產生了基板翹曲，導致該些凸塊 1 1 3與對應之連接墊丨2 i D之間的銲料間隙不一致的誤 差變化。在高溫與基板翹曲的應力兩者作用下，特定部 位的銲料1 3 〇不具有銲接黏著力而產生微接觸銲點斷 裂（如第1圖所示），容易引起各式各樣的銲接缺陷。 【發明内容】a plurality of flat pad-shaped connection pads 121D are formed by reflowing the solder 13 to bond the bumps 3 of the first semiconductor package 1 1 to the corresponding connection pads of the second semiconductor package 120 121D, in order to achieve the micro-contact type 'the semiconductor package 丨i 0 and 丨2 0 heap A and the use of the bumps 1 1 3 as a miniaturized contact point' can increase the number of signal pins (high pin Count) and can increase the trace area, and can also reduce the small stack POP stacking standoff (small POP stacking standoff). However, this _ 城城 w wood structure will become less tolerant to substrate warpage. Solder 200901408 After the soldering process is bonded to the stack, the first substrate η1 is subjected to repeated thermal cycle temperature changes, thereby causing warpage of the substrate, resulting in the bumps 1 1 3 and the corresponding connection pads 2 i D The solder gap is inconsistent with the error variation. Under the action of both high temperature and substrate warping stress, the specific part of the solder 1 3 〇 does not have solder adhesion and micro-contact solder joint breakage (as shown in Figure 1), which easily causes various soldering defects. . [Summary of the Invention]
Ο 本發明之主要目的係在於提供一種避免基板麵曲引 起之銲接缺陷之半導體封裝接合構造，縮小在可預知的 基板勉曲度下所引起辉料間隙差異，避免因基板翹曲引 起之銲接缺陷發生。 本發明之次-目的係在於提供一種避免基板龜曲引 起&干接缺陷之半導體封裝接合構造’能兼具有散熱性 與微間隔維持之功效。 本發明的目的及解、土甘 J汉解决其技術問題是採用 案來實現的。依據本發明，一 植牛導體封裝接合構造主 要包含至少一第一丰莲麯 1_封裘件、一封裝載體以及複數個 … 牛導體封裝件係包含-第-基板、一第一 晶片、複數個第一外技 接子與禝數個第二外接端子，其 中β亥二第一外接端子愈α 笛一 Α 二弟二外接端子係設置於該 垃—下表面。該封裝載體係包含複數個第-連 接知點與複數個笛- —接端點。該些複數個銲料係接合 该些第一外接端子至該此 二第一連接知點以及接合該些 第一外接端子至該此第_ 一罘一連接端點。 7 200901408 更進一步限定，該第一基板係定義有一中心線，該 些第一外接端子至該中心線之距離係小於該些第二外 接端子至該中心線之距離。 更進一步限定，該些第一外接端子與該些第二外接 端子係包含不等高之凸塊，用以縮小由該第一基板之翹 曲引起該些第一外接端子與該些第一連接端點之間以 及該些第二外接端子與該些第二連接端點之間的銲料 間隙差異。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述之半導體封裝接合構造中，當該第一基板之 周邊係遠離該封裝載體而往上翹起時，該些第二外接端 子係可具有更高於該些第一外接端子之補償高度。 在前述之半導體封裝接合構造中，當該第一基板之 周邊係接近該封裝載體而往下翹起時，該些第一外接端 子係可具有更高於該些第二外接端子之補償高度。 在前述之半導體封裝接合構造中，該第一晶片係可 設置於該第一基板之一上表面。 在前述之半導體封裝接合構造中，該第一基板係可 具有一沿著該中心線之第一槽孔，以顯露該第一晶片之 複數個銲墊。 在前述之半導體封裝接合構造中，該第一半導體封 裝件更可包含複數個第一銲線，該第一基板係可具有一 第一槽孔，該些第一銲線係可通過該第一槽孔而電性連 8 200901408 接該第一晶片與該第一基板。 在前述之半導體封裝接合構造中，該第一半導體封 裝件更可包含一第一封膠體，其係形成於該第一槽孔， 以密封該些第一銲線。 在前述之半導體封裝接合構造中，該第一封膠體係 可不覆蓋該第一晶片。 在前述之半導體封裝接合構造中，該封裝载體係可 為一印刷電路板。 在前述之半導體封裝接合構造中，該封裝載體係可 為一第二半導體封裝件，該第二半導體封裝件係可另包 含一第二基板、一第二晶片及複數個第三外接端子，其 中該些第三外接端子係設置於該第二基板之一下表 面，該些第一連接端點與該些第二連接端點係設置於該 第二基板之一上表面。 在前述之半導體封裝接合構造中，該第二晶片係可 設置於該第二基板之一上表面，且不覆蓋該些第一連接 端點與該些第二連接端點 在前述之半導體封裝接合構造中，該第二半導體封 裝件係可大致相同於該第一半導體封裝件，而包含有複 數個第二銲線與一第二封膠體。 在前述之半導體封裝接合構造中，該些第一外接端子 與該些第二外接端子係可為柱狀凸塊或結線凸塊。 在前述之半導體封裝接合構造中，該些第一外接端 子與該些第二外接端子係可具有半錐形截面。 ’ 9 200901408The main object of the present invention is to provide a semiconductor package bonding structure that avoids soldering defects caused by surface curvature of a substrate, reduces the difference in the glow gap caused by the predictable substrate tortuosity, and avoids soldering defects caused by substrate warpage. occur. The second objective of the present invention is to provide a semiconductor package bonding structure which avoids substrate torrefaction and dry contact defects, and which has both heat dissipation and micro-interval maintenance. The object and solution of the present invention and the technical problem of the Tu Han J Han are solved by using the case. According to the present invention, a bovine-conductor package-bonding structure mainly comprises at least one first Fenglian curved 1_sealing member, a package carrier, and a plurality of... The cow conductor package comprises a --substrate, a first wafer, a plurality The first external connector is connected to the plurality of second external terminals, wherein the first external terminal of the β-Second two is connected to the lower surface of the second external terminal. The package carrier includes a plurality of first-connection points and a plurality of flute-end points. The plurality of solders are coupled to the first external terminals to the two first connection terminals and to the first external terminals to the first connection terminal. 7 200901408 Further, the first substrate defines a center line, and the distance between the first external terminals and the center line is smaller than the distance between the second external terminals and the center line. Further, the first external terminals and the second external terminals comprise bumps of unequal height for reducing the first external terminals and the first connections caused by the warpage of the first substrate. A difference in solder gap between the terminals and between the second external terminals and the second connection terminals. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing semiconductor package bonding structure, when the periphery of the first substrate is lifted up away from the package carrier, the second external terminals may have a compensation height higher than the first external terminals. In the foregoing semiconductor package bonding structure, when the periphery of the first substrate is lifted up close to the package carrier, the first external terminals may have a compensation height higher than the second external terminals. In the foregoing semiconductor package bonding structure, the first wafer system may be disposed on an upper surface of the first substrate. In the foregoing semiconductor package bonding construction, the first substrate may have a first slot along the centerline to expose a plurality of pads of the first wafer. In the foregoing semiconductor package bonding structure, the first semiconductor package may further include a plurality of first bonding wires, the first substrate may have a first slot, and the first bonding wires may pass the first The slot and the electrical connection 8 200901408 are connected to the first wafer and the first substrate. In the foregoing semiconductor package bonding structure, the first semiconductor package may further include a first sealing body formed on the first slot to seal the first bonding wires. In the aforementioned semiconductor package bonding construction, the first encapsulation system may not cover the first wafer. In the aforementioned semiconductor package bonding construction, the package carrier can be a printed circuit board. In the foregoing semiconductor package bonding structure, the package carrier can be a second semiconductor package, and the second semiconductor package can further include a second substrate, a second chip, and a plurality of third external terminals, wherein The third external terminals are disposed on a lower surface of the second substrate, and the first connection terminals and the second connection terminals are disposed on an upper surface of the second substrate. In the foregoing semiconductor package bonding structure, the second wafer system may be disposed on an upper surface of the second substrate, and not covering the first connection end points and the second connection terminals in the foregoing semiconductor package. In the configuration, the second semiconductor package can be substantially the same as the first semiconductor package, and includes a plurality of second bonding wires and a second sealing body. In the foregoing semiconductor package bonding structure, the first external terminals and the second external terminals may be columnar bumps or junction bumps. In the foregoing semiconductor package bonding structure, the first external terminals and the second external terminals may have a semi-conical cross section. ’ 9 200901408
在另一實施例中’一種避免基板翹曲引起之銲接缺 陷之半導體封裝接合構造係至少包含至少一第一半導體 封裝件、一封裴載體以及複數個銲料。該第一半導體封裝件 係包含一第一基板、一第一晶片、複數個第一外接端子與複 數個第二外接端子，其中該些第一外接端子與該些第二外接 端子係設置於該第—基板之-下表面。該封裝载體係包含複 數個第一連接端點與複數個第二連接端點。該些銲料係接合 該些第一外接端子至該些第一連接端點以及接合該些第二 夕一卜接端子至該些第二連接端點。其中，該第—基板係定義有 一中心線，該些第一外接端子至該中心線之距離係小於該些 第一外接端子至該中心線之距離。 其特徵在於，該半導體封裝接合構造另包含有複數個 補償凸塊’其係、選擇性設置於該些第—連接端點與該些第二 連接端點之其中一群組’用以縮小由該第—基板之翹曲引起 該些第一外接端子與該些第一連接端點之間以及該些第二 外接知子與該些第二連接端點之間的銲料間隙差異。 【實施方式】 ' 伙像丰發明之第一具體實施例’揭示一種避免基板 翹曲引起之銲接缺陷之半導體封裝接合構造。 請參閱第2圖所示，-種半導體封|接合構造2〇〇 ^包含至H半導體封裝# 21G、—封裝載體22〇 以及複數個銲料230。該第一半導體封裝件210係設置於該 料㈣220上並以該些銲料23()結合與電性導通至 栽體220。 10 200901408 該第一半導體封裝件210係包含—第一基板211 一第一晶片212、複數個第一外接端子213與複數個 二外接端子2 1 4。該第一基板2丨丨係作為晶片載體與 片之電性轉接’通常係為印刷電路板。該第一基板2 係具有一上表面211A與一下表面211B。該第一晶 212係為積體電路，依其材質可為矽，依其功能可為 理器、記憶體、邏輯元件、特殊應用積體電路或上述 广 混合等等。其中，該些第一外接端子2 1 3與該些第二 接端子214係設置位於於該第一基板211之下表 21 1B之連接墊21 1D，可為柱狀凸塊或是打線形成之 線凸塊’其材質可為銅、金或其它導電材質。該些第 外接端子2 1 3與該些第二外接端子2 1 4係可具有半錐 截面’如半圓錐體或梯形體，可作為微接觸接點。 更具體而述’該第一基板211係為雙面導通之電 板’即在該上表面211A之連接塾可電性連接至在該 Q 表面211B之連接墊211D。該第一晶片212之一主動 係朝向該第一基板21 1 ’並以黏晶膠、膠帶或覆晶凸 接合在該第一基板211之上表面211A。在本實施例4 該第一基板211係具有一第一槽孔211C，其係貫穿 第一基板211之上表面211A與下表面211B，以顯露 第一晶片212之第一銲墊212A。而該第一半導體封 件2 1 0可更包含複數個第一銲線2 1 5，該些第一銲線2 係以打線方式形成’通過該第一槽孔2 1 1 C而電性連 該第一晶片212之第一銲墊212A與該第一基板21ι 第 晶 11 片 處 之 外 面 結 形 路 下 面 塊 r » 該 該 裝 15 接 之 11 200901408 内接指。 該第一半導體封裝件210可更包含一第一封膠體 2 1 6 ’以壓模或點膠方式’使其係形成於該第一槽孔 211C’以密封該些第一銲線215。該第一封膠體216係 可不覆蓋該第一晶片2 1 2，以使該第一晶片2 1 2之背面 為顯露，有利於散熱與封裝薄化。因此，為了達到薄化 與接合’該第一基板2 1 1之兩邊緣側係不被該第一晶片 r 212與該第一封膠體216所覆蓋，並且在該第一基板211 之上表面211A與下表面211B為非對稱之元件設置， 在溫度循環下會有基板翹曲之現象。 如第3圖所示，配合參閱第2圖，該第一基板211 係定義有一中心線2 1 7，該些第~外接端子2 1 3至該中 心線2 1 7之距離S 1係小於該些第二外接端子2 1 4至該 中心線2 1 7之距離S 2。其中，該中心線2 1 7係依據該 第一晶片212之中央銲墊設置方式所界定。而該第一基 板2 1 1之第一槽孔2 1 1 C係沿著該中心線2 1 7，以顯露 3亥第一晶片212之複數個第一銲塾211A。 再如第2圖所示，該封裝載體22〇係包含複數個第 一連接端點223與複數個第二連接端點224。在本實施 例中，該些第一連接端點223與該些第二連接端點224 係可為平坦狀金屬墊。其中，該第一半導體封裝件2 J 〇 係疊設在封裝載體220之上，並使該些第一外接端子 213對準於該些第一連接端點223，該些第二外接端子 2 1 4對準於該些第二連接端點2 2 4，以利銲接。通常該 12 200901408 些I干料2 3 0係可為無船銲劑，以錫9 6 5 % •銀3 % _銅〇 5 % 之銲料而言，在到達回銲溫度約攝氏217度以上，最高 溫約為攝氏2 4 5度時能產生銲接之濕潤性，而該些第一 外接端子2 1 3與該些該些第二外接端子2丨4係具有高於 上述回銲溫度之嫁點。 該些複數個銲料2 3 0係接合該些第一外接端子2 1 3 至遠些第一連接端點2 2 3以及接合該些第二外接端子 - 2 1 4至該些第二連接端點224。在本實施例中，該封裝 載體220大致與上述之第一半導體封裝件21〇相同。該 封裝載體220係可為一第二半導體封裝件，而包含有一 第二基板221、一第二晶片222及複數個第三外接端子 227，其中該些第三外接端子227係設置於該第二基板 221之一下表面221B，該些第一連接端點223與該些第 二連接端點224係設置於該第二基板221之一上表面 221B 〇 〇 本發明之其中一技術特點係為，該些第一外接端子 213與該些第二外接端子214係包含不等高之凸塊，用 以縮小由該第一基板2 1 1之翹曲引起該些第—外接端 子2 1 3與該些第一連接端點2 2 3之間以及該些第二外接 端子2 1 4與該些第二連接端點2 2 4之間的銲料間隙差 異。 在一模擬試驗中可預測該第一基板2丨丨之翹曲度， 當該第一基板211之周邊係遠離該封裝載體22〇而往上 翹起時’該些第二外接端子214係可具有更高於該些第 13 200901408 一外接端子213之補償高度。藉此，該些第二外接端子 '、4 1第一連接端點224之間的銲料間隙不會過度 擴大’相肖於該些第一外接料213與該些第一連接端 點223之間的銲料間隙，兩者差異值可被銲料23〇容許 而達到有效銲接’無斷路問題’亦不會有冷銲、空銲或 假銲等銲接缺陷。In another embodiment, a semiconductor package bonding structure that avoids soldering defects caused by substrate warpage includes at least a first semiconductor package, a germanium carrier, and a plurality of solders. The first semiconductor package includes a first substrate, a first chip, a plurality of first external terminals, and a plurality of second external terminals, wherein the first external terminals and the second external terminals are disposed on the first external terminal First - the lower surface of the substrate. The package carrier includes a plurality of first connection endpoints and a plurality of second connection endpoints. The solders bond the first external terminals to the first connection terminals and the second connection terminals to the second connection terminals. The first substrate is defined by a center line, and the distance between the first external terminals and the center line is smaller than the distance between the first external terminals and the center line. The semiconductor package bonding structure further includes a plurality of compensation bumps, wherein the plurality of compensation bumps are selectively disposed at the one of the first connection end points and the second connection end points. The warpage of the first substrate causes a difference in solder gap between the first external terminals and the first connection terminals and between the second external contacts and the second connection terminals. [Embodiment] The first embodiment of the invention of the invention discloses a semiconductor package bonding structure which avoids soldering defects caused by substrate warpage. Referring to FIG. 2, a semiconductor package bonding structure 2A includes a semiconductor package #21G, a package carrier 22A, and a plurality of solders 230. The first semiconductor package 210 is disposed on the material (four) 220 and electrically coupled to the carrier 220 by the solders 23(). 10 200901408 The first semiconductor package 210 includes a first substrate 211, a first wafer 212, a plurality of first external terminals 213, and a plurality of second external terminals 2 14 . The first substrate 2 is electrically connected to the wafer carrier and the wafer is typically a printed circuit board. The first substrate 2 has an upper surface 211A and a lower surface 211B. The first crystal 212 is an integrated circuit, which may be a germanium according to its function, and may be a processor, a memory, a logic element, a special application integrated circuit or the above-mentioned wide mixing according to its function. The first external terminal 213 and the second terminal 214 are disposed on the connection pad 21 1D of the table 21 1B under the first substrate 211, and may be a columnar bump or a wire. The wire bumps are made of copper, gold or other conductive materials. The second external terminals 2 1 3 and the second external terminals 2 14 may have a half-cone section such as a semi-conical or trapezoidal body, which can serve as a micro-contact. More specifically, the first substrate 211 is a double-sided conductive board, that is, a connection port on the upper surface 211A is electrically connected to the connection pad 211D on the Q surface 211B. One of the first wafers 212 is actively oriented toward the first substrate 21 1 ' and bonded to the upper surface 211A of the first substrate 211 by a bonding adhesive, tape or flip chip. In the fourth embodiment, the first substrate 211 has a first slot 211C extending through the upper surface 211A and the lower surface 211B of the first substrate 211 to expose the first pad 212A of the first wafer 212. The first semiconductor package 2 1 0 may further include a plurality of first bonding wires 2 15 , and the first bonding wires 2 are formed by wire bonding and electrically connected through the first slot 2 1 1 C The first pad 212A of the first wafer 212 and the outer surface of the first substrate 211 are connected to the lower block r » the device 15 is connected to the 11 200901408 internal finger. The first semiconductor package 210 may further include a first encapsulant 2 1 6 ' formed in the first slot 211C' by a die or a dispensing method to seal the first bonding wires 215. The first encapsulant 216 may not cover the first wafer 2 1 2 so that the back surface of the first wafer 2 1 2 is exposed, which is advantageous for heat dissipation and package thinning. Therefore, in order to achieve thinning and bonding, the two edge sides of the first substrate 2 1 1 are not covered by the first wafer r 212 and the first encapsulant 216, and the upper surface 211A of the first substrate 211 is It is provided with an element whose lower surface 211B is asymmetric, and there is a phenomenon that the substrate warps under temperature cycling. As shown in FIG. 3, referring to FIG. 2, the first substrate 211 defines a center line 2 1 7 , and the distance S 1 of the first to external terminals 2 1 3 to the center line 2 1 7 is smaller than the The distance S 2 from the second external terminal 2 1 4 to the center line 2 17 . The center line 2 17 is defined by the central pad arrangement of the first wafer 212. The first slot 2 1 1 C of the first substrate 2 1 1 is along the center line 2 1 7 to expose a plurality of first pads 211A of the first wafer 212. As further shown in FIG. 2, the package carrier 22 includes a plurality of first connection endpoints 223 and a plurality of second connection endpoints 224. In this embodiment, the first connection end points 223 and the second connection end points 224 may be flat metal pads. The first semiconductor package 2 J is stacked on the package carrier 220, and the first external terminals 213 are aligned with the first connection terminals 223, and the second external terminals 2 1 4 is aligned with the second connection terminals 2 2 4 to facilitate soldering. Usually 12 200901408 Some I dry material 2 3 0 series can be no ship flux, with tin 9.6 % • silver 3% _ copper 〇 5 % solder, reaching the reflow temperature of about 217 degrees Celsius or above, the highest When the temperature is about 245 degrees Celsius, the wettability of the soldering can be generated, and the first external terminals 2 1 3 and the second external terminals 2丨4 have a wedding point higher than the reflow temperature. The plurality of solders 230 connect the first external terminals 2 1 3 to the far first connection terminals 2 2 3 and the second external terminals - 2 1 4 to the second connection terminals 224. In the present embodiment, the package carrier 220 is substantially the same as the first semiconductor package 21A described above. The package carrier 220 is a second semiconductor package, and includes a second substrate 221, a second chip 222, and a plurality of third external terminals 227, wherein the third external terminals 227 are disposed on the second a lower surface 221B of the substrate 221, the first connection end 223 and the second connection end 224 are disposed on an upper surface 221B of the second substrate 221. One of the technical features of the present invention is that The first external terminals 213 and the second external terminals 214 include bumps of unequal height for reducing the warpage of the first substrate 2 1 1 to cause the first external terminals 2 1 3 and the A difference in solder gap between the first connection terminals 2 2 3 and between the second external terminals 2 1 4 and the second connection terminals 2 2 4 . In a simulation test, the warpage of the first substrate 2 can be predicted. When the periphery of the first substrate 211 is lifted away from the package carrier 22, the second external terminals 214 can be The compensation height is higher than the external terminal 213 of the 13th 200901408. Thereby, the solder gap between the first connection terminals 224 of the second external terminals '1, 4 1 is not excessively enlarged' between the first external materials 213 and the first connection terminals 223 The solder gap, the difference between the two can be allowed by the solder 23 to achieve effective soldering 'no open circuit problem' and there will be no soldering defects such as cold soldering, empty soldering or false soldering.
如第4圖所示’本發明之第二具體實施例揭示一種 導體封裝接合構造’其主要元件大致與第一具體實施 同其包含至少一第一半導體封裝件210、一封裝載 以及複數個銲料230。其中除了該第一 件W之第-基板-，、第-外接端子213,與第2 接端子214,有所不相同之外，其餘元件可為相同，故以 相同圖號表示之。其中，該些第一外接端子213，與該些 "外接端子2 1 4，係設置於該第一基板2 1 1之一下表 面211B之連接墊211D。該第一半導體封裝件21〇之一 第的片212係可設置於該第一基板211，之一上表面 11八並電性連接至該第一基板211，。 、/在模擬试驗中可預測該第一基板2 1 1 ’之輕曲度， 當該第—基板211，之周邊係接近該封裝載體22〇而往 I翹起時，該些第一外接端子2 1 3，係可具有更高於該些 第一外接端子2 1 4 ’之補償高度。因此，能縮小因第—基 板2 1 1 ’之翹曲所引起的銲料間隙差異，所指者係為該些 第外接端子213’與該些第一連接端點223之間的銲 料間隙相對於該些第二外接端子214與該些第二遠垃 14 200901408 端點224之間的銲料間隙。 如第5圖所示’繪示本發明之第三具體實施例之一種 半導體封裝接合構造’其係主要包含至少一半導體封裝 件210、一封裝載體320以及複數個銲料330，其中該半導 體封裝件21 0係與第一具體實施例之第一半導體封裝件2 i 〇 為大體相同’故以相同圖號標示之。該半導體封裝件2 1 〇 係包含一基板211、一晶片212、複數個第一外接端子 f 213與複數個第一外接端子214，其中該些第一外接端 子213與該些第二外接端子214係設置於該基板211之 一下表面211B。並且，該些第一外接端子213至該基 板2 1 1之一中心線之距離係小於該些第二外接端子2 i 4 至3亥中心線之距離。該晶片2 1 2係設置於該基板2 1 1之 上表面211A並電性連接至該基板211。該基板211之 下表面211B具有可供設置該些第一外接端子213與該 些第二外接端子214之連接墊211D。一封膠體216係 〇 可局部密封該晶片212,但不覆蓋該基板211之兩邊緣 侧，以利於散熱與封裝薄化。 έ亥封裝載體320係包含複數個第一連接端點321與 複數個第二連接端點3 22。該些複數個銲料3 3 〇係接合 該些第一外接端子213至該些第一連接端點321以及接 合該些第二外接端子214至該些第二連接端點322。在 本實施例中，該封裝載體3 2 〇係為一印刷電路板，例如 主機板、記憶體模組載板、顯示卡載板、記憶卡基板或 手機通訊板等等。 15 200901408 外接端子2 1 3與該些第 214係包含不等高 、 >、二乐二外接端子 凸塊’用以縮小由該基板 曲引起該些第-外接端子213與 ：？… 之間以及該些第二冰4 二第—連接端點32! 接端子214與該些第二連接端點 3 2 2之間的在干料間隙罢民 '、。如苐5圖所示，當該基板211 之周遭係遂離該封裝恭 載體320而在上翹起時，此 端子214係具有更高 J -外接As shown in FIG. 4, 'the second embodiment of the present invention discloses a conductor package bonding structure' whose main components are substantially identical to the first embodiment, comprising at least a first semiconductor package 210, a load, and a plurality of solders. 230. The first component W, the first external terminal 213, and the second terminal 214 are different from each other, and the other components may be the same, and thus are represented by the same reference numerals. The first external terminals 213 and the external terminals 2 1 4 are disposed on the connection pads 211D of the lower surface 211B of the first substrate 2 1 1 . A first piece 212 of the first semiconductor package 21 can be disposed on the first substrate 211, and an upper surface 11 is electrically connected to the first substrate 211. / In the simulation test, the lightness of the first substrate 2 1 1 ' can be predicted. When the periphery of the first substrate 211 is close to the package carrier 22 and the I is lifted, the first external connection The terminal 2 1 3 may have a compensation height higher than the first external terminals 2 1 4 '. Therefore, the solder gap difference caused by the warpage of the first substrate 2 1 1 ' can be reduced, and the solder gap between the first external terminal 213 ′ and the first connection terminals 223 is relative to A solder gap between the second external terminals 214 and the second ends 14 200901408 terminals 224. As shown in FIG. 5, a semiconductor package bonding structure of a third embodiment of the present invention mainly includes at least one semiconductor package 210, a package carrier 320, and a plurality of solders 330, wherein the semiconductor package The first semiconductor package 2 i is substantially the same as the first embodiment, and is denoted by the same reference numerals. The semiconductor package 2 1 includes a substrate 211 , a wafer 212 , a plurality of first external terminals f 213 and a plurality of first external terminals 214 , wherein the first external terminals 213 and the second external terminals 214 It is disposed on one lower surface 211B of the substrate 211. Moreover, the distance between the first external terminals 213 and one of the center lines of the substrate 2 1 1 is smaller than the distance between the center lines of the second external terminals 2 i 4 to 3 . The wafer 2 1 2 is disposed on the upper surface 211A of the substrate 2 1 1 and electrically connected to the substrate 211. The lower surface 211B of the substrate 211 has a connection pad 211D for arranging the first external terminals 213 and the second external terminals 214. A piece of colloid 216 can partially seal the wafer 212, but does not cover the two edge sides of the substrate 211 to facilitate heat dissipation and package thinning. The package carrier 320 includes a plurality of first connection endpoints 321 and a plurality of second connection endpoints 3 22 . The plurality of solders 3 3 are used to bond the first external terminals 213 to the first connection terminals 321 and the second external terminals 214 to the second connection terminals 322. In this embodiment, the package carrier 32 is a printed circuit board, such as a motherboard, a memory module carrier, a display card carrier, a memory card substrate, or a mobile communication board. 15 200901408 The external terminal 2 1 3 and the 214th portions include unequal heights, >, Erle 2 external terminal bumps ′ to reduce the number of the first-external terminals 213 and :? ... and between the second ice 4 second - the connection end 32! The terminal 214 and the second connection end point 3 2 2 between the dry material gaps. As shown in FIG. 5, when the periphery of the substrate 211 is lifted up from the package carrier 320, the terminal 214 has a higher J-external connection.
Ο 如第6圖所示，揭太Γ 13之補償高度。 盅.t _ 揭不本發明之第四具體實施例之一種 驻姓… ^ 4〇0纟要包含至少-第-半導體封 件、一封裝載體㈣以及複數個鮮料430,並且該半 導體封裝接σ構造4G0另包含有複數個補償凸塊44〇。 該第一半導體封裝件41〇係包含—第一基板4ιι、一第一 晶片412、複數個第—外接端子4U與複數個第二外接端子 414’其中該些第一外接 锥％千413與该些第二外接端子414 係設置於該第-基板411之一下表面4UB。該第—晶片412 係可設置於該第-基板411之—上表面4UA或下表面 411Β。並可利用複數個絆線415電性連接該第—晶片川之 銲塾412Α至該第一基板411。 —該封裝載體42G係包含複數個第—連接端點423與複數 個第二連接端點424。在本實施例中，該封裝載體420係可 為-第二半導體封裝件，更包含_第二基板421及一第二晶 片422。第二半導體封裝件之封裝類型係可與該第一半導體 封裝件410相同或不相同。該第二晶片422係設置於該第二 基板421，其係利用該些銲料43〇接合該些第一外接端子々η 16 200901408 至該些第一連接端點423以及接合該些第二外接端子414至 該些第二連接端點424。其中，該第一基板411係定義有一 中心線，該些第一外接端子413至該中心線之距離係小於該 些第二外接端子414至該中心線之距離。 a玄些補佔凸塊440係選擇性設置於該些第一連接端點 423與該些第二連接端點之424其中一群組，用以縮小由該 第一基板411之翹曲引起該些第一外接端子413與該些第一Ο As shown in Figure 6, the compensation height of the Γ太Γ13.盅.t _ Unexpressed a fourth embodiment of the present invention ... ^ 4〇0纟 to include at least a -th semiconductor package, a package carrier (four) and a plurality of fresh materials 430, and the semiconductor package The σ structure 4G0 further includes a plurality of compensation bumps 44〇. The first semiconductor package 41 includes a first substrate 4 ι , a first wafer 412 , a plurality of first external terminals 4 U and a plurality of second external terminals 414 ′ The second external terminals 414 are disposed on a lower surface 4UB of the first substrate 411. The first wafer 412 may be disposed on the upper surface 4UA or the lower surface 411 of the first substrate 411. The first substrate 411 can be electrically connected to the first wafer 412 by a plurality of turns 415. - The package carrier 42G comprises a plurality of first connection terminals 423 and a plurality of second connection terminals 424. In this embodiment, the package carrier 420 can be a second semiconductor package, and further includes a second substrate 421 and a second wafer 422. The package type of the second semiconductor package may be the same as or different from the first semiconductor package 410. The second chip 422 is disposed on the second substrate 421 by using the solder 43 to bond the first external terminals 々η 16 200901408 to the first connection terminals 423 and to the second external terminals. 414 to the second connection endpoints 424. The first substrate 411 defines a center line, and the distance between the first external terminals 413 and the center line is smaller than the distance between the second external terminals 414 and the center line. The a plurality of complementary bumps 440 are selectively disposed on the first connection end point 423 and one of the second connection end points 424 to reduce the warpage caused by the first substrate 411. Some first external terminals 413 and the first ones
連接端點423之間以及該些第二外接端子4丨4與該些第二連 接端點424之間的銲料間隙差異。再如第6圖所示當該第 一基板411之兩邊緣側受到熱應力而依遠離該封裝載體 之方向往上翹曲a夸’該些補償凸_ 44〇則設置於該些第二連 接端點之424 ’藉以縮小對不同群組外接端子之銲料間隙差 異’解決基板趣曲之銲接缺陷，特別適用於高密度立體（3D) 封裝堆疊（POP)之微接觸銲接。 、斤述僅疋本發明的較佳實施例而已，並非對 x乍1何形式上的限制，本發明技術方案範圍當依 所附申請專利範圍為準。体 +任何热悉本專業的技術人員可 利用上述揭示的技術内 ㈣ 作出些許更動或修飾為等同 變化的等效實施例，但w β 、 ^ 一 疋未脫離本發明技術方案的内 谷’依據本發明的技術實 „ 買對以上實把例所作的任何簡 卓修改、專同變化粗体 44；. _ 、>飾’均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】A difference in solder gap between the terminal blocks 423 and between the second external terminals 4丨4 and the second connection terminals 424 is connected. Further, as shown in FIG. 6, when both edge sides of the first substrate 411 are subjected to thermal stress and warped upward in a direction away from the package carrier, the compensation protrusions _ 44 设置 are disposed on the second connections. The end point of 424 'to reduce the difference in solder gap between different groups of external terminals' solves the soldering defects of the substrate, especially suitable for high-density stereo (3D) package stack (POP) micro-contact soldering. It is to be understood that the preferred embodiments of the present invention are not intended to limit the scope of the invention, and the scope of the present invention is intended to be limited by the scope of the appended claims. Anyone skilled in the art can use the above-disclosed technology to make some modifications or modifications to equivalent embodiments, but wβ, ^ does not deviate from the technical solution of the present invention. The technical practice of the invention is as follows: any simple modification of the above embodiment, the special modification bold 44;. _, > decoration 'all still fall within the scope of the technical solution of the present invention.
習知半導體封裝 接合構造之截面示意圖 17 200901408 第2圖··依據本發明之第—具體實施例，一種半導體封 裝接合構造之截面示意圖。 第3圖··依據本發明之第一具體實施例，該半導體封裝 接合構造之一半導體封裝件之底面透視示意 圖。 弟4圖·依據本發明之第二具體實施例，一種半導體封 裝接合構造之載面示意圖。 第5圖·依據本發明之第三具體實施例，一種半導體封 裝接合構造之截面示意圊。 第6圖：依據本發明之第四具體實施例，一種半導體封 裝接合構造之截面示意圖。 【主要元件符號說明】 S1距離 S2距離 100半導體封裝接合構造 110第一半導體封裝件 111第一基板 (j 111A上表面 111B下表面 111C第一槽孔 11 2第一晶片 11 3凸塊 11 4第一銲線 11 5第一封滕體 120第二半導體封裝件 121第二基板 121Λ上表面 121B下表面 121C第二槽孔 121D連接墊 122第二晶片 123凸塊 124第二銲線 125第二封膠體 130銲料 200半導體封裝接合構造 18 200901408 1 1 U 弟一 早導體 2UA k上表面 211C >連接墊 212 第一 晶片 213 第一 外接端 214 第二 外接端 215 第一 銲線 220 封裝載體 2 2 1A上表面 222 第二 晶片 224 第二 連接端 227 第三 外接端 320 封裝載體 330 銲料 410 第一 半導體 4ΠA上表面 412 第一 晶片 413 第一 外接端 415 第一 銲線 420 封裝 載體 422 第二 晶片 424 第二 連接端 封裝件 211B下表面 212A第一鲜墊 子213’第一外接端子 子214’第二外接端子 2 1 6第一封踢體 221第二基板 2 2 1B下表面 222A第二銲墊 點225第二銲線 子230銲料 321第一連接端點 封裝件 411B下表面 412A第一銲墊 子414第二外接端子 416第一封膠體 4 2 1第二基板 423第一連接端點 點430銲料 211第一基板 211C第一槽孔 2 1 7中心線 22Γ第二基板 221C第二槽孔 223第一連接端點 226第二封膠體 322第二連接端點 411第一基板 440補償凸塊 19Schematic diagram of a conventional semiconductor package joint structure 17 200901408 Fig. 2 is a schematic cross-sectional view showing a semiconductor package joint structure according to a first embodiment of the present invention. Fig. 3 is a perspective view showing a bottom surface of a semiconductor package of a semiconductor package bonding structure in accordance with a first embodiment of the present invention. Figure 4 is a schematic view of a carrier surface of a semiconductor package joint structure in accordance with a second embodiment of the present invention. Fig. 5 is a cross-sectional view showing a semiconductor package joint structure according to a third embodiment of the present invention. Figure 6 is a cross-sectional view showing a semiconductor package joint structure in accordance with a fourth embodiment of the present invention. [Main element symbol description] S1 distance S2 distance 100 semiconductor package bonding structure 110 first semiconductor package 111 first substrate (j 111A upper surface 111B lower surface 111C first slot 11 2 first wafer 11 3 bump 11 4 a bonding wire 11 5 first sealing body 120 second semiconductor package 121 second substrate 121 upper surface 121B lower surface 121C second slot 121D connecting pad 122 second wafer 123 bump 124 second bonding wire 125 second sealing Colloid 130 solder 200 semiconductor package bonding structure 18 200901408 1 1 U first conductor 2UA k upper surface 211C > connection pad 212 first wafer 213 first external end 214 second external end 215 first bonding wire 220 package carrier 2 2 1A Upper surface 222 second wafer 224 second connection end 227 third external end 320 package carrier 330 solder 410 first semiconductor 4A upper surface 412 first wafer 413 first external end 415 first bonding wire 420 package carrier 422 second wafer 424 Second connecting end package 211B lower surface 212A first fresh mat 213' first external terminal 214' second external terminal 2 1 6 first kicking body 221 second substrate 2 2 1B lower surface 222A second pad point 225 second wire 230 solder 321 first connection end package 411B lower surface 412A first pad 414 second external terminal 416 first seal 4 2 1 second substrate 423 first connection end point 430 solder 211 first substrate 211C first slot 2 1 7 center line 22 Γ second substrate 221C second slot 223 first connection end point 226 second encapsulant 322 Two connection end points 411 first substrate 440 compensation bumps 19