200901143 九、發明說明： 【發明所屬之技術領域】 士毛明係關於一種液晶顯示裝置及其驅動方法。 【先珂技術】 r J ::顯不裝置具有輕、薄、短小且耗電少等優點， 用於筆記型電腦、行動電話及個人數位助理等 現代化貧訊設備。 立明 > 閱圖1，係一種先前技術液晶顯示裝置之結構示 思圖、。該液晶顯示裝置100包括一液晶面請、用於控 制"亥液a曰面板10J之一閘極驅動器1〇2及一源極驅動器 103、=控制該閘極驅動器1〇2及該源極驅動器之時序 控制器104及一為該液晶面板1〇1提供公共電壓之公此 壓電路105。 、 该液晶面板101包括複數平行等間距設置之閘極線 U0、複數與該閘極線110平行且間隔設置之公共線13〇、 複數與該閘極線110絕緣垂直設置之資料線120及複數由 該間極線110及該資料線12〇交又界定之像素單元14〇。 其中，該閘極線110連接至該閘極驅動器102，該資料線 120連接至該源極驅動器1〇3，該公共線13〇連接至該公共 電壓電路105。 a 該像素單元140包括一薄膜電晶體ι41、一像素電極 142及一公共電極143。該薄膜電晶體14ι包括一閘極、一 源極及一汲極，其分別連接至該閘極線11〇、資料線12〇 及該像素電極142。該像素電極142、該公共電極ι43及夾 6 200901143 於二者間之液晶層組成一液晶電容147，該像素電極142、 該公共線130及二者間之絕緣層構成一存儲電容148。 . 當該液晶顯示裝置100顯示第N幀晝面時，該公共電 壓電路105產生公共電壓並施加至該公共線130及該公共 電極143。該閘極驅動器102在該時序控制器104產生之 時序訊號控制下產生掃描訊號，並依次施加至該閘極線 110，使與該閘極線110相連之一列薄膜電晶體141導通。 同時，該源極驅動器103在該時序控制器104產生之時序 " 訊號控制下將其產生之資料電壓施加至該資料線120，並 措由該薄膜電晶體141將該貧料電壓施加至該像素電極 142，且對該液晶電容147及該存儲電容148充電。該液晶 顯示裝置100顯示第N幀晝面時，該存儲電容148使該液 晶電容147保持一穩定之灰階電壓，直至第N + 1幀晝面掃 描訊號之到來。該公共電極143及該像素電極142間之液 晶分子在該灰階電壓作用下發生偏轉，控制通過該液晶面 板101之光能量，進而顯示晝面。 該像素單元140利用該存儲電容148保持第N幀之灰 階電壓，且該液晶顯示裝置100還存在大量寄生電容，如 存在於該薄膜電晶體141之閘極與源極間之閘源電容、閘 極與汲極間之閘汲電容及源極與汲極間之源汲寄生電容 等，故，該像素單元140之晝面由第N幀切換至第N + 1 幀時，受上述電容耦合訊號之影響，該公共電極143之電 位發生偏移。 請參閱圖2，係圖1所示液晶顯示裝置100中該像素 7 200901143 單疋140之驅動波形圖。其中，曲線201表示理想狀態下 該公共電極143之公共電壓Vcom’，曲線202表示該像素電 極142所接受之資料電壓’曲線203表示實際上該公此和 極⑷之公共電壓。 ” 在第N-1幀時資料電壓為Ui，公共電極143之公共電 C為等於公共電壓vc()m'，第N-1幀之灰階電壓為 Ul-Vl °第N幀之資料電壓為U2 ’其值小於資料電壓， 該公共電壓為Vs，第N幀之灰階電壓為％_乂2，因該像素 電極142及該公共電極143組成該液晶電容μ?及前述寄 生電容之影響，灰階電壓不會發生突變。故，第幀2 灰^私壓Ul~Vi等於第N幀之灰階電壓u2-V2，即R-V 112 V2，由此可以得出第n幀之公共電壓為v〜 即:2,〈"〜，使公共電W V y之初始階段被下拉，’然後恢復為公共電壓 vC〇m + ::;形圖上顯示為-尖峰。第N+1幀之公共電壓為 電壓為U3A於該資料電壓U2， =200901143 IX. Description of the invention: [Technical field to which the invention pertains] Shi Maoming relates to a liquid crystal display device and a driving method thereof. [Advanced Technology] r J: The display device is light, thin, short, and consumes less power. It is used in modern audio-visual equipment such as notebook computers, mobile phones, and personal digital assistants. Li Ming > FIG. 1 is a structural diagram of a prior art liquid crystal display device. The liquid crystal display device 100 includes a liquid crystal surface for controlling a gate driver 1〇2 of a liquid panel 10J and a source driver 103, controlling the gate driver 1〇2 and the source. The timing controller 104 of the driver and a common voltage circuit 105 for supplying a common voltage to the liquid crystal panel 101. The liquid crystal panel 101 includes a plurality of gate lines U0 arranged in parallel at equal intervals, a plurality of common lines 13 平行 parallel to the gate lines 110 and spaced apart from each other, and a plurality of data lines 120 and a plurality of lines vertically insulated from the gate lines 110. The pixel unit 14 is defined by the interpolar line 110 and the data line 12. The gate line 110 is connected to the gate driver 102, and the data line 120 is connected to the source driver 1?3, and the common line 13 is connected to the common voltage circuit 105. a The pixel unit 140 includes a thin film transistor ι41, a pixel electrode 142, and a common electrode 143. The thin film transistor 14i includes a gate, a source and a drain connected to the gate line 11A, the data line 12A and the pixel electrode 142, respectively. The pixel electrode 142, the common electrode ι43 and the clip 6 200901143 form a liquid crystal capacitor 147 between the liquid crystal layers. The pixel electrode 142, the common line 130 and the insulating layer therebetween constitute a storage capacitor 148. When the liquid crystal display device 100 displays the Nth frame, the common voltage circuit 105 generates a common voltage and applies it to the common line 130 and the common electrode 143. The gate driver 102 generates a scan signal under the control of the timing signal generated by the timing controller 104, and sequentially applies the gate signal to the gate line 110 to electrically connect one of the thin film transistors 141 connected to the gate line 110. At the same time, the source driver 103 applies the data voltage generated by the source driver 103 to the data line 120 under the timing control signal generated by the timing controller 104, and applies the thin film transistor 141 to apply the lean voltage to the data line 141. The pixel electrode 142 charges the liquid crystal capacitor 147 and the storage capacitor 148. When the liquid crystal display device 100 displays the Nth frame, the storage capacitor 148 maintains the liquid crystal capacitor 147 with a stable gray scale voltage until the N+1 frame scan signal arrives. The liquid crystal molecules between the common electrode 143 and the pixel electrode 142 are deflected by the gray scale voltage, and the light energy passing through the liquid crystal panel 101 is controlled to display the surface. The pixel unit 140 uses the storage capacitor 148 to maintain the gray scale voltage of the Nth frame, and the liquid crystal display device 100 also has a large amount of parasitic capacitance, such as the gate capacitance existing between the gate and the source of the thin film transistor 141, The gate capacitance between the gate and the drain and the source parasitic capacitance between the source and the drain, etc., so that when the pixel plane of the pixel unit 140 is switched from the Nth frame to the N+1 frame, the capacitive coupling is performed. The potential of the common electrode 143 is shifted by the influence of the signal. Please refer to FIG. 2 , which is a driving waveform diagram of the pixel 7 200901143 unit 140 in the liquid crystal display device 100 shown in FIG. 1 . Here, the curve 201 represents the common voltage Vcom' of the common electrode 143 in an ideal state, and the curve 202 indicates that the data voltage received by the pixel electrode 142' curve 203 represents the common voltage of the common electrode (4). The data voltage is Ui at the N-1th frame, the common power C of the common electrode 143 is equal to the common voltage vc()m', and the grayscale voltage of the N-1th frame is the data voltage of the Nth frame of the U1-V1° frame. It is U2' whose value is smaller than the data voltage, the common voltage is Vs, and the gray scale voltage of the Nth frame is %_乂2, because the pixel electrode 142 and the common electrode 143 constitute the liquid crystal capacitor μ? and the influence of the aforementioned parasitic capacitance The gray-scale voltage does not change. Therefore, the frame 2 ash ^ private pressure Ul~Vi is equal to the gray-scale voltage u2-V2 of the N-th frame, that is, RV 112 V2, thereby obtaining the common voltage of the n-th frame v~ ie: 2, <"~, make the initial stage of the public electric WV y pulled down, 'then return to the common voltage vC〇m + ::; the figure is shown as - spike. The public of the N+1th frame The voltage is U3A at the data voltage U2, =
以侍到第N+1幀夕八u兩r、 /ίΓ J 壓U3大於該資料電；7 £ V3 = Vc°m,+ (U3-U2)。因資料電 該公共電墨％於今第N2: L 3’>0’V2>V“，導致 為公共電壓Vc :二 貞之初始階被上拉，然後恢復 _ com “波升乂圖上亦表現為一尖峰。 電4=裝:::中’每-像素單一應之公共 導致電壓不準確，：==且受電容之輕合作用， 而使該液日日顯示裝置100出現串音， 8 200901143 影響顯不效果。 【發明内容】 有鑑於此，提供—種串立一 晶顯示裝置實為必要。 曰又-，頌示效果較佳之液 另，提供一種串音較 裝置之驅動方法實為必要-、、不，果較佳之液晶顯示 一種液晶顯示裝 路。該液晶面板接收外液晶面板與-極性重排電 性重排電路接枚第N(N=2 %《麥考電壓及訊號。該麵 第N幢顯示訊號進行調整二，：二)幅顯示訊號，且斜 顯示訊號所對應電壓之差估使弟Ν·“貞與調整後第N鴨 並輸出整理後之第N幢：不大於調整前之電壓差值， 乐幀顯不訊號。 種液晶顯示^ & —，接收第N(N = 2^ 3，4 方法，包括以下步驟：步驟 號；步驟二，調敕第 ：.···)幅顯不訊號與極性正負訊 後第N幀顯亍 ”'、員不訊號，使第N-1幀與調整 屢差值；對應—值不大於調整前之電 該液晶顯示掌置及並^之弟Ν_不訊號。 使調整後之第Ν幀顧-:、：*方法對顯示訊號進行調整， 之差值小於調整前義示訊號所對應電 之參考電壓受竽第值’進而使該液晶顯示裝置 考電_確，:二顯示訊號對應之電屋拉動較小，參 【實施方使液晶顯示裝置之串音得到有效控制。 '參閱圖3’係、本發明液晶顯示裝置—較佳實施方式 9 200901143 之結構示意圖。該液晶顯示裝置300包括一液晶面板301、 一閘極驅動器302、一源極驅動器303、一公共電壓電路 • 305、一存儲器306及一時序控制器304。 該時序控制器304包括一第一端口 314、一第二端口 324、一分析單元334、一查找表344及一極性重排電路 3 5 4。該第一端口 314接受來自外部之顯示訊號。該第二端 口 324連接至該閘極驅動器302，用於向該閘極驅動器302 提供時序訊號。該查找表344内部存儲不同顯示訊號所對 1 應之資料電壓值。該存儲器306内存儲相鄰二ψ貞顯示訊 號。該分析單元334之一端連接至該存儲器306，另一端 連接至該查找表344，可對相鄰二幀晝面顯示訊號所對應 之資料電壓值進行分析，該分析單元334還與該極性重排 電路354相連，向該極性重排電路354提供分析結果及顯 示訊號。該極性重排電路354接受該分析單元334之分析 結果，對顯示訊號進行整理，且向該源極驅動器303提供 資料訊號。 / 該閘極驅動器302及該源極驅動器303與該時序控制 器304相連，接受其輸出之訊號，且分別向該液晶面板301 提供掃描訊號及資料電壓。該公共電壓電路305向該液晶 面板301提供公共電壓。 該液晶面板301包括複數平行間隔設置之閘極線 310、複數與該閘極線310平行且間隔設置之公共線330、 複數與該閘極線310絕緣垂直之資料線320及複數由該資 料線320及該閘極線310分隔界定之像素單元340。其中， 10 200901143 該閘極線310連接至該閘極驅動器302，用於接收該閘極 驅動器302之掃描訊號。該資料線320連接至該源極驅動 ’器303，用於接收該源極驅動器303之資料電壓。該公共 線330連接至該公共電壓電路305，用於接收該公共電壓 電路305之公共電壓。 該像素單元340包括一薄膜電晶體341、一像素電極 342及一公共電極343。該薄膜電晶體341之閘極、源極及 汲極分別連接至對應之閘極線310、資料線320及像素電 ^ 極342。該公共電極343連接至該公共線330。該像素電極 342、該公共電極343及夾於二者間之液晶層構成一液晶電 容347。該像素電極342、該公共線330及夾於二者間之絕 緣層構成一存儲電容348。 該液晶顯示裝置300之基本工作原理如下所述： 該液晶顯示裝置300之時序控制器304接收外部之顯 示訊號，藉由該時序控制器304中之分析單元334從該查 找表344中查找相鄰二幀顯示訊號所對應之資料電壓值， 〆 且對每一像素單元340相鄰二幀之資料電壓值求差值。然 後，該分析單元334計算每一像素單元340後一幀顯示訊 號之資料電壓相對於公共電壓進行極性反轉後之資料電壓 值，且將每一像素單元340反轉後之資料電壓值與前一幀 資料電壓值求差值。接下來，該分析單元3 3 4將兩次求差 值進行比較，將較小差值所對應之資料電壓值作為像素單 元資料電壓之數值，並判斷該資料電壓相對於公共電壓之 極性正負，輸出資料電壓之極性正負訊號。最後，該分析 11 200901143 .料電壓之極性正負訊號及顯示訊號傳輸至該 Γ:=路。354。該極性重排電路…藉由該分析單^ : 心虎對顯不訊號進行調整，具體做法為：對該The waiter reaches the N+1th frame 八八u two r, /ίΓ J pressure U3 is greater than the data; 7 £ V3 = Vc°m, + (U3-U2). Because of the data, the public ink is now in the N2: L 3'>0'V2>V", resulting in the public voltage Vc: the initial step of the second is pulled up, and then restored _ com "wave rise map also shows It is a spike. Electricity 4 = installed::: in the 'every-pixel single, the common cause voltage inaccuracy, :== and by the light cooperation of the capacitor, so that the liquid daily display device 100 appears crosstalk, 8 200901143 effect is not obvious effect. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a tandem display device.曰 - -, 颂 效果 效果 较佳 颂 颂 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另 另The liquid crystal panel receives the outer liquid crystal panel and the -polar rearrangement electrical rearrangement circuit and the Nth (N=2% "McCow voltage and signal. The Nth display signal of the surface is adjusted by two, two: two) display signal And the difference between the voltages corresponding to the oblique display signal is estimated to be the first N building after the adjustment and the Nth duck after the adjustment: no more than the voltage difference before the adjustment, the music frame shows no signal. ^ & -, receive the Nth (N = 2^ 3, 4 method, including the following steps: step number; step two, tweeting::···) The amplitude of the signal and the polarity of the positive and negative after the Nth frame亍"', the staff does not signal, so that the N-1 frame and the adjustment of the repeated difference; corresponding - the value is not greater than the power before the adjustment of the liquid crystal display palm and ^ 之 Ν _ no signal. The adjusted third frame--:,:* method adjusts the display signal, and the difference is smaller than the reference voltage of the electric power corresponding to the pre-adjustment signal, and then the liquid crystal display device is tested. , : The second display signal corresponds to the electric house pulling less, and the implementation side enables the crosstalk of the liquid crystal display device to be effectively controlled. Referring to Fig. 3, a schematic structural view of a liquid crystal display device of the present invention, which is a preferred embodiment 9 200901143. The liquid crystal display device 300 includes a liquid crystal panel 301, a gate driver 302, a source driver 303, a common voltage circuit 305, a memory 306, and a timing controller 304. The timing controller 304 includes a first port 314, a second port 324, an analysis unit 334, a lookup table 344, and a polarity rearrangement circuit 345. The first port 314 accepts display signals from the outside. The second port 324 is coupled to the gate driver 302 for providing timing signals to the gate driver 302. The lookup table 344 internally stores data voltage values corresponding to different display signals. The memory 306 stores adjacent binary display signals. One end of the analyzing unit 334 is connected to the memory 306, and the other end is connected to the lookup table 344, and the data voltage value corresponding to the adjacent two frames of the display signal can be analyzed, and the analyzing unit 334 is further rearranged with the polarity. Circuitry 354 is coupled to provide analysis results and display signals to the polarity rearrangement circuit 354. The polarity rearranging circuit 354 receives the analysis result of the analyzing unit 334, sorts the display signal, and supplies the source driver 303 with a data signal. The gate driver 302 and the source driver 303 are connected to the timing controller 304, receive the signal of the output, and provide the scanning signal and the data voltage to the liquid crystal panel 301, respectively. The common voltage circuit 305 supplies a common voltage to the liquid crystal panel 301. The liquid crystal panel 301 includes a plurality of parallel spaced gate lines 310, a plurality of common lines 330 parallel to the gate lines 310 and spaced apart from each other, a plurality of data lines 320 insulated from the gate lines 310, and a plurality of data lines. 320 and the gate line 310 separate the defined pixel unit 340. Wherein, 10 200901143, the gate line 310 is connected to the gate driver 302 for receiving the scan signal of the gate driver 302. The data line 320 is coupled to the source driver 303 for receiving the data voltage of the source driver 303. The common line 330 is coupled to the common voltage circuit 305 for receiving a common voltage of the common voltage circuit 305. The pixel unit 340 includes a thin film transistor 341, a pixel electrode 342, and a common electrode 343. The gate, the source and the drain of the thin film transistor 341 are respectively connected to the corresponding gate line 310, the data line 320 and the pixel electrode 342. The common electrode 343 is connected to the common line 330. The pixel electrode 342, the common electrode 343, and the liquid crystal layer sandwiched therebetween constitute a liquid crystal capacitor 347. The pixel electrode 342, the common line 330, and the insulating layer sandwiched therebetween form a storage capacitor 348. The basic operation principle of the liquid crystal display device 300 is as follows: The timing controller 304 of the liquid crystal display device 300 receives an external display signal, and the analysis unit 334 in the timing controller 304 searches for the neighbors from the lookup table 344. The two frames display the data voltage values corresponding to the signals, and the difference between the data voltage values of two adjacent frames of each pixel unit 340. Then, the analyzing unit 334 calculates a data voltage value after the polarity of the data voltage of the display signal of the next frame of each pixel unit 340 is inverted with respect to the common voltage, and the data voltage value of each pixel unit 340 is inverted. One frame of data voltage value is used to determine the difference. Next, the analyzing unit 314 compares the two difference values, and uses the data voltage value corresponding to the smaller difference as the value of the pixel unit data voltage, and determines whether the data voltage is positive or negative with respect to the polarity of the common voltage. The polarity of the output data voltage is positive and negative. Finally, the analysis 11 200901143. The polarity of the material voltage positive and negative signals and display signals are transmitted to the Γ:= road. 354. The polarity rearrangement circuit... by the analysis list ^: the heart and tiger adjust the display signal, the specific method is:
二、：二，加—極性控制位’來充分表示顯示訊號及其對 應貧枓電壓相對於公丘+厭 JT 敕德fi -1 $ 、Λ /、电£之極性正負訊號。其中，該調 整後顯不訊號對應之資料帝殿 資料電壓值之罢佶丨、二，/、其耵—幀顯示訊號對應之 小於顯不訊號調整前之差值。然後，哕 極性重排電路354蔣，敕你+ 3S - ΠΛ 至該源極驅動電路3〇; 不訊號作為資料訊號傳輪 轉化為資料電壓施加至4: 严303將資料訊號 、士、私坚她加至該像素早疋340之像素電極342。 ^ Λ液日日顯不裝置300第X條閘極線330連接之像 小早元340為例做詳細描述： 當該液晶顯示裝置300顯示第ν(ν = 2，3，4,.. 夺：時序控制器3〇4產生時序訊號，並施加至兮 閘極驅動器302。 通 該閘極驅動态3〇2在該時序訊號作用下，產生 加至該閘極線31〇。當該掃描訊號施加 至肩弟X條閘極線310時’與該閘極線31〇相 列薄膜電晶體341導通。 Χ 垓呤序控制态3〇4藉由其第一端口 3 w接 像素皁兀340第Ν幀每一像素單元34〇之顯示訊號~列 2 ...... Dn，將其存儲於該存儲器306，並將該孽干 號H……、Dn傳輸至該分析單元334。 ‘4不讯 该分析單元334從該查找表344中查找將該顯示訊 12 200901143 .唬D: ?2、.·...·、Dn對應之資料電壓值u、n Un ’ έ亥貧料電壓值Ui、％、 1 U2、......、 將該顯示訊號Di、D、2 ··’.，_、Un係該源極驅動器303像素單Tt 34G像素電極34 ^化後對應施加至相應 元334從該存儲器3〇6令讀^值。同時，該分析單 N-1幀時每—像辛 列像素早元340在第 $不早凡340之顧+ 奋 Dn’’並將該顯示訊號Di，、〇2’、……、Ui’、U2’、··.·.·、u，從查找表中杳出。二;:！之，值 每一像素單元之第^貞資料電^^^析早兀说將 第N-1幀資料電壓值U〆、u ,、 2……、Un與每-資料電壓第Ν㈣："貞間之別得出IV、…> υη-υπ-〇 巾貞間之差值〜IV、υ2_ 該分析單元334還將 公共電極343之八Α + 不1Ν幀之貝枓電壓相對於該 轉極性之資:二二重\_之極性進行反轉，得到反…枓電壓值可、可、......、ΰ：，即Second, the second: plus - polarity control bit 'to fully indicate the display signal and its corresponding barren voltage relative to the Gongqiu + tired JT Jude fi -1 $, Λ /, electric £ polarity positive and negative signals. Wherein, after the adjustment, the voltage corresponding to the information of the Emperor's data is dissipated, the second, and the 耵-frame display signal corresponds to the difference before the adjustment of the signal. Then, 哕 polarity rearrangement circuit 354 蒋, 敕 you + 3S - 至 to the source drive circuit 3 〇; no signal as a data signal transfer wheel into a data voltage applied to 4: Yan 303 will be information signal, Shi, private She adds to the pixel electrode 342 of the pixel 340. ^ The sputum daily display device 300 X-th gate line 330 is connected as the small early 340 as an example for detailed description: When the liquid crystal display device 300 displays the first ν (ν = 2, 3, 4, .. The timing controller 3〇4 generates a timing signal and applies it to the gate driver 302. The gate driving state 3〇2 is generated by the timing signal to be applied to the gate line 31〇. When the scanning signal is When applied to the X-th gate line 310 of the shoulder brother, 'the thin film transistor 341 is turned on with the gate line 31〇. Χ The control state 3〇4 is connected to the pixel sap 340 by its first port 3 w The display signal ~ column 2 ... Dn of each pixel unit 34 is stored in the memory 306, and the dry numbers H..., Dn are transmitted to the analysis unit 334. '4 The analysis unit 334 does not search the lookup table 344 for the data voltage value u, n Un ' corresponding to the display signal 12 200901143 .唬D: ?2, . . . , Dn Ui, %, 1 U2, ..., the display signal Di, D, 2 ··', _, Un is the source driver 303 pixel single Tt 34G pixel electrode 34 ^ is correspondingly applied to Corresponding element 33 4 from the memory 3 〇 6 command to read the value. At the same time, the analysis of the single N-1 frame every time - like the sin-column pixel early 340 in the first $ 340 ff + 奋 Dn ' ' and the display signal Di,, 〇 2', ..., Ui', U2', ······, u, from the lookup table. Second;:!, the value of each pixel unit of the ^ ^ ^ ^ ^^ Analysis of the early Nguyen said that the N-1 frame data voltage values U 〆, u,, 2 ..., Un and each - data voltage Ν (four): " 贞 之 得出 得出 IV - Difference between the wipes 〜~IV, υ2_ The analysis unit 334 also reverses the impedance of the 电极8 不+ Ν1 frame of the common electrode 343 with respect to the polarity of the polarity: the polarity of the second and second weights , get anti... 枓 voltage value can, can, ..., ΰ:, ie
Ui-V Un-V :v ：v com· _ 1 5 U2-Vc〇m = Vc〇m- ΰ： , _....·， 料，此種情況下因該公共電壓Vc_與該資 %值之絕對值不變’透過液晶電容347中液晶分 :之ί透過率不變，故可保證顯示效果不變。然 分析早兀334將極性反轉之資料電壓值巧、可、、『 與第Ν—丄幀資料$壓值1,、％，、......、队’相減，分別得 出差值IVW、u2_U2’、……、U：_Un,，且將該差值盥該 貢枓電壓值第N巾貞與第N-1幀間之差值I，、 I；2’、……ϋη- IV分別進行比較，取較小差值對應之資^ com· com. 13 200901143 電壓值，例如：當可_ u 電壓值，並輸出一資料電二於〜〜時，㈣作為資料 'υ XJ ,H± ^ 、電ι呙反轉之訊息；當ϋ；_ ιν大於 υι-仏蚪，取仏作為資 公共電壓、之極性正負Γ 判斷該資料電壓對應 該顯示訊號經該分析 元34Π 1S _ . 啊早兀334處理後，部份像素單 兀340顯不§κ號對應之 + 像素單S 34"頁示訊?#之次'“進行極性反轉’其餘 艎。访八 σ _ )u貧料電壓值不需進行極性反 以刀斤早兀334將每—像素單it 340之顯示m號及 〜，.、員不訊號對應之資料電壓極性正負之訊息一送。至 該極性重排電路354。通當，1次& 、 ^ ^ 吊该—貝枓訊號為§位數位訊號， =256個灰階資料電厂堅。，然，該分析單元334處理 訊號包含資料電壓相對公共電極^之極性正 雜性重排電路354對該顯示訊號進行調整， I广二位，即利用9位數位訊號表示資料 個灰階資料電壓，例如：當8位數位訊 =不m灰階㈣電壓時’其顯示訊號為細應， =亥顯示訊號對應之資料電壓相對於公共電壓^極性 為正時，該極性重排電路將其轉化& 1〇ι〇ιι〇ιι，末位之 1作為極性控制位，代表轉化後資料訊號對應之資料電壓 相對公共電極VC()m之極性為9 料相對於公共電麼：。為:性rr:號對應之資 com倥Γ玍马負時，該極性重排電 路354將其轉化Ί〇1〇1麵，末位之〇亦作為極性控制 立，代表轉化後之貧料訊號對應之f料職相對公共電 極Vc〇m之極性為負。 a 14 200901143 . 經该時序控制器304之極性重排+ 後之資料訊號傳輸至該源極驅動器二：5:進行調整 3〇3將該資料訊號轉化為 ：：極驅動器 至該複數資料線320。同時，第乂^將^貝料電壓施加 閘極驅動器3〇2之掃 /專膜電晶體341在該 .. &饰^田訊唬作用下處於聱捅曲处 ^ ^ 枓電壓藉由該複數資料線32〇及 ，曰I怨，该貢 至該像素單元340之像素電極3427，4 Μ體341施加 該像素電極342之資料電壓盘哼干 共電壓間之存在差值，誃;，、电極343之公 α49 „ Λ是值為灰階電壓。該像辛㊉搞 及邊么共電極343間液晶層之液 ，、私11 作用下發生偏轉，控制通過該液曰夜;^在錢階電壓 晶顯示裝置3〇〇逹丨 日日g之光忐量，使該液 i衣直：5UU達到顯不圖像之目的。 相較先前技術，本發明液晶顯示裝置3 =^_應之#料電堡之極性進行 昏 不裝置300每一像素單元34〇調整 :該液曰日顯 應之資料電壓與帛Ν 負‘.，，員不訊唬對 小於調整前之差值，進:二:；：資料繼值 340相鄰裝置所有像素單元 電極343電壓因液日^ 1之^和比較小’最終使公共 i mm-、 谷之耦合作用受像素電極342之 弟N幢貧料電壓拉動 _ 342之 事音得到有效控制。即^共％極之電位較準確， 本發明液晶顯示裝置3〇〇 如該極性重排電路女 、’_义；上述實施例， 極性控制位，該分析單將顯示訊號增加-首位作為 。亥刀析早凡gw可與該極性重排電路Μ# 15 200901143 •正σ在起，该液晶顯示裝置300之;^ α 合至該時序控制器304。 00之存儲器306亦可整 請參閱圖4,係本發明液晶顯示事置3加 之流程圖。該驅動方法包括以下步：·· 00之驅動方法 步驟5 01，接收筮沾 _ 顯示訊號； 、不訊號，並存儲該第N幀 該時序控制器304藉由第 口 示裝置300第X列像素單 接收該液晶顯 ^ _ 干疋340第n幀顯亍句雜 _ 訊號傳輸至該分析單元334,同時將㈣:Λ該 入該存儲器306。 ，，〜，.，、員不Λ唬存儲 步驟502，讀取第Ν-1幀 與第Nf貞顯示訊號進行分析Υ具不讯號’並將其資料電璧 示訊號，該分析單元334 ::弟N-1鳩顯 之每一傻去留—〜查找表344中查找其對庫 象素早兀340之資料電壓值。 〜 334從查找表344中杳 、、後。亥刀析早元Ui-V Un-V :v :v com· _ 1 5 U2-Vc〇m = Vc〇m- ΰ: , _....·, material, in this case due to the common voltage Vc_ and the capital The absolute value of the % value does not change. 'The liquid crystal is divided by the liquid crystal capacitor 347: the transmittance is unchanged, so the display effect is guaranteed to be unchanged. However, the analysis of the early 兀334 334 reversed the polarity of the data voltage value, can be, and "with the first Ν - 丄 frame data $ pressure value 1,,%,, ..., team' subtracted, respectively The difference IVW, u2_U2', ..., U: _Un, and the difference 盥 the difference between the N-th frame and the N-1th frame of the Gongga voltage value I, I; 2', ... Ϋη- IV is compared separately, taking the corresponding value of the smaller difference ^ com· com. 13 200901143 voltage value, for example: when _ u voltage value, and output a data electricity two ~ ~, (four) as the data 'υ XJ, H±^, electric 呙 reversal message; when ϋ; _ ιν is greater than υι-仏蚪, take 仏 as the public voltage, the polarity is positive and negative Γ judge the data voltage corresponding to the signal through the analysis element 34 Π 1S _ . 啊 兀 兀 334 after processing, part of the pixel 兀 340 is not § κ number corresponding to + pixel single S 34 " page display? #次 '" polarity reversal' remaining 艎. Visit eight σ _) u poor material voltage value does not need to be reversed to the polarity of the knife 334 will be displayed per pixel single it 340 m and ~,., the signal is not the corresponding signal voltage polarity positive and negative information sent to The polarity rearrangement circuit 354. The normal, 1 time & ^ ^ hang the - Bellow signal is the § digit signal, = 256 gray scale data power plant. However, the analysis unit 334 processing the signal contains data The polarity positive cross-rearrangement circuit 354 of the voltage relative to the common electrode 354 adjusts the display signal, and the I wide two bits, that is, the 9-digit bit signal is used to indicate the gray scale data voltage of the data, for example, when the 8-bit bit information = not m When the gray level (four) voltage is 'the display signal is fine, when the data voltage corresponding to the display signal is positive relative to the common voltage ^ polarity, the polarity rearrangement circuit converts it to & 1〇ι〇ιι〇ιι Bit 1 is used as the polarity control bit, which represents the data voltage corresponding to the converted data signal. The polarity of the data relative to the common electrode VC()m is 9 material relative to the public power::: rt: the corresponding com 倥Γ玍 horse When negative, the polarity rearrangement circuit 354 converts it into Ί〇1〇1 surface, and the last position is also used as the polarity control, which represents that the polarity of the f-device relative common electrode Vc〇m corresponding to the converted poor signal is Negative. a 14 200901143 . via the timing controller 304 After the sex rearrangement + data signal is transmitted to the source driver 2: 5: adjust 3〇3 to convert the data signal into:: pole driver to the complex data line 320. At the same time, the first 将^ will be the material voltage The sweep/special film transistor 341 to which the gate driver 3〇2 is applied is in a meandering position under the action of the .. & ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The pixel electrode 3427, the pixel body 341 of the pixel unit 340 applies the difference between the data voltage and the common voltage of the pixel electrode 342, and the common electrode of the electrode 343 is α49 „ It is the gray scale voltage. The image of the liquid crystal layer of the common electrode 343 between the symplectic and the ninth, the deflection of the liquid crystal layer under the action of the private 11, the control through the liquid day and night; ^ in the money level voltage crystal display device 3 〇〇逹丨 day g light忐 ,, so that the liquid i clothing straight: 5UU to achieve the purpose of not showing images. Compared with the prior art, the liquid crystal display device of the present invention 3 = ^ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ,, the member does not inform the difference is less than the difference before the adjustment, into: two:;: data relay value 340 adjacent device all pixel unit electrode 343 voltage due to liquid day ^ 1 ^ and relatively small 'finally make public i mm- The coupling effect of the valley is effectively controlled by the sound of the negative electrode voltage of the pixel electrode 342. That is, the potential of the % pole is relatively accurate, and the liquid crystal display device 3 of the present invention is, for example, the polarity rearrangement circuit, and the polarity control bit of the above embodiment, the analysis signal increases the display signal to the first position. The knives of the liquid crystal display device 300 are coupled to the timing controller 304. The memory 306 of 00 can also be referred to FIG. 4, which is a flow chart of the liquid crystal display device 3 of the present invention. The driving method includes the following steps: ··· 00 driving method step 5 01, receiving the 筮 _ display signal; , no signal, and storing the Nth frame, the timing controller 304 by the first display device 300, the Xth column pixel The liquid crystal display _ 疋 340 nth frame display _ _ signal is transmitted to the analysis unit 334, while (4): Λ into the memory 306. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , : Differ N-1 鸠 之 每一 每一 — 〜 〜 〜 〜 〜 〜 查找 查找 查找 查找 344 344 344 344 344 344 344 344 344 344 344 344 ~ 334 from the lookup table 344 杳, , and after. Hai knife
值。节八&…賴7^訊號對應之資料電壓 值3亥分析早兀334將第N蝻夕次余丨+广 电S ，次Μ命^上、， 弟Ν幀之貝枓電壓值與第Ν-1幢 貝料笔麗值求差值。接下來， 。_ 、value. Section 8 & Lai 7^ signal corresponding to the data voltage value 3 Hai analysis early 兀 334 will be the Nth 蝻 次 丨 丨 广 广 广 广 广 广 广 广 广 广 广 广 广 广 , , , , , , , , , , , , , , , , , , , , - 1 bar material pen value is the difference. Next, . _ ,
牧r木巧刀析早兀334將第N 巾貞之貧料電壓進行相對丘带 極性反轉，並將極性反轉後之：：：厂3之電壓值進行 ^差值及刀析早兀334將兩次差值進行比較， =、域對應資料電壓值之顯示訊號，並得出顯示訊 =子，之貧料電壓相對於公共電壓Vc〇m之極性正負。該 刀析早7L 334將選取之顯示訊號及極性正負的訊息傳輪 16 200901143 至該極性重排電路354。 步驟5 0 3，根據分析結果，對顯示訊號進行極性重排，· 該極性重排電路354接收該分析單元334傳輸之顯 示訊號及極性正負的訊息，將該顯示訊號進㈣整，使 調整後第N幀顯示訊號對應資料電壓與第幀顯示訊 號對應資料電虔之差值小於調整前之差值。顯示訊號為 數位说5虎，該極性重排電路354根據極性反轉與否的訊 ，為該顯示訊號增加—極性控制位，該極性控制位為該 顯不訊號之末位。該極性重排電路354將經極性重排之 顯示訊號作為資料訊號，傳輸至該源極控制器3〇3。 、.步驟504,根據極性重排後之顯示訊號輸出資料電 該源極控制态303接收該極性重排電路輸出之 極1·生重排後之顯不訊號，並根據該顯示訊號將其對應 貝料電壓輪出至該資料線32〇。連接至該資料線且严 於導通狀態之薄膜電晶體341接收該資料電壓，並施2 至該像素單元34〇之像素電極342。該像素電極342 :: 料電壓與該公共電壓存在一電壓差值，該電壓差值= 階電壓。該像素單元34〇之液晶分子在該灰階電壓作= 下發生偏轉，控制透過液晶層之光能量，實現液 裝置300之顯示功能。 ‘，肩不 相較先前技術，本發明液晶顯示裝置3〇〇之驅動方 ^二將顯示訊號之極性進行調整，使該液晶顯示裝置3卯 每一像素單元340第N幀之資料電壓與第ν。幀資料電 17 200901143 .壓差值比較小，進而使液晶顯示裝置3〇〇所有像素單元 340相鄰二悄之資料電壓差值之總和比較小，最终使公丘 電極電壓因液晶電容347之輕合作用受像素電極⑷第: 資料電壓拉動比較小，即公共電極343 <電位比較 準確’串音得到有效控制。 本發明液晶顯示裝置300之驅動方法並不僅限於上 ^施例’其中’該極性重排電路祝#可將顯示訊號 心加一首位作為極性控制位。 ，本發”合發”财件，爰依法提出專 Ύ惟、’，以上所述者僅為本發明之較佳實施方式，本 :人^圍並不以上述實施方式為限，舉凡熟悉本案技藝 ，在板依本案發明精神所作之等效修飾或變化，皆 應包含於以下申請專利範圍内。 【圖式簡單說明】 $ 1係-種先前技術液晶顯示裝置之結構示意圖。 ;2係圖〇斤示液晶顯示裝置中像素單元之驅動波形圖。 ㈤係本發明液晶顯示裝置一較佳實施方式之結構示意 團。 θ 係本發明液晶顯示裝置 【主要元件符號說明】 液晶顯示裝置 資料線 像素單元 像素電極 100、300閘極線 120、320公共線 140、340薄膜電晶體 142、342公共電極 110、310 130、330 141 、 341 143、343 18 200901143 液晶電容 閘極驅動器 時序控制器 第二端口 查找表 公共電壓電路 147、 347 存儲電容 148 ' 348 102、 302 源極驅動器 103 ' 303 104、 304 第一端口 314 324 分析單元 334 344 極性重排電路 354 105、 3—05 存儲器 306 19牧r木木巧刀析早兀334 will reverse the polarity of the N-band 贫 相对 相对 相对 相对 相对 , , 相对 相对 相对 相对 相对 相对 相对 相对 相对 相对 相对 相对 : : : : : : : : : : : : : : : : : : : The difference is compared twice, and the field corresponding to the display voltage of the data voltage value is obtained, and the negative voltage of the display signal is positive and negative with respect to the polarity of the common voltage Vc〇m. The knife 7A 334 will select the display signal with the positive and negative polarity of the signal transmission 16 200901143 to the polarity rearrangement circuit 354. Step 5 0 3, according to the analysis result, the display signal is subjected to polarity rearrangement, and the polarity rearrangement circuit 354 receives the display signal transmitted by the analysis unit 334 and the positive and negative polarity information, and the display signal is (four) adjusted to make the adjustment In the Nth frame, the difference between the signal corresponding data voltage and the data corresponding to the first frame display signal is less than the difference before the adjustment. The display signal is digitally said to be 5 tigers. The polarity rearrangement circuit 354 adds a polarity control bit to the display signal according to the polarity inversion or not, and the polarity control bit is the last bit of the display signal. The polarity rearranging circuit 354 transmits the polarity rearranged display signal as a data signal to the source controller 3〇3. Step 504, according to the display signal output data after the polarity rearrangement, the source control state 303 receives the display signal of the pole rearrangement of the polarity rearrangement circuit, and correspondingly according to the display signal The feed material voltage is turned out to the data line 32〇. The thin film transistor 341 connected to the data line and in a conducting state receives the data voltage and applies 2 to the pixel electrode 342 of the pixel unit 34. The pixel electrode 342: the material voltage and the common voltage have a voltage difference, the voltage difference = step voltage. The liquid crystal molecules of the pixel unit 34 are deflected by the gray scale voltage =, and the light energy transmitted through the liquid crystal layer is controlled to realize the display function of the liquid device 300. ', the shoulder does not compare with the prior art, the driving side of the liquid crystal display device 3 of the present invention adjusts the polarity of the display signal so that the liquid crystal display device 3 资料 the data voltage of the Nth frame of each pixel unit 340 ν. The frame data is 17 200901143. The pressure difference is relatively small, so that the sum of the data voltage differences of the adjacent pixels of all the pixel units 340 of the liquid crystal display device 3 is relatively small, and finally the voltage of the dolomite electrode is light due to the liquid crystal capacitance 347. The cooperation is affected by the pixel electrode (4): The data voltage is relatively small, that is, the common electrode 343 < the potential is relatively accurate 'crosstalk is effectively controlled. The driving method of the liquid crystal display device 300 of the present invention is not limited to the above embodiment, wherein the polarity rearrangement circuit # can add a display bit as a polarity control bit. The "Fengfa" property of the "Fafa" is issued in accordance with the law, and the above is only the preferred embodiment of the present invention. This person is not limited to the above embodiment, and is familiar with the case. The equivalent modifications or variations of the art in the spirit of the invention in the present invention are intended to be included in the scope of the following claims. [Simple diagram of the diagram] $1 is a schematic diagram of the structure of a prior art liquid crystal display device. 2 is a diagram showing the driving waveform of the pixel unit in the liquid crystal display device. (5) A structural schematic of a preferred embodiment of the liquid crystal display device of the present invention. θ is a liquid crystal display device of the present invention. [Main element symbol description] Liquid crystal display device data line pixel unit pixel electrode 100, 300 gate line 120, 320 common line 140, 340 thin film transistor 142, 342 common electrode 110, 310 130, 330 141, 341 143, 343 18 200901143 Liquid crystal capacitor gate driver timing controller second port lookup table common voltage circuit 147, 347 storage capacitor 148 '348 102, 302 source driver 103 ' 303 104, 304 first port 314 324 analysis Unit 334 344 Polarity Rearrangement Circuit 354 105, 3-05 Memory 306 19