200849589 九、發明說明： 【發明所屬之技術領域】 本發明係與互補式金氧半電晶體（CMOS )有關’更 詳而言之是指一種可提升NM0S元件區電子遷移率 (mobi 1 ity)之互補式金氧半電晶體製法。 【先前技術】 按，為改善習知金氧半場效應電晶體 (Metal-Oxide-Semiconductor Field-Effect Transistor，M0SFET)之性能，近年來有不少應用異 質結構（Heterostructure)之技術被揭露，相關專利亦 甚多，關於互補式金氧半場效應（Complementary Meta 1-Oxide-Semiconductor，CMOS )電晶體之專利即 有中華民國發明第91 121285號「在選擇性主動區域上 製作應變通道層的方法」、第92127405號「具應變通 道之互補式金氧半導體及其製作方法」、第94133084 號「互補式金氧半電晶體及其製造方法」、第941 16457 號「應變互補式金氧半場效電晶體及其製造方法」及 第941 15798號「具有選擇形成及回填半導體基底區域 以增加元件特性之互補式金氧半導體」等專利案所示。 異質結構之技術主要係利用異質材料之應變 (strained)造成能隙（Band Gap)差異，而改善電子 與電洞之遷移率（mobility)，俾可藉由高電子或電洞 200849589 遷移率來改善電晶體之電流速度，進而提升電晶體之 性能，例如應變矽/矽鍺之異質結構，主要係利用發展 相當成熟之磊晶技術（如MBE，CVD)在矽鍺合金上生 成一層單晶石夕薄膜層，因石夕鍺之晶格長度與石夕不同， 所以將矽磊晶成長在矽鍺層上形成矽應變層所產生的 應變，可以使其在平面（in-plane ) X方向的晶格增 長以與石夕鍺層相同，在成長縱向（〇11卜〇f—plane) y 方向則縮小，此種結構的應變型式稱為雙軸（biaxial) 的擴張應變（tensile strain)，可同時改善電子/ 電洞之載子遷移率，及提高元件之驅動電流與操作速 度，而甚適合互補式金氧半場效應電晶體。 不過，習知金氧半場效應電晶體以磊晶成長法生 成應變層時多係於半導體基底上全面性地為之，惟， 並非所有類型之金氧半場效應電晶體皆可藉由具雙軸 擴張或雙轴壓縮應變之材料來改善元件性能，例如， 習知之拉伸應變矽/矽鍺通道層雖可增加NM0S之電子 遷移率，但卻亦會同時降低PM〇S之電洞遷移率。其 次，全面性拉伸應變矽薄膜層/矽鍺晶圓之價格亦甚為 昂貴。是以，製作包含有NM0S與PM0S之互補式金氧 半場效應電晶體時，以全面式磊晶成長方式形成應變 層並非最佳之方式。 【發明内容】 200849589 本發明之主要目的即在提供一種可提升麵5元 件區電子遷移率之互補式金氧半電晶體製法，盆僅將 異質結構之技術運用於_s元件區，即可獲致同時提 升_s元件區電子遷移率（m〇bi!土ty)及保持p刪元 件區原有性能（電子遷移率不會降低）之效果。 本發明之另-目的在於提供一種可提升麵s元 件區電子遷移率之互補式金氧半電晶體製法，其製作 成本較為低廉者。 緣是，為達成前述之目的，本發明係提供一種可 提升_s元件區電子遷移率之互補式金氧半電晶體 製法，至少包含有以下步驟·· a)提供一半導體基底， 並於該半V體基底表面沉積再圖案化形成一罩幕層； b) 移除部分罩幕層及與其對叙狀厚度半導體基； c) 於半導體基底被移除之區域形成—梦鍺層；d)移除 剩餘之罩幕層；e)於财鍺層與半導體基底表面形成 =㈣層；以及W淺溝渠關技術於財鍺層與 半V體基底之間形成—溝渠隔離區，而於該溝渠隔離 區二侧分別定義一 PM0S元件區與一 NM〇s元件區使 得該麵S石夕鍺層之表面石夕薄膜層具有拉伸應變。 此外，本發明更係提供一種可提升腿0S元件區電 子遷移率之互補式金氧半電晶體，包含有一半導體基 底其上部具有一移除區；一矽鍺層，填補於該半導 體基底之移除區内；―梦薄膜層，形成於該半導體基 200849589 底與石夕鍺層表面；及一溝渠隔離區，形成於該半導體 基底與石夕鍺屬之間，用以於其二侧定義一 NM0S元件區 與一 PM0S元件區。 【實施方式】 以下，茲舉本發明一較佳實施例，並配合圖式做 進一步之詳細說明如後： 請參閱各圖所示，本發明一較佳實施例之可提升 NM0S元件區電子遷移率之互補式金氧半電晶體製法， 其第一步驟：係先提供一半導體基底12，該半導體基 底12係矽基底，並於該半導體基底12表面沉積再圖 案化形成一罩幕層14,該罩幕層14係二氧化矽材質。 本發明之第二步驟：係運用習知電漿蝕刻（piasma Etch)技術去除部分保護層14及其下方之適當厚度半 導體基底12，使該半導體基底12上部產生一移^區 本發明之第三步驟：係於該半導體基底12之移除 區15内以磊晶成長法（Epi_gr〇w)形成一矽鍺層μ。 習知磊晶成長法（或稱選擇性磊晶成長法）係指材料 =積（化學氣相沉積法）於特定形態之表面，蟲晶係 指在某-晶格上成長另—完整排列之晶格材料， =對其…日所生長之基底而言，具相同之晶格結構與 向。由於該半導體基底12乃具有規則晶格排列之石夕 200849589 基而該導體基底12未被移除之部分表面具有表面 形態為非晶形之非晶質| (罩幕層14)，目此實施蠢 晶成長法時’僅會於結晶形之半導體基底12上成長2 晶（即石夕鍺層16 )。 本發明之第四步驟：係利用濕式姓刻移除剩餘之 罩幕層14 〇 本發明之第五步驟：係於該矽鍺層14與半導體基 底12表面形成一薄膜層18。該薄膜層18 (矽材質f 係以蟲晶成長法形成。 本發明之最後步驟係以習知電性絕緣之淺溝渠隔 離技術（Shallow Treneh ISQlatiQn，STI)於該石夕錯層 16與半導體基底12之間形成—溝渠隔離區μ，而於 該溝渠隔離區19二侧分別定義為一·〇s元件區。與 一 PM0S元件區24，並將該薄膜層18區分為一 NM〇s 薄膜部26與一 pm〇s薄膜部28，如圖六所示。基此， 可再運用習知閘極堆疊、離子植人及熱製程等相關步 驟製成互補式金氧半電晶體。 此外，本發明於該矽鍺層14與半導體基底12表 面形成薄膜層18前，可先將該矽鍺層14與半導體基 底12表面施以化學機械拋光硏磨（CMP)，俾使該矽 鍺層14與半導體基底12表面平坦化、使薄膜層a易 於磊晶成長。 藉此，本發明該薄膜層18(矽材質）之晶格長度與 200849589 石夕錯層16不同，故，該薄膜層18之NM〇s薄膜部26 會產生拉伸應變（tensile strain)而成為應變層， 而該PM0S薄膜部28與半導體基底12之材質皆為石夕， 故不會形成應變層。如此一來，由於本發明該元 件區22具有異質結構而pm〇s元件區24並無，俾可獲 致同時提升歷0S元件區22電子遷移率（mobility)及 保持PM0S元件區24原有性能（電子遷移率不會降低） 之效果。 其次，習知全面性應變矽層/矽鍺晶圓之價格甚為 昂貴（_$1，刚）’本發明僅將異質結構技術運用於該 0S元件區22,整體材料多仍為矽材質（bulk_Si)， 製作成本甚為低廉者（USD$35)。 雖然本發明已以較佳實施例揭露如上，然其並非 用以限定本發明，任何熟悉此項技藝者，在不脫離本 發明之精神和範圍内，當可作更動與潤飾，因此本發 明之保護範时視後社中料職圍所界定者為 10 200849589 【圖式簡單說明】 圖一至圖六係本發明一較佳實施例製造流程之剖 面示意圖。 【主要元件符號說明】 半導體基底12 罩幕層14 移除區15 石夕鍺層16 薄膜層18 溝渠隔離區19 NM0S元件區22 PM0S元件區24 NM0S薄膜部26 PM0S薄膜部28 11200849589 IX. INSTRUCTIONS: [Technical Field] The present invention relates to a complementary MOS transistor (CMOS). More specifically, it can improve the electron mobility (mobi ity) of an NM0S device region. Complementary MOS semi-transistor method. [Prior Art] In order to improve the performance of the conventional Metal-Oxide-Semiconductor Field-Effect Transistor (M0SFET), many techniques for applying Heterostructure have been disclosed in recent years. There are also many patents on the Complementary Meta 1-Oxide-Semiconductor (CMOS) transistor, which is the method of making the strain channel layer on the selective active region by the Republic of China Invention No. 91 121285. No. 92127405 "Complementary MOS semiconductor with strain channel and its fabrication method", No. 94133084 "Complementary MOS semi-electrode crystal and its manufacturing method", No. 941 16457 "Strain-complementary MOS field device" And its manufacturing method and the patent case No. 941 15798 "Complementary MOS semiconductor with selective formation and backfilling of semiconductor substrate regions to increase component characteristics". Heterogeneous structure technology mainly uses the strain of the heterogeneous material to cause the difference of Band Gap, and improves the mobility of electrons and holes, which can be improved by the high electron or hole 200849589 mobility. The current velocity of the transistor, which in turn enhances the performance of the transistor, such as the heterostructure of the strain 矽/矽锗, is mainly based on the development of a fairly mature epitaxial technology (such as MBE, CVD) to form a single crystal stone on the bismuth alloy. In the thin film layer, since the lattice length of the stone 锗 不同 is different from that of the stone eve, the strain generated by the 矽 strained layer formed on the 矽锗 layer can be made in the plane of the in-plane X direction. The growth of the lattice is the same as that of the Shi Xiyu layer, and the y direction is narrowed in the longitudinal direction of growth (〇11〇〇f-plane). The strain pattern of this structure is called the biaxial strain strain. It improves the carrier mobility of electrons/holes, and improves the driving current and operating speed of components, and is suitable for complementary MOS field-effect transistors. However, the conventional gold-oxygen half-field transistor generates a strained layer by epitaxial growth method, which is mostly based on a semiconductor substrate. However, not all types of gold-oxygen half-field transistors can be biaxially Expanded or biaxially compressive strained materials to improve component performance. For example, the conventional tensile strain 矽/矽锗 channel layer can increase the electron mobility of NM0S, but it also reduces the hole mobility of PM〇S. Second, the price of a comprehensive tensile strain 矽 film layer/矽锗 wafer is also very expensive. Therefore, when a complementary gold oxide half field effect transistor including NM0S and PM0S is fabricated, it is not optimal to form a strain layer in a full-scale epitaxial growth mode. SUMMARY OF THE INVENTION The main object of the present invention is to provide a complementary metal oxide semi-transistor method for improving the electron mobility of the surface region of the surface 5, and the basin can only obtain the technique of the heterostructure to be applied to the _s element region. At the same time, the electron mobility (m〇bi! soil ty) of the _s component region is improved and the original performance of the p-deleted component region (the electron mobility does not decrease) is improved. Another object of the present invention is to provide a method for producing a complementary MOS transistor which can increase the electron mobility of a surface s element region, which is relatively inexpensive to manufacture. Therefore, in order to achieve the foregoing object, the present invention provides a complementary metal oxide semi-transistor method for improving electron mobility of an _s element region, comprising at least the following steps: a) providing a semiconductor substrate, and The surface of the semi-V body substrate is deposited and patterned to form a mask layer; b) removing a portion of the mask layer and the semiconductor layer with respect to the thickness; c) forming a region where the semiconductor substrate is removed - a nightmare layer; d) Removing the remaining mask layer; e) forming a = (four) layer on the surface of the financial layer and the surface of the semiconductor substrate; and forming a shallow trench trench technology between the financial layer and the half V body substrate - the trench isolation region, and the trench A PMOS component region and an NM〇s device region are respectively defined on two sides of the isolation region, so that the surface of the surface S-stone layer has a tensile strain. In addition, the present invention further provides a complementary MOS semiconductor transistor capable of improving the electron mobility of the leg OS region, comprising a semiconductor substrate having a removal region on an upper portion thereof; and a germanium layer filling the semiconductor substrate In addition to the zone, a "dream film layer" is formed on the surface of the semiconductor substrate 200849589 and the surface of the stone layer; and a trench isolation region is formed between the semiconductor substrate and the genus Astragalus to define one side thereof NM0S component area and a PMOS component area. [Embodiment] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the drawings. As shown in the accompanying drawings, a preferred embodiment of the present invention can improve the electron mobility of the NM0S component region. The first step of the method is as follows: a semiconductor substrate 12 is provided on a substrate, and is deposited on the surface of the semiconductor substrate 12 to form a mask layer 14 . The mask layer 14 is made of ruthenium dioxide. The second step of the present invention is to remove a portion of the protective layer 14 and the appropriate thickness of the semiconductor substrate 12 underneath using a conventional plasma etching technique to cause a shift region in the upper portion of the semiconductor substrate 12 to be the third aspect of the present invention. Step: Form a germanium layer μ in an epitaxial growth method (Epi_gr〇w) in the removal region 15 of the semiconductor substrate 12. The conventional epitaxial growth method (or selective epitaxial growth method) refers to the material = product (chemical vapor deposition method) on the surface of a specific form, and the insect crystal system refers to a lattice that grows on a certain lattice - another complete arrangement. Material, = the same lattice structure and orientation for the substrate grown on the day. Since the semiconductor substrate 12 is a regular lattice arrangement of the Shi Xi 200849589 base and the surface of the conductor substrate 12 that has not been removed has an amorphous surface having a surface morphology of amorphous | (mask layer 14), the implementation is stupid In the crystal growth method, only two crystals (i.e., the stone layer 16) are grown on the crystalline semiconductor substrate 12. The fourth step of the present invention is to remove the remaining mask layer 14 by wet etching. The fifth step of the present invention is to form a film layer 18 on the surface of the germanium layer 14 and the semiconductor substrate 12. The film layer 18 is formed by a crystal growth method. The final step of the present invention is to use a conventional shallow insulating trench isolation technique (Shallow Treneh ISQlatiQn, STI) on the X-ray layer 16 and the semiconductor substrate. 12 is formed between the trench isolation region μ, and the two sides of the trench isolation region 19 are respectively defined as a 〇s element region, and a PMOS element region 24, and the thin film layer 18 is divided into a NM 〇 s thin film portion. 26 and a pm〇s film portion 28, as shown in Fig. 6. Accordingly, a complementary MOS transistor can be fabricated by using conventional gate stacking, ion implantation, and thermal processing steps. Before the formation of the thin film layer 18 on the surface of the germanium layer 14 and the semiconductor substrate 12, the surface of the germanium layer 14 and the surface of the semiconductor substrate 12 may be first subjected to chemical mechanical polishing (CMP), and the germanium layer 14 is The surface of the semiconductor substrate 12 is flattened, and the thin film layer a is easily epitaxially grown. Thus, the lattice length of the thin film layer 18 (the germanium material) of the present invention is different from that of the 200849589, and the NM of the thin film layer 18 〇s film portion 26 will produce tensile strain The strain layer is formed, and the material of the PMOS film portion 28 and the semiconductor substrate 12 are all stone-like, so that no strain layer is formed. Thus, since the device region 22 of the present invention has a heterostructure, the pm 〇 component region 24 No, the effect of simultaneously increasing the electron mobility of the 0S element region 22 and maintaining the original performance of the PM0S element region 24 (the electron mobility does not decrease) can be obtained. Second, the conventional comprehensive strain layer/矽锗The price of the wafer is very expensive (_$1, just) 'The invention only applies the heterostructure technology to the 0S element region 22, and the overall material is still bulky (bulk_Si), and the production cost is very low (USD$35). The present invention has been described in its preferred embodiments, and is not intended to limit the invention, and the present invention may be modified and retouched without departing from the spirit and scope of the invention. The protection period is defined as the poster of the post office. 10 200849589 [Simplified Schematic] FIG. 1 to FIG. 6 are schematic cross-sectional views showing a manufacturing process of a preferred embodiment of the present invention. Semiconductor substrate 12 Mask layer 14 Removal region 15 Stone layer 16 Thin film layer 18 Ditch isolation region 19 NM0S device region 22 PM0S device region 24 NM0S thin film portion 26 PM0S thin film portion 28 11