200849382 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種南張力薄膜的製作方法，尤指一種於一應變 ^(strained-silicon metal^oxide-semiconductor transistor)上形成高張力薄膜的方法。 【先前技術】 隨著半導體製程、線寬縮小至65奈米(nm)以下，以及元件微型 化之發展，如何改善元件效能，提昇金氧半導體(M〇s)電晶體元件 的載子遷移輪驅動電流，已成為半導·業巾之—大課題。而 為達到提昇MQS電晶體速度，目前業界係已發展出「應變石夕 (strained-S1liC0n)技術」，並將其視為提高電晶體速度的主要途徑。 應k石夕技術之主要係使閘極下方，亦即通道區(ehanndreg㈣ 的石夕曰曰格產生應變’降低電子移動時所受刺阻力，使電荷在通 過此應變之閘極通道時移動力增加。 應變石夕技術係大致分為兩類，第一種係利用一高應力(high stress)薄膜覆蓋於]\4〇8電晶體上來達成，例如多晶石夕應力層(㈣ 或接觸洞蝕刻停止層(c〇mactetchst〇player，以下簡稱 CESL)等；另-酬是直接湘應㈣晶圓作絲底或結合選擇性 磊晶成長(selective epitaxial growth，SEG)製程所進行元件的製作。 其中，利用應力薄膜提昇電晶體驅動電流之方法，又可依據NM〇s 電晶體與PMOS電晶體特性f求的不同而分為：糊—高張應力 200849382 薄膜(high tensile stressflIm)來提供一伸張應力，進而拉大丽⑽ 電晶體下就半導縣朗之，以缺善nmqs元件之 驅動電流(driVec_t)的方法，以及利用一高壓應力薄膜_ compressive stress fl丨m)來提供一壓縮應力，進而擠壓pM〇s電晶 體下方之半導縣朗之晶格制，關改善PM0S元件之效能 的方法。 明參閱第1圖，第1圖係為習知於Nm〇s電晶體表面製作一 高張應力薄膜之示意圖。如第丨圖所示，半導體基底1〇上設置有 NMOS電晶體12，其包含有一閘極結構，而閘極結構包含有一 閘極氧化層14，與一位於閘極氧化層14上之閘極16。閘極16頂 部係形成有一覆蓋層(caplayer)18 ;而閘極結構之側壁則包含有一 氧化物-氮化物-氧化物偏位側壁子(〇N〇〇ffsetspacer)2〇。此外， NMOS電晶體12另包含有一源極/汲極區域22 ;而環繞於NM〇s 私晶體12之半導體基底10内係設置有一淺溝隔離24。請繼續參 閱第1圖，NM0S電晶體12之表面利用電漿加強化學氣相沉積方 法(plasma-enhanced chemical vapor deposition，PECVD)形成一由氮 化石夕或氧化矽所組成之高張應力薄膜26。 一般而言，目前65奈米製程對於高張應力薄膜26之伸張應力 狀悲至少要求l 5GPa，而進入到45奈米製程時，對其伸張應力 狀態之要求則到達〇GPa以上。然而以目前電漿加強化學氣相沉 積方法所得到之高張應力薄膜26僅可得到l.5GPa。因此目前業 200849382、 界係於形成磁應力細26後進行—快速熱處理製程(Rapid .Thermamocessing，以下簡稱咖），利用一高於麵。⑽高溫調 整高張應力_ 26之伸張應力絲。值得注意献，由於〇亂 製程係於電晶體之閘極與源極/汲極表时完成金射化層製作之 半導體基底上製作’需考慮金屬魏層的低熱預算需求。為避免 金屬石夕化層毀損’需降低快速熱處理製程之溫度，使得高張應力 薄膜^調整後之伸張應力狀態低於目標值。也就是說，雖然RTp 為-驗並可有效達到目標伸張應力㈣之方法，域加於紐 應力薄膜26後可獲得較高應力值，但該方法係受限於〇亂製程。 除此之外1知技術亦提供另—料線硬化製程，用以調整高 張力薄膜26伸騎力，财法係湘—料線光賴射高張力薄 膜26 ’利用光子打斷高張力薄膜％中石夕_氣⑸-職與氮化石夕-氯 (SiN-H)鍵。也就是說，靠著移除高張應力薄膜％中之氣，紫外線 硬化製程係使高張應力薄膜26產生一不可逆之伸張應力，拉大 NMOS電晶體12下方之半導體基底1〇内之晶格排列，而氫移除 而才曰X長’且其效率及效果係受限於高張應力薄膜％之 度。 f 【發明内容】 匕因此’本發明於此提供—種製作高張力_之方法與機台 指種於應、變石夕金氧半導體電晶體上形成高張力薄膜的方法與 8 200849382 機台。 根據本發明之申請專利範圍’係提供一種製作多晶石夕應力層 (poly stressor)之方法，該方法包含有提供一表面形成有至少一電晶 體之基底、於該基底表面形成一多晶矽應力層、以及進行一紫外 線暨快速熱處理製程(ultra violate rapid thermal process，UVRTP) 以硬化該多晶石夕應力層，並調整該多晶石夕應力層之一伸張應力。 根據本發明之申請專利範圍，另提供一種製作接觸洞蝕刻停止 層(contact etch stop layer，CESL)之方法，包含有提供一表面包含 有至少-閘極、至少-側壁子以及―源極/汲極區域之基底、於該 基底上形成-金屬層、進行-快速熱退火製程，使該等金屬層分 別於〉及極/源極區域上以及該閘極上形成―過渡金㈣化物層 (inte—ded Salldde layer)、於該基底表面形成一接觸洞_曰停止 層、以及進行-紫外線暨快速熱處理製程以硬化該接觸洞韻刻停 止層，並調整該接觸洞蝕刻停止層之一伸張應力。 7 根據本發日狀帽專_圍，更提供—师作高張力薄膜 法’該方法包含有提供-表面包含有至少—閘極結構、至少 壁子以及-_/聽區域之聽、於雜絲_成 力薄膜、進行-第-紫外線暨快速熱處理製程(uvr :張 第一高張力薄臈’同時調整該第—高張力薄 更化： 移除該第-高張力薄膜，係於該基底上形成—待 9 200849382 :速:退火製程’使該等金屬層分別汲極/源極區域上以及該閘極 過渡金屬⑽物層。接下來於該基底表面形成一第二高 進行—第二紫外線暨快速熱處理製程以硬化該第二高 張力並調整該第二高張力_之—伸張應力。 献Λ1’根據本㈣之申料纖圍，更提供—節卜線暨快速 台’其包含有一反應腔室(chamber)，用以容納至少一半 2晶圓、—設於該反應腔室n碌載該半導體晶圓之承載 坐older)、以及一包含有一紫外線光源與一熱源之紫外線光 加熱裝置。 ^ 一由於本A明所提供之製作高張力薄膜之方法係於形成高張力 溥膜、多日⑽應力層、或娜_停止層之後紫外線暨 :速熱處理製賴整及硬倾膜層，同時結合光子的能量與熱能 來调整向張力薄膜之伸張應力狀態，故可在相對較短的製程時間 内或較低的溫度下形成具高伸張應力之_，因此更適用於應變 石夕製程與對溫度較敏感之接觸洞侧停止層製程。此外，製作接 觸_刻停止麟’料線暨快速熱處理餘係更可直接取代習 知，屬發化物製財之第二次快速熱處理製程，故本發明係更具 有簡化製程之功效。 【實施方式】 明參閱第2圖至第4圖’第2圖至第4圖係為本發明所提供之 200849382 .製作紐力_之方法，例如製作—多砂_之—第_較佳實 她例示心圖如第2圖所不，首先提供一基底3〇，例如—石夕晶 或-石夕覆絕緣基底，基底3G上包含至少—電晶體，如一繼〇s 電晶體之閘極結構32。而閘極結構32包含有-閘極介電層34， 以及-位於閘極介電層34上之間極％。問極％頂部係形成有— 覆蓋層㈣㈣38 ;而閘極結構32之側壁則形成有-氧化物-氮 化物-氧化物偏位側壁子(〇N〇〇ffsetspacer)4〇。閘極介電層％可 ，為減化或沈積輕程卿狀氧财或氮魏合物所構 成；而覆蓋層38則可由一用以保護閘極36之氮化石夕層_成。 此外’環繞於閘極結構32之半導體基底3G内係設置有—淺溝隔 離44，用以電性隔離電晶體與其他元件。 明 > 閱第3圖。隨後進行一離子佈植(ion implantation)製程，以 於閘極結構32周圍之基底30中形成-源極/沒極區域42。接下來 進行h夬速熱退火(rapi(J thermal anneaiing，以下簡稱為RTA)製 程，利用900°c至105CTC的高溫活化源極/汲極區域42中的摻雜 質，同時於RTA製程中修補於離子佈植製程中受損之基底晶格結 構。另外，亦可視產品需求及功能性考量，而於源極/汲極區域42 ，、閑極結構32之間分別形成一輕摻雜没極(Hghtiy (j〇pe(j办此， ldd)或源極/〉及極延伸(s〇urce/drain extensi〇n)，以上為習知該項技 藝者與具通常知識者所熟知，故於此不多加贅述。 請參閱第4圖。進行一沈積製程，如一電漿加強化學氣相沉積 11 200849382 製程(PECVD)，形成一由氮化矽、氧化矽、或氮氧化矽所組成之 高張應力薄膜，如一多晶矽應力層46,且多晶矽應力層46之初鍍 膜之伸張應力狀態約為1 ·5 GPa以下。接下來進行一紫外線暨快速 熱處理製程(Ultra Violet Rapid Thermal Process，以下簡稱為 UVRTP)，用以於硬化多晶矽應力層46的同時，調整多晶石夕應力 層46之應力狀態。此外，由於在進行UVRTP製程時，多晶石夕應 力層46係於一較短時間内接受大量熱能，此熱衝擊(thermal sh〇ck) 使知多晶石夕應力層46更具有一累積應力(accumuiatecj stress)，而使 得多晶矽應力層46之伸張應力值得以達到〇·5〜3.0 GPa。具有此 伸張應力之多晶石夕應力層46係可進而拉大閘極結構32下方之基 底30 ’即通道區之晶格排列，達到提升通道區之電子遷移率與 NMOS電晶體之驅動電流之目的。 根據本兔明之第一較佳貫施例，該紫外線暨快速熱處理製程 之溫度係介於150〜80CTC，其實施時間則為6〇分鐘之内，而紫外 線波長係介於100〜400奈米(nm)，製程之壓力係介於3〜5〇〇毫 托耳(mTorr)。另外’此紫外線暨快速熱處理製程中更包含通入一 氮氣或惰性氣體之步驟。 本發明所提供之高張力薄膜之製作方法係_—紫外線暨快 賴處理製程於硬化高張應力薄膜的同時調整其應力。換句話 况’本發明所提供之方法係同時結合光子的能量與熱能來調整高 張力薄膜之伸張應力狀態，故可在相對較短的製程時間内形成具 12 200849382 高伸張應力之薄膜。此外 擊之影響，高張應力薄膜 由於’、外_快賴翻製程中熱衝 1戶斤^于到之應力值你200849382 IX. Description of the Invention: [Technical Field] The present invention relates to a method for producing a south tension film, in particular to a high tension film formed on a strained-silicon metal oxide-semiconductor transistor. method. [Prior Art] With the semiconductor process, the line width is reduced to less than 65 nanometers (nm), and the miniaturization of components, how to improve the device performance, and improve the carrier migration wheel of the metal oxide semiconductor (M〇s) transistor component The driving current has become a big issue for semi-conductor and industrial towel. In order to improve the speed of MQS transistors, the industry has developed the "strained-S1liC0n" technology and regard it as the main way to increase the speed of the transistor. The main system of the K Shixi technique is to make the spur resistance under the gate below the gate, which is the channel of the ehanndreg (four), to reduce the spur resistance when the electron moves, so that the charge moves when passing through the strained gate channel. The strained stone technology system is roughly divided into two categories. The first type is achieved by coating a high stress film on the \4〇8 transistor, such as a polycrystalline stone stress layer ((4) or contact hole). An etch stop layer (c〇mactetchst〇player, hereinafter referred to as CESL), etc.; another pay is a direct Xiang (4) wafer as a silk bottom or combined with a selective epitaxial growth (SEG) process for the fabrication of components. Among them, the method of using the stress film to increase the driving current of the transistor can be further divided into: paste-high tensile stress 200849382 film (high tensile stress flIm) to provide a tensile stress according to the difference between the characteristics of the NM〇s transistor and the PMOS transistor. And then Ladali (10) under the transistor in the semi-conductor county, with the lack of good nmqs component driving current (driVec_t) method, and using a high-pressure stress film _ compressive stress fl丨m) Compressive stress, and then squeeze the crystal lattice system of the semi-conductor under the pM〇s transistor, to improve the performance of the PM0S component. See Figure 1, Figure 1 is a conventional Nm〇s transistor A schematic diagram of a high tensile stress film is formed on the surface. As shown in the first drawing, the semiconductor substrate 1 is provided with an NMOS transistor 12 including a gate structure, and the gate structure includes a gate oxide layer 14 a gate 16 on the gate oxide layer 14. A caplayer 18 is formed on the top of the gate 16; and a sidewall of the gate structure includes an oxide-nitride-oxide biased sidewall (〇N〇) 〇 ffsetspacer) 2. In addition, the NMOS transistor 12 further includes a source/drain region 22; and the semiconductor substrate 10 surrounding the NM〇s private crystal 12 is provided with a shallow trench isolation 24. Please continue to refer to FIG. The surface of the NM0S transistor 12 is formed by plasma-enhanced chemical vapor deposition (PECVD) to form a high tensile stress film 26 composed of nitride or yttrium oxide. Generally speaking, at present 65 Nano process for high The tensile stress of the stress film 26 requires at least 15 GPa, and when it enters the 45 nm process, the requirement for the tensile stress state reaches above 〇GPa. However, the high tensile state obtained by the current plasma enhanced chemical vapor deposition method. The stress film 26 can only obtain 1.5 GPa. Therefore, the current industry 200849382, the boundary is formed after the formation of the magnetic stress fine 26 - Rapid heat treatment process (Rapid. Thermamocessing, hereinafter referred to as coffee), using a higher surface. (10) High temperature adjustment of tensile stress of high tensile stress _ 26 . It is worth noting that due to the messy process, the fabrication of the semiconductor substrate on the gold emitter layer is performed on the gate and source/drain of the transistor. The low thermal budget requirement of the metal layer is considered. In order to avoid the damage of the metallization layer, it is necessary to reduce the temperature of the rapid heat treatment process, so that the tensile stress state of the high tensile stress film is adjusted to be lower than the target value. That is to say, although the RTp is a test and can effectively reach the target tensile stress (4), a higher stress value can be obtained after the field is applied to the stress film 26, but the method is limited to the disorder process. In addition to this, a known technology also provides an additional material line hardening process for adjusting the high tensile film 26 to ride the power. The financial system is a high-strength film for the line-light line. Zhong Shi Xi _ qi (5) - position and nitrite Xi - chlorine (SiN-H) bond. That is, by removing the gas in the high tensile stress film %, the ultraviolet curing process causes the high tensile stress film 26 to generate an irreversible tensile stress, and the lattice arrangement in the semiconductor substrate 1 below the NMOS transistor 12 is enlarged. The hydrogen removal is only 长X long' and its efficiency and effect are limited by the high tensile stress film %. f [Summary of the Invention] Thus, the present invention provides a method for producing a high-tension film and a method for forming a high-tension film on a glacial oxynitride transistor and a 2008-04382 machine. A method according to the present invention is directed to a method of fabricating a polycrystalline polystressor, the method comprising providing a substrate having a surface formed with at least one transistor, and forming a polycrystalline stress layer on the surface of the substrate. And performing an ultraviolet violation rapid thermal process (UVRTP) to harden the polycrystalline rock stress layer and adjusting one of the tensile stresses of the polycrystalline stone stress layer. In accordance with the scope of the present invention, a method of fabricating a contact etch stop layer (CESL) includes providing a surface including at least a gate, at least a sidewall, and a source/germanium. a base of the polar region, a metal layer is formed on the substrate, and a rapid thermal annealing process is performed to form a transition metal (four) layer on the > and the pole/source regions and the gate respectively (inte- A ded Salldde layer is formed on the surface of the substrate to form a contact hole, a stop layer, and an ultraviolet-ray and rapid heat treatment process to harden the contact hole and stop the layer, and adjust the tensile stress of the contact stop layer. 7 According to the hairdressing cap of this hairdressing, it is also provided as a high-strength film method. The method includes providing - the surface contains at least the gate structure, at least the wall and the -_/ listening area. _ _ force film, carry - the first ultraviolet and rapid heat treatment process (uvr: the first high tension thin 臈 ' while adjusting the first - high tension thinning: remove the first - high tension film, attached to the substrate Formed on - to be 9 200849382: speed: annealing process 'to make the metal layer on the drain/source region and the gate transition metal (10) layer. Then form a second high on the surface of the substrate - second The ultraviolet ray and rapid heat treatment process is used to harden the second high tension and adjust the second high tension _ the tensile stress. The Λ 1 1 according to the (4) of the application of the fiber circumference, more provides - the 节 线 line and the fast table 'which contains one a chamber for accommodating at least half of the two wafers, a carrier disposed in the reaction chamber, and an ultraviolet light heating device including an ultraviolet light source and a heat source . ^ The method for producing a high-tension film provided by the present invention is based on the formation of a high-tension enamel film, a multi-day (10) stress layer, or a Na-stop layer, followed by ultraviolet ray: rapid heat treatment, and a hard pour layer. Combining the energy and thermal energy of photons to adjust the tensile stress state of the tensile film, it can form a high tensile stress in a relatively short process time or at a lower temperature, so it is more suitable for the strain process and the pair The temperature is sensitive to the contact hole side stop layer process. In addition, the production of the contact _ stop lining material line and the rapid heat treatment system can directly replace the conventional one, which is the second rapid heat treatment process of the chemical production, so the invention has the effect of simplifying the process. [Embodiment] Referring to Figures 2 to 4, Figures 2 to 4 are the 200849382 provided by the present invention. The method of making the force _, for example, making - sand - _ better She exemplifies the heart diagram as shown in Fig. 2. First, a substrate 3 is provided, for example, a stellite or a stellite insulating substrate, and the substrate 3G includes at least a transistor, such as a gate structure of a s s transistor. 32. The gate structure 32 includes a gate dielectric layer 34, and - is located on the gate dielectric layer 34. The top portion of the gate structure is formed with a cladding layer (4) (four) 38; and the sidewall of the gate structure 32 is formed with an oxide-nitride-oxide bias sidewall spacer (〇N〇〇ffsetspacer). The gate dielectric layer may be formed by subtracting or depositing a light-weight sulphuric acid or nitrogen-based composite; and the cap layer 38 may be formed by a nitride layer for protecting the gate 36. In addition, a shallow trench isolation 44 is provided in the semiconductor substrate 3G surrounding the gate structure 32 for electrically isolating the transistor from other components. Ming > Read Figure 3. An ion implantation process is then performed to form a source/nomogram region 42 in the substrate 30 around the gate structure 32. Next, a h thermal anneaiing (RTA) process is performed, and the dopant in the source/drain region 42 is activated by a high temperature of 900 ° C to 105 CTC while being repaired in the RTA process. The base lattice structure damaged during the ion implantation process. In addition, depending on product requirements and functional considerations, a lightly doped immersion is formed between the source/drain region 42 and the idler structure 32. (Hghtiy (j〇pe (j do this, ldd) or source /> and extreme extension (s〇urce/drain extensi〇n), the above is known to the skilled person and the general knowledge, so This is not to be repeated. Please refer to Figure 4. Perform a deposition process such as plasma enhanced chemical vapor deposition 11 200849382 (PECVD) to form a high tensile stress consisting of tantalum nitride, hafnium oxide or hafnium oxynitride. The film, such as a polysilicon stress layer 46, and the initial stress state of the polycrystalline germanium stress layer 46 is about 1.25 GPa or less. Next, an Ultra Violet Rapid Thermal Process (hereinafter abbreviated as UVRTP) is performed. Used to harden polycrystalline At the same time as the stress layer 46, the stress state of the polycrystalline stone stress layer 46 is adjusted. In addition, since the polycrystalline stone stress layer 46 receives a large amount of heat energy in a short time during the UVRTP process, the thermal shock (thermal Sh〇ck) makes the polycrystalline stone stress layer 46 more cumulative stress (accumuiatecj stress), so that the tensile stress of the polycrystalline germanium stress layer 46 is worth 〇·5~3.0 GPa. The polycrystalline stone with this tensile stress The stress layer 46 can further enlarge the substrate 30' below the gate structure 32, that is, the lattice arrangement of the channel region, thereby achieving the purpose of improving the electron mobility of the channel region and the driving current of the NMOS transistor. In the example of the application, the temperature of the ultraviolet and rapid heat treatment process is between 150 and 80 CTC, and the implementation time is within 6 minutes, while the ultraviolet wavelength is between 100 and 400 nanometers (nm). It is between 3 and 5 Torr (mTorr). In addition, the UV and rapid heat treatment process further includes a step of introducing a nitrogen gas or an inert gas. The method for producing a high-tension film provided by the present invention is _ The ultraviolet ray fast processing process adjusts the stress while hardening the high tensile stress film. In other words, the method provided by the present invention combines the energy and thermal energy of the photon to adjust the tensile stress state of the high tensile film, so it can be relatively In the shorter process time, a film with a high tensile stress of 12 200849382 is formed. In addition, the effect of the impact, the high tensile stress film is due to the ', the outer _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
用熱氧化或沈積謂程所形成之氧切或氮魏合物所構成之閘 極介電層54、-位於閘極介電層54上之閘極兄、以及—氧化物_ 氡化物-氧化物偏位側壁子(〇肋識技啊咖)6〇。此外，環繞於電 曰曰體52之半導體基底5〇内係設置有—淺溝隔離㈠，用以電性隔 離電晶體與其他元件。 睛繼績參閱第5圖，隨後進行一離子佈植製程，以於閘極結構 52周圍之基底50中形成一源極/汲極區域62。另外，亦可視產品 需求及功能性考量，而於源極/汲極區域62與閘極結構52之間分 別形成一輕摻雜汲極(LDD)或源極/汲極延伸，以上為習知該項技 蟄者與具通常知識者所熟知，故於此不多加贅述。 凊參閱第5圖與第6圖。隨後於基底50上形成一金屬層66， 金屬層66可包含有鈷(Co)、鈦(Ti)、鎳(Ni)、鎢(W)、鉑(Pt)、鈀(Pd)、 13 200849382 鉬(Mo)或上述金屬之合金。並進行一 rtA製程，在400〜600 °C的 溫度環境下’使金屬層66分別與;:及極/源極區域62以及閘極56 接觸部分自行對準反應形成一過渡金屬石夕化物層(intergradecj SaliCidelayer)68。之後再利用一選擇性濕式蝕刻去除未反應成過 渡金屬石夕化物的金屬層66。 凊參閱第7圖。接下來於基底5〇表面藉由一沈積製程，如一 電漿加強化學氣相沉積(PECVD)製程，形成一 CESL7〇，其可包 含氤化矽、氧化矽或氮氧化矽等材料’且其初鍍膜之伸張應力狀 態係為1.5 GPa以下。隨後並對CESL7〇進行一紫外線暨快速熱 處理製程’於硬化CESL 70的同時調整CESL 7〇之伸張應力狀態， 以拉大閘極結構52下方之基底5〇，即通道區之晶格排列，達到提 升通道區之電子遷移率與_〇8電晶體之驅動電流之目的。 /請繼續參閱第7圖。值得注意的是，一般金屬石夕化物層之製作 係需要mTA製程’第-次RTA製程侧以形成晶粒較小而電 阻值較高的金屬魏物，即前述之過渡金屬魏物層；而第二次 RTA衣蝴彻—較高的溫度使過渡金射化物層產生—相轉變 並降低其電阻值’而形成—金屬魏物層。根據本發明所提供之 方法，係可利用針對CESL7〇所實施之紫外線暨快速熱處理聲程 於調整及硬化CESL 7G，同時使做金屬魏層68進行相轉變成 一f屬=化物層72。因此本發明所提供之高張力薄膜之製作方法 可省略則述之第—次腿製程；或者說本發賴提供之紫外線暨 14 200849382 :逮熱處理f程可直接取代習知金輕化層製程中之第二次說 衣私。此外，過渡金屬石夕化物層68於紫外線暨快逮熱處理製程中 所產生之相變化，除可使其轉而形成金屬魏物層η之外，亦使 得金屬石夕化物層π因相變化產生一張應力，故金屬石夕化物層η 與CESL 70整體所產生之伸張應力值係可達到0.5〜3.0 GPa。 ±該紫外線暨快速熱處理製程之溫度係條150〜800。〇其實施 間則為60分鐘之内，而料線波長齡於卿〜奈米㈣， 衣私之[力係介於3〜5〇〇毫托耳㈣㈣。另外，紫外線暨快速熱 處理^程巾更包含—通人·或惰性氣體的步驟；且_以形成 石夕化金屬層68的快速熱處理製程與該紫外線暨快賴處理製程係 了 X同位(in situ)方式或非同位(η〇η|η_3^)方式進行。 、由於本發明職供之CESL7G之製作方法係利用 一紫外線暨 快速熱處理製餅硬化c亂7G的同_整其應力 。也就是說， Μ月所提供之方法係同時結合光子的能量與熱能來調整cesl 之伸張應力狀您’故可在補較短的製程時間與較低的熱預算 内I成具W伸張應力之薄膜。此外，由於CESL7()製程中之紫外 線旦，速熱處理製程係更可用以取代取代習知金屬雜物層製程 中之第一次RTA製程，因此本發明所提供之方係可於簡化CESL 以及金屬破化物製程的同時，提升整體張應力狀態至〇5〜 挪，更滿足現今製程龍應力值之要求。 15 200849382 在第-較佳實施例中，多晶石夕應力層係可作 線暨快速熱處理製程產生-不可她 曰申張1力拉大電晶體下方之基底，即通道區之晶格排列。因 ^料線暨快速熱處理製程之後係可移除該第—高張 亚進仃前述第二較佳實施例所述之金屬魏物製程。如前 在形賴過渡金屬魏物層之後，係可於基底上形成一第二 兩張力_，_糾—次的料、》快賴處理触於硬化以 及為整δ亥第一局張力薄膜之伸張應力時，使過渡金屬石夕化物層進 行相轉變而成為金射化物層，同_由此相轉變提供一伸^應 力:且該第二高張力薄膜係可作為—C亂。換句話說，接連實ς 本第-較加實_與第二較佳實施例所教導之方法，可使基底通 道區之晶格㈣制二至三次的應力調整’故更可滿足現今製程 對伸張應力值之要求，_纽善NMQS元件之鶴電流。、 另外’請參閱第8目，第8圖係為本發明另提供之一種紫外線 暨快速熱處理機台之較佳實施例之示意圖。如第8圖所示，本實 施例所提供之紫外線暨快速熱處理機台觸係: 一 2,用以容納至少一晶圓104、一具有力 座(holder) 106，設於反應腔室1〇2内，用以承載晶圓ι〇4、以及— 紫外線光源與加熱裝置108。本發明所提供之紫外線暨快速熱處理 機台100另包含-快門元件110 ’用以控制紫外線之通過；以及— 溫度_裝置112，用以侧晶圓1Q4之溫度。另外，如第8圖所 示’紫外線暨快速熱處理機台1〇〇更可包含一氣體注入口 114盘 16 200849382 t體排出口 116,其可根據晶圓104所需之製程條件通入及排出 氮氣、惰性氣體、或其他反應氣體。 請參閱第9圖與第1〇圖，第9圖與第1〇圖係為紫外線光源與 加熱U 1G8之較佳實施例之示意圖。本發明所提供之紫外線暨 快速_理機台之紫外線光源與加熱褒置應係包含有至少一熱 源120與至少一紫外線光源122。熱源、12〇可為函素燈管或雷射 等，而紫外線光源122射提供一波長係介於1〇〇〜4〇〇奈米㈣) 之紫外線。此外，熱源110與料線光源112之設置方式，係可 ★第9圖所不呈父錯制方式設置；或如第⑺圖所示以蜂寫狀排 列方式設置。當然’熱源120與紫外線光源122亦可呈一矩陣交 錯排列等方式設置，而不限定於第9圖與第1〇圖所示。 根據本發明所提供之紫外線暨快速熱處理機台，係可單獨進行 —紫外線處理或快速熱處理，亦可於提供紫外線處理的同時，利 用幽素燈管或雷射進行-快速熱處理。也就是說，根據本發明所 提供之紫外線暨快速熱處理機台，係可_結合光子的能量愈執 能於一所需製程中。 〜“、 由於本發贿提供之高張力_之製作方闕於形成高張力 ^膜:多晶销力層、或CESL之後個—紫外線暨快速熱處理 衣私5周整及硬化該膜層’故可同時結合光子的能量她 高張力薄膜之伸張應力狀態，並提供較短的處理時^甚至= 17 200849382 的熱預算。也就是說，本發明所提供之製作高張力_之方法係 可在相對較短的時間内或較低的溫度下形成具高伸張應力之薄 膜’因此更適用於應變石夕製程與對溫度較敏感之CESL製程。此 外’本發明所提供之CESL之製作方法係更可直接取代金屬石夕化 ，製程中的第二次RTA製程，故更可簡化整體製程。财發明所 提供之^線暨快速熱處理機台係可滿足上述紐力細製作方 ^斤品更甚者纟於5亥紫外線暨快速熱處理機台係同時提供 紫外線與熱能，因此更可用於半導體製程中需要紫外線處理、快 速熱處理或同時需要兩種處理之步驟。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均㈣化與修飾，皆觸本伽之涵蓋範圍。 【圖式簡單說明】 糾圖為胃知於NM0S電晶體表面製作一高張力薄膜之示意圖。 弟2圖至第4圖係為本發明所提供之製作高張力_之方法之一 第一較佳實施例示意圖。 第5圖至第7 _為本發明所提供之製作高張力_之方法 二較佳實施例示意圖 =8圖係為本㈣提供之—種料_快速熱處Gate dielectric layer 54 formed by thermal oxidation or deposition of oxygen-cut or nitrogen-wet composites, gate gates on gate dielectric layer 54, and oxide-telluride-oxidation The object is biased to the side wall (〇 识 识 啊 啊 ) 〇 〇) 6 〇. In addition, the semiconductor substrate 5 surrounding the electrode body 52 is provided with a shallow trench isolation (1) for electrically isolating the transistor from other components. Referring to Figure 5, an ion implantation process is then performed to form a source/drain region 62 in the substrate 50 around the gate structure 52. In addition, depending on product requirements and functional considerations, a lightly doped drain (LDD) or source/drain extension is formed between the source/drain region 62 and the gate structure 52, as described above. This technical person is well known to those with ordinary knowledge, so it is not mentioned here.第 See Figures 5 and 6. A metal layer 66 is then formed on the substrate 50. The metal layer 66 may comprise cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), platinum (Pt), palladium (Pd), 13 200849382 molybdenum. (Mo) or an alloy of the above metals. And performing an rtA process, in a temperature environment of 400 to 600 ° C, 'the metal layer 66 and the :: the pole / source region 62 and the gate 56 contact portion self-aligned reaction to form a transition metal lithiate layer (intergradecj SaliCidelayer) 68. A selective metal wet etching is then used to remove the metal layer 66 which has not been reacted into the transition metal.第 See Figure 7. Next, a CESL7 crucible is formed on the surface of the substrate 5 by a deposition process, such as a plasma enhanced chemical vapor deposition (PECVD) process, which may include materials such as antimony telluride, antimony oxide or antimony oxynitride. The tensile stress state of the coating is 1.5 GPa or less. Subsequently, an ultraviolet and rapid heat treatment process of CESL7〇 is performed to adjust the tensile stress state of CESL 7〇 while hardening CESL 70, so as to enlarge the base 5〇 under the gate structure 52, that is, the lattice arrangement of the channel region, Improve the electron mobility of the channel region and the driving current of the _8 transistor. / Please continue to see Figure 7. It is worth noting that the general metallization layer requires the mTA process 'the first-second RTA process side to form a metal grain with a small grain size and a high resistance value, that is, the aforementioned transition metal grain layer; The second RTA is a high temperature that causes the transition metallization layer to produce a phase transition and reduce its resistance value to form a metal wafer layer. According to the method provided by the present invention, the ultraviolet light and rapid heat treatment acoustic path performed for CESL7 can be used to adjust and harden CESL 7G while phase-forming the metal germane layer 68 into a f-based layer. Therefore, the method for fabricating the high-tension film provided by the present invention may omit the first leg process described above; or the ultraviolet light provided by the present invention may be directly replaced by the conventional gold light layer process. The second time said the private. In addition, the phase change produced by the transition metallization layer 68 in the ultraviolet light-assisted heat treatment process can not only cause it to turn into a metal-wholesale layer η, but also cause the metal-lithium layer π to be phase-induced. A stress, so the metal lithium layer η and CESL 70 overall tensile stress value can reach 0.5~3.0 GPa. ± The temperature of the UV and rapid heat treatment process is 150 to 800.实施The implementation is within 60 minutes, and the wavelength of the feed line is in the Qing ~ nano (four), the private system [force is between 3 ~ 5 〇〇 mTorr (four) (four). In addition, the ultraviolet ray and rapid heat treatment process further includes a step of passing a person or an inert gas; and _ a rapid heat treatment process for forming the shihua metal layer 68 and the ultraviolet ray ray treatment process are X-in situ (in situ ) or non-homogenous (η〇η|η_3^) mode. Since the CESL7G manufacturing method of the present invention utilizes an ultraviolet ray and a rapid heat treatment to form a cake, the stress of the 7G is the same. That is to say, the method provided by Haoyue combines the energy and thermal energy of photons to adjust the tensile stress of cesl. Therefore, it can be used to compensate for the short process time and the lower thermal budget. film. In addition, due to the UV-ray process in the CESL7() process, the rapid heat treatment process can be used instead of replacing the first RTA process in the conventional metal-grain layer process. Therefore, the present invention can simplify the CESL and the metal. At the same time of breaking the compound process, the overall tensile stress state is raised to 〇5~ 挪, which satisfies the requirements of the current process dragon stress value. 15 200849382 In the first preferred embodiment, the polycrystalline lithospheric stress layer can be produced by a line and rapid thermal processing process - the substrate underneath the transistor, that is, the lattice arrangement of the channel region. The metal material process described in the second preferred embodiment may be removed after the material line and the rapid heat treatment process. As before, after the transition metal layer is formed, a second tension _, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ When the tensile stress is applied, the transition metallization layer is phase-transformed into a gold-emitting layer, and the phase transition provides a tensile stress: and the second high-tension film can be used as a C-disorder. In other words, successively, the method of the first-comparative embodiment and the second preferred embodiment can make the lattice adjustment of the lattice (4) of the base channel region two to three times, so that it can satisfy the current process pair. The requirement of tensile stress value, _ Newshan NMQS component crane current. Further, please refer to item 8, which is a schematic view of a preferred embodiment of an ultraviolet and rapid thermal processing machine according to the present invention. As shown in FIG. 8, the ultraviolet and rapid thermal processing machine contact system provided in this embodiment is: 2, for accommodating at least one wafer 104, and a holder 106, which is disposed in the reaction chamber. 2, for carrying the wafer ι 4, and - the ultraviolet light source and the heating device 108. The ultraviolet and rapid thermal processing machine 100 of the present invention further includes a shutter element 110' for controlling the passage of ultraviolet rays; and - a temperature device 112 for the temperature of the side wafer 1Q4. In addition, as shown in FIG. 8 , the 'ultraviolet and rapid thermal processing machine 1 ' can further include a gas injection port 114 disk 16 200849382 t body discharge port 116, which can be introduced and discharged according to the process conditions required for the wafer 104. Nitrogen, inert gas, or other reactive gases. Please refer to Fig. 9 and Fig. 1, and Fig. 9 and Fig. 1 are schematic views of a preferred embodiment of an ultraviolet light source and a heated U 1G8. The ultraviolet light source and the heating device provided by the present invention should include at least one heat source 120 and at least one ultraviolet light source 122. The heat source, 12 〇 can be a light tube or a laser, and the ultraviolet light source 122 provides ultraviolet light having a wavelength of 1 〇〇 to 4 〇〇 nanometer (4). In addition, the arrangement of the heat source 110 and the line source 112 can be set in the manner shown in Fig. 9 that is not in the parental mode; or in the form of a bee-like arrangement as shown in the figure (7). Of course, the heat source 120 and the ultraviolet light source 122 may be arranged in a matrix arrangement or the like, and are not limited to those shown in Fig. 9 and Fig. 1 . The ultraviolet and rapid heat treatment machine provided according to the present invention can be separately subjected to ultraviolet treatment or rapid heat treatment, or can be subjected to ultraviolet treatment, and can be subjected to rapid heat treatment using a light bulb or a laser. That is to say, according to the ultraviolet ray and rapid thermal processing machine provided by the present invention, the energy of the photon can be combined to be more in a desired process. ~ "Because of the high tension provided by this bribe _ the production side is in the formation of high tension ^ film: polycrystalline pin layer, or CESL - UV and rapid heat treatment clothing 5 weeks and hardened the film layer ' Simultaneously combines the energy of the photon with the tensile stress state of the high tension film and provides a shorter thermal budget for the processing time or even = 17 200849382. That is, the method of making the high tension provided by the present invention can be Forming a film with high tensile stress in a short period of time or at a lower temperature' is therefore more suitable for the strain-steel process and the temperature-sensitive CESL process. In addition, the CESL manufacturing method provided by the present invention is more Directly replace the metal Shi Xihua, the second RTA process in the process, so it can simplify the overall process. The ^ line and rapid heat treatment machine system provided by the financial invention can meet the above-mentioned new force fines. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 The above description is only a preferred embodiment of the present invention, and all the (four)izations and modifications made according to the scope of the patent application of the present invention are within the scope of the present gamma. [Simplified Schematic] Correction for the stomach is known to NM0S A schematic diagram of a high tension film on the surface of a transistor. Figures 2 through 4 are schematic views of a first preferred embodiment of a method for producing high tension provided by the present invention. Fig. 5 to 7 The method for producing a high tension provided by the invention is as follows: Fig. 8 is a diagram of the present invention.
施例之示意圖。 '口〈罕乂 1土I =圖至第關係為-料線光源與加熱裝置之較佳實施例之示 200849382 【主要元件符號說明】 10、30、50 基底 12、32、52 電晶體 14、34、54 閘極氧化層 16、36、56 閘極 18 > 38 覆蓋層 20、40、60 側壁子 22、42、62 源極/没極 24、44、64 淺溝隔離 26 高張力薄膜 46 多晶矽應力層 66 金屬層 68 過渡金屬石夕化物層 70 接觸洞蝕刻停止層 72 金屬石夕化物層 100 紫外線暨快速熱處理機台 102 反應腔室 104 晶圓 106 承載座 108 紫外線光源與加熱裝置 110 快門元件 112 溫度偵測裝置 114 氣體注入口 116 氣體排出口 120 熱源 122 紫外線光源 19Schematic diagram of the example. '口〈罕乂1土 I = diagram to the first relationship - the preferred embodiment of the line source and heating device 200849382 [Main component symbol description] 10, 30, 50 substrate 12, 32, 52 transistor 14, 34, 54 gate oxide layer 16, 36, 56 gate 18 > 38 cover layer 20, 40, 60 side wall 22, 42, 62 source / no pole 24, 44, 64 shallow trench isolation 26 high tension film 46 Polycrystalline germanium stress layer 66 metal layer 68 transition metallization layer 70 contact hole etch stop layer 72 metal lithium layer 100 ultraviolet ray rapid thermal processing machine 102 reaction chamber 104 wafer 106 carrier 108 ultraviolet light source and heating device 110 shutter Element 112 Temperature detecting device 114 Gas injection port 116 Gas discharge port 120 Heat source 122 Ultraviolet light source 19