200849016 九、發明說明： 明所屬《^技領域;j 發明領域 本發明涉及基於快閃§己憶體的大容量存儲設備。具體 5地說’硬碟控制部連接若干個包括緩衝器、NAND型快閃 記憶體及NAND型快閃記憶體控制部的存儲部；nand型快 閃記憶體控制部控制各存儲部内的NAND型快閃記憶體· 這種結構使其擁有便於對NAND型快閃記憶體擴容及控制 的特點。 10 【先前技術】 發曰月背景 電腦、PMP、MP3播放器等家電產品一般都使用硬碟、 快閃記憶體等保存資料的裝置。 隨著資訊通信的發展，需要處理的資料越來越多，對 15於存儲設備的容量要求也越來越高，需要將若干個存儲設 備連接在起來，作爲大容量存儲裝置來使用。特別是攜帶 方便、耐久性優秀的快閃記憶體是主流。 第1圖是原有技術基於快閃記憶體的大容量存儲設備 的結構圖。 20 如第1圖所示，使用原有技術基於快閃記憶體的大容量 存儲設備採用的結構是：硬碟控制部（100)通過硬碟介面與 主機(300)連接，硬碟控制部⑽)與若干細娜型快閃記 憶體(2〇0)連接並控制這些NAND型快閃記憶體 硬碟控制部⑽)爲了與_NAND型快閃記憶體(細） 200849016 進行資料傳輸，需要與NAND型快閃記憶體(200)數量相同 的緩衝器（110)數，且緩衝器（110)通過NAND介面與NAN型 快閃記憶體(200)連接。 不過，這種結構的大容量存儲設備的缺點是··由於硬 5碟控制部（1⑻)控制連接在其本身的若干個NAND型快閃記 憶體(200)，所以對於NAND型快閃記憶體(200)的擴容有局 限性而導致存儲空間的有限。 MLC(Multi Level Cell)的NAND型快閃記憶體(200)的 特點是産生大量的錯誤比特（Err〇r bit)，且由於這些個 10 NAND型快閃記憶體（200)的錯誤檢查和糾正動作 (EDC/ECC)都要由硬碟控制部（1〇〇)來完成，從而增加了硬 碟控制部的負荷。 另外’由於MLC的NAND型快閃記憶體(200)的壽命較 短’需要提供一個分散使用的方法，而且還有資料傳輸速 15 度較慢的問題。 發明概要 此-人發明疋爲了解決上述問題而進行的，發明的目的 在；& t、们有利於NAND型快閃記憶體的擴容和控制 2〇的、基於快閃記憶體的大容量存儲設備。其結構是：在硬 檠控制α卩連接包括緩衝器、nand型快閃記憶體、型 部的若干個存儲部；NANE^快閃記憶體 控制。P控制各存儲部内部的财仙型快閃記憶體 ，這樣有 利於NAND，_記憶㈣擴容和控制。 200849016 圖式簡單說明 第1圖：原有技術基於快閃記憶體的大容量存儲設備結 構圖； 第2圖本人t明基於快閃記憶體的大容量存儲設備結 5 構圖； 第3圖本人毛明中緩衝器使用Dual_p〇rt 的示意 圖； ~ 第4圖·將緩衝器的第2埠區域及共有區域使用爲硬碟 控制部的主記憶體示意圖。 10 【實方式】 具體實施方式 爲了達到上述目的’此設備包括通過硬碟介面與主機 連接並&理貝料傳輸的硬碟控制部、通過記憶體介面與硬 碟控制部相連的若干個存儲部；而存儲部又包括通過記憶 體”面，、硬茱控制部連接並臨時保存資料的緩衝器、通過 。己隐體；I 緩衝⑨連接的ΝΑΝ_快閃記憶體型 快閃記憶體以塊爲單位進行擦除操作）， 通過NAND型介面 與NAND型决閃兄憶體連接管理資料傳輸並充當硬碟控制 部和NANE^快閃記憶體介面的NAND型快閃記憶體控制 20 部。 在這裏上述緩衝器使用Dual-Port DRAM或者Dual-Port SRAM 中的一個，上述 Dual-Port DRAM 或者 Dual-Port SRAM必須包括臨時保存與上述从葡型快閃記憶體之間 傳輸的資料的第1埠區域、臨時保存與上述硬碟控制部之間 200849016 個同時使用 傳輸資料的糾區域及置於上述第吻域和上 區域之間並與第1埠區域或者第2埠區域中的— 的共有區域。 5 連接。 再則，硬㈣與若干個射料應料㈣通信璋 過記憶體介面或者串列通信介面中的至少 輸0 再則，硬碟控制部與料個存儲部應根據環境條件通 一個進行資料傳 再則，硬碟控制部和若干個存儲部之間的讀取和記錄 1〇資料應通過串列通信介面傳出，其他資料應通過記憶體介 面進行傳輸。 再則，硬碟控制部及NAND型快閃記憶體控㈣都應 包括檢查錯誤的EDC(ErrorDetection Code)及糾錯的 ECC(Error Correction Code)。 15 再則，硬碟控制部應將緩衝器的第2埠區域及公共區域 使用爲主記憶體。 再則，NAND型快閃記憶體控制部應將第丨埠區域使用 爲高速緩衝記憶體。 下面，利用附圖詳細介紹本次發明設備的工作實例。 20 第2圖：本次發明基於快閃記憶體的大容量存儲設備示 意圖。 從第2圖可以看出，本次發明的基於快閃記憶體大容量 存儲設備是以主機(30)連接硬碟控制部（10)、硬碟控制部（1〇) 連接若干個存儲部(20)爲基本結構的。 200849016 硬碟控制部（ίο)是爲了控制與其本身相連的若干個存 儲部(20)的部分，它通過硬碟介面與主機(3〇)連接；通過記 憶體介面與存儲部(20)連接；並包括檢查和糾錯傳輸資料的 EDC(Error Detection Code)及ECC(Error Correction Code)。 5 存儲部(20)包括緩衝器（23)、NAND型快閃記憶體控制 部（21)及NAND型快閃記憶體(25)。 緩衝器（23)通過記憶體介面與硬碟控制部（1〇)連接、通 過記憶體介面與NAND型快閃記憶體控制部（21)連接、臨時 保存硬碟控制部（10)和NAND型快閃記憶體控制部(21)之間 10 的資料。 NAND型快閃記憶體控制部（21)是控制NAND型快閃 記憶體(25)的部分，它通過NAND介面與若干個NAND型快 閃記憶體(25)連接並包括檢測和糾錯傳輸資料的EDC(Error Detection Code)及ECC(Error Correction Code) 〇 15 naND型快閃記憶體以塊爲單位進行擦除操作，通過 NAND型快閃記憶體控制部（21)的控制進行資料記錄和讀 取0 以前是硬碟控制部（10)控制若干個NAND型快閃記憶 體(25)的形式，本次發明則是由NAND型快閃記憶體控制部 20 (21)控制各存儲部（20)内部的NAND型快閃記憶體(25)，使 NAND型快閃記憶體(25)的控制更加容易。 本次發明基於快閃記憶體大容量存儲設備的硬碟控制 部（10)及NAND型快閃記憶體控制部（21)都包括EDC及 ECC，這樣的結構使得資料錯誤的檢查和糾錯能夠重復進 200849016 行從而提高了資料的準確性。 在這裏，硬碟控制部（10)及若干個存儲部(2〇)，除了通 、己U體介面連接還通過串列通信埠連接。所以應根據環 i兄條件，記憶體介面或者串列通信埠中至少通過一個渠道 5有選擇地進行資料傳送。 另外’讀取和記錄等高速資料通過高速串列通信埠傳 輸、其他的資料通過記憶體介面傳輸的方式分散處理資 料，從而提高了處理速度。 14時爲了統一處理通過串列通信埠及記憶體介面傳輸 10的貝料，應使用大容量的緩衝器（23)。 土於决閃§己憶體大容量存儲設備的記錄及讀取動作如 下： '200849016 IX. INSTRUCTIONS: The field of technology belongs to the field of invention. The invention relates to a large-capacity storage device based on flash § recall. Specifically, the hard disk control unit is connected to a plurality of storage units including a buffer, a NAND flash memory, and a NAND flash memory control unit, and the nand type flash memory control unit controls the NAND type in each storage unit. Flash Memory · This structure makes it easy to expand and control NAND flash memory. 10 [Prior Art] The background of the computer, PMP, MP3 player and other home appliances generally use a device such as a hard disk or a flash memory to store data. With the development of information communication, more and more data needs to be processed, and the capacity requirements for storage devices are becoming higher and higher, and several storage devices need to be connected to be used as a large-capacity storage device. In particular, flash memory that is easy to carry and excellent in durability is the mainstream. Fig. 1 is a structural diagram of a prior art mass storage device based on a flash memory. 20 As shown in FIG. 1 , the structure of the mass storage device based on the flash memory using the prior art is: the hard disk control unit (100) is connected to the host (300) through the hard disk interface, and the hard disk control unit (10) Connecting with a number of fine-type flash memories (2〇0) and controlling these NAND-type flash memory hard disk control units (10) for data transmission with _NAND type flash memory (thin) 200849016, The NAND type flash memory (200) has the same number of buffers (110), and the buffer (110) is connected to the NAN type flash memory (200) through the NAND interface. However, the disadvantage of the large-capacity storage device of this configuration is that the NAND type flash memory is used for the NAND type flash memory because the hard 5-disc control unit (1(8)) controls a plurality of NAND-type flash memories (200) connected to itself. The expansion of (200) has limitations and results in limited storage space. MLC (Multi Level Cell) NAND type flash memory (200) is characterized by generating a large number of error bits (Err〇r bit) and error checking and correction due to these 10 NAND type flash memories (200). The action (EDC/ECC) is done by the hard disk control unit (1〇〇), which increases the load on the hard disk control unit. In addition, since the lifetime of the MNC's NAND-type flash memory (200) is short, it is necessary to provide a method of distributed use, and there is also a problem that the data transmission speed is 15 degrees slow. SUMMARY OF THE INVENTION This invention has been made in order to solve the above problems, and the object of the invention is to facilitate the expansion and control of NAND-type flash memory, and to store mass storage based on flash memory. device. The structure is: in the hard control, the α卩 connection includes a buffer, a nand type flash memory, a plurality of storage parts of the type; NANE^ flash memory control. P controls the wealthy flash memory inside each storage unit, which is beneficial to NAND, _memory (four) expansion and control. 200849016 Schematic description of the simple picture: Figure 1: The structure of the large-capacity storage device based on the flash memory; Figure 2 shows the composition of the large-capacity storage device based on the flash memory; Figure 3: Mao Mingzhong The buffer uses the schematic diagram of Dual_p〇rt; ~ Figure 4: The second buffer area and the shared area of the buffer are used as the main memory of the hard disk control unit. 10 [Real mode] In order to achieve the above object, the device includes a hard disk control unit that is connected to the host through a hard disk interface and transmits a plurality of memories connected to the hard disk control unit through the memory interface. The storage unit includes a buffer that passes through the memory side, the hard control unit and temporarily stores the data, and passes through the hidden body; I buffer 9 connected ΝΑΝ _ flash memory type flash memory block For the unit to perform the erase operation, the NAND type interface is connected with the NAND type flash memory to manage the data transmission and serves as the NAND type flash memory control unit of the hard disk control unit and the NANE^ flash memory interface. Here, the above buffer uses one of Dual-Port DRAM or Dual-Port SRAM, and the above-mentioned Dual-Port DRAM or Dual-Port SRAM must include the first data temporarily stored and transferred from the above-mentioned Portuguese flash memory. Zone, temporary storage and the above-mentioned hard disk control unit 200849016 simultaneous use of the transmission data correction area and placed between the above-mentioned first and upper areas and the first area The common area of the area in the second area. 5 Connection. In addition, hard (four) and several injection materials (four) communication through the memory interface or at least 0 in the serial communication interface, then hard disk control The department and the storage department shall conduct data transmission according to the environmental conditions. The reading and recording between the hard disk control unit and several storage units shall be transmitted through the serial communication interface. Other materials shall pass. The memory interface is transmitted. In addition, both the hard disk control unit and the NAND flash memory controller (4) should include an error detection EDC (Error Detectionion Code) and an error correction ECC (Error Correction Code). The control unit should use the second area of the buffer and the common area as the main memory. In addition, the NAND type flash memory control unit should use the third area as the cache memory. This paper introduces the working example of the device of the present invention. 20 Fig. 2: This is a schematic diagram of a large-capacity storage device based on flash memory. This can be seen from Fig. 2, the large-capacity based on flash memory of the present invention. The storage device is based on a host (30) connected to the hard disk control unit (10) and a hard disk control unit (1) connected to a plurality of storage units (20). The 200829416 hard disk control unit (ίο) is for controlling a portion of a plurality of storage units (20) connected to itself, connected to the host (3〇) through a hard disk interface; connected to the storage unit (20) through a memory interface; and including EDC (Error) for checking and correcting transmission data Detection Code) and ECC (Error Correction Code). The storage unit (20) includes a buffer (23), a NAND type flash memory control unit (21), and a NAND type flash memory (25). The buffer (23) is connected to the hard disk control unit (1) through the memory interface, and is connected to the NAND flash memory control unit (21) via the memory interface, and temporarily stores the hard disk control unit (10) and the NAND type. 10 data between the flash memory control unit (21). The NAND type flash memory control unit (21) is a part for controlling the NAND type flash memory (25), which is connected to a plurality of NAND type flash memories (25) through a NAND interface and includes detection and error correction transmission data. EDC (Error Detection Code) and ECC (Error Correction Code) 〇15 naND type flash memory is erased in units of blocks, and data recording and reading are performed by the control of the NAND type flash memory control unit (21). Before taking 0, the hard disk control unit (10) controls a plurality of NAND type flash memories (25). In the present invention, the NAND type flash memory control unit 20 (21) controls each storage unit (20). The internal NAND type flash memory (25) makes the control of the NAND type flash memory (25) easier. The hard disk control unit (10) and the NAND type flash memory control unit (21) based on the flash memory mass storage device of the present invention both include EDC and ECC, and such a structure enables data error checking and error correction. Repeated into the 200849016 line to improve the accuracy of the data. Here, the hard disk control unit (10) and a plurality of storage units (2) are connected by a serial communication port in addition to the U-body interface. Therefore, data transmission should be selectively performed by at least one channel 5 according to the condition of the ring, the memory interface or the serial communication. In addition, high-speed data such as reading and recording is transmitted through high-speed serial communication, and other data is distributed through the memory interface to improve processing speed. At 14 o'clock, a large-capacity buffer (23) should be used in order to uniformly process the bead material transmitted through the serial communication port and the memory interface. The recording and reading operations of the large-capacity storage device of the ** 决 己 己 体 体 体 体 体 体 ' ' '
MiM. 從主機（30)傳送出來的記錄資料及控制信號通過硬碟 ;1面傳送到硬碟控制部（10)的，硬碟控制部（10)通過EDC對 相應的資料進行錯誤檢查，如果發現錯誤則通過ECC進行 糾錯。 然後硬碟控制部（10)通過記憶體介面將記錄數傳送到 緩衝器（23)臨時保存，然後通過記憶體介面傳送到NAND型 20快閃記憶體控制部（21)。 NAND型快閃記憶體控制部（21)通過EDC對於接收到 的兄錄資料進行錯誤檢查，如果發現錯誤就通過ECC進行 糾錯。 NAND型快閃記憶體控制部（21)通過NAND介面將記 200849016 錄資料及記錄控制資料傳到NAND型快閃記憶體(25)。 NAND型快閃記憶體(25)根據記錄控制資料將收到的 資料進行記錄。 讀取 5 主機（30)發出的讀取控制信號通過硬碟控制部（10)傳 送到NAND型快閃記憶體控制部(21)，NAND型快閃記憶體 控制部(21)通過NAND介面從NAND型快閃記憶體(25)讀取 相應貧料。 NAND型快閃記憶體控制部（21)通過EDC對讀取資料 10 進行錯誤檢查，如果有錯誤就通過ECC進行糾錯，然後 NAND型快閃記憶體控制部（21)通過記憶體介面將資料傳 送到緩衝器（23)並臨時保存。 臨時保存在緩衝器（23)的讀取資料通過記憶體介面傳 送到硬碟控制部（1〇)。 15 硬碟控制部（1〇)通過EDC對於收到的讀取資料進行錯 誤檢查，如果發現錯誤則通過ECC進行糾錯，然後硬碟控 制部（10)通過硬碟介面將讀取資料傳送到主機(3〇)。 本次發明的工作事例中，硬碟控制部（10)和存儲部(20) 是通過記憶體介面進行資料傳送的，但是如前面所述資料 20也可以根據環境條件在記憶體介面或者串列通信埠中選擇 一個進行資料傳送。 另外，也可以使用讀取或者記錄資料通過串列通信埠 傳輸、其他資料通過記憶體介面傳輸的分散處理的方式。 第3圖：緩衝器（23)由Dual-Port DRAM(27)體現的示意 11 200849016 圖。 如第3圖所示，本次發明所涉及的基於快閃記憶體大容 量存儲設備的緩衝器（23)可以通過Dual-Port DRAM(27)及 Dual-Port SRAM(無圖）來體現，但本次發明使用了 Dual_p〇rt 5 DRAM(27)。 這裏的Dual-Port DRAM(27)包括第1埠區域，第2埠區 域及共同區域。 弟1埠區域時保存與NAND型快閃記憶體控制部(21) 之間傳送的資料，第2埠區域臨時保存與硬碟控制部（1〇)之 10間的傳輸資料，共同區域與第1埠區域或者第2埠區域中的 一個共同使用。 即，第1埠區域和共同區域通過記憶體介面保存與 NAND型快閃記憶體控制部(21)之間傳輸的資料，第2埠域 域和共同區域通過記憶體介面保存與硬碟控制部（10)之間 15 傳送的資料，使資料處理速度得以提高。 以前使用大約2Kbyte的低容量緩衝器（23)，本次發明因 增加了可以連接的NAND型快閃記憶體(25)的數量，所以爲 提南資料處理速度而使用了 16Mbyte〜64Mbyte的大容量 緩衝器（23)。 2〇 特別是使用Dual-Port DRAM的緩衝器（23)，使硬碟控 制部（10)及NAND型快閃記憶體控制部(21)使用各自的專用 埠進行資料傳送，提高了處理性能。 另外，NAND型快閃記憶體控制部(21)將第1埠區域使 用爲高速緩衝記憶體，因爲之前從NAND型快閃記憶體(25) 12 200849016 收到的資料臨時保存在第1埠區域，如果即將收到相同資料 時不必從NAND型快閃記憶體(25)接收而是從第1埠區域接 收’彳之而提南傳輸效率。 第4圖：將緩衝器的第2埠區域及共有區域的組合使用 5在硬碟控制部的主記憶體的示意圖。 如第4圖所示，本次發明使用了 16Mbyte〜64Mbyte的 大容量緩衝器（23)，圖中第2埠區域及共同區域的組合爲緩 衝器（23)可同時用作硬碟控制部（1〇)的主記憶體。 因爲使用若干個64Mbyte〜256Mbyte的缓衝器（23)，第 10 2埠區域及共同區域的組合容量非常之大。即，硬碟控制部 (10)將大容量的第2埠區域及共同區域的組合使用爲Main 吕己憶體’所以不需要額外的]Vlain記憶體。 工業應用性 如上所述，本次發明是硬碟控制部連接缓衝器、NAND 15型快閃記憶體及包括NAND型快閃記憶體控制部的若干個 存儲部；NAND型快閃記憶體控制部控制各存儲部内部的 NAND型快閃記憶體使NAND型快閃記憶體的擴容和控制 更加容易。 另外因爲硬碟控制部及NAND型快閃記憶體控制部都 20包括EDC&ECC，使傳輸資料的錯誤檢查和糾錯重復進行 提高了資料的可靠性。 硬碟控制部及存儲部之間讀取或者記錄的資料通過串 列通信埠傳送，其他資料通過記憶體介面傳送的分散處理 方法提高了資料處理的效率。 13 200849016 將Dual-Port DRAM使用爲緩衝器，使負責與NAND型 快閃記憶體控制部之間資料傳輸的第1埠區域和負責與硬 碟控制部之間資料傳輸的第2埠區域區分，從而提高了資料 處理速度。 5 NAND型快閃記憶體控制部將第1埠區域使用爲Cache 記憶體，從而達到了提高資料傳輸效率作用。 另外，由於硬碟控制部將緩衝器的第2埠區域及共同區 域的組合使用爲Main記憶體，所以不必另外使用Main記憶 體。 10 雖然對於本次發明進行了上述說明，但是在發明宗旨 和範圍内可以對發明進行修改和變形，故申請專利範圍也 包括發明宗旨範圍内的修改和變形部分。 【圖式簡單說明3 第1圖：原有技術基於快閃記憶體的大容量存儲設備結 15 構圖； 第2圖：本次發明基於快閃記憶體的大容量存儲設備結 構圖， 第3圖··本次發明中緩衝器使用Dual_Port DRAM的示意 圖， 20 第4圖：將緩衝器的第2埠區域及共有區域使用爲硬碟 控制部的主記憶體示意圖。 【主要元件符號說明】 10…硬碟控制部 21—NAND型快閃記憶體控制部 20…存儲部 23…緩衝器 14 200849016 25…NAND型快閃記憶體 27· · - Dual-Port DRAM 30…主機 100···硬碟控制部 110···緩衝器 200—NAND型快閃記憶體 300…主機 15MiM. The recorded data and control signals transmitted from the host (30) are transmitted to the hard disk control unit (10) on one side, and the hard disk control unit (10) performs error checking on the corresponding data through the EDC. Errors are found through ECC for error correction. The hard disk control unit (10) then transfers the number of records to the buffer (23) through the memory interface for temporary storage, and then transfers it to the NAND type 20 flash memory control unit (21) through the memory interface. The NAND type flash memory control unit (21) performs an error check on the received brother data by the EDC, and performs error correction by ECC if an error is found. The NAND type flash memory control unit (21) transmits the 200849016 recording data and recording control data to the NAND type flash memory (25) through the NAND interface. The NAND type flash memory (25) records the received data based on the recording control data. The read control signal from the read 5 host (30) is transmitted to the NAND type flash memory control unit (21) through the hard disk control unit (10), and the NAND type flash memory control unit (21) is passed through the NAND interface. The NAND type flash memory (25) reads the corresponding poor material. The NAND type flash memory control unit (21) performs error check on the read data 10 by EDC, and corrects the error by ECC if there is an error, and then the NAND type flash memory control unit (21) passes the data through the memory interface. Transfer to buffer (23) and save it temporarily. The read data temporarily stored in the buffer (23) is transferred to the hard disk control unit (1) through the memory interface. 15 The hard disk control unit (1〇) performs error checking on the received data through the EDC. If an error is found, the error correction is performed by the ECC, and then the hard disk control unit (10) transmits the read data to the hard disk interface through the hard disk interface. Host (3〇). In the working example of the present invention, the hard disk control unit (10) and the storage unit (20) perform data transfer through the memory interface, but the data 20 as described above may also be in the memory interface or serial according to environmental conditions. Select one of the communication ports for data transfer. In addition, it is also possible to use a method of reading or recording data through serial communication, transmission, and other data through a memory interface. Figure 3: Schematic representation of the buffer (23) represented by the Dual-Port DRAM (27) 11 200849016. As shown in FIG. 3, the buffer (23) based on the flash memory mass storage device of the present invention can be embodied by Dual-Port DRAM (27) and Dual-Port SRAM (not shown), but This invention uses Dual_p〇rt 5 DRAM (27). The Dual-Port DRAM (27) here includes a first area, a second area, and a common area. The data transmitted between the NAND flash memory control unit (21) and the data transmission area of the hard disk control unit (1) are temporarily stored in the first area, and the common area and the One of the 1埠 area or the 2nd area is used together. That is, the first area and the common area are stored between the NAND flash memory control unit (21) via the memory interface, and the second area and the common area are saved by the memory interface and the hard disk control unit. (10) The information transmitted between 15 enables the data processing speed to be improved. Previously, a low-capacity buffer (23) of about 2 Kbyte was used. This invention increased the number of NAND-type flash memories (25) that can be connected, so a large capacity of 16 Mbyte to 64 Mbyte was used for the data processing speed of the South. Buffer (23). 2〇 In particular, the buffer (23) of the Dual-Port DRAM is used, and the hard disk control unit (10) and the NAND-type flash memory control unit (21) use their respective dedicated ports for data transfer, thereby improving the processing performance. In addition, the NAND type flash memory control unit (21) uses the first area as a cache memory because the data previously received from the NAND type flash memory (25) 12 200849016 is temporarily stored in the first area. If the same data is about to be received, it is not necessary to receive from the NAND type flash memory (25) but receive the transmission efficiency from the first area. Fig. 4 is a schematic diagram showing the combination of the second buffer area and the shared area of the buffer 5 in the main memory of the hard disk control unit. As shown in Fig. 4, the present invention uses a large-capacity buffer (23) of 16 Mbyte to 64 Mbyte, and the combination of the second area and the common area in the figure is a buffer (23) which can be simultaneously used as a hard disk control unit ( 1〇) The main memory. Since a plurality of buffers (23) of 64 Mbytes to 256 Mbytes are used, the combined capacity of the 10th 埠 area and the common area is very large. That is, the hard disk control unit (10) uses a combination of the large-capacity second-inch area and the common area as the main LV memory, so that no additional Vlain memory is required. Industrial Applicability As described above, the present invention is a hard disk control unit connection buffer, a NAND 15 type flash memory, and a plurality of storage units including a NAND type flash memory control unit; NAND type flash memory control The NAND-type flash memory inside the respective memory sections controls the expansion and control of the NAND-type flash memory. In addition, since both the hard disk control unit and the NAND type flash memory control unit include EDC & ECC, error checking and error correction of the transmission data are repeated to improve the reliability of the data. The data read or recorded between the hard disk control unit and the storage unit is transmitted through serial communication, and the distributed processing of other data through the memory interface improves the efficiency of data processing. 13 200849016 The Dual-Port DRAM is used as a buffer to distinguish between the first area responsible for data transfer with the NAND-type flash memory control unit and the second area responsible for data transfer between the hard disk control unit and the hard disk control unit. Thereby improving the data processing speed. 5 The NAND-type flash memory control unit uses the first area as the Cache memory, thereby improving the efficiency of data transmission. Further, since the hard disk control unit uses the combination of the second area of the buffer and the common area as the Main memory, it is not necessary to additionally use the Main memory. Although the invention has been described above, the invention may be modified and modified within the spirit and scope of the invention, and the scope of the invention also includes modifications and variations within the scope of the invention. [Simple diagram of the diagram 3 Figure 1: The original technology based on the flash memory mass storage device junction 15 composition; Figure 2: This invention is based on the flash memory mass storage device structure diagram, Figure 3 In the present invention, a schematic diagram of the Dual_Port DRAM is used for the buffer, and FIG. 4 is a schematic diagram showing the second memory area and the shared area of the buffer used as the main memory of the hard disk control unit. [Description of main component symbols] 10: Hard disk control unit 21 - NAND flash memory control unit 20: Storage unit 23: Buffer 14 200849016 25...NAND type flash memory 27·· - Dual-Port DRAM 30... Host 100··· hard disk control unit 110··· buffer 200—NAND flash memory 300... host 15