200846958 九、發明說明： — 【發明所屬之技術領域】 本發明有關一種半導體製程，特別是有關一種確認佈局圖 形(layout pattern)之方法。 【先前技術】 半導體製程中經常使用到微影(ph〇t〇Uth〇graphy)及触刻 • (etchmg)技術。微影技術包括將-複雜的積體電路圖形轉移至 半導體晶圓表面’以供餘刻時所用。此等圖形需要極準確， 以製造精密的積體電路。在微影步驟中，將光罩㈣ide)圖形轉 移至晶圓表面時，經常會產生偏差，影響半導體裝置之性能。 此種偏差與被轉移的圖形特性、晶圓的外形、及種種的製程參 數有關。其中，對於因為光學近接效應所引起的圖形偏差，已 有斗多補仏的方法，以改善影像轉移後的品質。其中，已知之 • 方法為光學近接修正(—cal proximity贿ecti〇n ，OPC)，並已 有市口 OPC車人體’將光罩的佈局圖形經由理論影像校正，欲獲 得晶圓上正確的影像圖形。 、、“第1, ®顯示習知技術中利用㈣來確認光罩之佈局圖形的 机知、百先’進行步驟撤，輸人—佈局圖形。紐對此佈局 回進行乂驟103之OPC的布林(Boolean)預處理，獲得初步佈 局圖形。技裟 w - 心 ，進行步驟104之0pC，以修正較特殊的圖形。 ;、、、後，個別進行步驟讓之工藝規則檢驗(process _ check， 6 200846958 PRC)與步驟 1G8 之光學規馳驗(lithography rule check， LRC) ’然後進•步驟11G之錯誤财及檢查，所狀圖形若均 正確可用’則予以輸出（步驟112)，若有錯誤，則進行步驟H4 之整修，無誤後再予以輸出。 在進行步驟觸之LRC檢驗時，是以如第2圖所示之LRC 流程進行。首先，進行步驟116，將佈局圖形根據模型資料進 ❿行opc之修正，對於此佈局圖形進行步驟118，即，模擬一光 阻層於使用-最佳聚焦曝光後於最佳的影像平面上所形成的圖 形。「最佳聚焦」-般是位於光阻層—半厚度之處。而，「最佳 的影像平面」是指光阻層以最佳聚焦曝光並經顯影後，於此聚 焦點的相同高度的影像平面。然後，進行步驟12〇的哪檢驗， 若影像圖形正確而堪用，則進行步驟122的佈局圖形輸出，若 有誤，則再進行步驟116的〇pc修正。如此，以檢測出狹小處 ❿ （pmch)、橋接處(bridge)、關鍵尺寸均勻性(CD unif_ity)等問 題，並修正佈局圖形。 然而，除了習知檢測的狹小處、橋接處、關鍵尺寸均勻性 等問題’在失焦曝光的情形下，也經常易發生因為底切㈣如咖) 所導致的圖形崩塌(Pattern collapse)以及膜減損(film i〇ss)的情 形，此係光阻層圖形三維立體構形上的嚴重缺陷。請參閱第3 圖，其顯示一光阻層於使用一最佳聚焦曝光後所形成的模擬圖 _ 形剖視圖。由於，現有的LRC方法僅模擬最佳曝光平面的影 200846958 像’即圖中之b平面的影像，因此並無法發現失焦時在頂部平 面a或底部平面e可能會發生賴形缺陷。、 =局_的好壞，最終是展現於_後所得的圖 但是模擬臈層在飯 ㈢口茶 來，㈣狀圖形，進而確認光罩之佈局圖 形則未冒有人提出。200846958 IX. DESCRIPTION OF THE INVENTION: - TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor process, and more particularly to a method of verifying a layout pattern. [Prior Art] The lithography (ph〇t〇Uth〇graphy) and the etchmg (etchmg) technique are often used in semiconductor processes. The lithography technique involves transferring a complex integrated circuit pattern to the surface of the semiconductor wafer for use in the remainder. These patterns need to be extremely accurate to make precision integrated circuits. In the lithography step, when the mask (four) ide) pattern is transferred to the wafer surface, variations often occur, affecting the performance of the semiconductor device. This deviation is related to the transferred pattern characteristics, the shape of the wafer, and various process parameters. Among them, there is a way to compensate for the pattern deviation caused by the optical proximity effect to improve the quality after image transfer. Among them, the known method is optical proximity correction (-cal proximity brici ecti〇n, OPC), and the existing OPC vehicle body 'corrects the layout pattern of the mask through the theoretical image to obtain the correct image on the wafer. Graphics. , "1, ® shows the use of (4) in the conventional technology to confirm the layout of the mask, the machine is known, the steps are removed, and the input-layout pattern is added. This layout is back to the OPC of step 103. Boolean pre-processing to obtain the preliminary layout graphics. Technique w - heart, perform 0pC of step 104 to correct the special graphics. After, ,, and then, individually perform the process rule inspection (process _ check , 6 200846958 PRC) and the lithography rule check (LRC) of step 1G8 'following the error and inspection of step 11G, if the pattern is correct and available, then output (step 112), if any If the error is made, the repair of step H4 is performed, and then output after error-free. When the step-by-step LRC check is performed, the LRC process is performed as shown in Fig. 2. First, step 116 is performed, and the layout pattern is entered according to the model data. Performing the correction of opc, step 118 is performed on the layout pattern, that is, simulating a pattern formed on the optimal image plane after using the best-focus exposure. The "best focus" is generally located. Light Layer - of the half thickness. The "best image plane" refers to the image plane at the same height of the focus of the focus layer after the photoresist layer is exposed to the best focus and developed. Then, which test of step 12 is performed, if the image pattern is correct, the layout pattern output of step 122 is performed, and if there is an error, the 〇pc correction of step 116 is performed. In this way, problems such as pmch, bridge, and CD unif_ity are detected, and the layout pattern is corrected. However, in addition to the problems of narrow spots, bridges, and uniformity of key dimensions that are conventionally detected, 'in the case of out-of-focus exposure, pattern collapse and film caused by undercuts (4) are often prone to occur. In the case of film i〇ss, this is a serious defect in the three-dimensional configuration of the photoresist layer pattern. Referring to Figure 3, there is shown a cross-sectional view of a photoresist layer formed using a best focus exposure. Since the existing LRC method only simulates the image of the best exposure plane, 200846958, which is the image of the b-plane in the figure, it cannot be found that the declination may occur at the top plane a or the bottom plane e when the focus is out of focus. The quality of the = _ is the result of the _ after the _, but the simulated enamel layer in the rice (three) mouth tea, (four) shape, and then confirm the layout of the reticle has not been proposed.
因此，需要-種良好的圖形佈局確認之方法， 光罩之佈局圖形。 以用以確認 【發明内容】 本發明之一目的是提供一種確認佈局圖形之方法，可用以 確認光罩之佈局_衫_，有效發現佈局_可能的缺 陷’例如據以形成之圖形有崩塌及膜減損的缺陷，而可修 正光罩之佈局圖形。 > S依據本發明之確認佈局圖形之方法，包括下列步驟。首先， 提供-佈局圖形。模擬經由佈局_做為—料，將佈局圖形 轉移至膜層’以獲賴層之下部模_形。另她經由佈局圖 形做為-光罩’將佈局_轉移頌層，以獲得膜層之上部模 擬圖形。最後，確認此等模擬圖形是否堪用。 、 於本《明之另-方面，依據本發g狀確認佈局圖形之方 200846958 ,法\包括下列步驟。首先，提供一佈局圖形。然後，對佈局圖 形進仃光學近接修正。模擬經由佈局圖形做為一光罩，將佈局 圖形轉移至膜層，獲得膜層之下部模擬圖形，及另模擬經由佈 j圖形做為-光罩，將佈局圖形轉移至膜層，獲得膜層之上部 模擬圖形。接著，確認此等模擬圖形是否堪用。當此等模擬圖 士不為翻時’對佈局®形再錢行絲近接修正。 • 【實施方式】 μ參閱第4圖’其顯示-依據本發明之確認佈局圖形之方 法之流程:依據本發明之確認佈局圖形之方法包括下列步驟。 百先’進仃步驟202，提供-佈局圖形。然後，進行步驟綱， 模擬經由佈局圖形做為一光罩將佈局圖形轉移至膜層，獲得膜 層之下部模擬圖形。步驟施係獨立於步驟204進行，另模擬 經由佈局圖形做為-光罩將佈局圖形轉移至膜層，獲得膜層之 • t部模擬圖形。最後’進行步驟細，確認此等模擬圖形是曰否 於依據本發明之確認佈局_之方时所提供之佈局圖 > 例如光罩的佈局圖形。如此，依據本發明之確認佈局 再進行光罩 可應用於光罩之佈局_的確認。待圖形確認 用’思即，所形成的__不會產生缺陷時， 的實際製造。 9 200846958 ;本文中’膜層」可指欲經由具有佈局卿之光罩轉移該 佈局圖$於其上之物，例如，絲層或光阻層所覆蓋之層。又， =阻，所覆盖之層即為待韻刻層’可為例如半導體製程中的石夕 运、氧化物層、氮化物層、及類似者。 以臈層為光阻層來舉例說明，於步驟綱 =?供的佈局圖形做為一光罩，對-光阻_^ 、圖心至光阻層’以模擬所獲得的光阻層下部影像圖 做為-弁Γ驟206中，模擬使用步驟202所提供的佈局圖形 層，以模擬所的光阻層模擬曝光以轉移佈局圖形至光阻 2^04盘206分又付的光阻層上部影像圖形。應注意的是，步驟 的次序並無限制，並且是獨立的，即，分 像圖形先阻層模擬曝光，《獲得先略部與上部的影 使用正型光阻之情形時，於步驟挪中的曝光較佳 獲得的光阻層：：)進：擬：擬曝光及_所 取得-影像圖形以供判斷是否7^層之同一高度之平面 底部的影像_。 阻層的下部影像圖形更佳是取位於 200846958 本發明之「負失焦」是指曝光時聚焦點位於最佳聚焦位置 的下方。一般，使用負失焦時，光阻層下部所接受的光強度相 對較強，易造成光阻層下部或底部過度曝光。對於正光阻而言， 顯影後所形成的光阻圖案的線條寬度在下部的部分會相對較 窄，當過窄甚或滅失時，將使光阻圖案線條崩塌。第5圖係模 擬以一負失焦對光阻層曝光顯影後的模擬圖形剖視圖，係使用 Mentor Graphics公司的模擬軟體所模擬獲得的。如圖所示，最 ❿佳影像平面d上的圖形仍具有良好的線寬，但是位於底部影像 平面e上的圖形線條寬度相對的細。因此，於本發明中，當使 用負失焦對正型光阻層曝光，獲取位於底部影像平面之影像模 擬圖形時，可了解所形成的圖形是否堪用。第6圖顯示使用依 據本發明之方法確認佈局圖形時所獲得的底部影像平面上的影 像模擬圖形之-例，與最佳平面上的影像模擬圖形比較之，顯 2中斷不連續之處或過細之處，所形成的光阻圖案因底切而恐 •有倒塌之虞，而可判定此佈局圖形並不堪用，需要進一步 又，在光阻層為正型光阻之情形時， 較佳使用正失焦(_細def。㈣進娜擬於步f綱中㈣ 後所獲得的光阻層上部影侧形。較佳曝先及顯景 得一影像_。如此，依據顺得 層之同一高度导 蝴一崎===== 200846958 示製私中恐會造成滅失，此即不為 形更佳是取位於頂部的影像圖形。 的上方。-正失焦」職曝光時m位於最佳聚焦位置 對較強。對用正失焦時，光阻層上部所接受的光強度相 产在上邻㈣、而言，顯影後所形成的光阻圖案的線條寬Therefore, there is a need for a good graphical layout confirmation method, a mask layout pattern. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for confirming a layout pattern, which can be used to confirm the layout of the reticle, effectively discovering the layout _ possible defects, such as the collapse of the formed pattern and The defect of the film damage, and the layout pattern of the mask can be corrected. > S The method for confirming a layout pattern according to the present invention comprises the following steps. First, provide - layout graphics. The simulation is transferred to the film layer via the layout_ as a material to obtain the lower portion of the layer. In addition, she uses the layout pattern as a mask to transfer the layout layer to obtain a pattern of the upper layer of the film layer. Finally, confirm that these analog graphics are available. In the case of this "the other side of the Ming Dynasty, the side of the layout figure is confirmed according to the present invention. 200846958, the law\ includes the following steps. First, a layout graphic is provided. Then, an optical proximity correction is made to the layout image. The simulation is used as a mask through the layout pattern, the layout pattern is transferred to the film layer, the simulation pattern under the film layer is obtained, and the simulation is performed by using the cloth j pattern as a mask, and the layout pattern is transferred to the film layer to obtain the film layer. The upper part of the simulation graphic. Next, confirm if these analog graphics are available. When these simulated figures are not turned over, the layout of the layout is corrected. • [Embodiment] μ Referring to Fig. 4' is a flowchart showing a method for confirming a layout pattern according to the present invention: the method for confirming a layout pattern according to the present invention includes the following steps. The first step proceeds to step 202, providing a layout graphic. Then, the step is performed, and the simulation is transferred to the film layer through the layout pattern as a mask to obtain an analog pattern under the film layer. The step is performed independently of step 204, and the simulation is performed by using a layout pattern as a mask to transfer the layout pattern to the film layer to obtain a simulation pattern of the film layer. Finally, the steps are detailed to confirm whether the simulated graphics are provided in accordance with the layout of the confirmation layout according to the present invention. For example, the layout pattern of the reticle. Thus, in accordance with the confirmation layout of the present invention, the reticle can be applied to the confirmation of the layout of the reticle. To be confirmed by the graphic, the actual manufacturing of the resulting __ does not produce defects. 9 200846958; The term "film layer" as used herein may refer to a layer over which the layout, such as a layer of silk or a photoresist layer, is to be transferred via a reticle having a layout. Further, = resist, the layer to be covered is the layer to be rhymed, and may be, for example, a stone in the semiconductor process, an oxide layer, a nitride layer, and the like. Taking the bismuth layer as the photoresist layer as an example, the layout pattern provided in the step ==? is used as a mask, and the photoresist-to-resistance _^, the core to the photoresist layer is used to simulate the obtained lower portion of the photoresist layer. In the figure 206, the simulation uses the layout pattern layer provided in step 202 to simulate the exposure of the photoresist layer to transfer the layout pattern to the upper portion of the photoresist layer of the photoresist 2? Image graphics. It should be noted that the order of the steps is not limited, and is independent, that is, the image of the first layer of the image is simulated by the first layer, and the image is obtained by using the positive photoresist in the first and upper shadows. The exposure is preferably obtained by a photoresist layer::) Into: Quasi-exposure and _ acquired-image graphics for judging whether the image of the bottom of the same height of the 7^ layer is _. The lower image pattern of the resist layer is preferably located at 200846958. The "negative out-of-focus" of the present invention means that the focus point is below the optimal focus position during exposure. Generally, when negative defocusing is used, the light intensity received by the lower portion of the photoresist layer is relatively strong, which tends to cause excessive exposure of the lower or bottom portion of the photoresist layer. For positive photoresist, the line width of the photoresist pattern formed after development will be relatively narrow in the lower portion, and when it is too narrow or even lost, the photoresist pattern line will collapse. Figure 5 is a cross-sectional view of the simulated pattern after exposure and development of the photoresist layer with a negative out-of-focus, simulated using Mentor Graphics' simulation software. As shown, the graphic on the best image plane d still has a good line width, but the width of the graphic line on the bottom image plane e is relatively thin. Therefore, in the present invention, when the negative o focus is used to expose the positive resist layer and the image embedding pattern located on the bottom image plane is obtained, it is understood whether the formed pattern is usable. Figure 6 shows an example of an image simulation image on the bottom image plane obtained by confirming the layout pattern according to the method of the present invention. Compared with the image simulation pattern on the best plane, the display 2 interrupt discontinuity or too fine Whereas, the formed photoresist pattern is feared by undercutting and there is a collapse, and it can be judged that the layout pattern is not suitable, and further, when the photoresist layer is a positive photoresist, it is preferably used. Defocusing (_fine def. (4) Entering the upper part of the photoresist layer obtained after the step (4). It is better to expose the image and obtain an image _. Thus, according to the same layer The height of the guide is a ===== 200846958 The private system will cause loss, which means that it is better to take the image at the top. - The positive focus is at the best exposure. The focus position is strong. When the positive defocus is used, the light intensity received by the upper part of the photoresist layer is produced in the upper neighbor (four), and the line width of the photoresist pattern formed after development is wide.
形已不存在或是過細而在實 堪用。光阻層的上部影像圖 會相對較窄，當過窄甚或滅失時，若有一段滅 :隹::阻圖案線條產生不連續的情形。第7圖係模擬以一正 失…、對光阻層曝光顯影後賴擬_剖視圖，如圖所示，最佳 &像平面g上的®形仍具有良好的線寬，但是位於頂部影像平 面f上的圖形線條寬度相對的細。因此，於本發明中，當使用 正失焦對正型細層曝光，觀位於頂部影像平面之影像模擬 圖形時’可了解卿成的圖形是否咖。第8議示使用依據 本發明之^法確認佈局圖形時所獲得的頂部影像平面上的影像 模擬圖形之-例，與最佳平面上的影像模姻形啸之，顯有 中斷不連_之處或過細之處，使得所形成的光阻目案恐有膜減 損之虞’而可判定此佈局圖縣不翻’需要進—步的圖形修 Π-L 〇 負失焦的值可為製程容許度(process window)的負極限 值’及正失焦的值可為製程容許度的正極限值，如此，可供確 認所提供的佈局圖形，在製程容許度的正負極限值下是否堪用。 12 200846958 外尚了進-步极擬經由佈局圖形 佳聚焦曝光以轉移該佈局圖形岸去、阻層以一取 獲仔之先阻層之峨擬圖形，以供更進一步的佈局圖形確認。 ή“另:方? ’在光阻層為負型光阻之情形時’為了於光阻層 焦，，所使_正失焦或負^ ==Γ影像模_;及使用負失焦一 I且層上。卩的衫像模擬圖形。 層以：==模擬經由佈局圖形做為-光罩對光阻 平面上_^=^ 姐層，於最佳影像 認。層之影像模擬圖形，以i供佈局圖形確 下進二臈，崎來舉例說明，步驟2〇4及鳥可分別如 及餘^/ ’挺擬經由佈局圖形做為—光罩，進行—第-微於 化，再對級層覆蓋的待^#_層上覆蓋之光阻層圖案 形至待飿卿，#=了㈣餘，轉移佈局圖 擬妳由佑i 彳叙下賴賴擬_;及，另植 由微影製程， 將待钱刻層上覆蓋之光阻層圖射 由佈局圖形做為—光罩，進行—第二微影及㈣製程： 匕 ’再對光阻層 13 200846958 •覆蓋的待韻刻層進行韻刻製程，以轉移佈局圖开…主 獲得待颜刻層之上部韻刻模擬圖形。進-步，進」刻層， 二微影及__件，及進行第 是，.隹— 料程谷許打限的餘條件。或 製程停:弟::影艺刻製程時，可採用其製程容許度下限的 度上限的製程條時’可採用其製程容許 下部模擬圖形之外二二步驟以獲得待_層的上 -隶佳製_件之微影及偏頂程， 衫進仃 層，獲得待钕刻層之最佳钱刻模擬圖形。…I至待餘刻The shape is no longer present or too thin and can be used. The upper image of the photoresist layer will be relatively narrow. If it is too narrow or even lost, if there is a period of extinction: 隹:: The pattern of the resist pattern is discontinuous. Figure 7 is a cross-sectional view of the simulation after exposure and development of the photoresist layer. As shown in the figure, the image shape on the image plane g still has a good line width, but is located at the top image. The width of the graphic lines on the plane f is relatively thin. Therefore, in the present invention, when the positive defocusing is used to expose the fine layer, and the image is simulated on the top image plane, it is possible to know whether or not the image is clarified. The eighth example shows an example of an image simulation image on the top image plane obtained by confirming the layout pattern according to the method of the present invention, and the image on the best plane is simulated and smothered, and the interruption is not connected. At or above the fine point, the formed photoresist pattern may be degraded by the film', and it can be determined that the layout map does not turn over. 'Requires the step-by-step graphic repair-L. The value of the defocus can be the process. The negative limit value of the process window and the positive out-of-focus value can be the positive limit of the process tolerance. Therefore, it can be confirmed whether the layout pattern provided can be used under the positive and negative limits of the process tolerance. . 12 200846958 Externally, the step-by-step method is recommended to pass the layout pattern. The focus is exposed to transfer the layout pattern to the shore, and the resist layer is used to obtain the simulated pattern of the first layer of the mask for further layout confirmation. ή “Other: square? 'When the photoresist layer is a negative photoresist, 'for the photoresist layer, _ positive defocus or negative ^ == Γ image mode _; and use negative defocus one I and the layer. The shirt of the 像 is like an analog figure. The layer is: == simulation through the layout of the pattern - the reticle on the photoresist plane _^=^ sister layer, in the best image recognition. Layer image simulation graphics, I use the layout graphic for i to enter the second floor. Sakizaki exemplified that step 2〇4 and the bird can be used as the mask, and the first-to-micro-chemical, The pattern of the photoresist layer covered on the layer of the layer to be covered by the layer is to be 饳 饳,#=了(四)余,,,,,,,,,,,,,,,,,,,,,,,, The lithography process, the photoresist layer covered by the layer of the money is printed by the layout pattern as a mask, the second lithography and the (four) process: 匕 'repeated to the photoresist layer 13 200846958 The engraving layer carries out the rhyme engraving process, and the transfer layout map is opened... The main body obtains the rhyme engraving simulation pattern on the upper part of the engraved layer. The step-by-step, the engraving layer, the second lithography and the __piece, and the first is, 隹Gu Cheng Xu expected to play more than limited conditions. Or the process stop: Brother:: When the film engraving process can be used, the process bar with the upper limit of the process tolerance lower limit can be used. 'The process can be used to allow the lower analog figure to be used in the second step to obtain the upper layer of the to-be-layer.佳 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ...I to wait for the moment
明參閱苐9圖所示之—呈辦杳纟a a丨.A 打之具體實_，於本發明之方法中， :此等模擬圖形是否堪用之後’當發現所獲得 ，，膜層之上部或下部模擬圖形)任一者有滅失或有： 虞:，表不不為堪用，則可進一步包括對所提供的佈形 行步驟210以修飾佈局圖形，可利用例如光學近接修正進行此 修飾。此賴_形是否堪狀確 檢驗來進行。打利用例如光學規則 於本發明之另-方面，應用上述之本發明之確認佈局圖形 之方法，可進-步提供一種確認佈局圖形之方法，請參閱第⑺ 圖所示之具體實施例以說明。首先，進行步驟2ιι，提供一佈 局圖形。紐’進行步驟212，將佈觸形根據模型資料進行 14 200846958 〇pc之修正。然後，對於 佈局圖形做為光 仃步驟214，模擬經由 得膜層之下部=層進行曝光以轉移佈局圖形至膜層，獲 相同。例:=T形。步驟214與步驟204之進行方: 在臈層為正型光阻層 的取負極限值的負失焦對正〜吟度 之底部影像模擬圖形。及，另進订曝先，並獲得光阻層 圖形做為-光罩對—膜層進驟216 ’亦模擬經由佈局 此步驟是為外膜屏、日丁"光以轉移佈局圖形至膜層，而 之進行方式^上部影像模擬圖形。步驟216與步驟2〇6 獲得光阻層之頂部影像模擬_。阻層進仃曝先，並 声二!1 進行曝光，轉移佈局圖形至光阻 先阻層之祕影像平面上之影像模_形 =驟:的咖檢驗以確顧形，若影像_正確而堪用， 的=:局圖形輸出，若有誤，則再進行_ 修正’以對於佈局圖形做修正，修正量可參酌所得膜声 ==形缺失的情形，即，可依據所得之模擬圖形缺失的二 ^小來奴佈關形於0PC程序切修正量。如此，可確認 佈局圖形亚進-步有效修正不㈣佈局圖形。 可有效模擬光阻圖形 使用本發明之確認佈局圖形之方法， 15 200846958 或其他圖形。例如，可直接應用於OPC校正，或可在進行習知 之OPC確認之後，再應用本發明之方法予以確認，然後可進一 步做佈局圖形的修正。使用本發明之確認佈局圖形之方法，亦 可應用於蝕刻(etching)技術，經過模擬後，確認所形成的蝕刻 模擬圖形是否堪用，以確認佈局圖形。本發明之確認佈局圖形 之方法可應用於任何之微影技術，例如一般的微影、解析度加 強技術(resolution enhancement technique，RET)、雙偶極微影 • (d〇uble dip〇le Iith〇gr_y，DDL)、雙重圖形(double patterni⑽ 技術、化學性收縮辅助之微影解析度增a(resoluti〇n enhancement of lithography by assist of chemical shrink ^ RELAS)、熱流(thermal flow)、用以加強解析度之收縮辅助膜 (shrmk assist film for enhanced resolution，SAFIER)等等。應用 本如月之方法可防止因為不良的操作條件導致良率的損失，並 且亦能夠減少光罩產出的成本與時間。再者，使用依據本發明 • 之方法可對二維空間的圖形予以確認，與習知之使用OPC僅能 確認二維圖形比較下，更為好用，此在45奈米製程尤為重要， 可避免具有膜層圖形特徵尺寸之線形崩塌或頂部膜減損而影響 元件性能。 ^ 一以上所述僅為本發明之較佳實施例，凡依本發明申請專利 辄圍所做之均等變化與修鄉，皆應屬本發明之涵蓋範圍。 ' 【圖式簡單說明】 16 200846958 第1圖顯示習知技術中利用OPC來確認光罩之佈局圖形的 流程。 第2圖顯示習知之LRC流程。 第3圖顯示一光阻層於使用一最佳聚焦曝光後所形成的模 擬圖形剖視圖。 第4圖顯示一依據本發明之確認佈局圖形之方法之流程。 第5圖係模擬以一負失焦對光阻層曝光顯影後的模擬圖形 剖視圖。 第6圖顯示使用依據本發明之方法確認佈局圖形時所獲得 的影像模擬圖形之一具體實施例。 第7圖係模擬以一正失焦對光阻層曝光顯影後的模擬圖形 剖視圖。 第8圖顯示使用依據本發明之方法確認佈局圖形時所獲得 的影像模擬圖形之一具體實施例。 第9圖顯示依據本發明之一具體實施例。 第10圖顯示依據本發明之一具體實施例。 【主要元件符號說明】 102、103、104、1〇6、108、110、112、114、116、118、120、 122、202、204、206、208、210、212、214、216、218、220、 222 步驟 17In the method of the present invention, it is as follows: In the method of the present invention, whether or not such simulated graphics are available, 'when found, the upper part of the film Or the lower analog graphic) either has a loss or has: 虞:, the table is not useful, may further include the provided line step 210 to modify the layout pattern, which may be modified by, for example, optical proximity correction . Whether the _ shape is correct or not. By using, for example, optical rules in another aspect of the present invention, the method of confirming the layout pattern of the present invention described above can be used to provide a method for confirming the layout pattern. Please refer to the specific embodiment shown in the figure (7) for explanation. . First, proceed to step 2 and provide a layout graphic. New' proceeds to step 212, and the cloth is shaped according to the model data to be corrected by 2008 200858. Then, for the layout pattern as the light step 214, the simulation is performed by exposing the lower layer of the film layer to transfer the layout pattern to the film layer, which is the same. Example: = T shape. Step 214 and proceeding to step 204: The bottom image of the negative defocusing of the positive resistive layer of the positive resistive layer is positive to negative. And, another order exposure, and obtain the photoresist layer pattern as - reticle pair - film layer step 216 'also simulates through the layout of this step is for the outer film screen, the Japanese light and the light to transfer the layout pattern to the film Layer, and the way to do it ^ upper image simulation graphics. Step 216 and step 2〇6 obtain the top image simulation _ of the photoresist layer. The resist layer is exposed first, and the sound is second! 1 Exposure, transfer the layout pattern to the image mode on the image plane of the resistive layer of the photoresist first layer _ shape = step: the coffee test to determine the shape, if the image _ correct Can be used, =: Bureau graphics output, if there is a mistake, then _correction to make corrections to the layout graphics, the correction can be determined by the film sound == shape missing, that is, can be based on the resulting simulated graphics missing The two ^ small slaves are cut in the 0PC program to cut the correction amount. In this way, it can be confirmed that the layout pattern sub-step effective correction does not (4) the layout pattern. Effectively Simulating Photoresist Patterns The method of confirming layout patterns using the present invention, 15 200846958 or other graphics. For example, it can be directly applied to OPC correction, or can be confirmed by applying the method of the present invention after performing the conventional OPC confirmation, and then the layout pattern can be further corrected. The method of confirming the layout pattern of the present invention can also be applied to an etching technique, and after the simulation, it is confirmed whether or not the formed etching simulation pattern is available to confirm the layout pattern. The method for confirming the layout pattern of the present invention can be applied to any lithography technique, such as general lithography, resolution enhancement technique (RET), double dipole lithography (d〇uble dip〇le Iith〇gr_y) , DDL), double pattern (double patterni (10) technique, chemical shrinkage assisted by lithography by assist of chemical shrink ^ RELAS, thermal flow, to enhance resolution Shrmk assist film for enhanced resolution (SAFIER), etc. The application of this method can prevent the loss of yield due to poor operating conditions, and can also reduce the cost and time of mask production. The method according to the present invention can be used to confirm the two-dimensional image, and it is more convenient to use the OPC only to confirm the two-dimensional image, which is particularly important in the 45 nm process, and the film layer can be avoided. Linear collapse of the feature feature size or damage to the top film affects component performance. ^ One or more of the above are only preferred embodiments of the present invention, All changes and repairs made in accordance with the patent application of the present invention should fall within the scope of the present invention. ' [Simple Description of the Drawings] 16 200846958 Figure 1 shows the use of OPC to confirm the mask in the prior art. Flow of layout graphics. Figure 2 shows a conventional LRC flow. Figure 3 shows a cross-sectional view of a simulated pattern formed by a photoresist layer using a best focus exposure. Figure 4 shows a confirmation layout pattern in accordance with the present invention. The flow of the method. Fig. 5 is a schematic cross-sectional view of the simulation after exposure and development of the photoresist layer with a negative out-of-focus. Figure 6 shows one implementation of the image simulation pattern obtained when the layout pattern is confirmed by the method of the present invention. Fig. 7 is a cross-sectional view showing the simulation of the photoresist layer after exposure and development with a positive defocus. Fig. 8 shows a specific embodiment of the image simulation pattern obtained when the layout pattern is confirmed by the method of the present invention. Figure 9 shows an embodiment in accordance with the present invention. Figure 10 shows an embodiment in accordance with the present invention. [Explanation of main component symbols] 102, 103, 104, 1〇6, 108, 110, 112, 114, 116, 118, 120, 122, 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222 Step 17