200845400 ， 九、發明說明： ^ 【發明所屬之技術領域】 本發明是有關於一種非揮發性記憶體（nonvolatile memory)，特別是指一種具有奈米點（nanocrystal)之電荷儲 存層（trapping layer)的非揮發性記憶體。 【先前技術】 近年來非揮發性記憶體雖然在市場上受到廣泛的重視 . ，但是卻有它本身的極限。最大的問題在於當非揮發性記 ® 憶體之元件尺寸持續微小化的同時，穿隧氧化層（tuimeling oxide layer)也隨之微小化。這將導致非揮發性記憶體的穿 隧氧化層必須於快速讀寫及優越的容忍性（endurance)、分立 (distributed)等元件特性之間作取捨。 ^ 因穿隧氧化層需要被多次且快速地讀寫而被要求需具 _ 備有較優越的隔絕能力，以使得當非揮發性記憶體在經過 多次的讀寫之後，仍可藉由穿隧氧化層的容忍性與分立等 0 特性來維持電荷的儲存，進而避免因為在穿隧氧化層形成 漏電路徑而使得所有儲存在浮停閘（floating gate)的電荷透 過穿隧氧化層的漏電路徑全數地流失掉。 如果考量使用較薄的穿隧氧化層時，則記憶體的保存 能力將會劣化；另一方面，若提高穿隧氧化層的厚度來增 加電荷儲存能力時，電荷讀寫的速度將會變慢。因此，必 需在非揮發性記憶體的讀寫速度、可靠度以及其穿隧氧化 層的厚度之間做取捨。 由於傳統的非揮發性記憶體主要是以多晶矽（poly Si)材 5 200845400 Λ £ 料做為電荷儲存層（即，多晶矽浮停閘），雖然可藉由多晶矽 本身的缺陷以提供儲存載子的電荷儲存中心（trapping center) ’但由於多晶石夕為半導體（seiniconductor)材料，儲存 於多晶矽中的電荷可於此電荷儲存層移動，因此，一旦在 穿隧氧化層產生一漏電路徑時，所有儲存於電荷儲存層的 電荷便會全部流失，這對於元件的特性、可靠度以及容忍 度都是一大挑戰。 φ 有鑑於傳統多晶矽浮停閘的缺點，目前常見之非揮發 ί生θ己丨思體可为為兩大類。一類是以載子遷移率較低的氮化 物（nitride)來取代多晶矽浮停閘並構成半導體—氧化物-氮化 物-氧化物-半導體（SONOS)結構的非揮發性記憶體，另一類 是奈米點非揮發性記憶體。 以奈米點非揮發性記憶體的結構來說，TWI268579及 TWI232582分別揭露出具有半導體奈米點之浮停閘的非揮 發性記憶體之結構。前揭兩篇中華民國專利主要是一種同 φ 時結合有SONOS結構及奈米點之非揮發性記憶體，其電荷 儲存層主要是利用電漿輔助化學氣相沉積法（PECVD)形成一 含有Ge、Si、N之組成，或一含有Ge、Si、N、Ο之組成 ，並利用600°C〜1000°C之間的熱處理溫度對前述之組成施 予高溫熱退火處理，以於前述組成中析出（precipitation)鍺 (Ge)奈米點，並作為獨立分離的電荷儲存中心，藉以改善電 何流失的缺失。 另，Jan De Blauwe 於 IEEE TRANSACTIONS ON NANOTECHNOLOGY，VOL. 1，MARCH 2002, R 72 〜75 揭 6 200845400 路出種奈米點非揮發性記憶體。前揭文獻之奈米點的製 作方法主要疋利用熱氧化法（thermal oxidation)的技術於 石夕基板上預先形成一厚度約介於2〇 ηπι ~ 30 nm之間的 i〇2層’進一步地’利用離子佈植（i〇n impiantati〇n)於該200845400, IX. Description of the invention: ^ TECHNICAL FIELD OF THE INVENTION The present invention relates to a nonvolatile memory, and more particularly to a charge storage layer having a nanocrystal. Non-volatile memory. [Prior Art] In recent years, non-volatile memory has received extensive attention in the market, but it has its own limits. The biggest problem is that while the component size of the non-volatile memory is continuously miniaturized, the tunneling oxide layer is also miniaturized. This will result in a non-volatile memory tunneling oxide layer that must be traded off between fast read and write and superior endurance, distributed, and other component characteristics. ^ Because the tunnel oxide layer needs to be read and written multiple times and quickly, it is required to have a superior isolation capability, so that when the non-volatile memory is read and written multiple times, it can still be used. The toleration and discrete zero characteristics of the tunnel oxide layer maintain charge storage, thereby avoiding leakage of all charges stored in the floating gate through the tunnel oxide layer due to the formation of a leakage path in the tunnel oxide layer. The path is completely lost. If a thinner tunneling oxide layer is used, the memory retention capacity will be degraded. On the other hand, if the thickness of the tunneling oxide layer is increased to increase the charge storage capacity, the charge reading and writing speed will be slower. . Therefore, it is necessary to make a trade-off between the read/write speed, reliability, and thickness of the tunneling oxide layer of the non-volatile memory. Since the conventional non-volatile memory is mainly made of polysilicon material (20084400) as a charge storage layer (ie, polycrystalline floating gate), although the defects of the polysilicon itself can be provided to provide storage carriers. Charge trapping center 'But because polycrystalline stone is a semiconductor (seiniconductor) material, the charge stored in the polysilicon can move in this charge storage layer, so once a leakage path is created in the tunnel oxide layer, The charge stored in the charge storage layer is completely lost, which is a challenge for the characteristics, reliability and tolerance of the component. φ In view of the shortcomings of traditional polycrystalline floating gates, the current non-volatile θ 丨 丨 丨 丨 可 可 。 。 。 。 。 。 。 。 。 。 。 。 。 。 One type is a non-volatile memory in which a semiconductor-nitride-nitride-semiconductor (SONOS) structure is replaced by a nitride with a lower carrier mobility and a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) structure. Rice point non-volatile memory. In terms of the structure of the nano-non-volatile memory, TWI268579 and TWI232582 respectively reveal the structure of the non-volatile memory with floating gates of semiconductor nano-dots. The two patents of the Republic of China are mainly non-volatile memory with SONOS structure and nano-dots combined with φ. The charge storage layer is mainly formed by plasma-assisted chemical vapor deposition (PECVD). a composition of Si, N, or a composition containing Ge, Si, N, and yttrium, and applying a high temperature thermal annealing treatment to the above composition by a heat treatment temperature between 600 ° C and 1000 ° C to form the composition Precipitation 锗(Ge) nano-dots are used as independent charge storage centers to improve the loss of electricity loss. In addition, Jan De Blauwe in IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, MARCH 2002, R 72 ~ 75 uncover 6 200845400 road out of the nano point non-volatile memory. The method for fabricating the nano-dots of the prior art mainly uses a thermal oxidation technique to pre-form a layer of i〇2 having a thickness between about 2〇ηπι and 30 nm on the Shixi substrate. 'Using ion implants (i〇n impiantati〇n)
Si〇2層内植入Si離子，並透過約1〇⑽。c的高温對該 層施予長達30分鐘的高溫熱退火，進而在該Si〇2層内析出 矽奈米點。 月；!揭中華民國專利與文獻之奈米點非揮發性記憶體， 於形成有漏電路徑時雖然不會造成致命的電荷流失；然而 ’其於製作奈米點非揮發性記憶體時所使用的製作方法， 不僅因Si及Ge等半導體奈米點的功函數（w〇rk functi〇n)與 能-態密度(density 〇f s恤e)較低，而導致其對於儲存效專' 貪料保存時間（retention)與記憶視窗（mem〇ry wind〇w)的貢獻 度有限；此外，最終所形成之奈米點的密度有限，且亦因 需透過高溫（通常溫度高達100(rc)的退火處理而增加了設備 與熱預鼻（thermal budget)上的成本。 由上述說明可知，在解決漏電路徑所產生的電荷流失 等問題的考量下以優化奈米點非揮發性記憶體的儲存效率 、保存時間與記憶視窗，同時亦需減少奈米點非揮發性記 憶體的設備與熱預算成本，是非揮發性記憶體相關領域者 所待突破的課題。 【發明内容】 <發明概要> 有鑑於形成於先前技術之電荷儲存層中的Ge或Si等 7 200845400 半導體不米點’因功函數與能態密度過低而 、資料保存時間與記憶視窗μ等問題。 存遑率 本發明主要是以-NixSiyM_y之組成 存層，JL中，电何儲 存層/、中Μ疋Ν、〇，或的一組合， 儲存層内具有複數鎳（Ni)夺乎 可 >>不木點。利用鎳本身具備有 數與能態密度的特點，以作為獨立分離的電荷儲存中〜 同N·利用氮化石夕或氧化石夕等介電材料包圍錄奈米點，進 優化奈米點非揮發性記憶體之健存速率、資料保 記憶視窗。 71、 值付提的疋，當Nl於該組成中的含量過高時， 立分離的電荷儲存中心將會消失並產生與一般多晶石夕浮停 閑記憶體相期問題;反之，當Ni於該組成中的含量過低 時，則储存效率亦將嚴重地下降。另，# Si於該組成中的 含量過高時，則過量的半導體材料將使得分離效果降低並 影響储存效率；反之’當Si於該組成的含量過低時，則該 組成中因沒有足夠的Si以與N4〇形成介電材料而降低分 離效果。因此，在該NixSiyMi〇〇x〆組成中，邮Kb; l〇$y$30。 〈發明目的〉 因此，本發明之㈣，即在提供一種具有奈米點之電 荷儲存層的非揮發性記憶體。 於是，本發明具有奈米點之電荷儲存層的非揮發性記 憶體，包含具有-源極及-與該源極相間隔設置的沒 極之半導體基板、一局部地疊置於該源極與汲極的電荷儲 200845400 存膜，及一疊置於該電荷儲存膜的閘極。 該书何儲存膜具有一形成於該半導體基板的穿隧氧化 运 形成於该穿隧氧化層的阻絕氧化層及一含有一 NWi具咖”之組成並夾置於該等氧化層之間的電荷儲存層 ，其中，l〇$x$25 ; 10<dM*NnN&〇 的-組合。該電荷儲存層具有複數錄奈米點。 々本I明之功效在於’在解決漏電路徑所產生的電荷流 失等問題的考量下，可優化奈米點非揮發性記憶體的儲存 效率、保存時間與記憶視窗。 【實施方式】 <發明詳細說明> 記«之-較佳實施例’包含：_具有—源極21及—財 源極相間隔設置的波極22之半導體基板2、—局部地晶 :於該源極21與汲極22的電荷儲存膜3，及一疊置於該； 何ί諸存膜3的間極4。 〃該電荷儲存膜3具有-形成於該半導體基板2的穿隨 ::層31、-形成於該穿隧氧化層3i的阻絕氧化層32及 -含有- NixSiyM—之組成並夹置於該等氧化層3卜” ，間的電荷儲存層t其中，1〇_5;i〇_3〇;m 疋N、〇,或！^及〇的一組合。 鎳奈米點33卜 衫何儲存層％具有複數 較仏地，Μ是N及〇的一組合；在本發明具有奈米點 之電荷儲存層的非揮發性記憶體之較佳實施例中，更包含 9 200845400 一覆蓋該半導體基板2與閘極4的保護膜5 ’及複數供該源 極21、汲極22、閘極4電性連接的接點插塞（contact phxg)6 •，該穿隧氧化層31與阻絕氧化層32是Si〇2 ’該閘極4是 多晶矽；該半導體基板2是p型矽基板。 更佳地，經由濺鍍法（sputtering)在一含有〇2與A且工 作壓力介於1 mTorr〜100 mTorr之間及工作溫度介於25 C 〜600°C之間的反應環境中，對一 SiNi靶材（target)施予60 W 〜200 W之間的輸出功率以預先形成該NixSiyMi〇〇_x_y之組成 ，並對該NixSiyM1()G-x_y之組成施予溫度介於150°C ~ 500°C 之間且時間介於10秒〜1〇〇秒之間的快速熱退火（rapid thermal annealing，簡稱RTA)以製得該電荷儲存層33,且 Si與Ni於該SiNi乾材中的重量百分比分別是介於5〇1〇11% 〜80 vol%之間及介於5〇 v〇1%〜2〇 v〇1%之間。 值得一提的是’ Ni的熱擴散遷移率高，且在不同材料 的界面處會產生成核驅動力（nucleati〇n driving force)以吸引Si ions were implanted into the Si〇2 layer and passed through about 1 〇 (10). The layer was subjected to high-temperature thermal annealing for a period of 30 minutes at a high temperature of c, and a germanium point was precipitated in the layer of Si 2 . Month;! Revealing the nano-point non-volatile memory of the Republic of China patents and literature, although it does not cause fatal charge loss when forming a leakage path; however, it is used when making nano-point non-volatile memory. The production method is not only due to the lower work function (w〇rk functi〇n) and energy density (density 〇fs shirt e) of semiconductor nano-dots such as Si and Ge, which leads to the special effect of storage efficiency. The contribution of retention and memory window (mem〇ry wind〇w) is limited; in addition, the resulting nano-dots have a limited density and are also required to pass through high temperatures (typically annealing at temperatures up to 100 (rc)). The treatment increases the cost of the device and the thermal budget. As can be seen from the above description, in order to solve the problem of charge loss caused by the leakage path, etc., to optimize the storage efficiency of the nano-point non-volatile memory, Saving time and memory window, and also reducing the equipment and thermal budget cost of nano-point non-volatile memory, is a subject to be solved in the field of non-volatile memory. [Summary] SUMMARY [In view of the problems such as Ge or Si, etc., which are formed in the charge storage layer of the prior art, the 2008-400400 semiconductor does not have a low work function and energy density, data retention time, and memory window μ. The invention is mainly composed of -NixSiyM_y, JL, a combination of electricity storage layer, medium bismuth, bismuth, or a combination of nickel (Ni) in the storage layer > Wood point. The use of nickel itself has the characteristics of number and energy density, as a separate separation of charge storage ~ with N · using nitride or oxidized stone and other dielectric materials to surround the nano-point, to optimize the nano-point The storage rate of non-volatile memory and the data retention memory window. 71. When the value of Nl is too high in this composition, the charge storage center of the vertical separation will disappear and produce polycrystalline Shi Xifu stops the memory phase problem; on the contrary, when the content of Ni in the composition is too low, the storage efficiency will also be seriously degraded. In addition, when #Si is too high in the composition, the excess is excessive. Semiconductor material will make separation Decrease and affect the storage efficiency; otherwise, when Si is too low in the composition, there is not enough Si in the composition to form a dielectric material with N4〇 to reduce the separation effect. Therefore, in the NixSiyMi〇〇x〆 In the composition, the mail Kb; l〇$y$30. <Object of the Invention> Therefore, (4) of the present invention provides a non-volatile memory having a charge storage layer of a nano-dots. Thus, the present invention has a nano-point. The non-volatile memory of the charge storage layer comprises a semiconductor substrate having a source and a drain electrode spaced apart from the source, and a charge reservoir partially deposited on the source and the drain. And a stack of gates placed on the charge storage film. The storage film of the book has a charge-forming oxide formed on the semiconductor substrate and formed in the tunneling oxide layer and a charge containing a composition of NW and sandwiched between the oxide layers. a storage layer, wherein, l〇$x$25; 10<dM*NnN&〇- combination. The charge storage layer has a plurality of nanometer dots. The effect of the present invention is to solve the charge loss caused by the leakage path. Under the consideration of the problem, the storage efficiency, storage time and memory window of the nano-point non-volatile memory can be optimized. [Embodiment] <Detailed Description of the Invention> The "preferred embodiment" includes: _ has - a source 21 and a semiconductor substrate 2 of a wave electrode 22 spaced apart from each other, a local crystal: a charge storage film 3 of the source 21 and the drain 22, and a stack of the same; The interpole 4 of the film 3. The charge storage film 3 has a layer formed on the semiconductor substrate 2: a layer 31, a resistive oxide layer 32 formed on the tunnel oxide layer 3i, and a - NixSiyM- Forming and sandwiching the oxide layer 3 Medium, 1〇_5; i〇_3〇;m 疋N, 〇, or! ^ and a combination of 〇. The nickel nano-point 33 has a storage layer% having a plurality of layers, and the tantalum is a combination of N and niobium; in a preferred embodiment of the non-volatile memory of the present invention having a charge storage layer of a nano-dots, Further comprising: 9 200845400 a protective film 5 ′ covering the semiconductor substrate 2 and the gate 4 and a plurality of contact plugs for electrically connecting the source 21 , the drain 22 and the gate 4 • The tunnel oxide layer 31 and the resistive oxide layer 32 are Si〇2'. The gate 4 is a polysilicon; the semiconductor substrate 2 is a p-type germanium substrate. More preferably, by sputtering, in a reaction environment containing 〇2 and A and having a working pressure of between 1 mTorr and 100 mTorr and an operating temperature of between 25 C and 600 ° C, The SiNi target is applied with an output power of between 60 W and 200 W to preliminarily form the composition of the NixSiyMi〇〇_x_y, and the composition of the NixSiyM1() G-x_y is applied at a temperature of 150 ° C ~ Rapid thermal annealing (RTA) between 500 ° C and between 10 seconds and 1 sec to prepare the charge storage layer 33, and Si and Ni in the SiNi dry material The weight percentages are between 5〇1〇11%~80 vol% and between 5〇v〇1%~2〇v〇1%. It is worth mentioning that 'Ni has a high thermal diffusion mobility, and nucleati〇n driving force is generated at the interface of different materials to attract
Nl聚集結曰曰曰’因此’本發明利用濺鍍法所預先形成的 NixSiyM.x_y之組成在實施1^八的過程中，可促使见往該 穿隧氧化層31與電荷儲存層33的界面移動並形成奈米點 。另’因Nl的熱擴散遷移率較高，當RTA的處理溫度大於 500 C時’則該等鎳奈米點331❺尺寸將逐漸變大，雖可適 用於非微小化元件製程，然而，對於微小化元件而言，將 影響所製付之微小化元件的電性且亦不適用於需進行低溫 製程的玻璃或塑膠等基板；反之，當RTA的處理溫度小於 150C時’則所提供的熱動能不足，將影，Ni $積效果與 10 200845400 周圍il %材料的產生，導致分離效果不明顯。 卜本發明該NixSiyMi(K)-x-y之組成是經由濺鑛法所 構成，於沉積過程中，Ni可均勻地分散於該 之組成中，因此，在實施RTA過程中，亦增加了奈米^ y 成核密度。Nl aggregation crucible 'so' the composition of NixSiyM.x_y pre-formed by the sputtering method of the present invention can promote the interface between the tunneling oxide layer 31 and the charge storage layer 33 during the implementation of the method Move and form a nano point. In addition, because Nl has a high thermal diffusion mobility, when the processing temperature of RTA is greater than 500 C, the size of the nano-nano-point 331 逐渐 will gradually become larger, although it can be applied to the process of non-miniature components, however, for tiny In terms of the components, it will affect the electrical properties of the micro-components that are manufactured and will not be suitable for substrates such as glass or plastics that require low-temperature processing. Conversely, when the processing temperature of RTA is less than 150C, the thermal kinetic energy provided Insufficient, will shadow, Ni $ product effect with 10 200845400 around il% of the material produced, resulting in a separation effect is not obvious. The composition of the NixSiyMi(K)-xy is formed by a sputtering method, in which Ni can be uniformly dispersed in the composition, and therefore, in the process of implementing the RTA, the nanometer is also added. y nucleation density.
另’值得一提的是，形成於該電荷儲存層33内的鎳奈 米之尺寸大小不僅涉及該NixSiyM100|y之組成中的 Ni含量，此外，亦涉及該電荷儲存層33本身的厚度。因此 ，為達到非揮發性記憶體微小化的目的，又更佳地，該電 何儲存層33的厚度是介於5 nm〜1〇 nm之間，且該等鎳奈 米點331的尺寸是介於4 nm〜7 nm之間。 有臟本I明文I述其屬技術内容、择點—知 以下配合參考圖式之'二個—具體例的詳細說明-中…，將可清楚-的呈現。 <具體例> 在本發明被詳細描述之前，要注意的是，在以下的說 明内谷中，類似的元件是以相同的編號來表示。 再參閱圖1 ’在本發明具有奈米點之電荷儲存層的非揮 發性記憶體之一具體例中，M是N及〇的一組合[即， NixSiy(NO)剛…y] ; χ=20 ; y=30，且該 NixSiyM!。。-x_y 之組成 為Ni^Si^N^O25 ;該半導體基板2是p型矽基板；該穿隧 氧化層31與阻絕氧化層32是Si〇2，且該穿隧氧化層31與 阻絕氧化層32的厚度分別是2 nm〜5 nm及15 nm〜30 ，該電荷儲存層33的厚度約8 nm ;該等鎳奈米點331的尺 11 200845400 寸約5 nm ;該閘極4是多晶石夕，且該閘極4的厚度是！5〇 mn〜200 nm ;該保護膜5是Si〇2，且該保護膜5的厚度是 500 nm 〜600 nm 〇 本發明該具體例之電荷儲存層33的製作方法，是簡單 地說明於下。 於一含有〇2與&之流量比約為2 sccm/1〇 sccm且工作 壓力及工作溫度分別為7·6 mT〇rr& 25。〇的反應環境中，對 一 Si^Ni3。靶材施予80 w的輸出功率以預先形成該 NixSiyM1G。·"之組成；進一步地，對該NixSiyMHy之組成 施予溫度為50(TC且時間為3〇秒的快速熱退火以製得該具 體例之電荷儲存層33。 ' :=參屯本發i該具體例之寒透式笔子顯微巍 (transmiss麵 electron micr〇sc〇pe，簡稱-tem)形貌圖顯示可 知，本發明該具體例之鎳奈米點的尺寸約5nm。 另，參關3，自本發明該具體例之電容比對間極電壓 曲線圖顯示可知，本發明該具體例於±1〇 v及電容比為 的條件下所取得之記憶視窗可達〗·25 v。 _ 本發明利用Ni本身具備有高功函數與能態密度的特點 ’以作為獨立分離的電荷儲存中心、，同時利用氮化矽或氧 切等介電材料包圍鎳奈米點，可解決漏電路徑所產生的 電荷流Μ問題’進而優化奈米點非揮發性記憶體之儲存 速率、資料保存時間與記憶視窗；再者，本發明所使用的 犯，因熱擴散遷移率高，且在不同材料的界面處會產生成 核驅動力以吸引Ni聚集結晶，亦降低了形成奈米點的熱預 12 200845400 算等成本。 、.’’τ、上所述本發明具有奈米點之電荷儲存層的非揮發 性記憶體，在解決漏電路徑所產生的電荷流失等問題的4 量下，可優化非揮發性記憶體的儲存效率、保存時間與記 憶視窗，此外’亦可減少非揮發性記憶體的設備與熱預算 成本，確實達到本發明之目的。 惟以上所述者，僅為本發明之較佳實施例而已，當不 Φ %以此限疋本發明實施之範圍’即大凡依本發明申請專利 _及發明朗内容所作之簡單料效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 一-一二一圖Λ是―一正視示意圖，說明本發明具有奈米點之電荷 儲存層的非揮發性記憶體之-較佳實施例；—―一— 回疋ΤΕΜ形貌圖，說明本發明具有奈米點之電荷 儲存層的非揮發性記憶體之一具體例；及 華 目3疋一電容比對閘極電屋曲線圖，說明本發明該且 體例之記憶視窗特性。 /、 13 200845400 【主要元件符號說明】 2 •………半導體基板 33···•…··電荷儲存層 21·········源極 331 ••…··鎳奈米點 22………汲極 3 ..........電荷儲存膜 31………穿隧氧化層 3 2………阻絕氧化層 4 .........•閘極 5 ........••保護膜 6 ..........•接點插塞 _ 14Further, it is worth mentioning that the size of the nickel nanoparticle formed in the charge storage layer 33 not only relates to the Ni content in the composition of the NixSiyM100|y, but also relates to the thickness of the charge storage layer 33 itself. Therefore, in order to achieve the purpose of miniaturization of the non-volatile memory, and more preferably, the thickness of the storage layer 33 is between 5 nm and 1 〇 nm, and the size of the nickel nano-dots 331 is Between 4 nm and 7 nm. There is a dirty I. It is a technical content, a selection point - the following is a detailed description of the two - specific examples - which will be clearly visible. <Specific Example> Before the present invention is described in detail, it is to be noted that in the following description, similar elements are denoted by the same reference numerals. Referring again to FIG. 1 'in one specific example of the non-volatile memory of the charge storage layer having a nano-point of the present invention, M is a combination of N and 〇 [ie, NixSiy(NO) just...y]; χ= 20; y=30, and the NixSiyM!. . The composition of -x_y is Ni^Si^N^O25; the semiconductor substrate 2 is a p-type germanium substrate; the tunneling oxide layer 31 and the resistive oxide layer 32 are Si〇2, and the tunneling oxide layer 31 and the resistive oxide layer The thickness of 32 is 2 nm to 5 nm and 15 nm to 30, respectively, and the thickness of the charge storage layer 33 is about 8 nm; the size of the nickel nano-point 331 is about 10 nm of 200845400 inches; the gate 4 is polycrystalline. Shi Xi, and the thickness of the gate 4 is! 5〇mn~200 nm; the protective film 5 is Si〇2, and the thickness of the protective film 5 is 500 nm to 600 nm. The method for fabricating the charge storage layer 33 of this specific example of the present invention is simply described below. . The flow ratio of 〇2 to & is about 2 sccm/1 〇 sccm and the working pressure and working temperature are 7·6 mT 〇rr & 25, respectively. In the reaction environment of ruthenium, a pair of Si^Ni3. The target was subjected to an output power of 80 w to preliminarily form the NixSiyM1G. The composition of the "further; a composition of NixSiyMHy is applied to a rapid thermal annealing at a temperature of 50 (TC and a time of 3 sec to prepare the charge storage layer 33 of this specific example. ' := i. The top view of the transmissive surface electron micr〇sc〇pe (-tem) shows that the size of the nickel nano-dots of this specific example of the present invention is about 5 nm. Referring to FIG. 3, the capacitance comparison diagram of the specific example of the present invention shows that the memory window obtained by the specific example of the present invention is ±1〇v and the capacitance ratio is up to 〖.25 v _ The present invention utilizes Ni itself to have the characteristics of high work function and energy density as a separate charge storage center, and at the same time, the nickel nano-dots are surrounded by a dielectric material such as tantalum nitride or oxygen cut to solve the leakage. The problem of charge flow generated by the path' further optimizes the storage rate, data retention time and memory window of the nano-point non-volatile memory; further, the use of the present invention is high due to thermal diffusion mobility and is different Nucleation drive at the interface of the material The force is used to attract the Ag to collect crystals, and the heat pre-forming of the nano-points is also reduced. 2008. The calorific value of the nano-charge storage layer of the present invention is It can optimize the storage efficiency, storage time and memory window of non-volatile memory under the four factors of solving the problem of charge loss caused by leakage path. In addition, it can also reduce the equipment and thermal budget cost of non-volatile memory. The above-mentioned objects are only the preferred embodiments of the present invention, and the scope of the present invention is not limited to Φ%, that is, the patent application according to the present invention and the contents of the invention are The simple material effect changes and modifications are still within the scope of the patent of the present invention. [Simplified description of the drawings] One-one-two-one diagram is a schematic view of the present invention, which illustrates the charge storage layer of the nano-point of the present invention. Non-volatile memory - preferred embodiment; - one - retrospective topography, illustrating a specific example of a non-volatile memory having a charge storage layer of a nano-point; 3 疋 电容 电容 电容 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 闸 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 Storage layer 21·········Source 331 ••...··Nickel point 22.........汲3..........charge storage film 31......... tunneling Oxide layer 3 2.........blocking oxide layer 4 .........•gate 5 ........••protective film 6 ..........•contact Plug _ 14