TW200845232A - Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system - Google Patents

Abstract

The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to "implant" metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material.

Description

200845232 IX. Description of the Invention: [Technical Field of the Invention] Embodiments of the present invention generally relate to a method and apparatus for forming a high-k (dielectric constant) dielectric layer. In particular, embodiments of the present invention are directed to methods of forming a gate die electrical iayer. Prior to surgery, a cascading circuit is composed of millions of components, such as a transistor, an electric grid, and A resistor, such as a field effect transistor, generally includes a source, a gate and a gate stack structure. The gate stack structure generally includes a substrate (eg, a germanium substrate), a gate dielectric layer, and a gate electrode. (eg, polysilicon) The gate dielectric layer on the gate dielectric layer is composed of a dielectric material such as hafnium oxide (S丨〇2) or a high-k dielectric material having a dielectric constant greater than 4.0, such as nitrogen oxide.矽(Si〇N), yttrium nitride (siN), yttrium oxide (Hf〇2), lanthanum strontium hydride (Hfsi〇2), yttrium oxynitride (HfSiON), yttrium oxide (Zr02), zirconium silicate (ZrSi) 〇 2), barium titanate (BaSrTi〇3 or BST), lead zirconate titanate (Pb(ZrTi)〇3 or ρζτ), etc. It should be noted that the film stack structure may comprise a film layer composed of other materials. FIG. 1 is a cross-sectional view showing a field effect transistor (FET) 10 including a gate dielectric layer 14. As shown, the substrate 12 is provided. The pole dielectric layer 14 and the idle electrode 16. The sidewall spacers 18 are adjacent to the vertical sidewalls of the gate dielectric layer 14 and the gate electrode 16. The source/drain junction 13 is formed in substantially adjacent gate In the substrate 12 of the opposite vertical sidewalls of the electrode 16. With the size of the integrated circuit and the size of the transistor thereon, the gate drive current required to increase the speed of the 200845232 crystal is also increased. The drive current will follow the gate. Capacitance increases and increases 'and capacitance == kA/d, where k is the dielectric constant of the gate' d is the dielectric layer thickness 'A is the component area. Reduces the dielectric layer thickness and improves the gate dielectric layer The dielectric constant is a method of increasing the gate capacitance and the drive current.

The thickness of the Si 〇 2 gate dielectric layer has been attempted to fall below 20 angstroms (person). However, the use of a Si〇2 gate dielectric layer of less than 20 A has been found to have an adverse effect on the performance and durability of the gate. For example, a boron-doped gate electrode can pass through a thin Si〇2 gate dielectric layer to reach the underlying germanium substrate. And the thin dielectric layer increases the power consumed by the gate, thereby increasing the gate leakage current (ie, the tunneling current). The thin SiO2 gate dielectric layer is susceptible to cracking by the NM〇s hot carrier, where high-energy carriers that traverse the dielectric layer can damage or destroy the channel. The thin SiCh gate dielectric layer is also susceptible to PM〇s negative bias temperature instability (NBTI), where the threshold voltage or drive current drifts with gate operation. A method of forming a gate dielectric suitable for a gold oxide half field effect transistor (M〇SFET) includes nitriding a oxidized oxide film in a nitrogen-containing plasma. The increase in dielectric constant by increasing the net nitrogen content of the gate oxide layer is based on several reasons. For example, an oxide dielectric layer block may be slightly added with nitrogen during plasma nitridation to reduce the equivalent oxide thickness (E〇T) on the original oxide layer. Due to the pinch-through effect when operating the FET, the gate leakage current can be reduced compared to the un-nitrided oxide dielectric layer having the same EOT. At the same time, increasing the nitrogen content can also reduce the damage caused by the F-N through current of 200845232 if the thickness of the dielectric layer falls within the F〇wler-Nordheim (F-N) pass-through current during subsequent processing operations. Another benefit of increasing the net nitrogen content of the gate oxide layer is that the nitrided gate dielectric layer is more resistant to undercut problems, thereby reducing gate edge defects and reducing leakage current. . Issued in the US Patent No. 6,610,615 of August 26, 2003, and the patent name is "Plasma Nitridation For Reduced Leakage Gate Dielectric Layers" McFadden et al. compared the nitrogen distribution of the yttrium oxide film in the thermal nitridation process and the plasma nitridation process (see Figure 1B). The nitrided oxide layer is on the tantalum substrate. The iB diagram shows the distribution of nitrogen in the crystalline enthalpy below the oxide film. The nitrogen distribution curve 22 obtained by the thermal nitridation process shows: the first nitrogen concentration on the top surface of the oxide layer, the nitrogen concentration generally decreased with the deep oxide layer, the cumulative nitrogen concentration at the interface of the oxide layer/the layer, and finally The nitrogen concentration gradient is generally reduced as it goes deep into the substrate. On the contrary, the nitrogen distribution curve 24 obtained by the plasma nitridation process shows that the nitrogen concentration is substantially reduced one by one from the top surface of the oxide layer to the substrate through the oxide layer/ruthenium layer. Ion bombardment with nitrogen plasma does not produce an accumulation of nitrogen concentration at the improper interface formed by the thermal nitridation process. Furthermore, the nitrogen concentration in all depths of the substrate during the electrification nitrogenization process is lower than that of the thermal nitridation process. As previously mentioned, the advantage of increasing the nitrogen concentration at the gate/gate oxide interface reduces the diffusion of dopants (e.g., boron) from the polysilicon gate electrode to the gate oxide layer or through the gate oxide layer. This can reduce, for example, defects in the gate oxide layer due to boron diffusion (in_diffused) in the doped boron-polysilicon gate electrode, thereby improving the reliability of the device. Lowering the gate oxide/dream channel boundary. The nitrogen containing 4 H point system can reduce the fixed charge and lower the low 8 200845232 Interface morphology density. This improves channel mobility and transconductance. Therefore, the plasma nitridation process is superior to the thermal nitridation process. As semiconductor components become smaller and smaller, the size of the nitriding gate oxide oxide layer has reached its limit. However, when the thickness of the nitrided dolomite layer is further reduced (from 1 〇 A), the gate leakage has increased to the extent that the component cannot be applied. New gate dielectric materials and/or processes are required to meet the ever-decreasing component size requirements. The replacement of cerium oxide (si〇2) with high-k dielectric materials has faced several challenges. For example, a deposition method of a two-k dielectric material generally employs chemical vapor deposition (VD) or atomic layer deposition (Ald), which tends to cause a carbon-containing precursor material to be mixed with other contaminants into the deposited film layer. Carbon and other contaminants can deteriorate the dielectric properties of the gate dielectric layer. In addition, the interface properties of the CVD “ALD” film layer and the channel region are not as solid as the cerium oxide layer. Therefore, the art requires a method and apparatus for forming a gate dielectric layer, the gate dielectric layer of which is formed to have better dielectric properties and a smaller Εοτ. SUMMARY OF THE INVENTION The moon generally provides a method of forming a semiconductor device, comprising: forming a dielectric layer having an eight-thickness thickness on a surface of a substrate, and placing a content of the first material into the dielectric layer, a first concentration gradient of at least a portion of the thickness of the dielectric layer formed; 'a second amount of material is placed into the dielectric layer to form a second concentration gradient across the thickness of the dielectric layer formed by at least the octagonal knife; And depositing a third material to recognize the bamboo material on the dielectric layer. The embodiment of the present invention further provides a method of forming a semiconductor device, package 9

200845232 includes: forming a germanium-containing dielectric layer having a predetermined thickness on a surface of the substrate; forming a high-k dielectric layer of a predetermined thickness on the germanium-containing dielectric layer; and implanting a content of a material into the high-k dielectric layer to Forming a first concentration gradient across at least a portion of the thickness of the formed k dielectric layer, wherein the first material is selected from the group consisting of 铪, 镧, 绍, 钛, 录, 总, 错, 纪, and 锁a second material into the dielectric layer to form a second concentration gradient across the thickness of the at least partially formed high-k dielectric layer, wherein the second material is selected from the group consisting of Giving, 镧, Ming, Titanium, Wrong, Record, Wrong, Ji and 钡Forming a group; depositing a gate material on the high-k dielectric layer, the first material, and the second material. [Embodiment] The present invention generally provides a method and apparatus for forming a high quality dielectric layer on a substrate. Embodiments include a method in which a plasma processing process is employed instead of a standard nitridation process to form a dielectric constant layer on a substrate. Embodiments further include apparatus for "implanting" lower energy gold to reduce ion bombardment damage to the gate dielectric layer (eg, dioxide) and to avoid metal atoms from bonding to the underlying germanium. For forming semiconductor components, such as logic or memory devices. Methods for fabricating high dielectric constant transistor gates Today's component processes are difficult to fabricate gates with an equivalent oxidation (EOT) of 5-1 0A and low leakage current. Dielectric layer. The EOT of 10-1 6 people currently used in the 65 nanometer 90 nanometer crystal node is the first high freedom to use plasma; the group electrode of the set system is south. Is a separation layer) Example layer thick rice to nitride 10 200845232 process. However, when the nitrided erbium gate dielectric layer becomes thinner (e.g., 10A), gate leakage may increase to such an extent that it cannot be used for components. In order to solve the gate leakage problem of a thin dielectric layer, the following processes can be utilized to form, for example, hafnium (Hf), hafnium (La), aluminum (Al), titanium (Ti), hammer (Zr), iron (Sr). A high-k dielectric oxide or a cerium material deposition process of erbium (Pb), yttrium (Y), or yttrium (Ba) is used instead of the plasma nitridation process. SUMMARY OF THE INVENTION The present invention comprises a method of fabricating a gate dielectric layer of a field effect transistor for use in a logic type application in which the gate dielectric layer is an equivalent (electrical) oxide layer thickness (E〇T) of about 5-io. The present invention also encompasses a method of fabricating a gate dielectric layer of a field effect transistor for use in a memory type application in which the gate dielectric layer is equivalent to an equivalent (electrical) oxide thickness (EOT) of about 1 〇 3 〇 . This process can be used to fabricate integrated semiconductor components and circuits. The method and apparatus for layering solve the problem of the common interpolar performance seen in the 45 nm process and the smaller MOS type components. A novel process has been developed to reduce and/or eliminate the lack of P曰' such as Fermi level. Termi-level pinning or critical electricity. In general, the process includes forming a high-k dielectric layer followed by termination of the deposited high-k material surface to form a good interface between the gate electrode and the high-k dielectric material. Embodiments of the present invention also provide a cluster tool 'for forming a high-k dielectric material, terminating a surface of a high-k dielectric material, performing one or more post-processing steps, and forming a polysilicon and/or a metal gate Floor. 2A is a diagram showing a processing procedure 25 1 of an embodiment of the present invention including a step 11 200845232 for serially fabricating a gate dielectric layer of a field effect transistor in accordance with an embodiment of the present invention. The processing program 251 generally includes a processing step performed on the substrate to form a gate structure of an MOS type element example. The region of the substrate 401 shown in FIGS. 3A-3F is a gate oxide layer and a gate formed by the processing procedure 251 of FIG. 2A. Figures 3A-3F are not drawn to scale and the illustration has been simplified. At least a portion of the process 251 can be performed using a processing reactor of the integrated semiconductor substrate processing system (i.e., a cluster tool) (as shown in Figure 7). The process 251 begins in step 252 and proceeds to step 268. Step 252 is to provide a bismuth (Si) substrate 401 (eg, a 200 mil wafer, a 300 mm semiconductor wafer) exposed to the cleaning solution to remove the native oxide layer 401A of the substrate surface (eg, two Cerium oxide (Si02)) (Fig. 3A). In one embodiment, the removal of the native oxide layer 4〇1A is a cleaning solution using hydrogen fluoride (HF) and deionized (DI) water. In one embodiment, the cleaning fluid is maintained at a temperature of from about 20 ° to about 30. (: an aqueous solution containing about 1-1% by weight of 1:1. In one embodiment, the cleaning solution contains about 5% HF in 5% and is maintained at about 25 ° C. In 252, the substrate 401 can be immersed in a cleaning solution and then washed with deionized water. Step 252 can be performed in a single substrate processing chamber or a plurality of batch type substrate processing chambers, which can include ultrasonic energy during processing. Alternatively, step 252 can be performed in a single substrate wet cleaning reaction chamber in integrated processing system 6 (Fig. 7). In another embodiment, the native oxide layer 401A can be removed using RCA cleaning. After step 252 is completed, the substrate 401 is placed into a vacuum-loaded lock chamber or a nitrogen-free (no ring or step 252 can be applied to the integrated processing system 6 (Fig. 7) 12 200845232. In step 254, a thermal oxide layer (Si〇2) 402 is formed on the surface 401B of the cleaned substrate 401 (Fig. 3B). The thickness of the thermal oxide layer 402 is generally from about 3 angstroms to about 35 angstroms. For example, the logic type application has a thermal oxide layer 4 〇 2 having a thickness of about 6 angstroms to about 15 angstroms; For example, the thickness of the thermal oxide layer 402 is from about 15 angstroms to about 4 angstroms. Embodiments of the invention may also be applied to the thermal oxide layer 402 having a thickness greater than 35 angstroms. The thermal oxidation step 254 may form a sulphur dioxide eve. The (Si〇2) sublayer (sUb-layer) is on the interface of the Shixi dielectric layer. Step 254 can improve the dielectric material on the deposited dielectric layer (such as the high-k dielectric layer 404 of FIG. 3D)/ The quality and reliability of the interface can also improve the mobility of the charge carriers in the channel region below the surface 401B. Step 254 can be performed on a rapid thermal processing (RTP) reactor, which is located in the substrate of the integrated processing system. One of the processing chambers 614 A-614F (Fig. 7). A suitable RTP chamber is the RTP chamber available under the trade name RADIANCE® from Applied Materials, Inc. of Santa Clara, California. In one embodiment, the 6A cerium oxide (SiO 2 ) layer is formed on the substrate 401 by a process of 18 seconds, 75 0 ° C, 2 Torr, and an oxygen (〇 2) flow rate of 2 slm. Surface 40 1B. In this embodiment, oxygen is the opposite of the injection of the thermal oxide layer 402 into the processing chamber. Gas should be; in some cases 'inert carrier gas can be added to the processing chamber to achieve a predetermined chamber pressure. Or in some cases, step 254 can use a reactive gas such as nitric oxide (NO), nitrous oxide ( N20), or a mixed reaction gas such as hydrogen (Ha) / oxygen (〇 2), and nitrous oxide (Ν 2 〇) / hydrogen (η 2). In step 257, the thermal oxide layer 402 is exposed to metal ions. 13 200845232 A plasma for doping a predetermined layer of light into a hot rolled layer to form a high-k dielectric layer 403. Step 257 is formed by 忐 + ^ , and the k-transist layer 403 may be a doped layer of erbium (Hf), steel (La) or the like. In an embodiment, the low energy deposition process is performed in a processing chamber similar to that described in reference to FIG. 4A-4C, which is illustrated in FIG. 4F. In the embodiment, the dopant material is transported to the thermal oxide layer 402. The rf energy of region 522 is processed to produce a plasma, followed by a cathode bias to the target (eg, component symbol 5〇5 of Figure 4A).

Ci or element symbol 571) of Figure 4B to sputter material from it. In one aspect, it is also desirable to RF bias, Dc bias, or ground the substrate support 562 to implant the sputtered and ionized material within a predetermined depth of the thermal oxide layer 4〇2. In another aspect, it is also desirable to electrically, float the substrate support 562' and create a self-biasing to cause the substrate support 562 to be generated relative to the plasma. The voltage is low voltage to reduce the energy of the ionized material striking the thermal oxide layer 402. Various methods of transferring the low energy material to dope the thermal oxide layer 402 will be described below with reference to Figures 4a-4F and 5A-5C. Careful control of chamber pressure, rF power, pulsed DC power, bias applied to the substrate support 562, and/or processing time can control the doping amount and concentration corresponding to the dopant material in the thermal oxide layer 402. The relationship of depth. In one embodiment, the plasma may comprise argon ions and metal ions such as ruthenium, osmium, aluminum, titanium, zirconium, hafnium, lead, bismuth and antimony, and may also comprise one or more selective inert gases. Typical inert gases may include helium (Ne), helium (He), gas (Kr), gas (Xe), gas (N2), etc. In one embodiment, the thermal oxide layer 402 is doped with 5-30 atomic % of the (Hf). It is generally desirable to reduce the dopant concentration of the thermal oxide layer 402 to a concentration of 14 2008452. 32 The interface between the thermal oxide layer 402 and the surface of the germanium channel (e.g., surface 4〇1B) or at least a few angstroms is reduced to near zero. In one embodiment, when an inductively coupled type of processing chamber is used (Fig. 4A) When the component symbol 500) is used, a process of 180 seconds and a chamber pressure of 10 Torr (for example, mainly argon) is used to place 铪 (Hf) having an average concentration of 10 atomic % into the thermal oxide layer 402. Inside, this process applies -l5〇VDC to the target (component symbol 5〇5) and uses a 5% duty cycle and, floating, pedestal, at a frequency of 13 MHz 50 watts (W) of power to deliver rf energy to the coil (component symbol 5 〇 9). In another embodiment, when using a fabrication configuration similar to the 4G diagram, it uses 80 ^ and 丽丽A process of 10 mTorr (for example, mainly argon) is used to place yttrium (Hf) having an average/density of 7 atom% into the thermal oxide layer 4〇2, and the process applies an average of about 〇^r ϋ 0 watts. RF power (ie about 5% energy cycle with a maximum RF power of about 2000 watts) to the ring target 5〇5, and use, floating, pedestal, 13 to M The frequency of Hz is applied to an average of about 10 watts of RF power (i.e., about 5% of energy < this rate period and a maximum rf power of about 2 watts) to coil 509. In the case of the phonogram, in order to avoid the destruction of the thermal oxide layer 402 when the step 257 is avoided, the RF power is maintained to be less than about 1000 watts. In another embodiment, the average RF power used to enter γ^9Λλ 仃ν 257 is less than about 200 watts. In another example, in the example, the power of the phrase used in step 2 5 7 is less than about 5 〇 ¥ 低 Θ υ 。. In one embodiment, step 257 is performed on a low-frequency plasma treatment of a person (such as a process chamber 500 or a process chamber 501) located in one of the substrate processing chambers 614A-614F of the integrated processing system. (di brother / figure). In one embodiment, as shown in the second and third 3D drawings, step 15 200845232 256 is used to perform a metal organic chemical vapor deposition (m〇CVd) process, an atomic layer deposition (ALD) process, or the like. A deposition process is performed to deposit a high-k dielectric layer 404 to the surface 4〇1B of the substrate 401 instead of performing steps 254 and 257 to form a high-k dielectric layer 403 ^ high-k dielectric layer from the thermal oxide layer 402.

404 may comprise oxidized (Zr〇2), cerium oxide (HfA10x), cerium lanthanum oxylate (HfxSii x〇y), cerium oxide (Lh〇3), and/or Alumina (Ah〇3), but not limited to this. Step 256 can be applied to an atomic layer deposition system, such as the Centura ALD High-K system obtained from Applied Materials. The ALD reactor can also be integrated. One of the substrate processing chambers 614A-614F of system 600 (Fig. 7). In step 259, the surface of high-k dielectric layer 403 or high-k dielectric layer 404 is terminated using a plasma deposition process to The termination region 〇5 is formed. The termination region 405 is formed by depositing a material layer and/or a region doped with the two-k dielectric layer 403 or the high-k dielectric layer 404. The addition of a passive material (such as yttrium oxide ( The termination region 405 of La2〇3) or Oxide (Al2〇3) is believed to be a passive state of the surface and a common Fermi level pinning or critical voltage drift problem common to the high-k layer of conventional ALD or MoCVD. In one embodiment, the high-k dielectric layer 403 or the high-k dielectric layer 404 is doped with about 0.1-10 atomic percent of lanthanum (La) and/or about 0.1-10 atoms. Aluminum (A1). In another embodiment, the high-k dielectric layer 403 or the high-k dielectric layer 404 is doped with about 0.25-5 at% of lanthanum (La) and/or about 1-10 atoms/❶. Aluminum (A1). It is desirable to reduce the dopant concentration of the high-k dielectric layer 403 or the high-k dielectric layer 404 such that the concentration extends only to a depth of several angstroms of the high-k dielectric layer 403 or the high-k dielectric layer 404. In the embodiment, the lanthanum (La) dopant is driven into the 16 200845232 high-k dielectric layer 4 〇 3 n using the processing chamber of the following 4A-4C. In one embodiment, i2 〇 second and chamber 1 采用 are employed. A process of millitorr (for example, mainly argon) is used to drive lanthanum (La) having an average concentration of hafnium into a 胄k dielectric layer doped with 1 〇 atomic percent, and the process applies -loo vdc to镧 target (such as element 505 of Figure 4A) and use 5% of the energy cycle and, floating, the pedestal delivers RF energy to the coil at a frequency of 13 56 -4 and 5 watts (eg 4A) Element symbol 509). In an embodiment, step 259 can be performed in a processing chamber similar to the 4A_4c processing chamber 500 or processing chamber 501. In this configuration, the final domain 405 is formed by employing a low energy similar to the above step 257. system In one aspect, transporting the dopant material to the upper region of the high-k dielectric layer 4〇3 is accomplished by using the rf energy delivered to the processing region 522 to form a cathode bias to the target 5〇5, From its sorbent material, the substrate support # 562 can be RF biased, Dc biased, grounded, and the sputtered and ionized material is implanted into the high-k dielectric layer 4〇3. The method of doping the high-k dielectric layer 4〇3 will be described below with reference to Figures 4A-4F and 5A-5C. By carefully controlling the chamber pressure power, the pulsed DC bias, the random bias applied to the substrate support 562, and/or the processing time, the doping amount and concentration can be controlled to correspond to the depth of the dopant material k dielectric layer 403. relationship. In one embodiment, the aluminum material, the cerium-containing material, or other similar material is doped. In one embodiment, step 259 can be performed in the processing chamber 5(R), in the substrate processing chamber 614a-6i4f of the integrated processing system 600 (Fig. 7). In one aspect, the processing chamber pressure used to perform step 259 is the most produced material of the .5 original 403 symbol MHz map, or the various photo, RF, and high One of its bits, 500 17 200845232, is different from the processing chamber used to perform step 257. In another embodiment, the single processing chamber 5 of the slave integrated processing system 600 is used to perform steps 257 and 259, but each step uses a different target that is placed in the processing region 522 of the processing chamber 500. . According to another embodiment of step 259, a mirror process is deposited into the high-k dielectric layer 403. The sputtering process is performed in a similar manner to the first example, and the termination region 405 is an additional material layer utilizing the splashed surface. In the processing room of the 4A-4C diagram, 50〇 or Ο

Ci chamber 5 (H's processing chamber. In this configuration, the termination region is formed by using the RF energy delivered to the processing region 522 to generate a plasma and then forming a cathode bias to the target 505 from The material is deplated to deposit a target onto the high-k dielectric layer 403. The substrate support 562 can be rf biased, grounded, or electrically placed to control implantation of the high-k dielectric layer 4〇3. The energy and depth of the sputtered and ionized material. In one embodiment, the deposited layer contains chains (A1), lanthanum (La), or other suitable materials. In a solid yoke example, the selective step 260 employs oxygen. The rf plasma oxidizes the exposed material and converts it into a dielectric material. In one embodiment, the high-k dielectric layer 403, the high-k dielectric layer 4〇4, and/or the termination region 4〇5 are exposed In an oxygen-containing plasma, to form alumina or yttria. In another embodiment, the nitrogen-containing (NO plasma may also contain one or more oxidizing gases, oxygen (〇2), nitric oxide (No) Nitrous oxide (N2〇). The plasma may also be G 3 one or more selective inert gases such as argon (Ar) and helium (ίί ^ \ 〇| V. Step 260 can be performed, for example, on a decoupled plasma nitriding (DPN) plasma reactor of integrated processing system 6 (Fig. 7). In one embodiment, the thermal oxidation step is replaced by a plasma oxidation step to oxidize. The exposed material is converted to a dielectric material of 18 200845232. In one embodiment, the plasma oxidation step uses a 5% energy cycle with a maximum RF power of 1000 watts (ie, an average power of 50 watts) at 13.56. The frequency of MHz is applied for 30 seconds and the exposed material is oxidized with a flow rate of about 1 〇〇seem of nitrogen and a flow rate of about 1 〇〇sccm of oxygen. In another embodiment, the optional step 262 is used instead of step 260. In step 262, the high-k dielectric layer 403 or the high dielectric layer 404, and the substrate 401 are annealed at about 600 ° C to about 11 ° C. Annealing is performed at a lower temperature (eg, The annealing temperature is from about 6 ° C to about 800. The ruthenium helps to prevent crystallization from occurring prior to deposition of the material, such as bismuth (Si), oxygen (〇2), or both. Step 262 can be performed as appropriate. Thermal annealing chamber, such as the RADIANCE® reactor or RTP XE + integrated processing system 600 The reactor, or a single substrate or batch of furnace tubes. Step 262 may form a niobic sublayer in the high-k dielectric layer 403 or termination region 405. In an embodiment, step 262 may be at least about 2_5 〇〇〇. Sccm oxygen (02) and about one 〇〇-5000 sccm of nitric oxide (NO) are carried out, or selectively mixed with nitrogen (N2)' and the substrate surface temperature is maintained from about 600 ° C to about 110 ( TC, process chamber pressure is about 0. 1-50 Torr. This process can be carried out for about 5-18 seconds. In one embodiment, step 262 is 15 seconds, 900. (:, i-Torr process, which uses oxygen (02) with a jaw speed of about 60 scem and nitrogen (>h) with a flow rate of about 940 seem. In another embodiment, the supply of oxygen (〇2) is About 2 〇〇 sec (for example, oxidized milk is about 2 〇〇 mT), nitrogen is about, and the chamber pressure is about 1 Torr at about C0 C for about 15 seconds. In the examples, NO is about 5 〇〇 scem, and the chamber pressure is maintained at about 5,000 Å for about 15 seconds at a substrate temperature of about (10). 19 200845232 In an embodiment, step 260 Or step 262 is performed after step 256, step 257 or step 259. According to an embodiment of the program 251, an oxidation step similar to step 260 or step 262 can be performed between step & step 259 t to terminate region 405 Deposition onto the high-k dielectric layer 4〇3, again oxidizing the dopant material deposited in step 257. At V 264 +, termination region 405 and high-k dielectric layer 403 or high-k dielectric layer 404 are nitrogen Slurry treatment to increase the nitrogen content of these areas. This process can use a DpN reactor and provides a base of about 20-500 C of nitrogen (N2) of about 1 〇 2 〇〇〇 sccm. Temperature, and chamber pressure of about 5-2 Torr. Radio frequency (RF) plasma, for example, at 13.56 ΜΗζ or 6 〇 MHz, and up to about 3-5 watts (kW) of continuous wave (cw) Or pulse plasma power supply to supply energy. When generating pulses, the maximum RF power, frequency and energy cycle period is generally about 10-3000 watts, about 10 kHz and about 2% _100%. This process can be carried out for about 1 second. About 180 seconds. In one embodiment, the supply of nitrogen (N2) is about 200 sccm, and the maximum rf power of about 1 watt is about 10 kHz and about 5% of the energy applied to the inductive plasma source. The cycle, a temperature of about 2 5 C [), and a pressure of about 1 〇-80 Torr are used to generate pulses for a period of about 15 seconds to about 180 seconds. The plasma can be generated using a quasi-remote source, an inductive plasma source, a radial Hne slotted antenna (RLSA) source, or other plasma source. In another embodiment, a CW and/or pulsed microwave power source can be used to form regions of high nitrogen content. In step 266, the substrate 401 can be annealed to reduce leakage current between the layers on the substrate 401 and to enhance mobility of the charge carriers in the channel region below the surface 4〇1B and to improve reliability of the formed components. Step 266 20 200845232 helps to reduce the number of defects in the film layer formed on the substrate 401. The nitride layer formed by the 'annealing or passivation step 264 in step 266 is believed to help promote the formation of an effective barrier layer to block the diffusion of boron from the boron-doped polysilicon gate electrode. Step 266 can be performed in a suitable thermal annealing chamber, such as a RADIANCE® reactor or RTP XE+ reactor integrated with processing system 600, or a single substrate or batch furnace tube. In one embodiment, the annealing process of step 2 66 can employ at least one of oxygen (〇2) having a flow rate of about 2 to 5000 seem and one of oxygen gas (NO) having a flow rate of about 100 to 5000 seem, or selectivity. Nitrogen gas (N2) was mixed, and the substrate surface temperature was maintained at about 800 ° C to about 1100 ° C, and the process chamber pressure was about oi^o. This process can be performed for about 5-180 seconds. In one embodiment, the oxygen (〇2) supply is about 500 seem, and the chamber pressure is maintained at about 1 Torr for about 15 seconds. In one embodiment, step 266 uses a process recipe similar to step 262 above. Once steps 260, 262, 264, or 266 are completed, step 268 is performed to deposit one or more layers of the film onto the formed film layer to form the gate region or gate electrode of the m〇s device. According to one embodiment of step 268, a polycrystalline layer is deposited into the gate region above the film layer to provide a gate electrode. In one embodiment, the deposition of the polycrystalline germanium layer is a conventional polycrystalline germanium deposition process. In one embodiment, a polysilicon deposition chamber (not shown) is part of the integrated processing system 600. In one embodiment, the polysilicon is deposited over the film layer formed by the process 251 using an evD or ALD reactor, such as the Centura CVD reactor available from Applied Materials, which includes the substrate of the integrated processing system 600. 21 of the processing chamber 61 4A-61 4F 2008 200823 1 (Fig. 7). According to another embodiment of step 268, as shown in FIG. 3F, the gate region 408 includes a plurality of conductor layers, such as a thin metal layer 4?7 and a polycrystalline layer 406. In one embodiment, the gate region 408 includes a thin metal layer 407 deposited on the film layer formed by the process 251 to provide a gate material having a higher carrier concentration than conventional polycrystalline slab gate materials. The thin metal layer 407 has a thickness of about 5 - 2 0 0 A, preferably less than about 30 A. In one embodiment, the thin metal layer 407 comprises a metal such as a button (Ta), tantalum nitride (TaN), a carbonized button (TaC), a nitride barrier (TaCN), a town (W), and a tungsten nitride (WN). ), nitride layer (TaSiN), hafnium (Hf), aluminum (A1), platinum (Pt), ruthenium (ru), cobalt (c〇), titanium (Ti), nickel (Ni), aluminum nitride titanium (TiAIN), tantalum nitride (ruN), nitrided iron (HfN), nickel (NiSi), titanium nitride (TiN), or other suitable materials. The formation of the thin metal layer 407 is preferably by using a processing chamber 500 (Fig. 4A) or a processing chamber 501 (Fig. 4B-4C), which is dependent on the integrated processing system 6 (Fig. 7). In this configuration, the 'thin metal layer 407 is formed by depositing dry material onto the film layer formed by the process 251, which uses RF energy to generate electricity and bias the target to sputter metal therefrom, followed by The substrate support 562 (Fig. 4A-4B) is selectively biased to deposit a sputtered and ionized metal material onto the previously formed film layer. The use of RF energy to drive the sputter deposition process allows a small amount of material to be reliably deposited on the surface of the substrate. Conversely, the sputtering (DC) voltage required to form a thin metal layer by reducing the deposition rate to a certain low level is usually unable to sustain the slag plasma. Therefore, traditional physical vapor deposition or mining techniques are strictly limited by It does have the ability to deposit small amounts of material. In other embodiments, the thin metal layer 407 can be formed by a conventional cvd, 22 200845232 PECVD or ALD process. FIG. 2B illustrates another embodiment of the processing program 251. The process 25 1 of Fig. 2B is the same as the step described in Fig. 2A except that at least one of the two selective steps 258A and/or step 258B is added to step 257 or between step 256 and step 259. In one embodiment, the plasma nitriding system is added to the processing program 251 for nitriding one of the high-k dielectric layer 403 or the high-k dielectric layer 404 formed by one of the steps 254, 256 or 257. Bite a variety of materials. In one embodiment, it is desirable to form a tantalum nitride-containing film layer using a plasma nitridation process to prevent the germanium material in the high-k dielectric layer 403 or the high-k dielectric layer 4〇4 from undergoing subsequent annealing steps (eg, Crystallization in step 25 8B, 262 or 266). In one embodiment, step 258A is the process described in step 264. In one embodiment, a selective thermal annealing step (step 2 5 8 B) is added to the processing sequence 251 to reduce defects and stresses in the formed high-k dielectric layer 403 or high-k dielectric layer 404, This further improves the reliability of the formed components. In one embodiment, step 25 8B is the process described in step 262 and/or step 264. In one embodiment, step 25 8B is performed after completion of step 258 A above. In one embodiment, step 2 5 8 B is a 15 second, 900 C, 1 Torr process using a flow rate of about 60 seem of oxygen (〇2) and a flow rate of about 940 seem of nitrogen (N2). FIG. 2C illustrates still another embodiment of the processing program 251. The processing program 251 of Fig. 2C is the same as the step described in Fig. 2A except that step 253 is added between step 252 and step 254, and step 256 is performed after step 254 is completed. In this embodiment, the plasma nitridation step (step 253) is followed by the removal of the native oxide layer step 252 of the process 251 or 256 to nitride the substrate surface prior to performing step 254 or 256. The nitrided tantalum substrate surface is believed to contribute to the formation of the desired silicon oxynitride (SiON) layer which remains on or near the surface of the tantalum oxide layer formed by the subsequent thermal oxidation step (step 254). * Forming a SiON layer on or near the surface of the dioxide layer helps to reduce the diffusion of the gate electrode material (step 268) into the gate dielectric layer during successive processing steps. The sequence of steps 256 and 254 in this embodiment is modified to form a niobium oxynitride (SiON) interface layer prior to the deposition of the high-k dielectric layer step 256. This will help improve the high-k dielectric layer and components. The interface properties of the channel area. Step 253 can be performed on a DPN reactor available from Applied Materials, Inc. of Santa Clara, California. In one embodiment, step 253 is a 1 second, 70 Torr process that uses an average power of 25 watts (5% energy cycle with a maximum rf power of 500 watts), 200 seem nitrogen gas flow, and about 25 The substrate temperature of °C. And in accordance with the embodiment of process 251, step 254 is modified to ensure that the nitrided _ surface obtained in step 253 retains the predetermined properties. In this case, it is also desirable to inject other reactive gases (e.g., nitrogen (NO) and oxygen into the processing chamber) during step 254 to ensure the formation of a high quality dielectric layer. In one embodiment, nitrogen oxides The ON (Si ON) layer is formed on the surface 4 〇 1b by a process of 3 〇, 〇 50 ° C, 5 Torr (ie, a partial pressure of oxygen of about 15 mT) using oxygen having a flow rate of about 15 seem. (o. with a flow rate of about 5 slm of nitrogen (N2), followed by a flow rate adjustment of 0.5 slm of oxygen (〇2) and about 4.5 slm of nitrogen (N2) for a period of 15 seconds. Figure 2D shows the processing procedure 251 Still another embodiment. The 24 200845232 processing program 25 1 of FIG. 2D is the same as the step described in FIG. 2A except that the second selective step 255A or the step 255B is added between the steps 254 and 257. In an embodiment The selective plasma nitridation step (step 255A) is added between step 2 54 and step 257 to nitride the upper surface of the thermal oxide layer formed in step 254 to form an SiON layer. The SiON layer can be used as a diffusion barrier layer. Used to prevent the gate electrode material from diffusing to the gate dielectric layer. In an embodiment, step 255A 30 seconds, 1 Torr milliohm process, using an average RF power of 5 watts (5% energy cycle and 1 watt maximum power), 2 〇〇seem nitrogen (N2) and about 25° The substrate temperature of C. Referring to FIG. 2D, in an embodiment, a selective thermal annealing step (step 255B) is added to the processing program 251 to reduce defects and stresses in the formed high-k dielectric layer 403. Thereby improving the reliability of forming the component. In an embodiment, the annealing treatment step 25 5B may employ at least one of oxygen (〇2) having a flow rate of about 15 seem and nitrogen (n2) of about 500 sccm, and maintaining the substrate. The surface temperature is about 1 〇 5 〇 ° c, and the process chamber pressure is about j _ 5 Torr. In another embodiment, step 255B is the process described in step 262 and/or step 266. In one embodiment Step 255B is performed after the completion of the above step 255A. Fig. 2E illustrates another embodiment of the processing program 251. The processing program 251 of Fig. 2E is the same as the step described in Fig. 2A except that step 254 is removed, and Step 252 is modified to wet cleaning step 252A to form an yttria-containing interface layer. In an embodiment, the new step 252A utilizes a wet cleaning process to clean and intentionally form an oxide layer on the substrate surface 401B. The new step 252A can be performed on EmerSi(R) from Applied Materials, Inc., Santa Clara, Calif. nTM reactor. Forming an oxide layer of 4-5 angstroms in a κ (7) history 'Step 252A, the method comprises: immersing the substrate in a μ & eight diluted hydrofluoric acid (HF) bath for 8 minutes, followed by washing the substrate and the substrate Still 'eight-times maintained at 50 °C in the first standard cleaning (SC1) bath (for example less than 5 vol.% of the hydroxide record (nh4〇h) / less than 3V0.% of the ruthenium peroxide (仏^ / measured go 6 minutes in ionized water, then washed in a megasonic starter tank (ie 15 watts) containing deionized water

The substrate is for a while. In another embodiment, the oxide layer is formed by a wet cleaning process using a cleaning solution containing ozone (〇3). FIG. 2F illustrates still another embodiment of the processing program 251. The processing program 251 of Fig. 2F is the same as the step described in Fig. 2A except that step 256 is performed after completion of step 254. In this embodiment, the sequence of steps 256 and 254 is modified to form a thin layer of germanium dioxide (Si 2 ) (e.g., less than 10 people) prior to the deposition of the high-k dielectric layer step 256. In one embodiment, the thin high-k dielectric layer 404 is deposited on the thermal oxide layer 402 grown in step 254 using an ALD type deposition process. The reason why this structure is useful is that the thin layer of ruthenium dioxide formed in step 254 provides good dielectric layer/channel region interface properties at the junction of the dielectric layer and the component channel region, while providing the desired intervening of the completed stack structure. Electrical properties. The design of the hardware device can be as described above, and the method of forming the high-k dielectric layer is desirably using a plasma process in conjunction with steps 257 and 259 above. A plasma processing process using a high plasma potential (e.g., tens of volts) may damage the thin gate dielectric layer and even bond the bombarded metal atoms to the channel region 26 200845232 domain below the formed MOS device. Destruction of a dielectric layer (such as a ruthenium dioxide layer) or the incorporation of metal atoms into the underlying regions is undesirable because it reduces component performance and increases leakage current. The various embodiments described below can utilize a plasma processing process to actually form a gate dielectric layer. Examples of equipment that can be used to perform such a metal plasma processing process will be described below in conjunction with Figures 4A-4C and 4F. Inductively Coupled Plasma Treatment 窒 Figure 4A illustrates a cross section of one embodiment of a plasma processing chamber 500 that can be used to perform step 257 and/or step 259 above. In this configuration, process chamber 500 is an inductively coupled plasma processing chamber that can process substrate 502, such as substrate 401 (Fig. 3A), in processing region 522. In one embodiment, process chamber 500 is a modified decoupled plasma nitriding (DPN) chamber available from Applied Materials, Inc. of Santa Clara, Calif., and using an inductively coupled RF source. Processing chamber 500 generally includes an inductive rf source assembly 591, a DC source assembly 592, a target 505, a system controller 602, a process chamber assembly 593, and a substrate support assembly 594. The process chamber assembly 593 generally includes an assembly that can form a vacuum in the processing region 522, allowing the plasma process to proceed there. The process chamber assembly 593 generally includes a chamber bottom 527, a chamber wall 528, and a chamber cover 529 that sealingly surrounds the treatment region 522. The treatment zone 522 can be evacuated to a predetermined vacuum pressure using a vacuum pump 510 that connects the treatment zone 522 via the chamber bottom 527 and/or the chamber wall 528. In general, chamber wall 528 and chamber bottom 527 may be constructed of metal, such as aluminum or other suitable material. In one embodiment, the chamber wall 528 has a removable chamber shield (not shown) to prevent the sputter material from the target 27 200845232 target 505 from falling onto the chamber wall 528. The inductive RF source assembly 591 typically includes an RF generator 508 and an RF matcher 508 A that is coupled to a coil 509 adjacent the chamber cover 5 29 . In one embodiment, RF generator 508 can operate from about 0 to 3000 watts at a frequency of from about 400 kHz to about 20 MHz. In one embodiment, the RF generator 508 operates at a frequency of 13.56 。. The chamber cover 529 is typically a dielectric component (e.g., quartz, ceramic material) for causing RF energy of the inductive RF source assembly 590 to form a plasma in the processing region 522. In one embodiment, the coil 509 is located adjacent the target 505 such that when sputtering is performed, the plasma generated in the processing region 522 will be formed adjacent the active surface of the target. Controlling the plasma near the activated surface helps control the plasma density near the target area where the low energy sputter deposition process is sputtered. Since the plasma is generated by the coil 509, this configuration also facilitates the reduction of improper plasma bombardment of the ultra-thin gate dielectric layer. In one embodiment, the chamber cover 529 is modified such that the vacuum-sealed electrical feed-through 504 contacts the target 505 located in the processing region 522. In this configuration, the coaxial cable 506 is connected to the vacuum-sealed electrical feed port 504 to deliver energy from the DC power supply 507, causing ions generated by the plasma to sputter the target 505 material onto the substrate 502. In one aspect, the system controller 602 described below in conjunction with Figures 5A-5C is used to synchronize the output of the RF generator 508 with the DC power delivered from the DC source assembly 592. In an embodiment, the target 505 may be composed of a single material or alloy selected from the group consisting of hafnium (Hf), lanthanum (La), aluminum (Al), titanium (Ti), zirconium (Zr), yttrium ( A group consisting of Sr), lead (Pb), yttrium (Y)' or yttrium (Ba). 28 200845232 In one aspect, the process chamber assembly 593 further includes a gas delivery system 550 for delivering one or more process gases to the chamber bottom 527, the chamber walls, and to the processing region 522 formed by the cover 529. The pressure of the treatment zone 522 can be controlled by the system controller 602, which is used to adjust the flow rate of the gas delivered by the gas delivery system 55 and the suction speed of the vacuum pump 51, while the pump 51 is regulated by the throttle valve 511. . In one aspect, the chamber pressure of the process is from about 5 Torr to about 1 Torr. The substrate support assembly 594 generally includes a substrate support 562 that includes a substrate support member 562a. The substrate support member 562A may be a conventional electrostatic chuck that actively holds the processing substrate, or simply a substrate support. The temperature controller 5 6 ^ is generally used to heat and/or cool the substrate support member 562A to a predetermined temperature, which is set by a conventional means by the temperature controller 561, such as embedding an impedance heating element or coupling to A fluid cooling passage of a heat exchanger (not shown). In one aspect, the temperature controller 561 is adapted to operate and heat the substrate 5〇2 placed on the substrate support member 562A to a temperature of from about 2 Torr to about 800 °C. As the process progresses, the substrate support 562 can be coupled to the rf generator 523 such that an RF bias can be applied to a portion of the substrate support to drag plasma ions generated in the processing region 522 to the substrate 5〇. 2 the surface. In one embodiment, the substrate support member 562A is grounded, DC biased, or electrically floated during the plasma process to reduce ion bombardment to destroy the substrate 502. Transferring the RF energy of the RF generator 508 to the processing region 522 will ionize the gas atoms in the processing region. The ionized ionized gas atoms are then attracted by the DC source component 592 applied to the cathode bias of the target 5〇5. 200845232 is directed to the target 505' whereby the material can be sputtered from the target 5〇5 and dropped On the surface of the substrate 502. In order to reduce the interference between the energy delivered by the inductive rf source component 591 and the DC bias applied by the DC source group & 592, the energy delivered from the DC source component 592 and the RF source component 591 is typically synchronized. In order to minimize mutual interference, and at the same time maximize deposition rate, film uniformity and film quality. By generating and maintaining a low electron temperature and a low ion 爿b plasma to generate an induced RF source pulse to excite the plasma, the problem of ruthenium plasma potential destroying the surface of the substrate can be alleviated. In general, pulsed RF induced plasma produces ions of low ion energy (e.g., less than 1 angstrom electron volt (eV)) and therefore does not destroy the substrate located within the plasma. This is more fully described in U.S. Patent No. 6,831, 〇 21, and the filing date is June 12, 003, which is incorporated herein by reference. Theoretical calculations (see Figure 4D) allude to the low ion energy of most inert gases such as argon (Ar) 'helium (Ne), helium (He), helium (Kr) or helium (Xe). Sufficient energy from the pulsed RF source will not be available to sputter the target atoms, where the target composition is hafnium (Hf), lanthanum (La), or other heavy metals or I] dielectric materials. For example, with argon plasma as an example, the critical energy of sputtering for Hf and La targets is 42.3 eV and 25.5 eV, respectively, and the safe ion energy of ion implantation gate oxide is usually less than 1 〇eV. Thus, in the case of RF induced electropolymerization, the ion energy that is low enough to form the gate dielectric layer is not sufficient to sputter the desired metal ions from the target. Therefore, the DC source component 592 is required to apply the D C bias to the stem to perform the splash process. Various aspects of the pulse deposition process will be described below in conjunction with Figures 5A-5C. 30 200845232 Capacitively Coupled Plasma Processing Chamber Section 4B-4C illustrates a cross section of another embodiment of a plasma processing chamber that can be used to perform step 257 and/or step 259 above. In this configuration, process chamber 501 is a capacitively coupled plasma processing chamber that can process substrate 502 located in processing region 522. Processing chamber 501 typically includes an ultra high frequency (VHF) source assembly 595, target assembly 573, system controller 602, process chamber assembly 596, and substrate support assembly 594. In this configuration, the capacitor shank is formed into a processing region 522 between the stem 571 and the grounded chamber wall 528 of the chamber assembly 596 by means of a VHF source assembly 595 coupled to the target 571. The process chamber assembly 596 generally includes all of the components of Figure 4A above, except that the chamber cover 529 is replaced by a target assembly 573 that is intimately coupled to the chamber wall 528 and an electrical insulator 572. The components of the process chamber assembly 596 and the substrate support assembly 594 are the same as or similar to the components of the process chamber 500 described above, and thus the same reference numerals will be used and will not be described again. Referring to FIG. 4B, in one embodiment, VHF source component 595 includes an RF source 524 and a matcher 524A for transmitting RF energy to processing region 522 through one or more components of target component 573. Target assembly 573 typically includes a backing plate assembly 570 and a target 571. The backplane assembly 570 can include a fluid passage (not shown) for cooling the target with a fluid transported by a heat exchanger (not shown) during processing, and including a magnetron assembly (not shown). To promote the full use of the target and improve the uniformity of deposition.

When the processing chamber 501 is in operation, the VHF source assembly 595 is used to bias the target 571' to deposit material atoms of the standard 571 onto the surface of the substrate 502. In one embodiment, the RF source 524 of the VHF source component 595 transmits power to the processing region 522 at an RF frequency of about 1 - 200 MHZ 31 200845232 and about 0. (H-5 kW and through the target component 573. In one embodiment, the ions generated by the plasma are sputtered out of the surface of the target 571 due to the pressure drop across the plasma sheath. Thus the VHF source component 595 is used to capacitively couple the target 5 7 1 Self-biasing is generated to provide sufficient energy. Since the surface area of the anode and the cathode (for example, the target 571) is different, the capacitor or the target 5 7 1 is uniformly biased by the capacitor biased by the VHF source. Voltage. The self-bias voltage reached during processing can be adjusted to optimize the sputtering rate of the target 571. Figure 4E is a plot of the self-bias voltage (Vdc) versus frequency. It is generally shown that when biased at a higher and higher frequency, the effect of the frequency on the self-bias voltage of the electrode. It will be noted that the self-bias voltage decreases as the frequency increases, so by increasing the VHF source component 5 The frequency of 9 5 can reduce the ion energy of the impact target. Under the condition that the pressure is 50 Torr and the argon and 3 watts of r]F power are used, the standard voltage biased by the RF signal with a frequency of 27 MHz will have a bias voltage of about -200 V, and 100 MHz. The RF signal biased header will only have a voltage of about 1 〇 V. In another embodiment, an RF power of about 400 watts is used to vary the RF frequency to about 60-1 〇〇 MHz, <Change the stem The bias voltage is about -50 V to about -20 V. The energy target 571 can be transmitted at the RF frequency in the VHF range, and the process results of step 257 and/or step 259 can be modified to make it better than the lower limit. The result of the process performed at the F frequency, which is due to the change in the DC bias on the flag, and the DC bias is a function of the frequency variation and the RF power variation delivered to the flag 571. The variation of the DC bias is reduced. Perform a low energy sputtering process 32

Li 200845232 is very important. Thus, by controlling the RF energy step, e.g., at a predetermined energy rate period (described below), the DC bias on the target can be properly and repeatedly controlled. The bias voltage ensures that the process of doping the ultrathin gate dielectric layer can be positive. Referring to FIG. 4D, in one embodiment, if the gas (Ar) is sputtered and the stem is composed of lanthanum (La), The energy required to dry the surface of the mine is at least 25.5 eV. That is, the voltage formed on the target needs to be high enough to generate an ion energy of about 25.5 eV, and the germanium atoms will be sputtered from the surface of the target. Therefore, by the frequency and power (e.g., watts) of the target 571, the ion energy of the subtracted atom, the ion energy of the sputtered atom, and the atomic energy on the atom can be controlled. And during the process, the bias voltage on the base can be adjusted to further control the energy of the sputtered atoms deposited on the gate into the gate dielectric layer. The picking process generally takes about 1-100 Torr in the processing chamber 501, an argon flow rate of about sCCm, and a degree of about 20 ° C to about 8 Torr. Preferably, the substrate temperature is 丨. 3 〇〇 C. The excitation frequency of the RF source 524 can be adjusted to about 200 MHz 'to get the correct self-biased dc voltage to be applied to the surface of the substrate and the substrate. Preferably, the excitation of the RF source 524 is from about 27 MHz to about 1 〇〇MHz; more preferably, the frequency can be adjusted to about 6 bribes. In the embodiment, the rate can be used to supply the desired splash energy and maintain the low energy rate and power, power to The target paste does control the DC's self-biasing of the argon atoms that are mainly argon to ensure partial control of transport to: plating rate, gas deposition on the substrate ί support 5 6 2 L dielectric layer or implant The chamber pressure is set to a heater temperature of 6 200 ° C to about 1 Μ Η z to about the material splash frequency can be adjusted to a frequency of about 30 MHz 60 MHz. In an embodiment of 33 200845232, it is desirable to change the substrate 5 02 The distance between the surface and the surface of the target 5 丨 to adjust the uniformity of the sputtered atoms deposited on the surface of the substrate and In one aspect, it is desirable to vary the spacing of the substrate 052 relative to the surface of the target 571 during deposition to adjust the depth and/or deposition uniformity of the sputter material within the gate oxide layer.

Figure 4C illustrates a second embodiment of a processing chamber 501 in which the VHF source component 595 of Figure 4B is replaced by a dual VHF source component 5 97 containing two RF sources 524, 525, respectively. The frequency and/or power is used to transfer energy to the processing region 522 of the processing chamber 501 to provide different sputtering properties for different processing times. The processing chamber 501 of Figure 4C generally includes an RF source 524, a second RF source 525, an RF switch 526, and a matcher 524A coupled to the target assembly 573. In this configuration, the energy transferred from the dual VHF source component 597 to the target component 573 can be switched between the RF source 524 and the second RF source 525 by the RF switch 526. The state of the switch 526 is controlled by the system controller 602. This embodiment can be used for targets that require rapid initial modulation to remove oxides that may form on the target surface when initially installed or after long periods of inactivity. The ability to switch to a lower frequency source (e.g., about 27 MHz or less) can form a high self-bias DC voltage on target 571, resulting in a faster target sputtering rate. Therefore, after the initial processing, the output of the dual VHF source ancestor 597 can be changed by switching to a higher frequency source (for example, 60 MHz) to slow down the sputtering rate and reduce the ion energy of the sputtered atoms, thereby reducing the potential destruction base. A gate dielectric layer on the surface of the material. In one embodiment, RF source 524 can transmit RF energy at a power of about 0-2000 watts at a frequency of about 27 MHz, while second RF source 525 can transmit about 0-500 at a frequency of about 40-200 MHz 34 200845232. The RF energy of the power of the tile. In one embodiment, DC source component 592 is one or more pulses that are selectively coupled to target component 573' to deliver dc energy in a plasma processing step. The DC bias can be superimposed on the VHF signal delivered by the VHF source components (e.g., component symbols 595 and 597). The DC voltage applied to target 571 can be used to more directly control the energy of the gas atoms that strike the target 571 by ionization during the sputtering process. In one embodiment, as described above, the substrate support member 562 can be coupled to the RF generator 523 while the process is being performed, with RF or VHF bias applied to a portion of the substrate support 562 to be in the plasma. The ions are dragged onto the surface of the substrate 502. In one embodiment, the substrate support member 562a is grounded, DC biased, or electrically floated during the plasma process to minimize ion bombardment damage to the substrate 502. Pulsating plasma treatment is shown in Fig. 5A_5C as a schematic diagram of various pulsed plasma processes, which can be used to deposit the target 505 or the 4B and 4C of FIG. 4A in the above step 257 and/or step 259. The material sputtered by the target 571 is to the surface of the substrate 5〇2. The pulsed plasma process of Figures 5A-5C is generally a series of continuous energy pulses and DC energy pulses, wherein the continuous energy pulses utilize an inductive rf source component 591 or a VHF source component (i.e., VHF source component 595 or dual vhf source component 597). Delivery to processing region 522 is a function of time, while dc energy pulses are delivered from DC source component 592 to the target. Figure 5A shows the induced RF source component 591 "Rf energy 531 and % 35 delivered by the VHF source component

The DC voltage 535 delivered by the source component 592 in 200845232 is in time. Figure 5A shows a diagram of the induced RF source component 591 or the delivered RF energy 531 and the DC electrical function delivered to the target. In this manner, the actual RF or VHF (hereinafter referred to as RF/VHF) is shown. In the same example, the pulses of RF energy 531 and DC voltage 535 are not applied simultaneously. The DC pulse 532 typically provides RF/VHF excitation ions in the short-electrode plasma, accelerating the ionizer toward the stem 505 to sputter the dry material onto the electrosprayed sputter material while generating the RF/VHF pulse 53 3 #月The plasma in 5 22, which can then be ionized. Sight base; whether it is biased by RF/VHF, ground or floating, can be applied to the surface of the substrate by means of a plasma generated near the surface of the substrate. In most cases, when a DC voltage pulse (or DC current pulse) is used to ensure the reach and clock rate, it is desirable to synchronize the RF/VHF to produce sufficient plasma in the process chamber. Continuing with reference to Figure 5A, it is generally desirable to have a chamber design such that during RF/VHF pulse 533, the rush 533 does not have sufficient energy to sputter the target atoms), and the energy is more easily controlled by the DC bias applied to the target. . It is desirable to use RF/VHF pulses to ionize the oscillating clock to apply a low potential bias on the susceptor on which the substrate is placed while the target atoms are accelerated and implanted onto the surface of the substrate. Diagram of the result of a state function V H F source component 5 9 5 Press 5 3 5 with time as the DC and step of the example. In this case, it is synchronized, so its temporary attraction is enough to absorb enough energy. Exciting the target region into the processing region, the support member 562A ionizes the original energy of the splash and delivers a low energy bias to the predetermined ion-tight pulse 5 3 3 end, inductively coupled with plasma ions (RF/VHF) The pulse is so hidden in the partial part of the 'target atom' to utilize the low voltage, the target, the DC voltage pulse (or DC current pulse) applied to the counter 36 200845232 and the pulse rf/vhf interrupt cycle (off -cycle) is synchronized so that the energy generated by the ions in the plasma is more easily controlled by applying DC energy to reduce the net increase in the energy of the paddle. The voltage of the DC pulse can be provided in the doping process. Enough energy to argon ions to dry the material to the plasma.

– It should be noted that the system controller 002 can be used to synchronize the RF/VHF pulse 53 3 # DC pulse 532 and the energy cycle to achieve the desired plasma density, sputter deposition rate, and plasma ion energy. Referring to Figure 5A, the energy period represented by the overall pulse time divided by the RF energy 531 by the on time (tl) can be optimized to ensure that the plasma having a predetermined average density is controlled. The start-up (〇n), time (t4) divided by the energy cycle represented by the overall pulse time of the DC voltage 535 can be optimized to ensure that the predetermined average deposition rate is reached. See Section 4B-4C With the 5A-5C diagram, in one embodiment, the VHF source component 595 is set to a pulse mode with a pulse frequency of iHz to 50 kHz and an energy rate/period of 〇·1%-99%. In this embodiment, a pulsed VHF source It is used to generate and maintain the plasma formed in the processing region 522 and reduce the average post-plasma and ion energy. The system controller 6〇2 can be used to adjust the energy cycle, pulse frequency, and RF energy (ie, rf power). And the frequency of the rf energy to control the energy of the plasma, ions, and sputter material. In one embodiment, to transfer the low energy sputtered material to the substrate surface, the system controller 602 can be about 1%-50% Energy rate cycle to deliver rf energy to coil 509 (Fig. 4A) Alternatively, or in one embodiment, the low energy sputtered material can be delivered to the surface of the substrate by delivering energy to target 571 (Fig. 4B) and 37 200845232 at an energy cycle of between about 1% and 50%. In some instances, it is desirable to maintain an energy rate of about 1%-10% delivered to coil 5〇9 (Fig. 4A) or target 571 (Fig. 4B) to minimize energy transfer to the plasma ions. A fifth embodiment illustrates another embodiment of a pulsed plasma process in which a pulsed RF energy delivered by a DC pulse 532 at an inductive RF source component 591 or a VHF source component (ie, VHF source component 595 or dual VHF source component 597). In at least part of the period of time 531 is transported. In still another embodiment, as shown in Fig. 5C, the RF energy 53 1 remains unchanged for a period of time t1, when the RF energy source is, the activation (〇n) At this time, the pulsed DC voltage 53 5 is delivered to the target 505. It should be noted that it is preferred to reduce the magnitude of the RF energy 531 during the DC pulse 532 to reduce any possible mutual interference between the transmitted signals. In one embodiment, it is desirable to use RF generator 523 (FIG. 4A) to bias substrate support 5 62 to generate attracting ions during different RF/VHF plasma generation phases and/or pulsed dc sputtering periods. To the bias on the substrate. In another embodiment, it is desirable to generate rF/VHF energy pulses such that ions generated in the plasma will not have sufficient energy to sputter the target. In this case (the 'DC biasing' is applied to the target to promote sputtering of the target. In one embodiment, a pulsed RF/VHF signal is applied to the substrate support 562 to create and maintain a ubiquitous basis. The plasma of the surface of the material. In one embodiment, the synchronized DC pulse is delivered to the label 517, and the synchronized vHF pulse is delivered to the substrate support 562 to sputter the target into the plasma. And doped into the gate dielectric layer. Grounded Collimator's thermal meter 38 200845232 Figure 4F shows a cross section of another embodiment of the Ray & poly processing chamber 500, which can be used to make a gate The metal-plasma treatment of the polar medium is a low-energy trapping process to open/draw the doped dielectric layer. In this embodiment, the grounded collimator 540 is sighed on the substrate 5. The metal ion is charged between the 02 and the standard 505. The grounded collimator 540 is used to promote the substantially implanted plating atoms to reach the substrate 502 to form a thin metal layer on the surface of the substrate 502 ( It may be as thin as a single layer.) The collimator is usually a grounding plate or wiring net with a plurality of holes 54〇Α, the hole 54〇Α is distributed throughout the ground plane, allowing neutral atoms (and perhaps some ions) to pass from the processing area near the target to the surface of the substrate. Because the energy of the neutral atom usually only accounts for the atoms of the target surface. A small portion of the energy and neutral atoms do not affect the plasma potential, so the deposition of this layer to the surface of the gate dielectric layer by this method generally results in minimal ion bombardment damage. The metal layer can then be subsequently oxidized. The layer combines 'to form a high dielectric constant (high-k) dielectric layer, and there is no metal or nitrogen ion implantation and related problems, such as destroying the layer of stone and metal over-penetrating the layer of the stone layer under the substrate. It will be understood by those skilled in the art that the processing chamber 501 of FIGS. 4B and 4C can also be provided with a grounded collimator 540 between the target 571 and the surface of the substrate 502 to have the same function to impact the charged particles against the surface of the substrate. Previously, a large amount of charged particles in the plasma were taken to reduce damage to the gate dielectric layer. Another design of the t-chamber 4G diagram shows a cross section of another embodiment of the plasma processing chamber 500, which is available Gate dielectric layer The metal plasma treatment, that is, the low energy 39 200845232 extinguishing process to form a doped gate dielectric layer. According to one embodiment of the processing chamber 5 (10), the output of the inductive RF source component 591 is connected to the target Thus, the coil 509 can be used to engage the capacitor with the capacitor 5〇5 to generate electricity in the processing region '5. In the embodiment, the label & 5G5 is transmitted through the coil 5〇8β to the RF matching II. 508Α is rotated, and when the generator 5〇8 delivers power via the rf matcher 508Α, the coil 5〇8β is the size of the threshold to achieve resonance. Referring to the fourth figure, the target 5〇5 is attached with ~κ t Bias can make Ο

The U coil 509 generates and forms a plasma and delivers it to the target u D 4 κ F frequency and the RF power can control the DC bias and the impact target 505 θ ~ away from the summer of 6; In addition, by using a 玑W 7 compliant coupling plasma generating component and a capacitive coupling plasma generating component that can generate pulses at a predetermined energy rate cycle, the DC bias applied to the target (ie, self-biasing) can be made easier and more tidy. , sputtering rate, and sputtering & By carefully controlling the chamber pressure, RF frequency, rf power, energy cycle, bias applied to the substrate support 562, and/or processing time, the amount of sputtering material can be controlled. Corresponding subtraction; the choice of the bond material in the dielectric layer & ^ 芡 relationship. The use of a single RF generator 508 and RF matcher 508A can also reduce reaction chamber cost and system complexity. In one embodiment, DC source component 592 is coupled to target 505 such that DC pulses can be delivered to target 505 during or between RF pulses generated by RF generator 508. In another embodiment, as shown in FIG. 4H, it is desirable to have an individual RF generator 565 and RF matcher 565A to supply target 505 RF energy ' and coil 509 is individually used by rf generator 508 and RF matcher 508A. It was abandoned by RF. In this configuration, the system controller 6〇2 can be used to individually control the components of the new RF matcher 565A and RF generator 565 and the sense 40 200845232 RF source component 591. In one aspect, the DC source component 592 is also stalked to the target 500, such that during the process of sensing the RF source component 591 and/or the RF generator 565 to deliver RF pulses or between RF pulses The DC pulse can be delivered to the target 505. Fig. 41 is a cross-sectional view showing another embodiment of the capacitive coupling type processing chamber 501, which can be used as a metal electric paddle treatment for the gate dielectric layer. In one embodiment, the processing chamber 510 can perform a low energy sputtering process, such as described with reference to steps 257, 259. In one embodiment, processing steps 257, 259 are performed on a substrate 502 located in processing chamber 501 that utilizes magnetron assembly 580 to assist in further control and enhancement of the plasma generated in processing region 522. And thus control and enhance the low energy sputtering process. In this configuration, the processing chamber 501 can include a power supply (eg, VHF source component 595, DC power supply 507), target component 573, system controller 602, process chamber component 596, magnetron assembly 58A, and Substrate support assembly 5 94. The magnetron assembly 580 generally includes a magnetron 581 and a magnetron actuator 582 that is adapted to move the manifold 581 relative to the target assembly 573 during processing and / or positioning. The magnetron 581 typically has at least one magnet 583 (three shown in FIG. 41), each magnet 5 83 having a pair of opposing magnetic poles (ie, N poles and S poles), and the magnetic poles are generated through the target assembly 573 and the processing area 5 22 - the magnetic field (B field; B-field). Generally, the magnet 583 is a permanent magnet (e.g., titanium, samarium cobalt or alnico magnet [Alnico]) or an electromagnet. The obstruction tube 581 and the magnetron actuator 582 are used to enhance the use of plasma uniformity or target material in low energy sputtering. In one embodiment, the Dc 41 200845232 source component 592 and the source component 595 are both transferred, and the DC power, RF power, and/or % and retarder 573 are transferred to the target component 573. In an embodiment, the medium=pulse may be desirably formed to form a material having a desired dielectric property in the layer of the anti-system transfer system 550 in a low energy quenching process: : = = the electroreactive gas may be For example, oxygen (〇2) is: ...' gas. U or a mixture thereof, the body-fired, gas delivery system 550 is adapted to deliver a reactive emulsion to deposit a high-k dielectric layer 4〇4 on the surface of the substrate 4G1. In one embodiment, the 'reaction gas may be a gas such as oxygen (〇2), nitrogen (NO or a mixture thereof). Examples of gate dielectric layers that may be formed using a PVD type process include, but are not limited to, yttrium oxide ( Hf〇2), citric acid (HfSi02), aluminate (HfA1〇x), bismuth oxynitride (HfSi〇N), oxidized (Zr〇2), zirconium zirconium (ZrSi〇2), acid Pin 钡 (BaSrTi034 BST), lead bismuth citrate (Pb(ZrTi) 〇 3 or PZT), etc. Plasma infusion process In one embodiment of the invention, the characteristics of the termination region 405 (Fig. 3E) may be Optimized, whereby the threshold voltage (Vt), dielectric constant, energy gap, and/or conduction band gap difference (CBO) can be optimized for the type of semiconductor component to be formed. Typical semiconductor elements formed may include, but are not limited to, nM〇S or p-MOS type elements. In one embodiment, the concentration and/or depth of dopant atoms within the dielectric layer may be modified to achieve one or more Expected component characteristics, such as: threshold voltage (Vt), energy gap 42 200845232 gate dielectric and dielectric constant. For example, expectation A material (ie, a dopant material) is doped to terminate the termination region 405, such as aluminum (A1), chin (Ti), erbium (Zr), (Hf), lanthanum (La), silver (Sr), lead ( Pb), gamma (gamma) and barium (Ba), the materials may be further modified to form a dielectric material in the high-k dielectric layer 403 or the high-k dielectric layer 404. For example, the The above list of material properties of possible dielectric materials that may be added to the dielectric layer formed in the processing program 251. Material dielectric constant energy gap E Conductive band energy gap difference

Ο

Si02

Si3N4 AI2O3

Ti〇2

Zr02

Hf02

Cj can be adjusted to exist in high-k mediation; step 259 is a modified concentration distribution, whereby the material in the electric layer 404 is formed in the termination region 405 and the gate region 4 3F) The expected electrical properties of the junction. The important electrical properties of the junction: the junction is the threshold voltage (v., which = allows conduction through the source of the component and between: ..., track & The required voltage measurement value. Generally speaking, the system phase 43 200845232 maintains the threshold voltage of the MOS type component of the 32 nm to 90 nm generation at about 0. 2 to 0.5 volt. In another embodiment, various types are desired. The dopant species are doped to the termination region 405 to form a closed-cell dielectric and the gate dielectric layer has improved component characteristics and better characteristics than other materials. FIG. 4J illustrates the formation step in the termination region 405 (Side view of high-k dielectric layer 403 or high-k dielectric layer 404 during the step of collapse, in this step, gate dielectric dopant material (see component symbol bombardment gate dielectric layer to form desired The dielectric layer of the semiconductor device of the characteristics can follow the steps shown in the figures 2A to 2F. The 4K figure shows that the concentration of the deposited material is a function of depth (eg, curve Ci), and this depth is entered into the substrate 401 along the path 421 by the surface of the high-k dielectric layer. Generally, after the subsequent heat treatment step (for example, steps 26〇~266), maintaining the concentration of the dopant material in the same k dielectric layer ensures that the doping does not accumulate at the interface or surface 4〇1B. Influencing the formed component C) The temple is present at the dielectric layer substrate interface (component symbol 401B). The material pass will result in a Vt shift and a decrease in carrier mobility. The subsequent Z steps (which may include steps 260-266) or In many cases, the material in region 405 is converted to a material having the desired high-k characteristics. In one embodiment, post-plasma processing is performed on the substrate to repair broken bonds and improve stability and improve interface. For example, the annealing treatment is carried out by supplying oxygen (〇2) until the oxygen/pressure of the chamber is between 1 mTorr and about 1 Torr, and the absolute value is in the second or electric layer. Dielectric material i 259 ) Section A), high k formation. Face 420 is expected to be used for dielectric annealing of the material's electrical dopants. The typical processing zone is maintained at 44 200845232. The substrate temperature is about 1000r, and the total chamber pressure is about ! The brackets are ~ about 1 Torr and last for about 1 second to about 60 seconds. Figure 4K is also an overview of an embodiment in which the low energy deplating process discussed in steps 257 is used. The temperature distribution of the first material of the thermal oxide layer 402 (see curve C.) extends to -depth ' in the formed high-k dielectric layer and is greater than the second material deposited in the termination region 405 in the step The depth. In some examples, by selecting Γ), the first material that is desired and does not react with the substrate material (for example, forming a lithium compound); (彳j if given) reaches the dielectric layer-substrate interface. Quality materials are not a problem. As shown in FIG. 4K, in one example, it is desirable to have a first material that does not react with the substrate material at normal processing temperatures, and then adjust the deposition process of the first material (eg, step 257), By the wave of the material (see curve Co), a state of formation or a uniform distribution of states is formed in the gate dielectric layer. Next, the first material is selected to form a good interface with the layer deposited on the gate dielectric layer (eg, the gate region 4〇8), and the deposition process is adjusted (step 2 to (, achieve a shallow concentration, β, , cloth (see curve c 1) 'This is by adjusting the cavity treasure variable to match the 筮 _ η / to the table - material characteristics (such as mass), by the desired thickness in the dielectric layer ^ ^Chengdu knife cloth. In an example, the second material ry such as titanium, aluminum and tantalum reacts with the substrate material at a temperature of c, a material (for example) A, ▲ For example, Si·, Si) reaction 愔10 (example material (see curve phase & 煲 first ~ compared to the second material (see curve C 丨) and distributed in the dielectric layer is more inverse ^ Ma Junyi. In this example, the average concentration of the first material in the dielectric layer of 45 200845232 (for example, the average value of Co) is larger than the average/length of the second material (for example, the average value of ci). See Fig. 4 κ). The 4L figure shows a ruthenium dioxide layer (such as thermal oxide layer 402) and a high-k dielectric layer 404. (See Fig. 2F) a side cross-sectional view in which the high-k dielectric layer 〇4 is shunted by the gate dielectric dopant material (see symbol A) in step 259 to form a termination with desired characteristics. Area 405. In

In one embodiment, the high-k dielectric layer 4〇4 may be hafnium oxide (Hf〇2), hafnium niobate (HfxSiy〇z), hafnium aluminate (Η1Α1〇χ) or hafnium oxide (HfLa〇). x), which is produced by ALD, M〇CVD or low-energy reactivity (eg 4A)

Vi and 41 are formed. Figure 4 shows an example of the concentration of the gate dielectric dopant strip as a function of depth (e.g., curve Μ, and this depth refers to the entry of the high-k dielectric layer from 420 along path 421 into the substrate 4〇1 In this configuration, it is generally expected that the text will be broadcast in the subsequent heat treatment step (for example, steps 260 to 266) for the ice y moxibustion to ensure the presence of the dopant material in the high-k dielectric layer. The concentration ensures that the deposited material WW does not accumulate on the surface 401B, but the electrical characteristics of the element formed by the scene. The 4N diagram shows the high-k dielectric re- 403 fen-electric layer 403 and/or A side cross-sectional view of the electrical layer 404, wherein the high-k dielectric 屛β, the bucket, the _slide 403, and/or the two-k dielectric layer 04 04 are exposed to the sluice during the step 259 The controlled dielectric wall of the extremely dielectric dopant material (see components A and B) is continuously or synchronously deposited to form a termination region 405 having the desired characteristics. The e-wall of the main and the main sound should be considered. The 4N diagram only shows that the two-gate dielectric dopant material is deposited continuously and in a substep manner, but this is not intended to limit the scope of the present invention. , J because this evening for seven different gate dielectrics having a dopant material to achieve the desired electrical sacrifice

The desired gate electrode for the special. 4C 46 200845232 Figure shows an example of the concentration of the deposited material as a function of depth (ie, dopant A is curve C!, quality change B is curve C2), and this depth is from the surface 420 of the high-k dielectric layer Path 421 enters substrate 401. In one example, it is desirable to continuously deposit titanium and etch into the high-k dielectric layer 403 and/or the high-k dielectric layer 404 to form the termination region 4 〇 5 ^ in this example, by various splicing - heat treatment ( Steps 260 to 266) and subsequent formation of titanium dioxide (Ti〇2), aluminum oxide (Ah〇3), titanium ruthenate, aluminum ruthenate or a mixture thereof may thereby assist in forming a termination layer 4〇5 having improved electrical properties. These electrical characteristics can include an increased threshold voltage of 70 pieces, a desired energy gap, an increased dielectric constant relative to a single doped alumina gate dielectric layer, and a single doped TiO 2 gate dielectric layer. Higher CB〇. The addition of a plurality of 70 elements in the termination region 4〇5 also assists in "blocking" one or more deposition materials, such as reducing their mobility in the gate dielectric layer, during subsequent processing steps or component life. Prevent its diffusion to the gate dielectric interface (eg surface 40 1 B ). Alternatively, the dielectric material properties of the formed component can be modified by controlling the deposition characteristics of each of the two or more gate dielectric dopant materials. Q In general, the properties of the deposited film can be controlled by varying the chamber process variables, which can include chamber pressure, substrate bias, and processing time to RF power delivered to the processing region (eg, RF) The power rate period, +^, the substrate temperature during processing, and/or the DC bias delivered to the target are as discussed above in connection with Figures 4A-41. These process variables can be adjusted for each deposition material and the desired/cutting knives formed in the gate dielectric layer. An example of a theoretical concentration distribution of a material delivered to the Si〇2 layer at an energy of 20 eV is shown in Figure 4P. 47 200845232 Figure 4 thus shows the change in temperature distribution in the high-k dielectric layer based on the quality of the different materials and their associated atoms.另一 Ο In another embodiment, it is desirable to select and modify a material type for forming a semiconductor element based on the kind of components formed in the processing program 251. In an embodiment, when an n_M〇s element is formed, It is desirable to select and modify the gate dielectric dopant material and deposition characteristics during the formation of the termination region 405 (ie, step 259) to achieve the desired component performance characteristics. When an n-MOS device is formed, it is desirable to incorporate or place yttrium (La), titanium (Ti), and/or erbium (Zr) into the surface of the high-k dielectric layer 4〇3 or the high-k dielectric layer 404. And then selecting and depositing material to form the gate region 4〇\ to provide the desired threshold voltage characteristics, for example, when contacted with the selected gate dielectric-exchange material, the ^^ system is between about 〇·2~0.5 Between the volts. It can be used in the gate region 408, and is exemplified by lanthanum (La), titanium (Ti), and/or dysfunction in the n_MOS structure type. (Examples of materials with good z 氮化 are carbonitride 钽 () and nitride (TaN) In other embodiments, when forming a pM〇s device, it is desirable to select and change the deposition characteristics of the gate dielectric dopant material used to form the termination region 4〇5. It is desirable to incorporate or place the inscription (A1) into the surface of the high-k dielectric layer 4〇3 or the high dielectric layer, and then select and deposit a material to form the gate region 4〇8, and the gate region 408, when in contact with the gate dielectric dopant material, provides a desired threshold voltage 'eg, Vt between about -2 and -5 volts. Can be used to form the gate region 408 and the aluminum with the p_M〇s component (Ai Examples of well-functioning materials include nails (Ru), Ming (Pt), nitrided cranes (WN), and cranes (w). The desired high-k dielectrics that can be used to form n-MOS components or p_M〇s components 48 200845232 Examples of layer 4 04 may include hafnium oxide (Hf02), hafnium ruthenate (HfxSiyOz), hafnium aluminate (HfA10x), hafnium oxide (HfLaOx), mixtures thereof a derivative thereof. In an example, as described above, the processing chambers illustrated in Figures 4A to 41 (e.g., processing chambers 500, 501) are used in nitrogen (N2), argon (Ar) containing or containing Sputtering in the helium (He) plasma and subsequent generation of metal ions (eg: A1+,

Ti+, Zr+, Hf+, La+, Sr+, Pb+, Y+, Ba+) to incorporate ions into the termination region 40 5 and form a top surface peak concentration gradient of the metal atoms in the dielectric layer. In addition, metal ions are introduced into the plasma by injecting a metal containing gas or vapor (e.g., CVD or Mo CVD precursor). Examples of a portion of the metal-containing gas or vapor that can be injected into the plasma processing chamber include: tridecyl aluminum, zirconium chloride (ZrCl 2 ), dicyclopentadiene dimethyl zirconium, tetra-diethylamino zirconium (TDEAZr) ), gasified hydrazine (HfCl2), dicyclopentadienyl fluorenyl hydrazine, or tetraethylenediamine hydrazine (TDEAHf). Using any deposition method, and subsequently deposited metal ions are then subjected to one or more subsequent heat treatment steps (ie, steps 2 6 0 to 2 6 6 ) to convert the deposited material into the dielectric material with desired High k characteristics. If the residual carbon (C), hydrogen (H), and chlorine (C1) placed in the formed gate dielectric layer are not incorporated into the dielectric layer in a sufficient amount, the element characteristics may be affected. Thus, one or more subsequent processing steps, such as vacuum thermal annealing, plasma annealing or thermal annealing, can be performed to reduce the incorporated contaminants. The plasma processing system one or more plasma processing chambers (for example, the above-mentioned 4A-4C and 4F diagrams 49 200845232 processing room) are preferably integrated into a plurality of reaction chambers, a plurality of process substrate processing platforms (for example, Figure 7 integrated processing system 6〇〇). An example of an integrated processing system that is beneficial to the present invention is described in U.S. Patent No. 5,8 8 2, 165, filed on March 16, 1999, PCT Application No. 5,186,718, Application 曰The application for February 16th, 193, and the US Patent No. 6,440,261, and the application for August 27, 2002, are attached for reference. The integrated processing system 600 can include a working interface 604, load ports 6〇5A-605D, a system controller 602, vacuum load lock chambers 606A, 606B, a transfer chamber 610, and a plurality of substrate processing chambers 614A-614F. The one or more substrate processing chambers 614 614 614 ρ may be a plasma processing chamber ', such as the processing chamber 5 上述 and/or one or more processing chambers 501 of Figures 2-5 above, for performing a plasma process. In other embodiments, the integrated processing system 600 can include more than six processing chambers. In accordance with an aspect of the present invention, an integrated processing system 6 generally includes a plurality of reaction chambers and robot arms 'and is preferably provided with a system controller 602 that is programmed to integrate and implement various processing methods and procedures. Processing system 600. The system controller 602 is typically used to assist in the control and automation of the entire system, and typically includes a central processing unit (CPU) (not shown), § memory (not shown), and a support circuit (or Input/output (1/〇)) (not shown). The CPU can be any type of computer processor used in industrial devices to control various system functions, reaction chamber processes and supporting hardware (such as detectors, robot arms, motors, gas source equipment, etc.), and to monitor systems and reactions. Chamber process (such as reaction chamber temperature, processing capacity, reaction chamber processing time, signal, etc.). The robotic arm 613 is located in the center of the transfer chamber 610 to load the substrate from the 50 200845232 load lock chamber 606 or 606, to one of the process chambers 614A-614F. The robot arm 613 is generally placed by the owner, and the 匕3 is connected to the blade assembly 613A of the robot arm drive assembly 613C, and the mechanical micro-motion is moved to the 豸 assembly 6 1 3 B. The robot arm 613 transfers the substrate "W" to each of the processing chambers in accordance with the deduction of the system controller 602. A manipulator that is beneficial to the present invention, and is described in U.S. Patent No. 5,469,035, entitled "Two-axis Magnetically Coupled Robot", from the second main platinum day to the west Application for August 30, 1994; US Patent Certificate

Ο 曰唬 5,447,409, the name "Robot Assembly", application by & ̄ to apply for the application of April 1, 1994; and the US patent says t~certificate 唬 6,379,095, the name " Robot arm for handling semiconductor substrates ^ (Robot For Handling

The application date of the Semiconductor Substrates) and the application date for the April 2nd (A) is attached for reference. A plurality of slit valves (not shown) can be used to selectively separate the processing chambers 614A-614F from the transfer chamber 610 so that each of the reaction chambers can be individually vacuumed for vacuum processing during processing. A significant benefit of integrating the plasma chamber into the integrated processing system 6 is that a series of process steps can be performed on the substrate without exposure to air. This allows the step of depositing the sputtered atoms to the surface of the substrate, e.g., in the above Figures 2-5, without oxidizing the as-deposited ultra-thin metal layer. The integration of multiple processing chambers into an integrated processing system 〇0 containing a processing chamber in which the annealing step can be performed also avoids runaway oxidation of the as-deposited material prior to the stable annealing process. The integrated system does not expose the substrate to an oxygen source environment that is unique to non-integrated processes, thus preventing materials in the high-k dielectric layer 403 or high-k dielectric layer 4〇4 51 200845232 (eg, doped wire/buy) Material) rolling. What is seen in the non-integrated process will directly affect the component system and the average performance of the component. According to one embodiment of the integrated processing system, the first processing chamber, the reaction chamber of the substrate processing chamber 614 s s 604 can be used to perform step 252 as described above.

Ο li's RCA cleaning step. Subsequent removal of the native oxide layer 4〇ia (see Figure μ) can be performed by conventional rapid thermal oxidation (10) 〇 process, plasma assisted chemical vapor deposition (pECVD), or ald in process chamber 614B to form a dielectric layer. An electrical layer (such as thermal oxide layer 4, high-k dielectric layer 404) is on the substrate. The substrate processing chambers 614C and 614D are plasma processing chambers similar to the processing chamber 5 and/or the processing chamber 5〇1 for performing steps 257 and 259. Therefore, the plasma process can treat the substrate in the processing chambers 61 4C and 61 4D, and maintain the substrate in a vacuum soil to avoid the growth of the native oxide layer on each layer of the substrate. This is especially important when the exposed film layer contains highly oxophilic materials such as ruthenium. In one aspect, step 260 is performed sequentially on the substrate in substrate processing chamber 614E to oxidize the metal surface formed in substrate processing chamber 614D. In another aspect, step 262 can be performed in an RTP chamber located in substrate processing chamber 614e. Next, a plasma nitridation process (step 264) (e.g., a DPN process available from Applied Materials) can be performed in substrate processing chamber 614F. In yet another aspect, step 266 can be performed in an RTP chamber located in substrate processing chamber 614E or substrate processing chamber 614F, if any. In another embodiment, step 252 (i.e., the step of removing the native oxide layer) and step 254 (i.e., the step of depositing the thermal oxide layer) can be performed in different systems. In this embodiment, substrate processing chambers 614A and 614B can be plasma processing chambers similar to processing chamber 500 and/or processing chamber 501 for performing steps 52 200845232 257 and 259. In one aspect, step 26 is sequentially applied to the substrate in substrate processing chamber 614c to oxidize the metal surface formed in substrate processing chamber 6 1 4B. Or in another aspect, step 262 can be performed on an RTP chamber disposed in processing chamber 614C. Next, a plasma nitridation process (step 264) (e.g., a dpn process available from Applied Materials, Inc.) can be performed in a processing chamber located in substrate processing chamber 614D. In one aspect, step 266 can be performed on an RTP processing chamber or substrate processing chamber 614C (if any) disposed in processing chamber 614E. In one aspect, after step 260 is completed in substrate processing chamber 614C, the surface nitridation step can be performed in substrate processing chamber 6丨4D without removing the substrate from the vacuum environment to contact the air. A method of forming a _--------------- Method 1 includes a series of steps performed on a substrate during the fabrication of a gate structure of a complementary metal oxide half (CMOS) field effect transistor example. Figure 6A shows the complete procedure of Method 1〇〇. At least some of the methods can be implemented in a process reactor of an integrated semiconductor substrate processing system (i.e., a cluster tool). One such processing system is the CENTURA® integrated processing system available from Applied Materials, Inc. of Santa Clara, California. Figure 6B-6G is a series of cross-sectional views of the substrate on which the gate structure is fabricated using the method of Figure 6A. The sections of Figures 6B-6G correspond to the individual process steps for fabricating the gate dielectric of a larger gate structure (not shown) in the transistor. Figure 6B-6G is not drawn to scale and has been simplified 53 200845232 Illustration. The method 100 begins at (4) 102 and proceeds to step 118. Referring first to Figures 6A and 6B, in step 1〇4, a substrate is provided (for example, a 200 mm wafer 3003⁄4 m wafer) which is exposed to a solution to remove the substrate. The native oxide layer (Si〇2) of the surface is 2〇4. In one embodiment, the native oxide layer 204 is removed using a cleaning fluid containing hydrogen fluoride (HF) and deionized (DI) water (i.e., 'hydrofluoric acid solution). In one embodiment, the cleaning solution is an aqueous solution containing HF by weight of from about 2 G ° C to about 3 generations. In another embodiment, the cleaning fluid comprises about O.Swtk HF and is maintained at about 25. . . In step 1〇4, the substrate 2〇〇 can be immersed in the cleaning solution and then washed with deionized water. Steps 1〇4 may be performed in a single substrate processing chamber or a plurality of batch type substrate processing chambers, which may include the delivery of ultrasonic energy during processing. Alternatively, step 1〇4 can be performed in a single substrate wet cleaning reaction chamber in integrated processing system 600 (Fig. 7). In another embodiment, the removal of the native oxide layer 204 can employ RCA cleaning. After completion of step 104, the substrate 2GG is placed in a vacuum-loaded lock chamber or in a nitrogen/(N2) environment.

U In step 1〇6, a thermal oxide layer (Si〇2) 2〇6 is formed on the substrate 2〇〇 (Fig. 6C). The thickness of the thermal oxide layer 2 〇 6 is generally from about 3 angstroms to about angstroms. In one embodiment, the thermal oxide layer 206 has a thickness of from about 6 angstroms to about 15 angstroms. The deposition of the thermal oxide layer step 106 can be carried out in an RTP reactor, such as a RADIANCE® RTP reactor located in integrated processing system 600 (Fig. 7). The Radiance® RTP reactor was obtained from Applied Materials, Inc. of Santa Clara, California. 54 200845232 β In 乂胄108, the thermal oxide layer 2〇6 is a plasma exposed to metal ions, such as 'Step 108, forming a ruthenium oxide metal layer or a Xi metal layer or a ruthenium oxynitride metal layer on the substrate 200. Metal sublayer Μ% figure). The metal layer 208 of about 1 angstrom to about 5 angstroms is preferably formed on the surface of the thermal oxide layer 206 when the step 1 〇 8 is performed. In one embodiment, the metal ion-containing plasma comprises an inert gas and at least one metal ion, such as a feed or a helium. The inert gas may comprise argon, and one or more selectively inert gases such as helium (Ne), helium (He), helium (Kr), or helium (Xe). # In one aspect, the metal ion-containing plasma may contain nitrogen (N2). In step 110, the thermal oxide layer 2〇6 is exposed to the oxygen-containing plasma to oxidize the metal sub-layer 209, and the metal layer 208 (when the layer is applied) is converted into the dielectric region 210 (Fig. 6E) . In another embodiment, the plasma may comprise nitrogen (N2), and one or more oxidizing gases such as oxygen (〇2), an oxidizing atmosphere (NO), and nitrous oxide (Να). The plasma may also contain one or more inert gases such as argon (Ar), helium (Ne), helium (He), helium (Kr), or helium (Xe). Step 110 can be performed, for example, on a decoupled plasma nitriding (DPN) plasma reactor of integrated processing system 6 (Fig. 7).

U In another embodiment, step 11 2 is used to replace the step 丨丨〇 to anneal the substrate 200 at a temperature of from about 800 ° C to about 1100 ° C. Step 112 can be performed in a suitable thermal annealing chamber, such as a Radiance® reactor or RTP XE+ reactor integrated with treatment system 600, or a single substrate or batch furnace tube. The thermal oxidation step 112 forms a dielectric region 2 1 含有 containing a dielectric material. In one aspect, the dielectric region 210 can comprise a silicate material. In one embodiment, the annealing step 112 may employ oxygen (〇2) at a flow rate of about 2-5000 seem and nitrogen monoxide (N〇) at 55 200845232 of about 100-5000 sccm, or selective mixing of nitrogen (N2). And maintaining the surface temperature of the substrate from about 8 ° C to about 丨丨〇〇. 〇, the chamber pressure is about 1 1 - 5 0 Torr. This annealing process can be carried out for about 5-180 seconds. In the examples, the supply flow rate of oxygen (?2) is about 500 seem, and the chamber pressure is maintained at about 1000 °C for about 15 seconds. In another embodiment, the supply flow rate of nitric oxide (N0) is about 5 〇〇 scem, and the chamber pressure is maintained at about 1000 ° C for about 15 Torr for a period of about 15 seconds. In step 114, the surface of the substrate 200 is exposed to nitrogen plasma to increase the nitrogen content of the surface constituting the structure, and the nitride layer 214 is formed (Fig. 6F). This process can use a DPN reactor and provides about 10-2000 sccm of nitrogen (N2), about 20-500. The base temperature of the crucible and the reaction chamber pressure of about 5-1000 mTorr. Radio frequency (RF) plasma supplies energy, for example, at 13.56 Torr, and up to about 3-5 watts of continuous wave (CW) or pulsed plasma power. When generating pulses, the maximum RF power, frequency, and energy cycle periods are typically in the range of about 10-3 000 watts, about 2-1 00 kHz, and about 2%-100%, respectively. This process can be carried out for about 1 second to about 180 seconds. In one embodiment, the supply of nitrogen (N2) is about 200 seem, and the maximum RF power of about 1000 watts is pulsed at about 1 kHz and about 5% of the energy cycle applied to the inductive plasma source, about 25 A pulse is generated for a temperature of 〇c and a pressure of about 10-80 Torr, for a period of about 15 seconds to about 18 seconds. The plasma can be generated using a quasi-remote plasma source, an inductive plasma source, a radiant slotted antenna (RLSA) source, or other plasma source. In another embodiment, a C W and/or pulsed microwave power source can be used to form the nitride layer 214. A nitride layer 214 may be formed on the upper surface of the dielectric region 210 (Fig. 6E). 56 200845232

Ο In step 116, the gate dielectric layer (oxide layer 2〇6, nitride layer 214 and metal sublayer 2〇9), and substrate 2〇〇 may be annealed. Step li6 can reduce the leakage current between the oxide layer 206, the nitride layer 214 and the metal sublayer 2〇9, and improve the mobility and improvement of the charge carrier in the channel region below the cerium dioxide (si〇2) sublayer 216. The overall reliability of the gate dielectric layer. Step 116 can be carried out in a suitable thermal annealing chamber, such as a RADIANCE 8 reactor or RTP ΧΕ + reactor integrated with a treatment system, or a single substrate or batch furnace tube. The thermal oxidation step 116 can form a cerium oxide (si02) sublayer 216 at the 矽/dielectric layer interface (Fig. 6G). Step 116 enhances the mobility of the charge carriers in the channel region below the cerium oxide (Si〇2) sublayer 216 and improves the reliability of the dielectric/germanium interface. In an embodiment, the annealing process of step 1 i 6 may employ at least about 2-5000 sccm of oxygen (〇2) and about 1〇〇5〇〇〇sccm of nitric oxide (NO), or - Nitrogen (N2) is mixed in, and the surface temperature of the substrate is maintained at about 8 Torr (TC to about 11 Torr (rc, the pressure in the processing chamber is about 〇丨50 Torr. This process can be carried out at about 5-180 Torr. In the examples, the supply of oxygen (02) is about 500 SCCm, and the chamber pressure is maintained at about 1 Torr (about 15 seconds) for about 15 seconds. After step 116, step 118 is to terminate the method 1. The fabrication of the integrated circuit _ 1 〇〇 facilitates the formation of an ultra-thin gate dielectric layer, and can reduce the leakage current and the mobility of the charge carriers in the channel (4). Although the present invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and it is to be understood that those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. The protection of the present invention 57 200845232 The scope of the patent application is defined by the scope of the patent application. In order to make the above-mentioned features of the present invention more comprehensible, the present invention may be described in conjunction with the reference embodiments, and the drawings are illustrated in the accompanying drawings. It is noted that although the attached drawings illustrate certain embodiments of the present invention, they are not To clarify the spirit and scope of the present invention, any one of ordinary skill in the art can make various modifications and alternatives. Ο Figure 1A (previous technique) shows the cross section of the FET, and can be based on The invention is produced. Figure 1B (previous technique) is a nitrogen concentration distribution diagram of a conventional thermal nitridation process and a conventional plasma nitridation process according to secondary ion mass spectrometry data. FIG. 2A is a diagram according to the present invention. The embodiment shows a flow chart for fabricating a gate dielectric layer of a field effect transistor. FIG. 2B is a flow chart showing the fabrication of a gate dielectric layer of a field effect transistor according to an embodiment of the invention. 2C is a flow chart showing the fabrication of a gate dielectric layer of a field effect transistor according to an embodiment of the invention. FIG. 2D is a diagram showing the fabrication of a gate of a field effect transistor according to an embodiment of the invention. Flow chart of the dielectric layer. Figure 2E is based on One embodiment of the invention shows a flow chart of manufacturing a gate dielectric layer of a field effect transistor. FIG. 2F is a diagram showing the fabrication of a gate dielectric layer of a field effect transistor according to an embodiment of the invention. 58 200845232 Figures 3A-3F are a series of substrate profiles on which the gate structure fabricated using the method of Figure 2A. Figure 4A illustrates a plasma processing chamber in accordance with another embodiment of the present invention. Fig. 4B is a cross section of a plasma processing chamber according to still another embodiment of the present invention. Fig. 4C is a cross section of a plasma processing chamber according to still another embodiment of the present invention. (%ί 4D is According to an embodiment of the present invention, a theoretical calculation table for various properties of the target and the target is described. Figure 4 is a graph of self-bias voltage versus frequency for a capacitively coupled plasma processing chamber in accordance with an embodiment of the present invention. Figure 4F is a cross-sectional view of a plasma processing chamber in accordance with an embodiment of the present invention. Figure 4G is a cross-sectional view of a plasma processing chamber in accordance with an embodiment of the present invention. Figure 4 is a cross-sectional view of a plasma processing chamber in accordance with an embodiment of the present invention. Figure 41 is a cross-sectional view of a plasma processing chamber in accordance with an embodiment of the present invention. Figure 4J depicts a side view of a high-k dielectric layer formed on the surface of a substrate as described in one embodiment of the invention. Figure 4K is a diagram of the concentration in Figure 4J versus the depth in the high-k dielectric region of the substrate in one embodiment of the invention. 59 200845232 Figure 4L is a side elevational view of a high-k dielectric layer formed on a surface of a substrate as described in one embodiment of the invention. Figure 4M is a diagram of the concentration in the 4L image versus the depth in the high-k dielectric region of the substrate in one embodiment of the invention. Figure 4N is a side elevational view of a high-k dielectric layer formed on a surface of a substrate as described in one embodiment of the invention. Figure 40 is a graph showing the concentration in the 4N figure versus the depth in the high-k dielectric region of the substrate in one embodiment of the invention. fX Figure 4P illustrates modular data used in accordance with an embodiment of the present invention. Figure 5A is a timing diagram showing the interrupted cycle of pulsed RF/VHF excitation energy and pulsed DC voltage applied to the target in accordance with another embodiment of the present invention. Figure 5B is a timing diagram showing the interrupted cycle of pulsed RF/VHF excitation energy and pulsed DC voltage applied to the target in accordance with yet another embodiment of the present invention. Figure 5C is a timing diagram showing the interrupt cycle of the pulsed DC voltage applied to the target and the continuous RF/VHF energy, in accordance with yet another embodiment of the present invention. Figure 6A is a flow chart showing a method 100 of fabricating a gate dielectric layer of a field effect transistor in accordance with an embodiment of the present invention. Fig. 6B-6G is a series of substrate cross-sections on which the gate structure fabricated by the method of Fig. 6A is used. FIG. 7 illustrates an integrated processing system in accordance with an embodiment of the present invention. 60 200845232

Ο [Main component symbol description] 10 transistor 12 substrate 13 junction 14 dielectric layer 16 gate electrode 18 spacers 11, 24 curve 100 method 200 substrate 204, 206 oxide layer 208 metal layer 209 metal sub-layer 210 Electrical region 214 nitride layer 216 sub-layer 251 Procedure 401 Substrate 401 A, 402 Oxide layer 401 Β Surface 403, 404 Dielectric layer 405 Region 406 Polysilicon layer 407 Metal layer 408 Gate region 420 Surface 421 Path 500, 5 0 1 Processing Room 502 substrate 504 feed port 505, 5 7 1 target 506 coaxial cable 507 power supply 508, 523, 565 generator 508A, 524A, 565A 508 Β, 509 coil 510 pump 511 throttle valve 522 processing area 524, 525 RF Source 526 Switcher 527 Room Bottom 528 Chamber Wall 529 Chamber Cover 531 RF Energy 532 DC Pulse 533 RF/VHF Pulse Matcher 61 200845232 Ο 535 DC Voltage 540A Hole 561 Temperature Controller 562A Support Member 572 Insulation 5 8 0 Magnetic Control assembly 582 magnetron actuator 591 RF source assembly 593, 596 process chamber assembly 595, 597 VHF source assembly 602 controller 605A-605D load port 610 transmission 613A Blade Assembly 6 1 3 C Drive Assembly W Substrate 540 Collimator 550 Gas Delivery System 562 Support 570 Back Plate Assembly 573 Target Assembly 581 Magnetron 5 83 Magnet, 592 DC Source Assembly 594 Substrate Support Assembly 600 System 6 04 Working interface 606A, 606B Load lock chamber 613 Robot arm 6 1 3 B Robot arm assembly 614A-614F Process chamber A Modification material 62

Claims (1)

200845232 X. Patent Application Range: 1. A method for forming a semiconductor device, comprising at least forming a dielectric layer having a predetermined thickness on a substrate, a first content of a first material to the dielectric layer Internally, the first material of the thickness of the dielectric layer formed by the through portion is filled with a content of the second material into the dielectric layer, and the thickness of the dielectric layer formed by the through portion is Diluting and depositing a third material on the dielectric layer. 2. The method of claim 1, further comprising annealing the substrate between 800 ° C and about 1100 ° C. 3. The method of claim 1, wherein the thickness is less than about 40 Angstroms. 4. The method of claim 1, wherein the first plating material is placed in the dielectric layer by a plating process, and the energy sputtering process comprises a first radio frequency (RF; radio frequency and a first RF power to provide a radio frequency energy to a processing region of a chamber such that the first material of a target is centered on the surface; forming an at least gradient; forming an at least gradient; The method of claim 1, wherein the first layer of the second material is used in the method of claim 1, wherein the dielectric layer is a low energy source and the low frequency is low energy. A group consisting of aluminum, zirconium, titanium, niobium, tantalum, niobium, lead and niobium is selected. 6. The method of claim 1, wherein the dielectric is at least one material selected from the group consisting of cerium oxide, oxidic acid, hafnium silicate oxide, and is acid. A group consisting of ruthenium, osmium, iridium oxide, and aluminum oxide. The method of claim 1, wherein the first given 'and the concentration of the first material in the dielectric layer is less than about 3 atomic percent; and the second material is Tantalum or aluminum, and the concentration of material in the dielectric layer is less than about 10 atomic percent. 8. The method of claim 5, further comprising exposing the ruthenium layer, the first material, the second material, and the third material to an environment, wherein the oxidizing environment uses a thermal oxidation process or An electric process. 9. The method of claim 3, wherein the third material comprises a material selected from the group consisting of polycrystalline samarium, tantalum, tantalum nitride, domain carbon nitride, H, nitrided, A group consisting of nitriding stone group, giving, Ming, Ming, and titanium, nickel, and titanium nitride. The material of the zirconium oxide and the yttrium oxide material is atomic %. The second dielectric oxidizing material package is described in Japanese Patent Application No. Hei. The low energy sputtering process comprises: ^ generating the RF energy by a first frequency, and the RF energy is delivered by an RF generator; the pulse generates a DC current voltage, and the DC voltage is from the DC source. The component is delivered to the target; and a system controller is used to synchronize the RF energy of the pulse with the DC voltage of the pulse. 11. The method of claim 1, further comprising forming Prior to exposing the surface of the substrate to a nitrogen-containing radio frequency plasma, a method of forming a semiconductor device, the method comprising: forming at least one dielectric layer having a predetermined thickness On a surface L) of a substrate; forming a high dielectric constant (high-k) dielectric layer having a predetermined thickness on a germanium-containing dielectric layer; placing a first content of the first material to the high k dielectric layer Forming a first concentration gradient of the thickness of the high-k dielectric layer formed by at least a through portion, wherein the first material is selected from the group consisting of ruthenium, osmium, aluminum, titanium, zirconium, hafnium, lead, niobium, and tantalum a group formed by; 65 200845232 placing a second amount of a second material into the high-k dielectric layer to form a second gradient of the thickness of the ancient "a dielectric layer formed by at least a through portion" Wherein the second material is a group consisting of ruthenium, free ruthenium, ruthenium, aluminum, titanium, erbium, bismuth, lead, antimony and bismuth; and a gate electrode material is deposited in the ancient < , the first material and the second material. 13. The method of claim 12, further comprising annealing the substrate between about 800 C and about 11 C. 14. The method of claim 12, wherein the high-k dielectric layer comprises a material selected from the group consisting of cerium oxide, oxidized ox, oxalic acid oxide, strontium aluminate, cerium oxide, oxidized. A group consisting of yttrium and alumina. 15. The method of claim 12, further comprising exposing the base or the formed germanium-containing dielectric layer to a radio frequency paddle containing nitrogen. 16 16 as claimed in claim 12 The method wherein the combined thickness of the germanium containing layer and the two k dielectric layers is less than about 4 Å. 1 7· If you apply for a patent scope! The method of claim 2, wherein the first electrical material is electrically conductive, and the concentration of the first material in the dielectric layer is less than about 30 atomic percent. 18. The method of claim 12, wherein the first material is ruthenium or osmium, and the concentration of the first material is less than about 10 atomic percent, or the second material is aluminum, and The concentration of the second material is less than about 10 atomic percent. f) 19. The method of claim 12, further comprising exposing the first material and the second material to an oxidizing environment, wherein the oxidizing environment uses a thermal oxidation process or a plasma oxidation process . The method of claim 12, wherein the gate electrode material comprises a material selected from the group consisting of polycrystalline germanium, germanium, tantalum nitride, carbon nitride, tantalum carbide, tungsten, and nitrogen. A group consisting of tungsten, tantalum nitride, niobium, aluminum, platinum, rhodium, cobalt, titanium, nickel, and titanium nitride. ϋ 67