TW200842704A - Method for performing jump and translation state change at the same time - Google Patents
Method for performing jump and translation state change at the same time Download PDFInfo
- Publication number
- TW200842704A TW200842704A TW96114889A TW96114889A TW200842704A TW 200842704 A TW200842704 A TW 200842704A TW 96114889 A TW96114889 A TW 96114889A TW 96114889 A TW96114889 A TW 96114889A TW 200842704 A TW200842704 A TW 200842704A
- Authority
- TW
- Taiwan
- Prior art keywords
- state
- transition
- transition state
- register
- address
- Prior art date
Links
Landscapes
- Executing Machine-Instructions (AREA)
- Storage Device Security (AREA)
Abstract
Description
200842704 九、發明說明: 【發明所屬之技術領域】 本發明係有關於具有轉換狀態變更的資料處理機制,尤指_ 種跳躍指令與轉換狀態變更操作能同時被執行的資料處理機制。 【先前技術】 於習知電腦系統中,資料與程式指令被儲存於可由一執行中 程式(亦即一處理程序(process))使用一虛擬位址或一實體位址來 加以定址之一記憶體儲存裝置中。於使用者模式(Userm〇de)中之 處理程序係使用虛擬位址來存取記憶體,而於核心模式(Kernei mode)中之處理程序則可使用虛擬位址或實體位址,當使甩虛擬位 址時,其必須被轉換為相對應之實體位址以存取該電腦系統中之 實體記憶體,此外,虛擬位址與實體位址之間的映射(mapping)s 完全地由核心模式處理程序(Kernel mode process)所控制,如此一 來’除非核心模式處理程序允許,否則的話,使用者模式處理程 序(User mode process)便不能存取記憶體。此記憶體位址轉換 (memory address translation)係由稱之為記憶體管理單元㈤咖町200842704 IX. Description of the Invention: [Technical Field] The present invention relates to a data processing mechanism having a transition state change, and more particularly to a data processing mechanism in which a jump instruction and a transition state change operation can be simultaneously executed. [Prior Art] In a conventional computer system, data and program instructions are stored in a memory that can be addressed by an executable program (ie, a process) using a virtual address or a physical address. In the storage device. The processing in the user mode (Userm〇de) uses virtual addresses to access the memory, while the processing in the kernel mode (Kernei mode) can use virtual addresses or physical addresses. When a virtual address is translated, it must be converted to the corresponding physical address to access the physical memory in the computer system. In addition, the mapping between the virtual address and the physical address is completely controlled by the core mode. Controlled by the Kernel mode process, this way, the user mode process cannot access the memory unless the core mode handler allows it. This memory address translation is called memory management unit (5)
Management Umt,MMU)的硬體裝置所執行,其允許實體記憶體 =間被動態地配置。酬上’使用者模式處理程序總是將轉換狀 態開啟(亦即賴虛擬位址),細,核心模式處難序則可選擇 性地將轉換狀態開啟(亦即制虛擬位址)或者將轉換狀態關閉 (亦即使时體位址)。經常執行之記憶齡_存取包含有擷取 程式指令以及讀取與寫入程式資料之操作。 6 200842704 理一外 ,時’崎職称_崎_物件所中斷且 換開啟狀態 式1。懈#_«调咖蝴=1處理常 吏用者模式處理程序中而欲處 邊電腦系統將切換至依據不同 輕換關·n — 城用丨月麵處於轉_啟狀綠 w奐關閉“下之核心模式處理程序(亦即―外部 …戈 以對貫體記憶體進行存取,所以在此—狀態下執行的好^;The hardware device of Management Umt, MMU) is executed, which allows physical memory = to be dynamically configured. The user mode handler always turns on the transition state (that is, the virtual address), and the core mode can selectively turn the transition state on (or virtual address) or convert it. The status is off (also the time body address). Frequently executed memory age_access includes operations for capturing program instructions and reading and writing program data. 6 200842704 The first time, the time of the 'saki job title _ saki _ object is interrupted and changed to open state. Lax #_«调咖花1=1Processing the user mode processing program and the computer system will switch to the different light switch ·n - the city is in the turn of the moon _ 状 green m 奂 off " The core mode handler (that is, the external...Go accesses the memory, so it is good to execute in this state);
料可_護以贼触,·且資料㈣能被_地管理,如此來貝, 可用貝體德體之_料致於造衫統 :細之下存取記憶體時,則具有不消耗着 、在线錯誤或開機時不需準備和依賴任何轉換資訊,以 及糟由略賴有必須_齡咖增加記,_存取魏等等的優 點。既然轉換開啟狀態與轉換關閉狀態有其各自優點,作業系統 。主要之核。模式#式便有需要於不同的使職況下選擇於轉換 開啟狀態或轉換關閉狀態中執行。 、 於習知系統中’當-中斷發生時,轉換狀態係為首先更新至 -預疋轉雜祕’該系、纟雄著便等待此—讎狀態變更 (translation statechange)e,^^^,tmtfL, , (jump) 至使用新縣狀態下之核心料巾_理財(Kemd撕心 interrupthandlingp零am)。上述操作的過程係内含於第i圖中指 示從轉換開啟狀態⑽)切換到轉換關閉狀態⑽)的,,中斷,, 指不線(102)中。如第1圖所示,預定之新的轉換狀態係為轉換 關閉狀態。 7 200842704 • 帛1圖係為電腦系統之核心模式程式中-正常中斷處理 的流程圖,其依據習知技術㈣電·統基於記憶體f理單: 轉制啟狀態與轉侧職態的不_執行的不同步驟分置於卢 右兩攔中。該正常中斷處理程序包含以下步驟: 、二 步驟則:執行使用者模式下之程式資料處理,讀接收到—中 步驟102:由硬體接受該中斷,從使用者模式轉換至核傳式,盘 從轉換開啟狀態切換至轉換_狀態,並於轉換關閉 • 狀態下開始擷取核心模式程式; 步驟腿:於轉換關狀態之下,進行核心模式的程式指令操㈣ 資料處理; 步驟1〇5 ·由肖心板式程式指令將轉換狀態變更至轉換開啟 態; 步驟浙:執行-指令以等待轉換狀態變更的運作執行完成; 步驟辦:跳躍t需要於轉換開啟狀態下執行(操取指令,讀取/ ⑩寫入貢料)之核心模式程式; 理; 步驟⑴:於轉制啟狀態之下,執行好核心模式的程式資料處 步驟115 :由一核心模式鞀今4t 、T八和令來將轉換狀態變更至轉換關閉狀 態; 步驟117 :執行一指令以箄拄 寺待轉換狀態變更的運作執行完成; 步驟119 :跳躍(返回)至靈| 专於轉換關閉狀態下執行(擷取指令,讀 取/寫入資料)之核心模式程式; 步驟123 ·於轉換關閉狀熊 〜下’執行更多核心模式的程式資料處 200842704 理; 步驟核心模式下的程式中斷處理返回至被中斷之使用者模 式的程式; v驟I27 .於雜換開啟模式之下,自中斷點之後繼續進行使用者 模式的資料處理。 田系、洗□ $巾Μ事件而移至核心模式下進行程式資料處理 鲁犄(步驟1〇3),轉換狀態係先被變更至一轉換關閉狀態以便能順利 的進行-使用者模式至一核心模式的切換。在轉換關閉狀態 下田於某些貧料處理完成之後,便有需要執行(呼叫)一些需於轉 換開啟狀您之下執行的函式,所以,此時—連串之習知個別操作 乎啊更由矛王式指令所執行以完成此函式。首先,一指令被用於變 更雜換狀悲從轉換關閉狀態至轉換開啟狀態(步驟1〇5),然後, 於執行函式呼叫步驟(步·驟1〇9中之跳躍指令)之前,一特定指令先 ⑩被細崎硬體祕科轉換狀態已完成變更之確認訊息(步驟 實際上,步驟1〇9中的跳躍指令不需要於轉換開啟狀態下執 二然而,因為步驟109中的跳躍指令無法保證步驟113中的指 7係處於轉換開啟狀態之下,為了破保步驟⑴的程式指令娜 ,、的於轉換開啟狀態下來開始執行,步驟浙中之指令必需先於 步驟109中的跳躍指令之前來執行。 • 於習知方法下,步驟浙與步驟1〇9中的指令需要其指令位 . 蚊轉映射(記憶體管理單元的位址轉換單元使虛擬位址等於實 9 200842704 库Γ由取這些指令時’它們所處轉換狀態可依據 …、的州情況而為開啟或_,所以不能明確地被判定。第 1圖中的步驟1〇7(鱼步 雜制錄態與轉換It can be protected by thieves, and the information (4) can be managed by _, so come to the shell, you can use the body of the body to make the shirt: when accessing the memory under the fine, it does not consume There is no need to prepare and rely on any conversion information when online error or booting, and the advantages of having to rely on _ age coffee increase, _ access Wei and so on. Since the conversion on state and the conversion off state have their respective advantages, the operating system. The main core. The mode # type needs to be selected in the transition on state or in the transition off state under different conditions. In the conventional system, when the 'when-interruption occurs, the transition state is first updated to - pre-twisted and miscellaneous', and the system waits for this - translation statechange e, ^^^, tmtfL, , (jump) to the use of the core of the new county towel _ wealth management (Kemd tearing interrupthandlingp zero am). The above-described operation is included in the i-th diagram indicating switching from the switching-on state (10) to the switching-off state (10), and the interruption is indicated in the line (102). As shown in Figure 1, the predetermined new transition state is the transition off state. 7 200842704 • 帛1 diagram is the core mode program of the computer system - the flow chart of normal interrupt processing, based on the conventional technology (4) electric system based on the memory f single: the turn-on state and the turn-side position are not _ The different steps of execution are placed in the two blocks of Lu You. The normal interrupt processing program includes the following steps: Step 2: Execute the program data processing in the user mode, read and receive - in step 102: accept the interrupt by the hardware, switch from the user mode to the nuclear transfer mode, Switch from the conversion on state to the conversion state, and start to capture the core mode program in the conversion off state. Step leg: Under the conversion off state, perform the kernel mode program instruction operation (4) Data processing; Step 1〇5 · The conversion state is changed to the transition open state by the syllabic program command; Step: The execution-instruction waits for the execution of the conversion state change to be completed; Step: The jump t needs to be executed in the conversion-on state (fetch instruction, read / 10 write tribute) the core mode program; rational; step (1): under the transition state, execute the core mode of the program data step 115: by a core mode 鼗 4t, T eight and order will be converted The status changes to the conversion off state; Step 117: Execute an instruction to complete the operation of the change of the state to be converted; Step 119: Jump (return) ) to the spirit | specializes in the conversion of the closed state of the implementation (take instructions, read / write data) of the core mode program; Step 123 · in the conversion off the bear ~ down 'execute more core mode of the program information at 200842704 The program interrupt processing in the step core mode returns to the interrupted user mode program; v. I27. In the miscellaneous switching mode, the user mode data processing is continued from the interruption point. The field system and the washing machine are moved to the core mode to process the data processing (step 1〇3), and the conversion state is first changed to a conversion-off state so that the user can smoothly proceed. Switching to the core mode. After the conversion is turned off, after some of the poor materials are processed, there is a need to execute (call) some functions that need to be executed under the conversion open, so at this time - a series of conventional operations are more Executed by the Spearman instruction to complete this function. First, an instruction is used to change the mismatched transition state to the transition-on state (step 1〇5), and then, before performing the function call step (the jump instruction in step 1〇9), The specific instruction first 10 is confirmed by the change of the state of the subsidiary hardware. The step is actually that the jump instruction in step 1〇9 does not need to be executed in the conversion open state, however, because the jump instruction in step 109 cannot be performed. It is ensured that the finger 7 in step 113 is in the state of being switched on, in order to break the program command of step (1), the execution of the step is started in the state of the transition, and the instruction in the step must be preceded by the jump instruction in step 109. To perform: • Under the conventional method, the instruction in step Zhejiang and step 1〇9 requires its instruction bit. Mosquito-to-mapping (the address management unit of the memory management unit makes the virtual address equal to real 9 200842704 In these instructions, 'the transition state they are in can be turned on or _ depending on the state of ..., so it cannot be determined explicitly. Step 1〇7 in Figure 1 (fishing stray recording and conversion)
關閉狀心之左右兩攔之間,用絲示此時轉換狀態 理論^使這雜令__於其齡位址上Μ行的,但實際 省娜實仃,戏’如此作將使得_轉換關閉狀態以節 沾官理單元之轉換資源的功能失效;此外,因為這些指令 _換步驟必須被予以執行,程式的執行效率將會降低;另外, 映射記憶體管理機制,如此作則很難管理記 門要於轉換開啟狀tT執行之函式返回至需要於轉換關 閉狀您中執狀呼叫函式時,同樣地,—連串之習知指令需要被 、細17及麵叫,__與步驟 19中之‘令而^同樣具有指令位址恆等映射的需求。 【發明内容】 _有鑑於此’本發明的目的之一在於提供一種關於跳躍與轉換 狀悲虻更的方法,以解決習知技術之問題。 、 因此’本m實施難揭露—種方法,其包含··於一 ,換狀態中執行-第一函式中之—連串指令;以及執行—跳躍指 ?以跳躍至-第二函式中—目標位址並在同—時間啟動且完成一 10 200842704 •轉換狀態變更以切換至-第二轉換狀態;其中,於—第—Close the left and right between the two stops, use the silk to show the state of the transition state at this time ^ make this miscellaneous __ on the site of its age, but the actual economy is sturdy, the play 'so will make _ conversion The shutdown state disables the function of converting resources of the official unit; in addition, because these instructions must be executed, the execution efficiency of the program will be reduced; in addition, the mapping memory management mechanism is difficult to manage. When the function of the conversion open tT execution is returned to the function of the call function that needs to be turned off, the same sequence of conventional instructions needs to be, fine 17 and face called, __ and step In 19, the command also has the requirement of an immutable mapping of the address. SUMMARY OF THE INVENTION One of the objects of the present invention is to provide a method for jumping and transitioning grievances to solve the problems of the prior art. Therefore, 'this m implementation is difficult to expose - a method that includes · in one, in the state of execution - in the first function - a series of instructions; and execution - jump refers to jump to - in the second function - the target address is started at the same time and completed a 10 200842704 • The transition state is changed to switch to the second transition state; wherein, at - the first
中儲存該跳躍指令之後—下-指令之—位址以作為-返回U 本發明之另-實施例包含:於—第—轉換狀態中執行一第一 函式中連串指令;執行一跳躍指令以跳躍至-第二函式中一目 Μ立止並在同4間啟動且完成—轉換狀態變更以切換至一第二 轉換狀態;於—第—暫存器中儲存該跳躍指令之後之—下一指令 •之;;位址以作為—返回位址;於—第二暫存器中儲存該第-ϋ 狀態作為-返回轉換狀態;以及於執行該第二函式中一連串指令 找,行—返邮令峨該第—暫存ϋ巾擷取該返回位址 從該第二暫存器中擷取該返回轉換狀態,啟動及完成—轉換狀態 變更以切換至該返_換狀態及同—_卿至該返回位址。 【實施方式】 • 本發明的目的在於同時執行跳躍與轉換狀態變更的操作以提 供更有效率的轉換狀態變更管理,本發明亦可消除作業系統核心 程式的記«位_換_管理所遭遇之恆等位址映射的需求/問 題。本發明作法將由下述實施例與附屬說明來加以敘述。 於所揭露的第-實施例中,本發财法係提烟於同時袖 跳躍與轉換狀態變更的操作(第2圖中的步驟205與步驟2⑹ 於核心模式中斷處雜序巾(其雜帽切換細㈣_ fsiti〇n)2〇2已發生之後,從步驟2〇3開始執行),記憶體管理^ 200842704 下執二t㈣初係為轉換關陳態’然後,於該轉換關閉狀態 ^連串核心模式的指令處理之後,有必要予以呼叫(跳躍 的跳躍/Γ2執行於轉換開啟狀態下之核心函式,因此,本發明 h仏令(步驟則此時便被執行予以完成函式呼叫程 t其幅躍/呼叫指令於執行時會同時完成—轉換狀態變更以切 人將3二轉換狀態與跳躍至—目標位址。本翻之跳躍/呼叫指 7將儲存跟隨此跳躍/呼叫指令之後下—指令的位址至一暫存器 2作-鏈結暫存器Ginkregister)),用於之後作為一跳躍/返回指 =返回目標她;糾,本剌之卿呼叫齡祕儲存一原 好·(亦即第2圖中之轉換咖狀態)於—轉換狀態堆叠 匕子球ansition state stack register)中以便後續作為一跳躍/返回 指令的返回目標轉換狀態。After storing the jump instruction - the address of the instruction - the address is taken as - returning U - another embodiment of the invention comprises: executing a series of instructions in the first function in the - transition state; executing a jump instruction Jump to - the second function in a second function and start and complete in the same 4 - switch state change to switch to a second transition state; after the - the first register stores the jump instruction - the next An instruction; the address is used as the return address; the second temporary register stores the first - state as a - return transition state; and in the execution of the second function a series of instructions are found, the line - Returning to the mail order, the first temporary storage mask retrieves the return address from the second temporary register, and initiates and completes the transition state change to switch to the return state and the same _ Qing to the return address. [Embodiment] It is an object of the present invention to simultaneously perform operations of jump and transition state change to provide more efficient transition state change management, and the present invention also eliminates the problem of the "bit_change_management" of the core program of the operating system. Requirements/problems for identity mapping. The invention will be described by the following examples and accompanying description. In the disclosed embodiment, the present financing method is an operation for simultaneously changing the sleeve jump and the transition state (step 205 and step 2 (6) in the second figure are interrupted at the core mode. Switch fine (4) _ fsiti 〇 n) 2 〇 2 has occurred, starting from step 2 〇 3), memory management ^ 200842704 under the second two (t) first is the conversion off state 'then, then in the conversion off state ^ series After the command processing of the core mode, it is necessary to call (the jump jump / Γ 2 is executed in the core function in the transition open state, therefore, the present invention is executed (the step is executed at this time to complete the function call procedure t The hop/call command is completed at the same time as the execution - the transition state is changed to switch the 2-3 transition state to the target address. The hop/call finger 7 will be stored following this hop/call command. - the address of the instruction to a register 2 - link register Ginkregister)), used as a jump / return finger = return to the target her; correct, BenQ Zhiqing call the age of the secret storage a good (that is, the conversion coffee in Figure 2) The state is in the - state transition state stack register) for subsequent return state conversion as a jump/return instruction.
本發明之跳躍/呼叫指令方法可避免習知技術中所提及之怪等 映射所造成關題,既鋪絲胁娜卿/糾齡的過程中 未曾變更,義躍/呼叫指令之指令位址便沒有轉換與否的問^, ^可使用先前齡之同-轉触餘縣進行轉換以使跳躍/呼叫 $令可正確地執行。當本發狀卿/呼叫指令完稱,轉換狀離 錢的操作則必定會完成’ _於擷取目標齡之記憶體管理單 元所執行的轉換狀態亦可明確地決定出來。所以,於執行本發明 之跳躍/呼叫指令時便沒必要為了跳躍/呼叫指令於執行過程中天的 轉換狀㈣更而建立-虛齡址等於—實體位址之轉換映射。、 12 200842704 需要於轉換開啟狀態 中 執行的第二核心函式中的指令便可步 連串之指令處理完成時,此财㈤213),當此一 謝執轉-核心函式=有需要獅至必須於轉換關閉 程序(步 態變更 疊暫存器 :切=返回的原始轉換狀態並跳躍至原始函式中之: 二rtr址由本發明之跳躍/返回指令從該鏈結暫存器中所 倾操取出t回的原始轉換狀態也同時自該轉換狀態堆 本^之卿/相指令方法可避免習知技術巾所提及之恒等 未=成=:然轉換狀態於擷取跳躍/返回指令㈣^ …^躍/返回指令之指令位址便沒有轉換與否的問 、的二 前齡之同—轉触微絲猜轉換以使跳躍/ 可t確地執行。當本發明之跳躍/相指令完成時,轉換 崎作必定會完成,且祕擷取目標返回指令之記憶體 官理单=所執行的轉換亦刊確地_來。所以,於執行树 明之跳躍:返回指令時便沒必要為了跳躍/返回指令於執行過程中Χ 的轉換狀_更而建立—虛擬位址等於—實體位址之轉換映射。 明茶考第3圖’第3圖顯示三個子圖3Α、3Β與3C,其分別 對應於本發明之第—實施例、第二實施例與第三實施例。於此第 13 200842704 結暫存器301係以單 一貫施例巾,轉換狀態堆疊暫存H 303與鏈 獨的暫存絲分別實作(第3A圖)。 二=施例巾’轉換錢堆4暫如可_鏈結指標暫存 =儲存於相位址之較低侃(未使祕元)巾,因此,當返 立址被存取時,則返回轉換狀態亦可同時被存取。 =本發__三實_中’細_封於鍵結指 不暫存請之較高位元中予以實作(第3c圖),亦即轉換狀離 的編碼可儲存於返回位址之較高位元(未使用位元)中,因此Γ =返龍址被存取時,則返_換狀__會被存取。值得注 思的是,上述兩個實施例均符合本發明之精神。 第2圖係為本發财法朗於電腦核中核心模式程式之中 斷處理程序之-#施_流賴,其雜基於記憶齡理單元之 轉換開啟狀_賴_狀態料_執行的柯步驟分置於左 右兩襴。本發明方法包含以下步驟·· 步驟20丨:於使用者模式下進行程式資料處理與接收一尹斷; 步驟皿:硬體接受該情,從使用者模式城至核心模式,從轉 換開啟狀_換為轉換關閉狀態,並於轉換關閉狀態 下開始操取核心模式程式; 14 200842704 步驟203 :於轉換關閉狀態之 處理;了如核心㈣的程式齡擷取與 步驟205 :於轉換開啟模式下 丁 H 跳路(呼叫)至需於轉換開啟狀態 下^丁(擷取指令、讀取/寫入資料)之核心模式程式, 保轉換狀錢更會跟著跳躍操作_完成; 步驟213:於轉換_礙下,執行更多核心模式的程式資料處 Ϊ里,The jump/call instruction method of the present invention can avoid the problems caused by the strange mapping mentioned in the prior art, and the instruction address of the Yiyue/call instruction is not changed during the process of laying the threatening Naqing/correcting the age. If there is no conversion or not, ^ can use the previous age-to-touch Yuxian to convert so that the jump/call $ order can be executed correctly. When the hairline/call command is completed, the transfer of the money transfer operation will be completed. _ The conversion status performed by the memory management unit of the target age can also be clearly determined. Therefore, when performing the jump/call command of the present invention, it is not necessary to establish a transition map of the virtual address equal to the physical address for the transition/call instruction in the execution process. , 12 200842704 The instruction in the second core function that needs to be executed in the conversion open state can be completed when the instruction processing of the series is completed, this financial (five) 213), when this is a thank-to-core function = there is a need for the lion to The program must be closed (the gait change stack register: cut = return the original transition state and jump to the original function: the second rtr address is dumped from the link register by the jump/return instruction of the present invention The original conversion state of the t-return is also at the same time. From the state of the transition state, the method of the phase/phase command can avoid the constants of the conventional technology towel not ===: the transition state is in the jump/return command (4) ^ ... ^ jump / return instruction instruction address is not converted or not asked, the second two years of the same - touch the microwire guess conversion to make jump / can be executed exactly. When the jump / phase of the present invention When the instruction is completed, the conversion will be completed, and the secretary will take the memory of the target return instruction. The executed conversion is also reported. Therefore, in the execution of the jump, it is not necessary to return the instruction. In order to jump/return instructions during executionΧ The conversion pattern _ is more established - the virtual address is equal to - the conversion mapping of the physical address. The tea chart 3 of the Ming tea test 3 shows three sub-pictures 3 Α, 3 Β and 3 C, which respectively correspond to the first embodiment of the present invention The second embodiment and the third embodiment. The 13th 200842704 junction register 301 is a single consistent embodiment towel, and the conversion state stacking temporary storage H 303 and the chain storage temporary storage wire are respectively implemented (Fig. 3A) 2 = Example towel 'converting money pile 4 temporarily _ link indicator temporary storage = stored in the lower phase of the phase address (not secret) towel, therefore, when the return address is accessed, then Return to the conversion state can also be accessed at the same time. = This issue __ three real _ middle 'fine _ sealed in the key node refers to not temporarily stored in the higher bit to be implemented (3c), that is, the transition The code can be stored in the higher bit (unused bit) of the return address, so when the return address is accessed, the return___ will be accessed. It is worth noting that the above Both embodiments are in accordance with the spirit of the present invention. The second figure is the interrupt processing procedure of the core mode program in the computer core - #施_流赖The method according to the present invention comprises the following steps: Step 20: Performing program data processing in the user mode is performed on the left and right sides of the memory-based unit. Receiving a Yin broken; Steps: The hardware accepts the situation, from the user mode city to the core mode, from the transition open state to the transition closed state, and starts to operate the core mode program in the transition closed state; 14 200842704 203: processing in the conversion off state; the program age acquisition as in the core (four) and step 205: in the conversion on mode, the D jump (call) to the need to switch on the state (read instruction, read) / write data) the core mode program, the conversion of the money will follow the jump operation _ complete; Step 213: under the conversion _, execute more core mode of the program data,
步驟216 :經由所儲存之先前轉_ (亦即轉換關閉狀態)跳躍 (返回)至需於轉換關閉狀態下執行的核心模式程 以確保賴狀態變更會跟卿操作同時完成; 步驟223 :於轉換關閉狀態之下,執杆 轨仃更夕核心梹式的程式資料處 理; 步驟奶:從核心模式程式之中斷處理程柄回至被中斷之使用者 模式程式; 步驟227:於轉換開啟模式之下,從中斷點之後繼續執行使用者模 式的資料處理。 ' 本發明之弟四貫歸㈣要換狀態堆疊暫存哭,於 此實施例巾,其假定先前雛狀態係為已知的,因此,如果一跳 躍操作係於轉換開啟狀態下執行,則一认絲 狀心下執行;相仿地,如果-跳職作係於轉換騎狀態下執行, 則一返回操作必定於轉換開啟狀態下執行。 15 200842704 • 於本發明之第五實施例巾’電腦緖巾之記憶體管理單元可 以有個別的指令擷轉換狀態與㈣存取娜狀態,於此一實施 例中’轉換狀態將包含指令轉換狀㈣訊與f料轉換狀態資= 者,而可被瞭解的是這些資訊沒有必要儲存於鏈結指標暫存哭之 同一部份中,請注意,此僅為—範例制,而本發明料祕此。 以上所述僅為本發明之較佳實施例,凡依本發明申請專利範 • 目所做之均等變化與修都,皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知使用記憶體管理單元轉換開啟與關閉狀態之電腦系 統中核心模式程式之中斷處理程序中所執行之方法的流程 圖。 弟2圖為=發明—實施例之使用記憶體管理單元轉換開啟與關閉 狀態之電腦系統中核心模式程式之中斷處理程序中所執行 之方法的流程圖。 第3A圖為本㈣暫存雜構之第-實施例的示意圖。 弟3B圖為本發明暫存器架構之第二實施例的示意圖。 弟3c圖林發晴存轉構之红實關的示賴。 【主要元件符號說明】 301 303^ 鏈結暫存器 16Step 216: Jump (return) to the core mode that needs to be executed in the conversion off state via the stored previous transition_ (ie, the transition off state) to ensure that the Lai state change is completed simultaneously with the clear operation; Step 223: Converting In the closed state, the program is processed by the core program of the master track; step milk: returning from the interrupt processing handle of the core mode program to the interrupted user mode program; Step 227: under the conversion open mode , continue to perform user mode data processing from the point of interruption. The fourth embodiment of the present invention (four) is to change the state stack to temporarily store crying, in this embodiment towel, it is assumed that the previous state is known, therefore, if a jump operation is performed in the transition-on state, then one The silk-like heart is executed; similarly, if the jump-to-job operation is performed in the transition riding state, a return operation must be performed in the transition-on state. 15 200842704 • In the fifth embodiment of the present invention, the memory management unit of the computer computer can have an individual command conversion state and (4) access state. In this embodiment, the conversion state will include a command conversion state. (4) The information and the conversion status of the f-materials are the same, but it can be understood that the information does not need to be stored in the same part of the link indicator temporary crying. Please note that this is only the example system, and the invention is secret. this. The above is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the patent application of the present invention are within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing a method executed in an interrupt processing program of a core mode program in a computer system that converts an open and a closed state using a memory management unit. Figure 2 is a flow chart of the method performed in the interrupt handling routine of the core mode program in the computer system for converting the open and closed states using the memory management unit. Fig. 3A is a schematic view showing the fourth embodiment of the (iv) temporary storage. Figure 3B is a schematic diagram of a second embodiment of the register architecture of the present invention. Brother 3c Turin sent a clear and transferred to the red real customs of the show. [Main component symbol description] 301 303^ Link register 16
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW96114889A TWI334572B (en) | 2007-04-27 | 2007-04-27 | Method for performing jump and translation state change at the same time |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW96114889A TWI334572B (en) | 2007-04-27 | 2007-04-27 | Method for performing jump and translation state change at the same time |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200842704A true TW200842704A (en) | 2008-11-01 |
TWI334572B TWI334572B (en) | 2010-12-11 |
Family
ID=44211983
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW96114889A TWI334572B (en) | 2007-04-27 | 2007-04-27 | Method for performing jump and translation state change at the same time |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI334572B (en) |
-
2007
- 2007-04-27 TW TW96114889A patent/TWI334572B/en active
Also Published As
Publication number | Publication date |
---|---|
TWI334572B (en) | 2010-12-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI373769B (en) | Block management method for flash memory and storage system and controller using the same | |
TWI477967B (en) | System and method for implementing gpu accelerated address translation and graphics processor | |
CN102033734B (en) | Data processing engine | |
CN103871447A (en) | NAND flash memory array, NAND flash memory chip, and methods for accessing, reading and managing NAND flash memory array | |
TW200816001A (en) | System and method for garbage collection in heterogeneous multiprocessor systems | |
TW200525355A (en) | Microprocessor and apparatus for performing speculative load operation from a stack memory cache | |
TW201246064A (en) | Multilevel conversion table cache for translating guest instructions to native instructions | |
TWI223756B (en) | Automatic register backup/restore system and method | |
JP2000231549A (en) | Microprocessor | |
CN100504799C (en) | Method for snapping magnetic disc using snap index | |
TW201033897A (en) | Microprocessor, and methods for initializing a microprocessor | |
TW200921385A (en) | Storage system for improving efficiency in accessing flash memory and method for the same | |
JP2000339210A (en) | Data base copying device, data base copying method and recording medium in which data base copying program is recorded | |
JP2001034537A (en) | Address converting circuit | |
CN104657239B (en) | Polycaryon processor transient fault recovery system and its transient fault restoration methods based on separate type daily record | |
TW518460B (en) | Thread-oriented debugging | |
TWI332627B (en) | Method and electronic apparatus for micro-code execution | |
TW200842704A (en) | Method for performing jump and translation state change at the same time | |
TWI261197B (en) | Method for finding function call stack in run time for a computer system | |
TWI733741B (en) | Apparatus and method for memory address translation management | |
JP2001265620A (en) | Program debugging system for rom | |
JP2000231550A (en) | Microprocessor | |
TWI230899B (en) | Processor and method using parity check to proceed command mode switch | |
JP2552738B2 (en) | Data processing device | |
CN104156241B (en) | The initiated configuration method and system of processor microprogram |