CN104657239B - Polycaryon processor transient fault recovery system and its transient fault restoration methods based on separate type daily record - Google Patents
Polycaryon processor transient fault recovery system and its transient fault restoration methods based on separate type daily record Download PDFInfo
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Abstract
Polycaryon processor transient fault recovery system and its transient fault restoration methods based on separate type daily record, belong to field of computer technology.The problem of certainty fault recovery in order to solve polycaryon processor non-deterministic event lacks high-availability solution.The system includes：Separate type logger module, non-deterministic event information for recording corresponding kernel, will be recorded separately using the dependence of point-to-point to memory contention daily record, the first generation side of dependence is recorded in the answer party of consistency protocol, the rear generation side of dependence is recorded in requesting party, to outside interruption logging interrupt type and interrupt address；Separate type daily record controller module, the mapping relations for setting up log recording space and checkpointing；Recover hardware module, rollback recovery technology and Deterministic Replay technology for combining separate type daily record complete the certainty behind the checkpoint of transient fault and recovered.For polycaryon processor fault recovery.
Description
Technical field
The invention belongs to field of computer technology.
Background technology
The technology given priority in current high-effect trusted computer is System Fault Tolerance.Fault recovery is to eliminate fault recovery
And the important step for continuing to run with system.Only the purpose of System Fault Tolerance can be just achieved after fault recovery link.
Meanwhile, the polycaryon processor transient fault Restoration Mechanism of High Availabitity is conducive to widening multi-core processor chip in adverse circumstances meter
The application in numerous high reliability request fields such as calculation, Industry Control, digital medical, automatic intelligent instrument, mobile computing.
It is the fields such as parallel architecture, fault-tolerant calculation, system reliability design that polycaryon processor hardware fault, which is recovered,
Study hotspot.But for the certainty fault recovery of polycaryon processor non-deterministic event, it has been suggested that based on software and hardware
The technical method Performance And Reliability of recovery is difficult to meet actual demand, really can't effectively solve multi-core processor chip
Fault restoration problem, lacks the solution of high availability non-deterministic event transient fault recovery.
The content of the invention
Certainty fault recovery the invention aims to solve polycaryon processor non-deterministic event lacks height can
The problem of with property solution, the present invention provide a kind of polycaryon processor transient fault recovery system based on separate type daily record and
Its transient fault restoration methods.
The polycaryon processor transient fault recovery system based on separate type daily record of the present invention,
The system includes separate type logger module, separate type daily record controller module and recovers hardware module；
Embedded separate type logger module and recovery hardware module in each kernel of processor,
The separate type logger module, the non-deterministic event information for recording corresponding kernel, to memory contention
Daily record will be recorded separately using the dependence of point-to-point, and the first generation of dependence is recorded in the answer party of consistency protocol
Side, records the rear generation side of dependence, to outside interruption logging interrupt type and interrupt address in requesting party；
The separate type daily record controller module, the mapping relations for setting up log recording space and checkpointing；
The recovery hardware module, rollback recovery technology and Deterministic Replay technology for combining separate type daily record are complete
Recover into the certainty behind the checkpoint of transient fault.
The separate type logger module includes circulation and occurs the sequence first side's of generation register Pred_IIC, blank(ing) instruction
Counter IIC, circulation occur the side of generationing register Succ_IIC after sequence, overflow register OVF, N number of write sign WF and N number of reading
Sign RF；The N is the interior check figure of processor；
The sequence first side's of generation register Pred_IIC occurs for circulation, for marking non-deterministic event to be first generation side；
Blank(ing) instruction counter IIC, the blank(ing) instruction count value of event is recorded for recording adjacent uncertainty；
Generation side register Succ_IIC after sequence occurs for circulation, for marking generation side after non-deterministic event is；
Overflow register OVF, for marking the register size and non-deterministic event type that determine from record event,
First place is 0 expression memory contention, and first place represents to interrupt for 1, and second represents that, using the storage of 2B registers, second is 1 table for 0
Show using the storage of 4B registers；
N number of to write signature WF, for recording write conflict address set in N number of kernel memory contention, N number of kernel is recorded in interrupting
Interrupt jump address；
N number of to read signature RF, for recording read conflict address set in N number of kernel memory contention, N number of kernel is recorded in interrupting
Interrupt spot address.
Separate type daily record controller includes N number of reading signature address register and N number of writing signature address register；
It is N number of to read signature address register, for mapping N number of termination address for reading signature RF；
It is N number of to write signature address register, for mapping N number of termination address for writing signature WF.
The recovery hardware module includes N number of CP registers, N number of CS registers and an IIC register；
N number of CP registers, the count value for recording the wakeup message for being sent to a certain thread of other kernels；
N number of CS registers, the count value for recording the instruction blocked because of a certain thread of other kernels；
One IIC register, the blank(ing) instruction count value of event is recorded for recording adjacent uncertainty.
The transient fault restoration methods of polycaryon processor transient fault recovery system based on separate type daily record, methods described
Comprise the following steps：
Methods described comprises the following steps：
Step 1：When hardware check point starts storage, using separate type logger module, signature address register is read
Non-deterministic event information is recorded with signature address register is write；
Step 2：When being recovered from hardware check point module, kernel reads signature address register and writes signature ground
The information of location register record, terminates if the information that will be read exceedes address, otherwise performs step 3；
Step 3：16 information are read from memory contention daily record, reading 32 is needed if overflow register OVF has mark
Position information；Judge it is competition conflict or external interrupt according to the first in the information that overflow register OVF is read, if then competing
Conflict, performs step 4；If external interrupt, step 6 is performed；
Step 4：Overflow register OVF second information is read, judges it is first generation side or afterwards hair according to type types
Life side；If first generation side, the count value of the CP registers of kernel adds up, and the meter after instruction has been performed CP registers
Numerical value is sent to remaining kernel as wakeup message；If rear generation side, the count value of the CS registers of kernel adds up, wait until
The wakeup message that remaining kernel is sent performs this instruction again when identical with the count value of CS registers；
Step 5：Instruction perform after the completion of blank(ing) instruction counter IIC value add up, after wakeup message has been sent or
After receiving wakeup message and having performed instructions corresponding thereto, kernel repeats step 2；
Step 6：Read signature register and obtain and interrupt start address, the external equipment of interruption is called again, from writing label
Name register address starts to continue executing with；Kernel repeats step 2.
The process of the step 1 comprises the following steps：
Step one：When hardware check point module start storage when, the reading signature register of separate type log control module and
Signature register is write to reset；Separate type logger module start recording non-deterministic event information；It is interior when detecting conflict
When depositing competition, step 2 is performed；When it is external interrupt to detect conflict, step 5 is performed；
Step 2：Blank(ing) instruction counter IIC adds 1, when the value of the IIC is not less than 214When, stored from 4B registers
And made marks in overflow register OVF, otherwise from the storage of 2B registers；Overflow register OVF storages first place, which is marked, is,
Second includes first generation side or rear generation side as type described in the type mark of competition conflict, is transferred to step 3；
Step 3：The corresponding address of memory block that there will be memory contention is added to all reading signature register or writes label
Name register, occurs the sequence first side's of generation register Pred_IIC and circulation hair according to the type decision of competition conflict in circulation
Generation side register Succ_IIC does different marks after raw sequence, is transferred to step 4；
Step 4：Separate type log control module is updated to read signature register or write the IIC terminations of signature register record
Address, return to step one；
Step 5：Blank(ing) instruction counter IIC adds 1, when the value of the IIC is not less than 214When, stored from 4B registers
And made marks in overflow register OVF, be otherwise to turn from the first mark of 2B registers storage overflow register OVF storages
Enter step 6；
Step 6：The address that signature register preserves external interrupt is read, signature register is write and preserves the address redirected, be transferred to
Step 7；
Step 7：Update separate type log control module and read signature register and with writing the termination of signature register record
Location, return to step one.
The beneficial effects of the present invention are, separate type log recording mechanism is realized, non-deterministic event expense is reduced,
Concurrent resume speed is improved, more accurate certainty recovers the implementation procedure before transient fault occurs, improves high availability.
Brief description of the drawings
Fig. 1 is the polycaryon processor transient fault recovery system based on separate type daily record described in embodiment one
Principle schematic；
Fig. 2 is the principle schematic of the separate type logger module described in embodiment two；
Fig. 3 is the separate type daily record controller module described in embodiment four.
Fig. 4 is the principle schematic of the recovery hardware module described in embodiment three；
Fig. 5 be embodiment six in, the principle schematic of separate type logger module memory contention recording mechanism.
Embodiment
Embodiment one：With reference to Fig. 1 illustrate present embodiment, described in present embodiment based on separate type daily record
Polycaryon processor transient fault recovery system, the system includes separate type logger module, separate type daily record controller mould
Block and recovery hardware module；Embedded separate type logger module and recovery hardware module in each kernel of processor,
The separate type logger module, the non-deterministic event information for recording corresponding kernel, to memory contention
Daily record will be recorded separately using the dependence of point-to-point, and the first generation of dependence is recorded in the answer party of consistency protocol
Side, records the rear generation side of dependence, to outside interruption logging interrupt type and interrupt address in requesting party；
The separate type daily record controller module, the mapping relations for setting up log recording space and checkpointing；
The recovery hardware module, rollback recovery technology and Deterministic Replay technology for combining separate type daily record are complete
Recover into the certainty behind the checkpoint of transient fault.
Present embodiment illustrated exemplified by the processor chips of 4 cores there is provided transient fault restoration methods pin
To the polycaryon processor of frequent interactive information, separate type logger module is added in processor core and recovers hardware module,
Realize that the non-deterministic event of transient fault recovers.
Embodiment two：Illustrate present embodiment with reference to Fig. 2, present embodiment is to described in embodiment one
The polycaryon processor transient fault recovery system based on separate type daily record further restriction, the separate type log recording mould
Block includes circulation generation sequence, and first the side's of generation register Pred_IIC, blank(ing) instruction counter IIC, circulation occur to occur after sequence
Square register Succ_IIC, overflow register OVF, it is N number of write signature WF and N number of reading signature RF；The N is the kernel of processor
Number；
The sequence first side's of generation register Pred_IIC occurs for circulation, for marking non-deterministic event to be first generation side；
Blank(ing) instruction counter IIC, the blank(ing) instruction count value of event is recorded for recording adjacent uncertainty；
Generation side register Succ_IIC after sequence occurs for circulation, for marking generation side after non-deterministic event is；
Overflow register OVF, for marking the register size and non-deterministic event type that determine from record event,
First place is 0 expression memory contention, and first place represents to interrupt for 1, and second represents that, using the storage of 2B registers, second is 1 table for 0
Show using the storage of 4B registers；
N number of to write signature WF, for recording write conflict address set in N number of kernel memory contention, N number of kernel is recorded in interrupting
Interrupt jump address；
N number of to read signature RF, for recording read conflict address set in N number of kernel memory contention, N number of kernel is recorded in interrupting
Interrupt spot address.
Embodiment three：Illustrate present embodiment with reference to Fig. 3, present embodiment is to described in embodiment two
The polycaryon processor transient fault recovery system based on separate type daily record further restriction, separate type daily record controller includes
It is N number of to read signature address register and N number of write signature address register；
It is N number of to read signature address register, for mapping N number of termination address for reading signature RF；
It is N number of to write signature address register, for mapping N number of termination address for writing signature WF.
Embodiment four：Illustrate present embodiment with reference to Fig. 4, present embodiment is to described in embodiment three
The polycaryon processor transient fault recovery system based on separate type daily record further restriction, it is described recovery hardware module bag
Include N number of CP registers, N number of CS registers and an IIC register；
N number of CP registers, the count value for recording the wakeup message for being sent to a certain thread of other kernels；
N number of CS registers, the count value for recording the instruction blocked because of a certain thread of other kernels；
One IIC register, the blank(ing) instruction count value of event is recorded for recording adjacent uncertainty.
Embodiment five：Present embodiment is at the multinuclear based on separate type daily record described in embodiment four
The transient fault restoration methods of device transient fault recovery system are managed,
Methods described comprises the following steps：
Methods described comprises the following steps：
Step 1：When hardware check point starts storage, using separate type logger module, signature address register is read
Non-deterministic event information is recorded with signature address register is write；
Step 2：When being recovered from hardware check point module, kernel reads signature address register and writes signature ground
The information of location register record, terminates if the information that will be read exceedes address, otherwise performs step 3；
Step 3：16 information are read from memory contention daily record, reading 32 is needed if overflow register OVF has mark
Position information；Judge it is competition conflict or external interrupt according to the first in the information that overflow register OVF is read, if then competing
Conflict, performs step 4；If external interrupt, step 6 is performed；
Step 4：Overflow register OVF second information is read, judges it is first generation side or afterwards hair according to type types
Life side；If first generation side, the count value of the CP registers of kernel adds up, and the meter after instruction has been performed CP registers
Numerical value is sent to remaining kernel as wakeup message；If rear generation side, the count value of the CS registers of kernel adds up, wait until
The wakeup message that remaining kernel is sent performs this instruction again when identical with the count value of CS registers；
Step 5：Instruction perform after the completion of blank(ing) instruction counter IIC value add up, after wakeup message has been sent or
After receiving wakeup message and having performed instructions corresponding thereto, kernel repeats step 2；
Step 6：Read signature register and obtain and interrupt start address, the external equipment of interruption is called again, from writing label
Name register address starts to continue executing with；Kernel repeats step 2.
Embodiment six：Present embodiment is to the multinuclear based on separate type daily record described in embodiment five
The further restriction of the transient fault restoration methods of processor transient fault recovery system, the process of the step 1 is including as follows
Step：
Step one：When hardware check point module start storage when, the reading signature register of separate type log control module and
Signature register is write to reset；Separate type logger module start recording non-deterministic event information；It is interior when detecting conflict
When depositing competition, step 2 is performed；When it is external interrupt to detect conflict, step 5 is performed；
Step 2：Blank(ing) instruction counter IIC adds 1, when the value of the IIC is not less than 214When, stored from 4B registers
And made marks in overflow register OVF, otherwise from the storage of 2B registers；Overflow register OVF storages first place, which is marked, is,
Second includes first generation side or rear generation side as type described in the type mark of competition conflict, is transferred to step 3；
Step 3：The corresponding address of memory block that there will be memory contention is added to all reading signature register or writes label
Name register, occurs the sequence first side's of generation register Pred_IIC and circulation hair according to the type decision of competition conflict in circulation
Generation side register Succ_IIC does different marks after raw sequence, is transferred to step 4；
Step 4：Separate type log control module is updated to read signature register or write the IIC terminations of signature register record
Address, return to step one；
Step 5：Blank(ing) instruction counter IIC adds 1, when the value of the IIC is not less than 214When, stored from 4B registers
And made marks in overflow register OVF, be otherwise to turn from the first mark of 2B registers storage overflow register OVF storages
Enter step 6；
Step 6：The address that signature register preserves external interrupt is read, signature register is write and preserves the address redirected, be transferred to
Step 7；
Step 7：Update separate type log control module and read signature register and with writing the termination of signature register record
Location, return to step one.
Wherein, in separate type logger module during memory contention, recording mechanism is as shown in figure 5, comprise the following steps that：
Step 1：Processor core i and processor core j perform respective operation respectively；
Step 2：When system detectio to conflict j：2wr (x)-＞ i：At 3wr (x), it is contemplated that reducible the subtracting property of conflict, reality
Device core j is managed with IIC=2, type=0 form records the current occurred sequence 2- ＞ 3 of conflict correspondence first generation side to corresponding
In memory contention daily record, wherein 0 represents the first generation side of conflict, 2 represent the blank(ing) instruction number apart from the conflict of last time log recording.
Meanwhile, processor core i record IIC=3, type=1 form recorded in i memory contention daily record, wherein 1 represents conflict
Generation side afterwards.The resets of the instruction processing unit core IIC after conflict are performed.
Step 3：When system detectio to conflict i：1rd (m)-＞ j：4wr (m), processor core i with IIC=3, type=0,
Processor ＞ is with IIC=1, and type=1 form recorded the logger module of respective processor respectively.Perform after conflict
Instruction processing unit core IIC reset.
Step 4：When system detectio to conflict j：4wr (m)-＞ i：During 5rd (m), processor core j is with IIC=1, type=
0, processor core i are with IIC=2, and type=1 form recorded the logger module of respective processor respectively.Punching is performed
Instruction processing unit core IIC after prominent resets.
Step 5：When system detectio to conflict i：3wr (x)-＞ j：During 6wr (x), processor core i is with IIC=2, type=
0, processor core j are with IIC=1, and type=1 form recorded the logger module of respective processor respectively.Punching is performed
Instruction processing unit core IIC after prominent resets.
The foregoing is only a preferred embodiment of the present invention, these embodiments are all based on the present invention
Different implementations under general idea, and protection scope of the present invention is not limited thereto, it is any to be familiar with the art
Technical staff the invention discloses technical scope in, the change or replacement that can be readily occurred in, should all cover the present invention
Within protection domain.
Claims (4)
1. the polycaryon processor transient fault recovery system based on separate type daily record, it is characterised in that the system includes separation
Formula logger module, separate type daily record controller module and recovery hardware module；Embedded point in each kernel of processor
From formula logger module and recovery hardware module,
The separate type logger module, the non-deterministic event information for recording corresponding kernel, to memory contention daily record
Will be recorded separately using the dependence of point-to-point, the first generation side of dependence is recorded in the answer party of consistency protocol,
Requesting party records the rear generation side of dependence, to outside interruption logging interrupt type and interrupt address；
The separate type daily record controller module, the mapping relations for setting up log recording space and checkpointing；It is described
Recover hardware module, rollback recovery technology and Deterministic Replay technology for combining separate type daily record complete transient fault
Certainty behind checkpoint is recovered；
Separate type daily record controller module includes N number of reading signature address register and N number of writing signature address register；
It is N number of to read signature address register, for mapping N number of termination address for reading signature RF；
It is N number of to write signature address register, for mapping N number of termination address for writing signature WF；
The separate type logger module includes circulation and occurs the sequence first side's of generation register Pred_IIC, blank(ing) instruction counting
Device IIC, circulation occur generations side register Succ_IIC after sequence, overflow register OVF, N number of write sign WF and N number of reading and sign
RF；The N is the interior check figure of processor；
The sequence first side's of generation register Pred_IIC occurs for circulation, for marking non-deterministic event to be first generation side；
Blank(ing) instruction counter IIC, the blank(ing) instruction count value of event is recorded for recording adjacent uncertainty；
Generation side register Succ_IIC after sequence occurs for circulation, for marking generation side after non-deterministic event is；
Overflow register OVF, it is the first for marking the register size and non-deterministic event type that determine from record event
Memory contention is represented for 0, the first is 1 expression interruption, and second is that 0 expression uses 2B registers to store, and second represents to adopt for 1
Stored with 4B registers；
N number of to write signature WF, for recording write conflict address set in N number of kernel memory contention, N number of kernel is recorded in interrupting and interrupted
Jump address；
N number of to read signature RF, for recording read conflict address set in N number of kernel memory contention, N number of kernel is recorded in interrupting and interrupted
Site address.
2. the polycaryon processor transient fault recovery system according to claim 1 based on separate type daily record, its feature exists
In the recovery hardware module includes N number of CP registers, N number of CS registers and an IIC register；
N number of CP registers, the count value for recording the wakeup message for being sent to a certain thread of other kernels；
N number of CS registers, the count value for recording the instruction blocked because of a certain thread of other kernels；
One IIC register, the blank(ing) instruction count value of event is recorded for recording adjacent uncertainty.
3. the transient fault based on the polycaryon processor transient fault recovery system based on separate type daily record described in claim 2
Restoration methods, it is characterised in that methods described comprises the following steps：
Step 1：When hardware check point starts storage, using separate type logger module, read signature and address register and write
Address register of signing records non-deterministic event information；
Step 2：When being recovered from hardware check point module, kernel reads signature address register and writes signature address and posts
The information of storage record, terminates if the information that will be read exceedes address, otherwise performs step 3；
Step 3：16 information are read from memory contention daily record, need to read 32 letters if overflow register O steps F has mark
Breath；Judge it is competition conflict or external interrupt according to the first in overflow register O walks the information that F is read, if then competition punching
It is prominent, perform step 4；If external interrupt, step 6 is performed；
Step 4：Reading overflow register O step F second information, judges it is first generation side or rear generation according to type types
Side；If first generation side, the count value of the CP registers of kernel adds up, and the counting after instruction has been performed CP registers
Value is sent to remaining kernel as wakeup message；If rear generation side, the count value of the CS registers of kernel adds up, Deng Daoqi
The wakeup message that remaining kernel is sent performs this instruction again when identical with the count value of CS registers；
Step 5：Blank(ing) instruction counter IIC value adds up after the completion of instruction is performed, after wakeup message has been sent or ought connect
By wakeup message and perform after instructions corresponding thereto, kernel repeats step 2；
Step 6：Read signature register and obtain interruption start address, the external equipment of interruption is called again, is posted from signature is write
Storage address starts to continue executing with；Kernel repeats step 2.
4. the transient fault of the polycaryon processor transient fault recovery system according to claim 3 based on separate type daily record
Restoration methods, it is characterised in that the process of the step 1 comprises the following steps：
Step one：When hardware check point module starts storage, the reading signature register of separate type log control module and label are write
Name register is reset；Separate type logger module start recording non-deterministic event information；It is competing for internal memory when detecting conflict
When striving, step 2 is performed；When it is external interrupt to detect conflict, step 5 is performed；
Step 2：Blank(ing) instruction counter IIC adds 1, when the IIC value be not less than 214 when, from 4B registers storage and
Made marks in overflow register O steps F, otherwise from the storage of 2B registers；Overflow register O step F storages first place, which is marked, is, the
Type described in two type marks as competition conflict includes first generation side or rear generation side, is transferred to step 3；
Step 3：The corresponding address of memory block that there will be memory contention is added to all reading signature register or writes signature and posts
Storage, determines occur the sequence first side's of generation register Pred_IIC and circulation occurred sequence in circulation according to the type of competition conflict
Generation side register Succ_IIC does different marks after row, is transferred to step 4；
Step 4：The IIC termination addresses that separate type log control module reads signature register or writes signature register record are updated,
Return to step one；
Step 5；Blank(ing) instruction counter IIC adds 1, when the IIC value be not less than 214 when, from 4B registers storage and
Made marks in overflow register O steps F, be otherwise to be transferred to from the first mark of 2B registers storage overflow register O step F storages
Step 6；
Step 6：The address that signature register preserves external interrupt is read, signature register is write and preserves the address redirected, be transferred to step
Seven；
Step 7：The termination address that separate type log control module reads signature register and writes signature register record is updated, is returned
Return step one.
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| CN106681911B (en) * | 2016-12-08 | 2019-05-14 | 浙江大学 | A kind of implementation method of certainty playback that supporting direct fault location |
| CN107193661B (en) * | 2017-05-15 | 2020-08-21 | 哈尔滨工业大学（威海） | Optimized segmented memory competition recording system and method for deterministic replay of multi-core processor |
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