200842594 九、發明說明 【發明所屬之技術領域】 本發明是有關中斷控制電路、電路基板、光電裝置及 電子機器。 【先前技術】 例如，在下記非專利文獻1中揭示有對CPU ( Central Processing Unit )進行中斷控制的中斷控制電路之一例。 此中斷控制電路是由：將自外部輸入的複數個中斷要因信 號的邏輯和信號亦即中斷信號輸出至CPU的OR電路、及 將對應於上述中斷要因信號的中斷向量信號輸出至CPU 的中斷向量發生電路所構成。例如CPU設於個人電腦時 ，自滑鼠或鍵盤等輸出中斷要因信號。並且，所謂中斷向 量信號是顯示儲存有按照中斷要因信號，CPU所應實行的 中斷處理程式之記憶體上的位址之信號。 OR電路若是複數的中斷要因信號内至少1個被控制 於高位準，則會將高位準的中斷信號輸出至CPU。中斷向 量發生電路會將對應於所被控制成高位準的中斷要因信號 之中斷向量信號輸出至CPU。在此，中斷向量發生電路是 在2個以上的中斷要因信號被控制於高位準時，按照被預 定的優先順位，將對應於優先順位高的中斷要因信號之中 斷向量信號輸出至CPU。CPU若被輸入高位準的中斷信號 ，亦即辨識出發生中斷要求，則實行被儲存於中斷向量信 號所示之記憶體上的位址的中斷處理程式，進行中斷處理 -4- 200842594 該等中斷控制電路及CPU是根據共通的時脈信號來 動作的同步型電路，中斷控制電路是與時脈信號同步來輸 出中斷信號，並且CPU是以時脈信號所規定的所定時序 來監視自中斷控制電路輸入的中斷信號的狀態，在該時序 辨識出中斷信號的狀態爲高位準時進行中斷處理。 [非專利文獻1]圖解Z80微電腦應用系統入門硬體 編第2版 p 1 8 6 【發明內容】 (發明所欲解決的課題） 如上述，以往的同步型電路時，由於需要中斷信號的 監視處理，因此CPU的消費電力會變大，且因爲全部的 動作時序是以時脈信號規定，所以動作速度慢。另一方面 ，近年來爲了實現電子電路的高速化及低消費電力化，不 需要共通的時脈信號之非同步電路受到注目。然而，如上 述，由於以往的中斷控制電路需要與CPU共通的時脈信 號，因此對於非同步型的CPU而言難以進行中斷控制。 所以，無法使用非同步型的CPU，難以實現高速化及低消 費電力化。 本發明是有鑑於如此的情事而硏發者，其目的是在於 提供一種可對非同步型的CPU進行中斷控制，可實現高 速化及低消費電力化的中斷控制電路。又，其目的是在於 提供一種可藉由具備如此的中斷控制電路，對非同步型的 -5- 200842594 C P U進行中斷控制，可實現高速化及低消費電力化之 基板、光電裝置及電子機器。 (用以解決課題的手段） 爲了達成上述目的，本發明的中斷控制電路，係 以fe:照來自1個或複數個外部電路的中斷要因信號來 中斷處理之中斷信號、及顯示對應於中斷要因信號的 處理程式的儲存端之中斷向量信號予以輸出至中斷處 行電路，其特徵爲： 與從上述中斷處理實行電路輸入之顯示中斷處理 理可能狀態的中斷受理信號同步來輸出中斷信號。 若利用具備如此特徴的中斷控制電路，則會與從 等的中斷處理實行電路輸入之顯示中斷處理的受理可 態的中斷受理信號同步來輸出上述中斷信號，因此不 以往那樣的共通時脈信號，可對應於非同步型的CPU 現高速化及低消費電力化。 又，本發明的中斷控制電路中，最好是具備： 中斷信號發生電路，其係與上述中斷受理信號的 同步將上述中斷信號復位，另一方面，與上述中斷受 號的復位同步設定上述中斷信號；及 中斷向量發生電路，其係與上述中斷信號的設定 輸出上述中斷向量信號。 就非同步電路彼此間的通信協定而言，是在從 等的中斷處理實行電路輸出設定狀態的中斷受理信號 電路 將用 要求 中斷 理實 的受 CPU 能狀 需要 ，實 設定 理信 同步 CPU 的期 -6 - 200842594 間，禁止從中斷控制電路輸出中斷信號至中斷處理實行電 路。 因此，如此與中斷受理信號的設定同步來使中斷信號 復位，另一方面，與中斷受理信號的復位同步來設定中斷 信號，與此中斷信號的設定同步來輸出中斷向量信號，藉 此可進行準照非同步電路彼此間的通信協定之信號的處理 〇 又，本發明的中斷控制電路中，最好是具備·· 中斷要因記憶電路，其係對應於上述中斷要因信號的 數量而設置，記憶上述中斷要因信號的狀態，輸出顯示該 狀態的中斷要因狀態信號，另一方面，與復位信號的輸入 同步，將所記憶的上述中斷要因信號的狀態予以復位；及 復位信號發生電路，其係判定上述中斷向量信號是對 應於哪個的中斷要因信號而輸出，與上述中斷受理信號的 設定同步，將上述復位信號輸出至對應於所被判定的中斷 要因信號之中斷要因記憶電路， 上述中斷信號發生電路係至少1個的中斷要因狀態信 號爲設定狀態時設定上述中斷信號，上述中斷向量發生電 路係輸出對應於設定狀態的中斷要因狀態信號之中斷向量 信號。 藉此’即使複數的中斷要因信號被同時設定，還是可 記憶哪個中斷要因信號被設定，對應於1個中斷要因信號 的中斷處理終了後，可連續進行對應於其次的中斷要因信 號的中斷處理。並且，與中斷受理信號的設定同步，將對 200842594 應於終了的中斷處理之中斷要因信號的狀態予以復位，藉 此可防止其次進行的中斷處理與終了的中斷處理重複。 在以往的中斷控制電路中，因爲沒有將中斷要因信號 的狀態予以記憶或初期化的機能，所以必須將如此的機能 設於外部電路側’導致設計作業效率降低’設計期間的長 期化。相對的，本發明的中斷控制電路是具備：將中斷要 因信號的狀態予以記憶或初期化的機能、亦即中斷要因記 憶電路、及將復位信號輸出至該中斷要因記憶電路的復位 信號發生電路，因此可實現設計作業效率的提升及設計期 間的短縮。 又，本發明的中斷控制電路中，最好在上述外部電路 側設有：記憶上述中斷要因信號的狀態’輸出顯示該狀態 的中斷要因狀態信號，另一方面，與復位信號的輸入同步 ，將所記憶的上述中斷要因信號的狀態予以復位之中斷要 因記憶電路時，具備復位信號發生電路’其係判定上述中 斷向量信號是對應於哪個中斷要因信號來輸出，與上述中 斷受理信號的設定同步，將上述復位信號輸出至對應於所 被判定的中斷要因信號之中斷要因記憶電路，上述中斷信 號發生電路係至少1個的中斷要因狀態信號爲設定狀態時 設定上述中斷信號，上述中斷向量發生電路係輸出對應於 設定狀態的中斷要因狀態信號之中斷向量信號。 如此一來，即使像以往那樣’在外部電路側設有將中 斷要因信號的狀態予以記憶或初期化的機能之中斷要因記 憶電路，還是可以藉由在外部電路側輸出用以將中斷要因 -8 - 200842594 信號的狀態復位之復位信號來對應。 又，本發明的中斷控制電路中，最好上述中斷向量發 生電路，係設定狀態的中斷要因狀態信號爲複數存在時’ 輸出對應於優先順位高的中斷要因狀態信號之中斷向量信 號。 又，本發明的中斷控制電路中，最好是具備： 第1脈衝發生電路，其係對應於上述中斷要因的數量 而設置，與上述中斷要因狀態信號的設定同步輸出脈衝信200842594 IX. Description of the Invention [Technical Field] The present invention relates to an interrupt control circuit, a circuit board, an optoelectronic device, and an electronic device. [Prior Art] For example, an example of an interrupt control circuit that performs interrupt control on a CPU (Central Processing Unit) is disclosed in Non-Patent Document 1 below. The interrupt control circuit is an interrupt circuit that outputs a plurality of interrupt cause signal logic signals, that is, an interrupt signal, to the CPU, and an interrupt vector signal corresponding to the interrupt factor signal to the CPU. The circuit is formed. For example, when the CPU is set in a personal computer, the output signal is interrupted by a mouse or a keyboard. Further, the interrupt vector signal is a signal indicating that the address on the memory of the interrupt processing program to be executed by the CPU is stored in accordance with the interrupt factor signal. If the OR circuit is a complex interrupt cause, at least one of the signals is controlled to a high level, and a high level interrupt signal is output to the CPU. The interrupt vector generation circuit outputs an interrupt vector signal corresponding to the interrupt factor signal that is controlled to a high level to the CPU. Here, the interrupt vector generation circuit outputs an interrupt vector signal interrupt vector signal corresponding to the priority order high to the CPU in accordance with the predetermined priority order when two or more interrupt factor signals are controlled to the high level. If the CPU inputs a high level interrupt signal, that is, the interrupt request is recognized, the interrupt processing program of the address stored in the memory indicated by the interrupt vector signal is executed, and the interrupt processing is performed - 200842594 The control circuit and the CPU are synchronous circuits that operate according to a common clock signal. The interrupt control circuit outputs an interrupt signal in synchronization with the clock signal, and the CPU monitors the self-interrupt control circuit at a predetermined timing specified by the clock signal. The state of the input interrupt signal is interrupted when the timing recognizes that the state of the interrupt signal is high. [Non-Patent Document 1] A description of the Z80 microcomputer application system entry hardware version 2 p 1 8 6 [Explanation] (Problems to be solved by the invention) As described above, in the case of the conventional synchronous circuit, the monitoring of the interrupt signal is required. Since the CPU consumes a large amount of power, and since all the operation timings are specified by the clock signal, the operation speed is slow. On the other hand, in recent years, in order to achieve high speed of electronic circuits and low power consumption, asynchronous circuits that do not require a common clock signal have attracted attention. However, as described above, since the conventional interrupt control circuit requires a clock signal common to the CPU, it is difficult for the asynchronous CPU to perform the interrupt control. Therefore, it is impossible to use a non-synchronous CPU, and it is difficult to achieve high speed and low power consumption. The present invention has been made in view of such circumstances, and an object of the present invention is to provide an interrupt control circuit capable of performing interrupt control on a non-synchronous CPU and achieving high speed and low power consumption. Further, the object of the invention is to provide a substrate, an optoelectronic device, and an electronic device capable of interrupting the asynchronous type -5-200842594 C P U by such an interrupt control circuit, thereby achieving high speed and low power consumption. (Means for Solving the Problem) In order to achieve the above object, the interrupt control circuit of the present invention is configured to interrupt an interrupt signal processed by an interrupt factor signal from one or a plurality of external circuits, and display an interrupt factor corresponding to the interrupt. The interrupt vector signal of the storage end of the signal processing program is output to the interrupt line circuit, and is characterized in that the interrupt signal is output in synchronization with the interrupt acceptance signal from the interrupt processing execution circuit input display interrupt processing processing possible state. When the interrupt control circuit having such a characteristic is used, the interrupt signal is output in synchronization with the interrupt reception signal of the display interrupt processing executed by the interrupt processing execution circuit, and the common clock signal is not used. It can correspond to the asynchronous type of CPU and high power consumption and low power consumption. Further, the interrupt control circuit of the present invention preferably includes an interrupt signal generating circuit that resets the interrupt signal in synchronization with the interrupt accepting signal, and sets the interrupt in synchronization with the reset of the interrupt receiving number. And an interrupt vector generation circuit that outputs the interrupt vector signal and the setting of the interrupt signal. In the communication protocol between the asynchronous circuits, the interrupt reception signal circuit that outputs the set state from the interrupt processing execution circuit is required to be interrupted by the CPU, and the CPU is set to be synchronized. Between -6 and 200842594, it is prohibited to output an interrupt signal from the interrupt control circuit to the interrupt processing execution circuit. Therefore, the interrupt signal is reset in synchronization with the setting of the interrupt reception signal. On the other hand, the interrupt signal is set in synchronization with the reset of the interrupt reception signal, and the interrupt vector signal is output in synchronization with the setting of the interrupt signal. In the interrupt control circuit of the present invention, it is preferable that the interrupt control circuit of the present invention has an interrupt factor memory circuit which is provided corresponding to the number of the interrupt factor signals and memorizes the above. Interrupting the state of the signal, outputting the interrupt cause signal of the state, and, on the other hand, synchronizing with the input of the reset signal, resetting the state of the interrupted signal due to the signal; and resetting the signal generating circuit, which determines The interrupt vector signal is output corresponding to the interrupt factor signal, and the reset signal is output to the interrupt factor memory circuit corresponding to the determined interrupt factor signal in synchronization with the setting of the interrupt acceptance signal, and the interrupt signal generating circuit is At least one interrupt cause signal Setting the set state when the interrupt signal, the output of the circuit based interrupt vector corresponding to the set state occurs interrupt cause status signals interrupt vector signal. Therefore, even if the plurality of interrupt cause signals are simultaneously set, it is possible to memorize which interrupt cause signal is set, and after the interrupt processing of one interrupt factor signal is completed, the interrupt processing corresponding to the next interrupt factor signal can be continuously performed. In addition, in synchronization with the setting of the interrupt acceptance signal, the state of the interrupt factor signal of the end interrupt processing of 200842594 is reset, thereby preventing the next interrupt processing from being repeated with the final interrupt processing. In the conventional interrupt control circuit, since the state of the signal of the interrupt cause signal is not memorized or initialized, it is necessary to provide such a function on the external circuit side, which results in a decrease in design work efficiency, and the design period is prolonged. In contrast, the interrupt control circuit of the present invention includes a function of memorizing or initializing the state of the interrupt factor signal, that is, the interrupt factor memory circuit and a reset signal generating circuit for outputting the reset signal to the interrupt factor memory circuit. Therefore, the efficiency of the design work can be improved and the design period can be shortened. Further, in the interrupt control circuit of the present invention, preferably, the external circuit side is provided with: a state in which the signal of the interrupt factor is stored, an output of the interrupt factor state signal indicating the state, and a synchronization signal input. The memory interrupted by the state of the signal is interrupted by the state of the signal, and the reset signal generating circuit determines that the interrupt vector signal is output corresponding to the interrupt factor signal, and is synchronized with the setting of the interrupt receiving signal. And outputting the reset signal to an interrupt factor memory circuit corresponding to the determined interrupt factor signal, wherein the interrupt signal generating circuit sets the interrupt signal when at least one interrupt factor state signal is in a set state, and the interrupt vector generating circuit is configured An interrupt vector signal corresponding to the interrupt factor of the set state is output. In this way, even if the interrupt circuit of the function that memorizes or initializes the state of the interrupt factor signal is provided on the external circuit side as in the related art, it can be outputted on the external circuit side to interrupt the factor -8. - 200842594 The reset signal of the status reset of the signal corresponds. Further, in the interrupt control circuit of the present invention, it is preferable that the interrupt vector generation circuit outputs an interrupt vector signal corresponding to the interrupt factor state signal having the higher priority when the interrupt signal of the set state is a plural. Further, the interrupt control circuit of the present invention preferably includes: a first pulse generating circuit that is provided corresponding to the number of the interrupt factors, and outputs a pulse signal in synchronization with the setting of the interrupt factor state signal;
Ptfe · 疏， 第2脈衝發生電路，其係與中斷受理信號的復位同步 輸出脈衝信號； 第1邏輯和電路，其係輸出：從上述第1脈衝發生電 路所輸出的脈衝信號與從上述第2脈衝發生電路所輸出的 脈衝信號的邏輯和信號； 第2邏輯和電路，其係輸出上述中斷要因狀態信號的 第2邏輯和信號；及 第3脈衝發生電路，其係與上述中斷受理信號的設定 同步輸出脈衝信號， 又，上述中斷信號發生電路，係與上述第1邏輯和信 號同步將上述第2邏輯和信號的狀態作爲中斷信號輸出， 另一方面，與從上述第3脈衝發生電路輸出的脈衝信號同 步使上述中斷信號復位，上述復位信號發生電路，係與從 上述第3脈衝發生電路輸出的脈衝信號同步輸出上述復位 信號。 -9- 200842594 由於本發明的中斷控制電路爲非同步電路，因此無共 通的時脈信號。藉此，如上述般產生脈衝信號之下，可作 爲規定各電路的動作時序之擬似時脈信號利用。 又，本發明的中斷控制電路中，最好上述復位信號發 生電路係由： 判定電路，其係判定到底對應於哪個中斷要因信號來 輸出上述中斷向量信號，輸出顯示該判定結果的判定信號 ;及 邏輯積電路，其係對應於上述中斷要因記憶電路而設 置’輸入上述判定信號及上述第3脈衝發生電路所輸出的 脈衝信號； 所構成， 並且，上述判定電路係將輸出至邏輯積電路的判定信 號予以控制成設定’該邏輯積電路係對應於記憶所被判定 的中斷要因信號的狀態之中斷要因記憶電路，上述邏輯積 電路係將上述判定信號與上述第3脈衝發生電路所輸出的 脈衝信號之邏輯積信號作爲上述復位信號輸出。 藉由採用如此的構成，可簡易地設計復位信號發生電 路’可寄與設計作業效率的提升。 又，本發明的中斷控制電路中，最好上述第1脈衝發 生電路係由： 第1延遲電路，其係使顯示上述中斷要因狀態信號只 延遲所定時間； 第1邏輯反轉電路，其係輸出藉由上述第1延遲電路 -10- 200842594 所延遲的中斷要因狀態信號的邏輯反轉信號； 第1邏輯積電路，其係將自上述第1邏輯反轉電路輸 出的邏輯反轉信號與上述中斷要因狀態信號的邏輯積信號 作爲脈衝信號而輸出； 所構成。 藉由採用如此的構成，可簡易地設計第1脈衝信號發 生電路，可寄與設計作業效率的提升。 又，本發明的中斷控制電路中，最好上述第2脈衝發 生電路，係由： 第2延遲電路，其係使上述中斷受理信號只延遲所定 時間； 第2邏輯反轉電路，其係輸出上述中斷受理信號的邏 輯反轉信號； 第2邏輯積電路，其係將藉由上述第2延遲電路來使 延遲的中斷受理信號與從上述第2邏輯反轉電路輸出的邏 輯反轉信號之邏輯積信號作爲脈衝信號而輸出； 所構成 藉由採用如此的構成，可簡易地設計第2脈衝信號發 生電路，可寄與設計作業效率的提升。 又，本發明的中斷控制電路中，最好上述第3脈衝發 生電路係由： 第3延遲電路，其係使上述中斷受理信號只延遲所定 時間； 第3邏輯反轉電路，其係輸出藉由上述第3延遲電路 -11 - 200842594 來延遲的中斷受理信號的邏輯反轉信號；及 第3邏輯積電路’其係將從上述第3邏輯反轉電路輸 出的邏輯反轉信號與上述中斷受理信號的邏輯積信號作爲 脈衝信號而輸出； 所構成。 藉由採用如此的構成’可簡易地設計第3脈衝信號發 生電路，可寄與設計作業效率的提升。 又，本發明的中斷控制電路中，最好在上述第1邏輯 和電路與上述中斷信號發生電路之間，更具備第4延遲電 路，其係使從上述第1邏輯和電路輸出的上述第1邏輯和 信號只延遲所定時間而輸出至上述中斷信號發生電路。 由於中斷信號發生電路是與第1邏輯和信號同步將第 2邏輯和信號的狀態作爲中斷信號來輸出，因此第1邏輯 和信號必須比第2邏輯和信號更遲被輸出。於是，如上述 ，在第1邏輯和電路與上述中斷信號發生電路之間設置第 4延遲電路，藉此滿足上述的條件。 另一方面，本發明之電路基板的特徵係具備上述中斷 控制電路。藉此，對非同步型的CPU之中斷控制可能， 可取得能夠實現高速化及低消費電力化的電路基板。 又’本發明之光電裝置的特徵係具備上述電路基板。 藉此，對非同步型的CPU之中斷控制可能，可取得能夠 實現高速化及低消費電力化的光電裝置。 又’本發明之電子機器的特徵係具備上述光電裝置。 藉此，對非同步型的CPU之中斷控制可能，可取得能夠 -12- 200842594 實現高速化及低消費電力化的電子機器。 又，有關上述本發明的中斷控制裝置的一個形態，其 特徵係生成： 中斷信號，其係用以按照複數的中斷要因的發生來執 行中斷要求；及 中斷向量信號，其係顯示對應於上述複數的中斷要因 的其中之一的中斷處理程式的儲存端， 並，將上述中斷信號及上述中斷向量信號輸出至中斷 處理實彳了電路，且， 與從上述中斷處理實行電路輸入之顯示中斷處理的受 理可能狀態的中斷受理信號同步來進行上述中斷信號及上 述中斷向量的輸出値的控制。 在上述一個形態中，最好具有：中斷信號發生電路、 及中斷向量發生電路， 上述中斷信號發生電路，係上述中斷受理信號的變化 爲顯示中斷處理的受理的設定時，使上述中斷信號復位， 上述中斷受理信號的變化爲顯示中斷處理的受理的復位時 ，進行上述中斷信號的更新動作， 上述中斷向量發生電路，係輸入中斷向量發生條件， 上述中斷受理信號的變化爲顯示中斷處理的受理的復位時 ，按照上述中斷向量發生條件來進行上述中斷向量信號的 更新動作。 並且，在上述一個形態中，最好具有：復位信號發生 電路、及記憶上述複數的中斷要因的狀態之中斷要因記憶 -13- 200842594 電路， 上述復位信號發生電路，係上述中斷受理信號的變化 爲顯示中斷處理的受理的設定時，生成復位信號，其係使 上述中斷向量信號所示的上述複數的中斷要因的其中之一 復位， 上述中斷要因記憶電路，係根據上述記憶的狀態來生 成上述中斷向量發生條件，且辨識上述複數的中斷要因的 其中之一的發生時，對上述中斷信號發生電路指示中斷信 號的設定， 上述記憶的狀態，係根據上述複數的中斷要因的其中 之一的發生及上述復位信號之上述中斷向量信號所示的上 述複數的中斷要因的其中之一的復位來更新。 【實施方式】 以下，一邊參照圖面一邊說明本發明的中斷控制電路 、電路基板、光電裝置及電子機器之一實施形態。 〔中斷控制電路〕 (第1實施形態） 首先，說明有關本發明的中斷控制電路的第1實施形 態。圖1是表示第1實施形態的中斷控制電路c1的構成 方塊圖。如該圖1所示，第1實施形態的中斷控制電路 C1是由：觸發電路（flip-flop circuit) 1、延遲電路2、 倒相電路（inverter circuit) 3、AND電路4、觸發電路5 -14- 200842594 、延遲電路6、倒相電路7、AND電路8、觸發電路9、延 遲電路1 0、倒相電路1 1、AND電路1 2、延遲電路1 3、倒 相電路1 4、AND電路1 5、延遲電路1 6、倒相電路1 7、 AND電路18、〇R電路19、延遲電路2〇、〇R電路21、觸 發電路22、中斷向量發生電路23、解碼器電路（decoder circuit) 24、AND 電路 25、AND 電路 26 及 AND 電路 27 所構成。 觸發電路1、5及9是相當於本發明的中斷要因記憶 電路的構成要素。延遲電路2、倒相電路3及AND電路4 是相當於構成本發明的第1脈衝發生電路的第1延遲電路 、第1邏輯反轉電路及第1邏輯積電路的構成要素。延遲 電路6、倒相電路7及AND電路8亦相當於構成本發明的 第1脈衝發生電路的第1延遲電路、第1邏輯反轉電路及 第1邏輯積電路的構成要素。延遲電路1 0、倒相電路1 1 及AND電路1 2亦相當於構成本發明的第1脈衝發生電路 的第1延遲電路、第1邏輯反轉電路及第1邏輯積電路的 構成要素。延遲電路1 3、倒相電路1 4及AND電路1 5是 相當於構成本發明的第3脈衝發生電路的第3延遲電路、 第3邏輯反轉電路及第3邏輯積電路的構成要素。延遲電 路1 6、倒相電路1 7及AND電路1 8是相當於構成本發明 的第2脈衝發生電路的第2延遲電路、第2邏輯反轉電路 及第2邏輯積電路的構成要素。OR電路19是相當於本發 明的第1邏輯和電路，延遲電路20是相當於本發明的第4 延遲電路，OR電路2 1是相當於本發明的第2邏輯和電路 -15- 200842594 ，觸發電路2 2是相當於本發明的中斷信號發生電路，中 斷向量發生電路23是相當於本發明的中斷向量發生電路 的構成要素。解碼器電路24、AND電路25、AND電路26 及A N D電路2 7是相當於構成本發明的復位信號發生電路 的判定電路及邏輯積電路的構成要素。 本第1實施形態的中斷控制電路C 1是輸入自外部電 路（未圖示）輸出的中斷要因信號SA、SB及SC、及自未 圖示的CPU (中斷處理實行電路）輸出的中斷受理信號 S 7 ’按照該等各信號來將中斷信號s 1 2及中斷向量信號 S13輸出至CPU者。中斷要因信號SA是被輸入至觸發電 路1，中斷要因信號SB是被輸入至觸發電路5，中斷要因 信號SC是被輸入至觸發電路9。並且，中斷受理信號S7 是被輸入至延遲電路13、AND電路15、延遲電路16及倒 相電路1 7。另外，本實施形態的中斷控制電路C 1是正邏 輯電路，將信號的狀態從低位準遷移至高位準的情形記載 爲設定，將從高位準遷移至低位準的情形記載爲復位。 觸發電路1是附有作爲記憶中斷要因信號SA的狀態 之暫存器的機能的設定復位之觸發電路，與中斷要因信號 S A的設定同步，將高位準的中斷要因狀態信號S 1輸出g 延遲電路2、AND電路4、OR電路21及中斷向量發生電 路23。並且，此觸發電路1是與自AND電路25輸入的復 位信號S 1 4的設定同步，將上述的中斷要因狀態信號S 1 控制於低位準（復位）。 延遲電路2是使中斷要因狀態信號S 1只延遲所定_ •16- 200842594 間來輸出倒相電路3。倒相電路3是將藉由上述延遲電路 2所延遲的中斷要因狀態信號S 1的邏輯反轉信號輸出至 AND電路4。AND電路4是將自觸發電路1輸入的中斷要 因狀態信號S 1與自倒相電路3輸入的中斷要因狀態信號 S 1的邏輯反轉信號之邏輯積信號亦即脈衝信號s 2輸出至 〇 R電路1 9。 觸發電路5是附有作爲記憶中斷要因信號S B的狀態 之暫存器的機能的設定復位之觸發電路，與中斷要因信號 SB的設定同步，將高位準的中斷要因狀態信號S3輸出至 延遲電路6、AND電路8、OR電路21及中斷向量發生電 路23。並且，此觸發電路5是與自AND電路26輸入的復 位信號S 1 5的設定同步’將上述的中斷要因狀態信號S 3 控制於低位準（復位）。 延遲電路6是使中斷要因狀態信號S3只延遲所定時 間來輸出至倒相電路7。倒相電路7是將藉由上述延遲電 路6所延遲的中斷要因狀態信號S 3的邏輯反轉信號輸出 至AND電路8。AND電路8是將自觸發電路5輸入的中 斷要因狀態信號S3與自倒相電路7輸入的中斷要因狀態 信號S3的邏輯反轉信號之邏輯積信號亦即脈衝信號S4輸 出至Ο R電路1 9。 觸發電路9是附有作爲記憶中斷要因信號SC的狀態 之暫存器的機能的設定復位之觸發電路，與中斷要因信號 SC的設定同步，將高位準的中斷要因狀態信號S5輸出至 延遲電路1〇、AND電路12、OR電路21及中斷向量發生 -17- 200842594 電路23。並且，此觸發電路9是與自AND電路27輸入的 復位信號S16的設定同步，將上述中斷要因狀態信號S5 控制於低位準（復位）。 延遲電路1 0是使中斷要因狀態信號S 5只延遲所定時 間來輸出至倒相電路1 1。倒相電路1 1是將藉由延遲電路 1 〇所延遲的中斷要因狀態信號S5的邏輯反轉信號輸出至 AND電路12。AND電路12是將自觸發電路9輸入的中斷 要因狀態信號S 5與自倒相電路1 1輸入的中斷要因狀態信 號S 5的邏輯反轉信號之邏輯積信號亦即脈衝信號S 6輸出 至Ο R電路1 9。 延遲電路1 3是使中斷受理信號S 7只延遲所定時間來 輸出倒相電路1 4。倒相電路1 4是將藉由上述延遲電路1 3 所延遲的中斷受理信號S 7的邏輯反轉信號輸出至AND電 路1 5。AN D電路1 5是將中斷受理信號S 7與自倒相電路 14輸入的中斷受理信號S7的邏輯反轉信號之邏輯積信號 亦即脈衝信號S8輸出至觸發電路22、AND電路25、AND 電路26及AND電路27。 延遲電路1 6是使中斷受理信號S 7只延遲所定時間來 輸出至AN D電路1 8。倒相電路1 7是將中斷受理信號s 7 的邏輯反轉信號輸出至AND電路18。AND電路18是將 藉由延遲電路1 6所延遲的中斷受理信號S7與自倒相電路 1 7輸出的中斷受理信號S 7的邏輯反轉信號之邏輯積信號 亦即脈衝信號S 9輸出至OR電路1 9。 Ο R電路1 9是將脈衝信號S 2、S 4、S 6及S 9的邏輯和 -18- 200842594 信號輸出至延遲電路20。延遲電路20是將使自〇R電路 1 9輸入的邏輯和信號只延遲所定時間的同步信號s〗〇輸 出至觸發電路22。OR電路21是將中斷要因狀態信號S1 、S3及S5的遞輯和彳g號S11輸出至觸發電路22。觸發電 路22是附復位觸發電路’與同步信號Sl〇的設定同步， 將邏輯和信號S11的狀態作爲中斷信號si2輸出至CPU 及中斷向量發生電路23。並且，此觸發電路22是與自 AND電路1 5輸入的脈衝信號S 8的設定同步，將上述的中 斷信號S 1 2控制於低位準（復位）。 中斷向量發生電路23是與中斷信號S12的設定同步 ，將封應於中斷要因狀態fg號S 1、S 3、S 5的中斷向量信 號S13輸出至CPU及解碼器電路24。此中斷向量信號 S 1 3是顯示儲存有按照對應於高位準的中斷要因狀態信號 之中斷要因信號，CPU所應實行的中斷處理程式之記憶體 上的位址之信號。亦即，中斷向量發生電路23是例如中 斷要因狀態信號S 1的狀態爲高位準時，輸出顯示儲存有 按照中斷要因信號SA，CPU所應實行的中斷處理程式之 記憶體上的位址之中斷向量信號S 1 3。另外，當複數的中 斷要因狀態信號的狀態爲高位準時，中斷向量發生電路2 3 是按照預定的優先順位，輸出對應於優先順位高的中斷要 因狀態信號（中斷要因信號）之中斷向量信號s 1 3。本實 施形態是將中斷要因信號SA設爲優先順位最高，中斷要 因信號S C設爲優先順位最低。 解碼器電路2 4是解碼中斷向量信號S 1 3，判定中斷 -19- 200842594 向量信號s 1 3爲對應於哪個中斷要因信號而輸出者，將高 位準的判定信號輸出至對應於記憶該判定後的中斷要因信 號的狀態的觸發電路（1、5、9)而設置的AND電路（25 、26、27) 。·具體而言，當解碼器電路24判定中斷向量 信號S13爲對應於中斷要因信號SA而輸出者時，對AND 電路25輸出高位準的判定信號，當判定中斷向量信號 S13爲對應於中斷要因信號SB而輸出者時，對AND電路 26輸出高位準的判定信號，又，當判定中斷向量信號S ! 3 爲對應於中斷要因信號SC而輸出者時，對AND電路27 輸出高位準的判定信號。 AND電路25是將自AND電路15輸入的脈衝信號S8 與自解碼器電路24輸入的判定信號之邏輯積信號亦即復 位丨§號S14輸出至觸發電路1。AND電路26是將自AND 電路1 5輸入的脈衝信號S8與自解碼器電路24輸入的判 疋丨目號之遍輪積fe號亦即復位信號S 1 5輸出至觸發電路5 。AND電路27是將自AND電路15輸入的脈衝信號S8與 自解碼器電路24輸入的判定信號之邏輯積信號亦即復位 信號S16輸出至觸發電路9。 如以上，圖1是表示中斷要因信號爲3個時的構成例 ，但可按照中斷要因信號的個數來適當追加•削除用以記 憶中斷要因信號的狀態之附設定復位觸發電路、用以輸出 復位信號的AND電路、構成脈衝發生電路的延遲電路、 倒相電路及AND電路。又，本實施形態雖是表示由正邏 輯電路所構成的中斷控制電路例，但並非限於此，亦可由 -20- 200842594 負邏輯電路所構成，其係將信號的狀態從低位準遷移至 位準的情形當作復位，將從高位準遷移至低位準的情形 作設定。 其次，利用圖2的時序圖來説明有關上述那樣構成 第1實施形態之中斷控制電路C 1的動作。 首先，在時刻，一旦中斷要因信號SA被控制（ 定）於高位準，則觸發電路1會與中斷要因信號SA的 定同步，將高位準的中斷要因狀態信號S 1輸出至延遲 路2、AND電路4、OR電路21及中斷向量發生電路23 在時刻Ti，OR電路21是被輸入高位準的中斷要因 態信號S 1，因此會將高位準的邏輯和信號S 1 1輸出至 發電路22。並且，在時刻，藉由延遲電路2、倒相電 3及AND電路4所構成的脈衝發生電路，與中斷要因狀 信號S1的設定同步來將脈衝信號S2輸出至OR電路19 由於OR電路19是在時刻T!被輸入高位準的脈衝信號 ，因此將同樣的脈衝狀的邏輯和信號輸出至延遲電路20 延遲電路20是使自OR電路1 9輸入的脈衝狀的邏輯和 號只延遲所定時間，在時刻T2將脈衝狀的同步信號S 輸出至觸發電路22。 在時刻Τ2，觸發電路22是與同步信號S 10的設定 步，將邏輯和信號S 1 1的狀態（在此是高位準）作爲中 信號S12輸出至CPU及中斷向量發生電路23。並且， 時刻丁2，中斷向量發生電路23是與中斷信號S12的設 同步，將對應於中斷要因狀態信號S 1的中斷向量信 局 當 的 設 設 電 〇 狀 觸 路 態 0 S2 〇 信 10 同 斷 在 定 號 -21 - 200842594 S13輸出至CPU及解碼器電路24。亦即，中斷向量發生 電路23因爲中斷要因狀態信號S 1的狀態爲高位準，所以 輸出顯示儲存有按照中斷要因信號SA，CPU所應實行的 中斷處理程式的記憶體上的位址之中斷向量信號S 1 3。並 且，解碼器電路24會判定中斷向量信號S 1 3爲對應於中 斷要因信號SA而輸出者，對AND電路25輸出高位準的 判定信號。 另一方面，若CPU在時刻T2被輸入高位準的中斷信 號S 1 2，亦即一旦辨識出發生中斷要求，則會實行被儲存 於中斷向量信號S 1 3所示之記憶體上的位址之中斷處理程 式，進行對應於中斷要因信號SA的中斷處理。 接著，在時刻Τ3，若中斷要因信號SB被控制（設定 )於高位準，則觸發電路5會與中斷要因信號SB的設定 同步，將高位準的中斷要因狀態信號S3輸出至延遲電路 6、AND電路8、OR電路21及中斷向量發生電路23。在 時刻T3，由於OR電路21是中斷要因狀態信號S 1及S 3 爲高位準，因此將高位準的邏輯和信號S 1 1持續輸出至觸 發電路22。 並且，在時刻T3，藉由延遲電路6、倒相電路7及 AND電路8所構成的脈衝發生電路，與中斷要因狀態信號 S3的設定同步來將脈衝信號S4輸出至OR電路19。由於 or電路1 9是在時刻T3被輸入高位準的脈衝信號S4，因 此將同樣的脈衝狀的邏輯和信號輸出至延遲電路2 0。延遲 電路2 0是使自Ο R電路1 9輸入的脈衝狀的邏輯和信號只 -22- 200842594 延遲所定時間，在時刻T4將脈衝狀的同步信號s 1 0輸出 至觸發電路22。 如上述，在時刻T4，脈衝狀的同步信號s 1 0會被輸入 至觸發電路2 2，但在此時間點規定觸發電路2 2的復位之 脈衝信號S8不會被輸入，因此觸發電路22是無關同步信 號S 1 0的輸入，持續輸出高位準的中斷信號s 1 2。又，由 於中斷向量發生電路2 3是中斷信號S丨2會被維持於高位 準，因此持續輸出對應於中斷要因信號S A的中斷向量信 號S13。亦即，解碼器電路24是對and電路25持續輸出 高位準的判定信號。 然後，CPU會完成對應於中斷要因信號SA的中斷處 理’在時刻T 5，假想將顯示遷移至其次的中斷處理的受理 可能的中斷受理信號S 7控制（設定）於高位準。 在該時刻I，由延遲電路1 3、倒相電路14及AND 電路1 5所構成的脈衝發生電路是與中斷受理信號s 7的設 定同步，將脈衝信號S8輸出至觸發電路22、AND電路25 、AND電路26及AND電路27。觸發電路22是在時刻T5 與脈衝信號S 8的上升同步將中斷信號S丨2控制（復位） 於低位準。另一方面，AND電路25是在時刻丁5被輸入高 位準的判定信號、及高位準的脈衝信號S 8，因此將脈衝 狀的復位信號S 1 4輸出至觸發電路1。藉此，觸發電路1 是在時刻T 5與復位信號S 1 4的設定同步，將中斷要因狀 態信號S 1控制（復位）於低位準。另外，在此時間點， 因爲中斷要因狀態信號S 3是高位準，所以0 R電路2 1是 -23- 200842594 持續輸出高位準的邏輯和信號s 1 1。 然後，在時刻τ6，若中斷受理信號S 7被控制（復位 )於低位準，則以延遲電路1 6、倒相電路1 7及AND電路 18所構成的脈衝發生電路是與中斷受理信號S7的復位同 步將高位準的脈衝信號S9輸出至OR電路19。OR電路 1 9是在時刻T6被輸入高位準的脈衝信號S 9，因此將同樣 的脈衝狀的邏輯和信號輸出至延遲電路20。延遲電路20 是使自OR電路1 9輸入的脈衝狀的邏輯和信號只延遲所定 時間，在時刻T7將脈衝狀的同步信號S 1 0輸出至觸發電 路22。 在時刻Τ7，觸發電路22是與同步信號S10的設定同 步，將邏輯和信號S 11的狀態（在此是高位準）作爲中斷 信號S12來輸出至CPU及中斷向量發生電路23。並且， 在時刻T 7，中斷向量發生電路2 3是與中斷信號S 1 2的設 定同步，將對應於中斷要因狀態信號S 3的中斷向量信號 S13輸出至CPU及解碼器電路24。亦即，中斷向量發生 電路23是中斷要因狀態信號S 3的狀態爲高位準，因此輸 出顯示儲存有按照中斷要因信號SB，CPU所應實行的中 斷處理程式的記憶體上的位址之中斷向量信號S 1 3。並且 ’解碼器電路24會判定中斷向量信號S13爲對應於中斷 要因信號SB而輸出者，對AND電路26輸出高位準的判 定信號。 另一方面’若CPU在時刻T7被輸入高位準的中斷信 號S 1 2 ’亦即一旦辨識出發生中斷要求，則會實行被儲存 -24- 200842594 於中斷向量信號S 1 3所示之記憶體上的位址之中斷處理程 式，進行對應於中斷要因信號S B的中斷處理。然後， C P ϋ會完成對應於中斷要因信號S b的中斷處理，在時刻 T s，假想將顯示遷移至其次的中斷處理的受理可能狀態之 中斷受理信號S7控制（設定）於高位準。 在該時刻Τ8，由延遲電路1 3、倒相電路14及AND 電路1 5所構成的脈衝發生電路是與中斷受理信號s 7的設 定同步’將脈衝信號S8輸出至觸發電路22、AND電路25 、AND電路26及AND電路27。觸發電路22是在時刻T8 與脈衝信號S 8的設定同步將中斷信號S丨2控制（復位） 於低位準。另一方面，AND電路26是在時刻T8被輸入高 位準的判定信號、及高位準的脈衝信號S 8，因此將脈衝 狀的復位信號S 1 5輸出至觸發電路5。藉此，觸發電路5 是在時刻Τ8與復位信號S 1 5的設定同步，將中斷要因狀 態信號S 3控制（復位）於低位準。另外，在該時間點， 因爲全部的中斷要因狀態信號是形成低位準，所以OR電 路2 1是輸出低位準的邏輯和信號S 1 1。 以後，同樣按照中斷要因信號SA、中斷要因信號SB 、中斷要因信號SC、中斷受理信號S7的狀態來輸出中斷 信號S12及中斷向量信號S13。 如以上，若根據本第1實施形態的中斷控制電路C 1 ’則會與自CPU等的中斷處理實行電路輸入的中斷受理 信號S 7同步輸出中斷信號S 1 2，因此不必像以往那樣的 共通時脈信號，可對應於非同步型的CPU，可實現高速化 -25· 200842594 及低消費電力化。並且，在以往的中斷控制電路中’因爲 沒有將中斷要因信號的狀態予以記憶或初期化的機能’所 以必須將如此的機能設於外部電路側，導致設計作業效率 降低，設計期間的長期化。相對的，本中斷控制電路C1 是具備：將中斷要因信號的狀態予以記憶或初期化的機能 、亦即中斷要因記憶電路（觸發1、5、9 )、及將復位信 號輸出至該中斷要因記憶電路的復位信號發生電路（解碼 器電路24、AND電路25、26、27 )，因此可實現設計作 業效率的提升及設計期間的短縮。 (第2實施形態） 其次，說明有關本發明的中斷控制電路的第2實施形 態。圖3是表示第2實施形態之中斷控制電路C2的構成 方塊圖。另外，在圖3中，對於與圖1同樣的構成要素賦 予同一符號，且省略説明，以下針對與圖1相異的點進行 説明。 本第2貫施形態是表不各外部電路具備將中斷要因信 號的狀態予以記憶及初期化的機能時之中斷控制電路c 2 的構成者。亦即，在中斷控制電路C 2中未設有觸發電路 1、5及9，外部電路3 0具備觸發電路1，外部電路4〇具 備觸發電路5，外部電路5 0具備觸發電路9。 本中斷控制電路C2是輸入自外部電路3 〇的觸發電路 1輸出的中斷要因狀態信號S 1、自外部電路4 0的觸發電 路5輸出的中斷要因狀態信號S3、自外部電路50的觸發 -26- 200842594 電路9輸出的中斷要因狀態信號S 5。中斷要因狀態 S1是被輸入至延遲電路2、AND電路4、OR電路21 斷向量發生電路23，中斷要因狀態信號S3是被輸入 遲電路6、AND電路8、OR電路21及中斷向量發生 23，中斷要因狀態信號S5是被輸入至延遲電路10、 電路12、OR電路21及中斷向量發生電路23。 並且，AND電路25是將復位信號S14輸出至外 路30的觸發電路1。AND電路26是將復位信號S15 至外部電路40的觸發電路5。AND電路27是將復位 S 1 6輸出至外部電路5 0的觸發電路9。 另外，顯示上述構成的第2實施形態之中斷控制 C2的動作時序圖是與第1實施形態（圖2 )同樣，因 略説明。 如此，各外部電路具備將中斷要因信號的狀態予 憶及初期化的機能時，同樣可藉由使用本中斷控制 C2來對應於非同步型的CPU，可實現高速化及低消 力化。 〔電路基板〕 其次，說明有關具備上述中斷控制電路C 1或C2 路基板。a second pulse generating circuit that outputs a pulse signal in synchronization with a reset of the interrupt receiving signal; the first logic sum circuit outputs a pulse signal output from the first pulse generating circuit and the second signal from the second a logical sum signal of a pulse signal output from the pulse generating circuit; a second logical sum circuit that outputs a second logical sum signal of the interrupt factor state signal; and a third pulse generating circuit that sets the interrupt receiving signal Synchronizing the output pulse signal, the interrupt signal generating circuit outputs the state of the second logical sum signal as an interrupt signal in synchronization with the first logical sum signal, and outputs the output from the third pulse generating circuit. The pulse signal is synchronized to reset the interrupt signal, and the reset signal generating circuit outputs the reset signal in synchronization with a pulse signal output from the third pulse generating circuit. -9- 200842594 Since the interrupt control circuit of the present invention is a non-synchronous circuit, there is no common clock signal. Thereby, the pulse signal is generated as described above, and can be used as a pseudo clock signal for specifying the operation timing of each circuit. Further, in the interrupt control circuit of the present invention, preferably, the reset signal generating circuit is: a determining circuit that determines which interrupt factor signal is output corresponding to the interrupt signal signal, and outputs a determination signal indicating the determination result; The logic product circuit is configured to provide the input of the determination signal and the pulse signal output by the third pulse generation circuit in response to the interruption, and the determination circuit outputs the determination to the logic product circuit. The signal is controlled to set the logic supply circuit to correspond to an interrupt factor memory circuit that memorizes the state of the interrupt factor signal determined by the memory, and the logic product circuit sets the determination signal and the pulse signal output by the third pulse generation circuit The logical product signal is output as the above reset signal. By adopting such a configuration, the reset signal generating circuit can be easily designed to improve the efficiency of design work. Further, in the interrupt control circuit of the present invention, preferably, the first pulse generating circuit is configured to: the first delay circuit delays display of the interrupt factor state signal by only a predetermined time; and the first logic inverting circuit outputs a logic inversion signal of the interrupt factor state signal delayed by the first delay circuit-10-200842594; a first logic product circuit that outputs a logic inversion signal output from the first logic inversion circuit and the interrupt It is composed of a logical product signal of the state signal as a pulse signal; By adopting such a configuration, the first pulse signal generating circuit can be easily designed, and the design work efficiency can be improved. Further, in the interrupt control circuit of the present invention, preferably, the second pulse generating circuit is configured to: the second delay circuit delays the interrupt reception signal by only a predetermined time; and the second logic inversion circuit outputs the a logic inversion signal for interrupting the reception signal; and a second logic product circuit for logically integrating the delayed interrupt reception signal and the logic inversion signal output from the second logic inversion circuit by the second delay circuit The signal is output as a pulse signal. With such a configuration, the second pulse signal generating circuit can be easily designed, and the design work efficiency can be improved. Further, in the interrupt control circuit of the present invention, preferably, the third pulse generating circuit is configured to: the third delay circuit delays the interrupt reception signal by only a predetermined time; and the third logic inversion circuit outputs the signal by the third logic inversion circuit a logic inversion signal of the interrupt reception signal delayed by the third delay circuit -11 - 200842594; and a third logic product circuit 'the logic inversion signal output from the third logic inversion circuit and the interrupt reception signal The logical product signal is output as a pulse signal; By adopting such a configuration, the third pulse signal generating circuit can be easily designed, and the design work efficiency can be improved. Further, in the interrupt control circuit of the present invention, preferably, the first logic circuit and the interrupt signal generating circuit further include a fourth delay circuit for outputting the first one from the first logic and circuit The logical sum signal is outputted to the above-described interrupt signal generating circuit only for a predetermined time. Since the interrupt signal generating circuit outputs the state of the second logical sum signal as an interrupt signal in synchronization with the first logical sum signal, the first logical sum signal must be output later than the second logical sum signal. Then, as described above, the fourth delay circuit is provided between the first logic sum circuit and the interrupt signal generating circuit, thereby satisfying the above conditions. On the other hand, the circuit board of the present invention is characterized in that it has the above-described interrupt control circuit. As a result, it is possible to control the interrupt of the asynchronous CPU, and it is possible to obtain a circuit board capable of achieving high speed and low power consumption. Further, the photovoltaic device of the present invention is characterized in that the circuit board is provided. As a result, it is possible to control the interrupt of the asynchronous CPU, and it is possible to obtain an optoelectronic device capable of achieving high speed and low power consumption. Further, the electronic device of the present invention is characterized in that it includes the above-described photovoltaic device. In this way, it is possible to control the interrupt of the asynchronous CPU, and it is possible to obtain an electronic device capable of achieving high speed and low power consumption by -12-200842594. Further, an aspect of the interrupt control device according to the present invention is characterized in that: an interrupt signal is generated for performing an interrupt request in accordance with occurrence of a plurality of interrupt factors; and an interrupt vector signal is displayed corresponding to the complex number Interrupt processing of one of the interrupt processing programs, and outputting the interrupt signal and the interrupt vector signal to the interrupt processing circuit, and the display interrupt processing from the interrupt processing execution circuit input The interrupt reception signal that accepts the possible state is synchronized to control the output signal of the interrupt signal and the interrupt vector. In the above aspect, preferably, the interrupt signal generating circuit and the interrupt vector generating circuit are configured to reset the interrupt signal when the change of the interrupt accepting signal is a setting for receiving the interrupt processing. When the change of the interrupt reception signal is the reset of the reception interrupt processing, the interrupt signal update operation is performed, and the interrupt vector generation circuit inputs an interrupt vector generation condition, and the change of the interrupt reception signal is acceptance of the display interrupt processing. At the time of reset, the update operation of the interrupt vector signal is performed in accordance with the above-described interrupt vector generation condition. Further, in the above aspect, preferably, the reset signal generating circuit and the interrupt factor for memorizing the state of the plurality of interrupt factors are stored in the circuit 13-200842594, and the reset signal generating circuit is changed by the interrupt receiving signal. When the setting of the interrupt processing reception is displayed, a reset signal is generated, which resets one of the plurality of interrupt factors indicated by the interrupt vector signal, and the interrupt is caused by the memory circuit to generate the interrupt according to the state of the memory. When the vector occurs condition and the occurrence of one of the plurality of interrupt factors is recognized, the interrupt signal generating circuit instructs the setting of the interrupt signal, and the state of the memory is based on the occurrence of one of the plurality of interrupt factors. The reset signal is updated by resetting one of the plurality of interrupt factors indicated by the interrupt vector signal of the reset signal. [Embodiment] Hereinafter, an embodiment of an interrupt control circuit, a circuit board, a photovoltaic device, and an electronic device according to the present invention will be described with reference to the drawings. [Interrupt Control Circuit] (First Embodiment) First, a first embodiment of the interrupt control circuit according to the present invention will be described. Fig. 1 is a block diagram showing the configuration of an interrupt control circuit c1 according to the first embodiment. As shown in FIG. 1, the interrupt control circuit C1 of the first embodiment is composed of a flip-flop circuit 1, a delay circuit 2, an inverter circuit 3, an AND circuit 4, and a flip-flop circuit 5 - 14-200842594, delay circuit 6, inverter circuit 7, AND circuit 8, trigger circuit 9, delay circuit 10, inverter circuit 1 1, AND circuit 1, 2. delay circuit 13, inverter circuit 14, and AND circuit 1 5, delay circuit 16 6, inverter circuit 17, 7, AND circuit 18, 〇R circuit 19, delay circuit 2 〇, 〇R circuit 21, trigger circuit 22, interrupt vector generation circuit 23, decoder circuit (decoder circuit) 24. An AND circuit 25, an AND circuit 26, and an AND circuit 27 are formed. The flip-flop circuits 1, 5 and 9 are constituent elements corresponding to the interrupt factor memory circuit of the present invention. The delay circuit 2, the inverter circuit 3, and the AND circuit 4 are constituent elements corresponding to the first delay circuit, the first logic inversion circuit, and the first logic circuit that constitute the first pulse generation circuit of the present invention. The delay circuit 6, the inverter circuit 7, and the AND circuit 8 also correspond to the components of the first delay circuit, the first logic inversion circuit, and the first logic circuit that constitute the first pulse generation circuit of the present invention. The delay circuit 10, the inverter circuit 1 1 and the AND circuit 1 2 also correspond to the components of the first delay circuit, the first logic inversion circuit, and the first logic circuit that constitute the first pulse generation circuit of the present invention. The delay circuit 13, the inverter circuit 14 and the AND circuit 15 are constituent elements corresponding to the third delay circuit, the third logic inversion circuit, and the third logical product circuit constituting the third pulse generating circuit of the present invention. The delay circuit 16 and the AND circuit 18 are constituent elements corresponding to the second delay circuit, the second logic inversion circuit, and the second logic circuit which constitute the second pulse generating circuit of the present invention. The OR circuit 19 corresponds to the first logic and circuit of the present invention, the delay circuit 20 corresponds to the fourth delay circuit of the present invention, and the OR circuit 2 1 corresponds to the second logic and circuit -15-200842594 of the present invention. The circuit 2 2 is an interrupt signal generating circuit corresponding to the present invention, and the interrupt vector generating circuit 23 is a component corresponding to the interrupt vector generating circuit of the present invention. The decoder circuit 24, the AND circuit 25, the AND circuit 26, and the A N D circuit 27 are constituent elements corresponding to the determination circuit and the logic product circuit constituting the reset signal generating circuit of the present invention. The interrupt control circuit C1 of the first embodiment is an interrupt request signal SA, SB, and SC input from an external circuit (not shown), and an interrupt reception signal output from a CPU (interrupt processing execution circuit) not shown. S 7 ' outputs the interrupt signal s 1 2 and the interrupt vector signal S13 to the CPU in accordance with the respective signals. The interrupt factor signal SA is input to the trigger circuit 1, and the interrupt factor signal SB is input to the flip-flop circuit 5, and the interrupt factor signal SC is input to the flip-flop circuit 9. Further, the interrupt reception signal S7 is input to the delay circuit 13, the AND circuit 15, the delay circuit 16, and the inverter circuit 17. Further, the interrupt control circuit C1 of the present embodiment is a positive logic circuit, and the case where the state of the signal is shifted from the low level to the high level is described as the setting, and the case where the transition from the high level to the low level is described as reset. The trigger circuit 1 is a trigger circuit for setting a reset with a function of a register as a state of the memory interrupt cause signal SA. In synchronization with the setting of the interrupt factor signal SA, the high-level interrupt factor signal S 1 is output as a g delay circuit. 2. An AND circuit 4, an OR circuit 21, and an interrupt vector generation circuit 23. Further, the flip-flop circuit 1 is synchronized with the setting of the reset signal S 14 input from the AND circuit 25, and controls the above-described interrupt factor state signal S 1 to a low level (reset). The delay circuit 2 outputs the inverter circuit 3 by delaying the interrupt factor state signal S1 by only _16-200842594. The inverter circuit 3 outputs a logic inversion signal of the interrupt factor state signal S 1 delayed by the delay circuit 2 to the AND circuit 4. The AND circuit 4 outputs a logical product signal, that is, a pulse signal s 2 of the logical inversion signal of the interrupt factor state signal S 1 input from the flip-flop circuit 1 and the interrupt factor state signal S 1 input from the inverter circuit 3 to the 〇R. Circuit 1 9. The trigger circuit 5 is a trigger circuit for setting reset of a function of a register as a state of the memory interrupt factor SB, and outputs a high level interrupt factor state signal S3 to the delay circuit 6 in synchronization with the setting of the interrupt factor signal SB. The AND circuit 8, the OR circuit 21, and the interrupt vector generating circuit 23. Further, the flip-flop circuit 5 is synchronized with the setting of the reset signal S 15 input from the AND circuit 26 to control the above-described interrupt factor state signal S 3 to a low level (reset). The delay circuit 6 outputs the interrupt factor state signal S3 to the inverter circuit 7 by delaying only the timing. The inverter circuit 7 outputs a logic inversion signal of the interrupt factor state signal S 3 delayed by the delay circuit 6 to the AND circuit 8. The AND circuit 8 outputs a logical product signal, that is, a pulse signal S4, which is a logical inversion signal of the interrupt factor state signal S3 input from the flip-flop circuit 5 and the interrupt factor state signal S3 input from the inverter circuit 7, to the R circuit 1 9 . . The trigger circuit 9 is a trigger circuit for setting and resetting a function of a register as a state of the memory interrupt factor SC, and outputs a high level interrupt factor state signal S5 to the delay circuit 1 in synchronization with the setting of the interrupt factor signal SC. 〇, AND circuit 12, OR circuit 21, and interrupt vector generation -17- 200842594 circuit 23. Further, the flip-flop circuit 9 is synchronized with the setting of the reset signal S16 input from the AND circuit 27, and controls the interrupt factor state signal S5 to a low level (reset). The delay circuit 10 outputs the interrupt signal state signal S 5 to the inverter circuit 11 only by delaying the timing. The inverter circuit 11 outputs a logic inversion signal of the interrupt factor state signal S5 delayed by the delay circuit 1 to the AND circuit 12. The AND circuit 12 outputs a logical product signal, that is, a pulse signal S 6 , which is a logical inversion signal of the interrupt factor state signal S 5 input from the flip-flop circuit 9 and the interrupt factor state signal S 5 input from the inverter circuit 11 to the pulse signal S 6 . R circuit 1 9. The delay circuit 13 outputs the inverter circuit 14 by delaying the interrupt reception signal S 7 for only a predetermined period of time. The inverter circuit 14 outputs a logic inversion signal of the interrupt reception signal S 7 delayed by the delay circuit 13 to the AND circuit 15. The AN D circuit 15 outputs a logical product signal, that is, a pulse signal S8, which is a logical inversion signal of the interrupt reception signal S7 input from the inverter circuit 14 to the flip-flop circuit 22, the AND circuit 25, and the AND circuit. 26 and AND circuit 27. The delay circuit 16 outputs the interrupt reception signal S 7 to the AN D circuit 18 only for a predetermined time. The inverter circuit 17 outputs a logic inversion signal of the interrupt reception signal s 7 to the AND circuit 18. The AND circuit 18 outputs a logical product signal, that is, a pulse signal S9, which is a logical inversion signal of the interrupt reception signal S7 delayed by the delay circuit 16 and the interrupt reception signal S7 output from the inverter circuit 17, to the OR. Circuit 1 9. The R circuit 1 9 outputs the logical sum -18-200842594 signals of the pulse signals S 2, S 4, S 6 and S 9 to the delay circuit 20. The delay circuit 20 outputs a synchronization signal s that delays the logic sum signal input from the 〇R circuit 19 to the trigger circuit 22 by only delaying the predetermined time. The OR circuit 21 outputs the retransmission of the interrupt factor state signals S1, S3, and S5 and the 彳g number S11 to the flip-flop circuit 22. The trigger circuit 22 is synchronized with the setting of the synchronization signal S1, and the state of the logical sum signal S11 is output to the CPU and the interrupt vector generation circuit 23 as the interrupt signal si2. Further, the flip-flop circuit 22 is synchronized with the setting of the pulse signal S 8 input from the AND circuit 15 to control the above-described interrupt signal S 1 2 to a low level (reset). The interrupt vector generation circuit 23 outputs the interrupt vector signal S13 enclosed in the interrupt factor states fg Nos. S1, S3, S5 to the CPU and the decoder circuit 24 in synchronization with the setting of the interrupt signal S12. The interrupt vector signal S 1 3 is a signal for displaying an address on the memory of the interrupt processing program to be executed by the CPU in accordance with the interrupt factor signal corresponding to the interrupt level state signal corresponding to the high level. That is, when the interrupt vector generation circuit 23 is, for example, the state of the interrupt factor state signal S1 is high, the output display stores an interrupt vector of the address on the memory of the interrupt processing program to be executed by the CPU according to the interrupt factor signal SA. Signal S 1 3. In addition, when the state of the plurality of interrupts is due to the state of the state signal being high, the interrupt vector generating circuit 23 outputs the interrupt vector signal s 1 corresponding to the interrupt factor state signal (interrupt factor signal) corresponding to the higher priority according to the predetermined priority order. 3. In this embodiment, the interrupt factor signal SA is set to the highest priority, and the interrupt factor signal S C is set to the lowest priority. The decoder circuit 24 is a decoding interrupt vector signal S 1 3, and it is determined that the interrupt -19- 200842594 vector signal s 1 3 is output corresponding to which interrupt factor signal, and the high level decision signal is output to correspond to the memory. The interrupt is an AND circuit (25, 26, 27) that is set by the trigger circuit (1, 5, 9) of the state of the signal. Specifically, when the decoder circuit 24 determines that the interrupt vector signal S13 is output corresponding to the interrupt factor signal SA, it outputs a high level decision signal to the AND circuit 25, and determines that the interrupt vector signal S13 corresponds to the interrupt factor signal. When the SB is the output, the AND circuit 26 outputs a high level determination signal, and when it is determined that the interrupt vector signal S! 3 is output corresponding to the interrupt factor signal SC, the AND circuit 27 outputs a high level determination signal. The AND circuit 25 outputs a logical product signal of the pulse signal S8 input from the AND circuit 15 and the determination signal input from the decoder circuit 24, that is, the reset signal S14 to the flip-flop circuit 1. The AND circuit 26 outputs the pulse signal S8 input from the AND circuit 15 to the trigger circuit 5, that is, the reset signal S1, which is the pass number of the judgment target number input from the decoder circuit 24. The AND circuit 27 outputs a reset signal S16, which is a logical product signal of the pulse signal S8 input from the AND circuit 15 and the decision signal input from the decoder circuit 24, to the flip-flop circuit 9. As described above, FIG. 1 shows an example of a configuration in which the interrupt factor signals are three. However, it is possible to appropriately add and erase the set reset trigger circuit for storing the state of the interrupt factor signal in accordance with the number of the interrupt factor signals, and to output the signal. An AND circuit of a reset signal, a delay circuit constituting a pulse generation circuit, an inverter circuit, and an AND circuit. Further, although the present embodiment is an example of an interrupt control circuit including a positive logic circuit, the present invention is not limited thereto, and may be constituted by a negative logic circuit of -20-200842594, which shifts the state of the signal from a low level to a level. The situation is reset as a reset and will be set from a high level to a low level. Next, the operation of the interrupt control circuit C 1 of the first embodiment as described above will be described using the timing chart of Fig. 2 . First, at the moment, once the interrupt cause signal SA is controlled (determined) to the high level, the trigger circuit 1 synchronizes with the interrupt factor signal SA, and outputs the high level interrupt factor signal S1 to the delay path 2, AND. The circuit 4, the OR circuit 21, and the interrupt vector generating circuit 23 at the time Ti, the OR circuit 21 is input with the high-level interrupt factor signal S1, so that the high-level logical sum signal S 1 1 is output to the transmitting circuit 22. At the time, the pulse generating circuit including the delay circuit 2, the inverter circuit 3, and the AND circuit 4 outputs the pulse signal S2 to the OR circuit 19 in synchronization with the setting of the interrupt factor signal S1. Since the OR circuit 19 is Since the pulse signal of the high level is input at time T!, the same pulse-like logic sum signal is output to the delay circuit 20. The delay circuit 20 delays the pulse-like logical sum input from the OR circuit 19 by only a predetermined time. The pulse-shaped synchronization signal S is output to the flip-flop circuit 22 at time T2. At time Τ2, the flip-flop circuit 22 is a set step with the synchronizing signal S10, and the state of the logical sum signal S1 1 (here, the high level) is output as a medium signal S12 to the CPU and the interrupt vector generating circuit 23. Moreover, at time T2, the interrupt vector generation circuit 23 is synchronized with the setting of the interrupt signal S12, and the set-up contact state of the interrupt vector signal corresponding to the interrupt factor state signal S1 is 0 S2 The output is off to the CPU and decoder circuit 24 at the fixed number -21 - 200842594. That is, the interrupt vector generation circuit 23 outputs an interrupt vector storing the address on the memory of the interrupt processing program to be executed by the CPU according to the interrupt factor signal SA because the state of the interrupt factor state signal S1 is high. Signal S 1 3. Further, the decoder circuit 24 determines that the interrupt vector signal S 1 3 is output corresponding to the interrupt factor signal SA, and outputs a high level decision signal to the AND circuit 25. On the other hand, if the CPU inputs the high level interrupt signal S 1 2 at time T2, that is, once the interrupt request is recognized, the address stored in the memory indicated by the interrupt vector signal S 13 is executed. The interrupt processing program performs interrupt processing corresponding to the interrupt factor signal SA. Next, at time Τ3, if the interrupt factor SB is controlled (set) to a high level, the trigger circuit 5 synchronizes with the setting of the interrupt factor signal SB, and outputs the high level interrupt factor signal S3 to the delay circuit 6, AND. The circuit 8, the OR circuit 21, and the interrupt vector generating circuit 23. At time T3, since the OR circuit 21 is at the high level of the interrupt factor state signals S1 and S3, the high level logic sum signal S11 is continuously output to the trigger circuit 22. Further, at time T3, the pulse generating circuit constituted by the delay circuit 6, the inverter circuit 7, and the AND circuit 8 outputs the pulse signal S4 to the OR circuit 19 in synchronization with the setting of the interrupt factor state signal S3. Since the or circuit 19 is the pulse signal S4 to which the high level is input at the time T3, the same pulse-like logical sum signal is output to the delay circuit 20. The delay circuit 20 delays the pulse-like logical sum signal input from the Ο R circuit 19 by only -22-200842594, and outputs the pulse-shaped synchronization signal s 1 0 to the flip-flop circuit 22 at time T4. As described above, at time T4, the pulse-shaped synchronizing signal s 1 0 is input to the flip-flop circuit 2 2, but at this time point, the reset pulse signal S8 of the flip-flop circuit 2 2 is not input, so the flip-flop circuit 22 is Independent of the input of the synchronization signal S 1 0, the high level interrupt signal s 1 2 is continuously output. Further, since the interrupt vector generating circuit 23 maintains the interrupt signal S丨2 at the high level, the interrupt vector signal S13 corresponding to the interrupt factor signal S A is continuously output. That is, the decoder circuit 24 is a decision signal for continuously outputting a high level to the AND circuit 25. Then, the CPU completes the interrupt processing corresponding to the interrupt factor signal SA. At time T5, it is assumed that the interrupt reception processing signal S7, which is the transition to the next interrupt processing, is controlled (set) to a high level. At this time I, the pulse generating circuit including the delay circuit 13, the inverter circuit 14, and the AND circuit 15 synchronizes with the setting of the interrupt reception signal s7, and outputs the pulse signal S8 to the flip-flop circuit 22 and the AND circuit 25. AND circuit 26 and AND circuit 27. The trigger circuit 22 controls (resets) the interrupt signal S丨2 to a low level in synchronization with the rise of the pulse signal S8 at time T5. On the other hand, the AND circuit 25 outputs the pulse-shaped reset signal S 1 4 to the flip-flop circuit 1 by inputting the high-level determination signal and the high-level pulse signal S8 at the time λ5. Thereby, the trigger circuit 1 synchronizes (resets) the interrupt factor state signal S 1 to the low level in synchronization with the setting of the reset signal S 14 at time T 5 . In addition, at this point of time, since the interrupt factor state signal S 3 is at a high level, the OR circuit 2 1 is -23-200842594 and continuously outputs the high level logic sum signal s 1 1 . Then, at time τ6, when the interrupt reception signal S7 is controlled (reset) to the low level, the pulse generation circuit including the delay circuit 16, the inverter circuit 17 and the AND circuit 18 is the interrupt reception signal S7. The reset synchronization outputs the high level pulse signal S9 to the OR circuit 19. The OR circuit 197 is a pulse signal S9 which is input to the high level at time T6, and therefore outputs the same pulse-like logical sum signal to the delay circuit 20. The delay circuit 20 delays the pulse-like logical sum signal input from the OR circuit 19 by only a predetermined time, and outputs a pulse-like synchronization signal S 1 0 to the trigger circuit 22 at time T7. At time Τ7, the flip-flop circuit 22 is synchronized with the setting of the synchronizing signal S10, and the state of the logical sum signal S11 (here, the high level) is output to the CPU and the interrupt vector generating circuit 23 as the interrupt signal S12. Further, at time T7, the interrupt vector generating circuit 23 synchronizes with the setting of the interrupt signal S 1 2, and outputs the interrupt vector signal S13 corresponding to the interrupt factor state signal S 3 to the CPU and the decoder circuit 24. That is, the interrupt vector generation circuit 23 is in the state where the state of the interrupt factor state signal S3 is high, and therefore the output display stores the address vector of the address on the memory of the interrupt processing program to be executed by the CPU according to the interrupt factor signal SB. Signal S 1 3. Further, the decoder circuit 24 determines that the interrupt vector signal S13 is output corresponding to the interrupt factor signal SB, and outputs a high level decision signal to the AND circuit 26. On the other hand, if the CPU inputs the high-level interrupt signal S 1 2 ' at time T7, that is, once the interrupt request is recognized, the memory shown in the interrupt vector signal S 1 3 is stored. The interrupt processing program of the upper address performs interrupt processing corresponding to the interrupt factor signal SB. Then, C P 完成 completes the interrupt processing corresponding to the interrupt factor signal S b , and at time T s , the interrupt reception signal S7 that is supposed to shift the display to the next possible acceptance processing of the interrupt processing is controlled (set) at the high level. At this time Τ8, the pulse generating circuit composed of the delay circuit 13, the inverter circuit 14, and the AND circuit 15 is synchronized with the setting of the interrupt receiving signal s7. The pulse signal S8 is output to the flip-flop circuit 22, the AND circuit 25. AND circuit 26 and AND circuit 27. The trigger circuit 22 controls (resets) the interrupt signal S丨2 to a low level in synchronization with the setting of the pulse signal S8 at time T8. On the other hand, the AND circuit 26 outputs a pulse-shaped reset signal S 1 5 to the flip-flop circuit 5 by inputting a high-level determination signal at a time T8 and a high-level pulse signal S8. Thereby, the trigger circuit 5 synchronizes (resets) the interrupt factor state signal S 3 to the low level in synchronization with the setting of the reset signal S 15 at time Τ8. Further, at this point of time, since all the interrupt cause state signals are formed at a low level, the OR circuit 21 is a logical sum signal S 1 1 which outputs a low level. Thereafter, the interrupt signal S12 and the interrupt vector signal S13 are output in accordance with the state of the interrupt factor signal SA, the interrupt factor signal SB, the interrupt factor signal SC, and the interrupt acceptance signal S7. As described above, the interrupt control circuit C 1 ′ according to the first embodiment of the present invention outputs the interrupt signal S 1 2 in synchronization with the interrupt reception signal S 7 input from the interrupt processing execution circuit of the CPU, and thus does not have to be common to the conventional one. The clock signal can be used for a non-synchronous CPU, which can achieve high speed -25. 200842594 and low power consumption. Further, in the conventional interrupt control circuit, since the function of memorizing or initializing the state of the interrupt factor signal is not required, it is necessary to provide such a function to the external circuit side, resulting in a decrease in design work efficiency and a long period of design period. In contrast, the interrupt control circuit C1 has a function of memorizing or initializing the state of the interrupt factor signal, that is, the interrupt factor memory circuit (trigger 1, 5, 9), and outputting the reset signal to the interrupt factor memory. The reset signal generating circuit (decoder circuit 24, AND circuit 25, 26, 27) of the circuit can improve the design work efficiency and shorten the design period. (Second Embodiment) Next, a second embodiment of the interrupt control circuit according to the present invention will be described. Fig. 3 is a block diagram showing the configuration of an interrupt control circuit C2 of the second embodiment. In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted. Hereinafter, points different from those in FIG. 1 will be described. This second embodiment is a configuration of the interrupt control circuit c 2 when each external circuit is provided with a function of memorizing and initializing the state of the interrupt factor signal. That is, the flip-flop control circuit C 2 is not provided with the flip-flop circuits 1, 5 and 9, the external circuit 30 has the flip-flop circuit 1, the external circuit 4 has the flip-flop circuit 5, and the external circuit 50 has the flip-flop circuit 9. The interrupt control circuit C2 is an interrupt factor state signal S1 output from the flip-flop circuit 1 of the external circuit 3, an interrupt factor state signal S3 output from the flip-flop circuit 5 of the external circuit 40, and a trigger from the external circuit 50-26 - 200842594 The interrupt of the output of circuit 9 is due to the status signal S 5 . The interrupt factor state S1 is input to the delay circuit 2, the AND circuit 4, and the OR circuit 21 break vector generation circuit 23, and the interrupt factor state signal S3 is the input delay circuit 6, the AND circuit 8, the OR circuit 21, and the interrupt vector generation 23, The interrupt factor signal S5 is input to the delay circuit 10, the circuit 12, the OR circuit 21, and the interrupt vector generating circuit 23. Further, the AND circuit 25 is a flip-flop circuit 1 that outputs a reset signal S14 to the outer path 30. The AND circuit 26 is a flip-flop circuit 5 that resets the reset signal S15 to the external circuit 40. The AND circuit 27 is a flip-flop circuit 9 that outputs a reset S 16 to the external circuit 50. The operation timing chart of the interrupt control C2 of the second embodiment having the above-described configuration is the same as that of the first embodiment (Fig. 2). In this way, when each external circuit has a function of recalling and initializing the state of the interrupt factor signal, it is also possible to achieve higher speed and lower power consumption by using the interrupt control C2 in accordance with the asynchronous type CPU. [Circuit Substrate] Next, a description will be given of the above-described interrupt control circuit C 1 or C2 circuit substrate.
圖4是表示具備本發明的中斷控制電路C1或C2 路基板60之一實施例的槪略平面圖。如圖4所示， 路基板60是在可撓性基板61上形成有具備有機TFT 信號 及中 至延 電路 AND 部電 輸出 信號 電路 此省 以記 電路 費電 的電 的電 本電 (未 -27- 200842594 圖示）作爲主動元件的顯示區域62，在顯示區域62的周 邊部配置有用以驅動有機TFT的第1驅動電路63及第2 驅動電路64、及經由匯流排配線65來連接至該等第1驅 動電路63及第2驅動電路64的CPU66、RAM67、天線圖 案（Antenna Pattern) 68、類比RF電路69及太陽電池70 〇 可撓性基板6 1不限於透明性、非透過性，可藉由各 種材料來構成。本實施形態是採用塑膠基板，可撓性特佳 者。具體而言，可爲以聚乙烯對苯二甲酸酯（ polyethylene terephthalate, PET )、酸乙二酯（ polyethylene naphthalate，PEN)、聚本酸石风（Polyether sulfone，PES)、聚碳酸酯（Polycarbonate，PC)、芳香族 聚酯（液晶聚合物）、聚醯亞胺（PI )等所構成的塑膠基 板（樹脂基板）。又’亦可採用其他具有可撓性者’例如 玻璃基板、砂基板、金屬基板、砷化鎵（Gallium Arsenide)基板等。 第1驅動電路63及第2驅動電路64是包含低温多晶 矽薄膜電晶體（LTPS_TFT )的半導體晶片’集合於可撓 性基板61的相隣的2邊的周緣部’沿著圖中的X方向及 γ方向來成列（兀件晶片列）而配置。％ 1驅動電路6 3 及第2驅動電路6 4是藉由黏劑來固定於可撓性基板6 1上 。第1驅動電路6 3及第2驅動電路6 4的具體構成並無特 別加以限定，但若使用LTPS_TFT ’則可取得高電場效果 速度，可高速驅動的同時，可撓性基板6 1上的佔有面積 -28- 200842594 小，因此非常合適。 資料線63a是在顯示區域62中延伸於圖4中的Y方 向的配線，在顯示區域62内連接至有機TFT的源極電極 ，且在從顯不區域6 2延伸出至+ Y方向的位置與第1驅動 電路63電性連接。掃描線64a是在顯示區域62中延伸於 X方向的配線，與顯示區域62内的有機TFT的閘極電極 電性連接，且在從顯示區域62延伸出至-X方向的位置與 第2驅動電路64電性連接。第1驅動電路63是對有機 f: TFT的資料線63a供給電力，第2驅動電路64是對掃描 線64a供給驅動信號，藉此可主動驅動有機TFT。 其次，參照圖5來針對有機TFT62a進行説明。圖5 是沿著圖4的A-A’線的位置的要部剖面圖。有機TFT62a 是由可撓性基板6 1側積層源極電極及汲極電極80、有機 半導體層8 1、絶緣層82、閘極電極83而形成的所謂頂閘 極構造的電晶體。並且，對應於有機TFT62a來設有圖示 省略的畫素電極，畫素電極是經由接觸孔來與汲極電極8 0 \； 電性連接。另外，本實施形態雖是針對頂閘極構造來進行 説明，但並非限於該構造，亦可爲底閘極構造。 有機TFT62a的閘極電極83是直接或經由其他的配線 來與延伸於可撓性基板6 1的Y方向之掃描線64a電性連 接，且經由形成於可撓性基板6 1的周緣部之連接部84來 與第2驅動電路64的端子部85電性連接。有機TFT6 2a ，如圖5所示，在其外周部，絶緣層82會形成階差部82a ，因此形成於絶緣層8 2上的掃描線6 4 a是以能夠沿著該 -29- 200842594 階差部8 2 a的方式覆蓋絶緣層8 2的表面而達連接部8 4形 成。連接部84是形成於可撓性基板6 1上的金屬墊等，設 於各配線上，第2驅動電路64是藉由黏劑86來固定於可 撓性基板6 1。並且，在第2驅動電路64與可撓性基板61 呈對向的一側的面所形成的端子部8 5會與可撓性基板6 1 上的連接部84抵接而電性連接。 在圖5中雖省略圖示，但實際有機TFT62a的源極電 極8 0是與沿著可撓性基板6 1的Y方向延伸的資料線6 3 a 直接或經由其他的配線來連接，資料線63 a的端部是連接 至設於第1驅動電路63的端子部。 在此，源極電極80及資料線63a是形成於絶緣層82 的下層，因此在第1驅動電路63側的絶緣層82的端部， 資料線63a是從可撓性基板61與絶緣層82之間延伸出至 圖4的-X方向，該延出部會形成與第1驅動電路63的連 接端子。 回到圖4説明。CPU66是根據經由天線圖案68及類 比RF電路69所取得的基頻（base band)信號來統括性 地控制本電路基板60的全體動作之半導體晶片。RAM6 7 是被使用於CPU66的控制動作之工作記憶體。天線圖案 68是接受自外部傳送的RF信號而輸出至類比RF電路69 。類比RF電路69是對經由上述天線圖案68而接受的RF 信號進行放大、頻率變換、解調等的信號處理，變換成基 頻信號而輸出至CPU66。太陽電池70是對上述第1驅動 電路63、第2驅動電路64、CPU66、RAM67、類比RF電 -30- 200842594 路69供給電源電壓。另外，該等CPU66、RAM67、天線 圖案68、類比RF電路69及太陽電池70亦藉由黏劑等來 固定於可撓性基板6 1上。 本發明的中斷控制電路C1及C2可作爲對上述CPU66 的中斷控制電路採用，設於CPU66或類比RF電路69的 内部。藉此，CPU66可使用非同步電路對應的CPU，可取 得能夠實現高速化及低消費電力化的電路基板。 〔光電裝置〕 其次，說明有關具備上述電路基板60的光電裝置。 另外’在本實施形態是說明有關光電裝置爲使用上述電路 基板60來構成的電泳顯示裝置。圖6是表示本電泳顯示 裝置1 〇 〇的槪略構成剖面圖。如該圖6所示，電泳顯示裝 置1〇〇是使用電路基板60作爲TFT基板，以能夠對向該 電路基板60之方式來配置對向基板90，在該等兩基板60 、9 0之間配置電泳層（光電層）9 1。 在此’電泳層91是具備複數的微囊（microcapsule) 91a。此微囊91a是藉由樹脂皮膜所形成，大小是與1畫 素的大小同程度’以能夠覆蓋顯示區域全域的方式複數配 置。並且，微囊9 1 a實際上是隣接的微囊9丨a彼此間密合 ，因此顯示區域62是藉由微囊9 1 a無間隙覆蓋。在微囊 91a中封入具有分散媒92、電泳粒子93等的電泳分散液 94 ° 其次，說明有關具有分散媒92、電泳粒子93的電泳 -31 - 200842594 分散液94。 電泳分散液94是使電泳粒子93分散於藉由染料所染 色的分散媒92中。電泳粒子93是由無機氧化物或無機氫 氧化物所構成之直徑〇·〇1μπι〜ΙΟμηι程度的大略球狀的微 粒子，具有與上述分散媒92相異的色相（包含白色及黒 色）。在由如此氧化物或氫氧化物所構成的電泳粒子93 中存在固有的表面等電點，依照分散媒92的氫離子指數 pH，其表面電荷密度（帶電量）會變化。 在此，所謂表面等電點是依照氫離子指數pH來表示 水溶液中的兩性電解質的電荷的代數和爲形成零的狀態者 。例如，當分散媒92的pH等於電泳粒子93的表面等電 點時，粒子的實效電荷是形成零，粒子是對外部電場而言 形成無反應的狀態。又，當分散媒92的pH比粒子的表面 等電點更低時，粒子的表面是根據下式（1 )帶正的電荷 。相反的’分散媒92的pH比粒子的表面等電點更高時， 粒子的表面是根據下式（2 )帶負的電荷。 pH 低：M-OH + H + (過剩）+ ΟΗ· —Μ-ΟΗ2 + + ΟΗ· · · .(1) pH 高：Μ-ΟΗ + Η + + ΟΙΓ(過剩）— M-OH一+ H+ · · · (2) 另外’當擴大分散媒92的pH與粒子的表面等電點的 差時，按照反應式（1 )或（2 )，粒子的帶電量會増加， 但若該差形成所定値以上則大致飽和，即使令pH更以上 變化’帶電量也不會變化。該差的値雖是依粒子的種類、 大小、形狀等而有所差異，但大槪i以上，則無論在何種 的粒子中’帶電量也會大致飽和。 -32- 200842594 上述的電泳粒子9 3，例如爲使用二氧化鈦，氧化鋅， 氧化鎂，紅色氧化鐵，氧化鋁，黑色低氧化鈦，氧化鉻， 勃姆石，二氧化砂，氫氧化鎂，氫氧化鎳，氧化鉻，氧化 銅等。 又，如此的電泳粒子93並非僅爲單獨的微粒子，亦 可在實施各種表面改質的狀態下使用。如此的表面改質方 法，例如有以丙烯酸樹脂，環氧樹脂，聚酯樹脂，聚尿烷 樹脂等的聚合物來塗佈處理粒子表面的方法、或以矽烷系 ’酞酸酯系，鋁系，氟系等的耦合劑來耦合處理的方法、 或與丙烯酸系單體，苯乙烯單體，環氧系單體，聚異氰酸 酯系單體等接枝聚合處理的方法等，可將該等的處理予以 單獨或二種類以上組合進行。 對於分散媒92而言是使用烴，鹵化烴，醚等的非水 系有機溶媒，藉由醇溶黑，油溶黃，油溶藍、油溶綠、 BALII FIRST BLUE、MACRO REX BLUE、油溶棕、蘇丹 黑’堅牢橘等的染料來染色，而呈現與電泳粒子93相異 的色相。 在如此構成的電泳顯示裝置1 00中，是形成具備上述 電路基板60的構成，因此可高速化及低消費電力化，且 形成可撓性的顯示裝置。另外，利用本發明的電路基板60 之光電裝置並非限於本實施形態，當然亦可適用於液晶顯 示器或有機EL顯示器等。 〔電子機器〕 -33- 200842594 上述電泳顯示裝置100是適用於具備顯示部的各種電 子機器。以下，說明有關具備上述電泳顯示裝置100的電 子機器之例。 首先’說明有關將電泳顯示裝置1 0 0適用於可撓性的 電子紙之例。圖7是表示該電子紙的構成立體圖，電子紙 2 0 〇是具備本發明的電泳顯示裝置丨〇 〇作爲顯示部。電子 紙200是具備由具有和以往的紙同樣質感及柔軟性的薄片 所構成的本體2 0 1。 又’圖8是表示電子筆記的構成立體圖，電子筆記 3〇〇是圖7所示的電子紙200被複數張捆紮，被封套301 所夾著。封套3 0 1是具備例如輸入從外部的裝置傳送的顯 示資料之未圖示的顯示資料輸入手段。藉此，可按照該顯 示資料，維持電子紙200捆紮的狀態不動，變更或更新顯 示内容。 又，除了上述例子以外，其他例子還有··液晶電視機 ，取景器型或監視器直視型的攝影機，衛星導航裝置，呼 & 叫器，電子記事本，計算機，打字機，工作站，電視電話 ，POS終端機，及具備觸控板的機器等。當然，本發明的 光電裝置亦可適用於如此電子機器的顯示部。 【圖式簡單說明】 圖1是表示本發明的第1實施形態之中斷控制電路的 構成方塊圖。 圖2是表示本發明的第1實施形態之中斷控制電路的 -34- 200842594 動作時序圖。 圖3是表示本發明的第2實施形態之中斷控制電路的 構成方塊圖。 圖4是表示具備本發明的中斷控制電路的電路基板之 一實施例的平面圖。 圖5是表示具備本發明的中斷控制電路的電路基板之 一實施例的剖面圖。 圖6是表示具備本發明的電路基板的光電裝置之一實 施例的剖面圖。 圖7是具備本發明的光電裝置之電子機器的第1實施 例。 圖8是具備本發明的光電裝置之電子機器的第2實施 例。 【主要元件符號說明】Fig. 4 is a schematic plan view showing an embodiment of an interrupt control circuit C1 or a C2 substrate 60 of the present invention. As shown in FIG. 4, the circuit board 60 is formed with a circuit having an organic TFT signal and an intermediate-to-extension circuit AND electrical output signal circuit on the flexible substrate 61. 27- 200842594 In the display area 62 as an active element, the first drive circuit 63 and the second drive circuit 64 for driving the organic TFT are disposed in the peripheral portion of the display region 62, and the bus line 65 is connected to the display circuit 62. The CPU 66, the RAM 67, the antenna pattern 68, the analog RF circuit 69, and the solar cell 70 of the first drive circuit 63 and the second drive circuit 64 are not limited to transparency and impermeability. It is made up of various materials. In this embodiment, a plastic substrate is used, and the flexibility is particularly excellent. Specifically, it may be polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), polycarbonate (Polycarbonate). , PC), a plastic substrate (resin substrate) composed of an aromatic polyester (liquid crystal polymer) or polyimine (PI). Further, other flexible persons such as a glass substrate, a sand substrate, a metal substrate, a gallium arsenide substrate, or the like may be used. The first drive circuit 63 and the second drive circuit 64 are semiconductor wafers including a low-temperature polysilicon thin film transistor (LTPS_TFT), which are collected on the adjacent two sides of the flexible substrate 61 in the X direction and along the X direction in the figure. The gamma direction is arranged in a row (piece wafer row). The %1 drive circuit 633 and the second drive circuit 614 are fixed to the flexible substrate 61 by an adhesive. The specific configuration of the first drive circuit 633 and the second drive circuit 614 is not particularly limited. However, when the LTPS_TFT' is used, a high electric field effect speed can be obtained, and the high-speed drive can be performed while occupying the flexible substrate 61. The area -28- 200842594 is small, so it is very suitable. The data line 63a is a wiring extending in the Y direction in FIG. 4 in the display region 62, is connected to the source electrode of the organic TFT in the display region 62, and extends from the display region 62 to the position in the +Y direction. It is electrically connected to the first drive circuit 63. The scanning line 64a is a wiring extending in the X direction in the display region 62, electrically connected to the gate electrode of the organic TFT in the display region 62, and extends from the display region 62 to the position in the -X direction and the second driving. Circuitry 64 is electrically connected. The first drive circuit 63 supplies power to the data line 63a of the organic f:TFT, and the second drive circuit 64 supplies a drive signal to the scan line 64a, whereby the organic TFT can be actively driven. Next, the organic TFT 62a will be described with reference to FIG. 5. Fig. 5 is a cross-sectional view of an essential part taken along a line A-A' of Fig. 4; The organic TFT 62a is a transistor of a so-called top gate structure in which a source electrode and a drain electrode 80, an organic semiconductor layer 81, an insulating layer 82, and a gate electrode 83 are laminated on the flexible substrate 61 side. Further, a pixel electrode (not shown) is provided corresponding to the organic TFT 62a, and the pixel electrode is electrically connected to the gate electrode 80 via the contact hole. Further, although the present embodiment has been described with respect to the top gate structure, the present invention is not limited to this structure, and may be a bottom gate structure. The gate electrode 83 of the organic TFT 62a is electrically connected to the scanning line 64a extending in the Y direction of the flexible substrate 61 directly or via another wiring, and is connected via the peripheral portion formed on the flexible substrate 61. The portion 84 is electrically connected to the terminal portion 85 of the second drive circuit 64. The organic TFT 6 2a, as shown in FIG. 5, has a step portion 82a formed on the insulating layer 82 at its outer peripheral portion, so that the scanning line 64a formed on the insulating layer 8 2 is capable of following the step -29-200842594 The portion of the insulating layer 8 2 covers the surface of the insulating layer 8 2 to form the connecting portion 84. The connecting portion 84 is a metal pad or the like formed on the flexible substrate 61, and is provided on each of the wirings. The second driving circuit 64 is fixed to the flexible substrate 61 by an adhesive 86. Further, the terminal portion 85 formed on the surface on which the second drive circuit 64 and the flexible substrate 61 face each other is electrically connected to the connection portion 84 on the flexible substrate 6 1 . Although not shown in FIG. 5, the source electrode 80 of the actual organic TFT 62a is connected to the data line 6 3 a extending in the Y direction of the flexible substrate 161 directly or via another wiring, and the data line is connected. The end of 63 a is connected to the terminal portion provided in the first drive circuit 63. Here, since the source electrode 80 and the data line 63a are formed under the insulating layer 82, the data line 63a is from the flexible substrate 61 and the insulating layer 82 at the end of the insulating layer 82 on the first drive circuit 63 side. The extension extends to the -X direction of FIG. 4, and the extension portion forms a connection terminal with the first drive circuit 63. Return to Figure 4 for explanation. The CPU 66 is a semiconductor wafer that collectively controls the overall operation of the circuit board 60 based on a base band signal acquired via the antenna pattern 68 and the analog RF circuit 69. The RAM 6 7 is a working memory used for the control operation of the CPU 66. The antenna pattern 68 is an RF signal that is received from the outside and output to the analog RF circuit 69. The analog RF circuit 69 performs signal processing such as amplification, frequency conversion, demodulation, and the like on the RF signal received via the antenna pattern 68, converts it into a baseband signal, and outputs it to the CPU 66. The solar battery 70 supplies a power supply voltage to the first drive circuit 63, the second drive circuit 64, the CPU 66, the RAM 67, and the analog RF power -30-200842594. Further, the CPU 66, the RAM 67, the antenna pattern 68, the analog RF circuit 69, and the solar cell 70 are also fixed to the flexible substrate 61 by an adhesive or the like. The interrupt control circuits C1 and C2 of the present invention can be used as an interrupt control circuit for the CPU 66, and are provided inside the CPU 66 or the analog RF circuit 69. Thereby, the CPU 66 can use a CPU corresponding to the asynchronous circuit, and can obtain a circuit board capable of achieving high speed and low power consumption. [Photoelectric Device] Next, a photovoltaic device including the above-described circuit substrate 60 will be described. Further, in the present embodiment, an electrophoretic display device in which the above-described circuit substrate 60 is used in the photovoltaic device is described. Fig. 6 is a schematic cross-sectional view showing the structure of the electrophoretic display device 1 〇 。. As shown in FIG. 6, the electrophoretic display device 1A uses the circuit board 60 as a TFT substrate, and the counter substrate 90 is disposed so as to be able to face the circuit board 60, between the two substrates 60 and 90. The electrophoretic layer (photoelectric layer) 9 1 is disposed. Here, the electrophoretic layer 91 is a plurality of microcapsules 91a. The microcapsules 91a are formed by a resin film, and the size is the same as the size of one pixel, and is plurally arranged so as to cover the entire area of the display region. Further, the microcapsules 9 1 a are actually adjacent to each other, and the display region 62 is covered by the microcapsules 9 1 a without gaps. The electrophoretic dispersion liquid having the dispersion medium 92, the electrophoretic particles 93, and the like is sealed in the microcapsules 91a. Next, the electrophoresis -31 - 200842594 dispersion liquid 94 having the dispersion medium 92 and the electrophoretic particles 93 will be described. The electrophoretic dispersion 94 disperses the electrophoretic particles 93 in a dispersion medium 92 dyed by a dye. The electrophoretic particles 93 are substantially spherical microparticles having a diameter of 〇·〇1 μm to ΙΟμηι composed of an inorganic oxide or an inorganic hydroxide, and have a hue (including white and ochre) different from the dispersion medium 92 described above. In the electrophoretic particles 93 composed of such an oxide or hydroxide, there is an inherent surface isoelectric point, and the surface charge density (charge amount) varies depending on the hydrogen ion index pH of the dispersion medium 92. Here, the surface isoelectric point is an algebra of the electric charge of the amphoteric electrolyte in the aqueous solution in accordance with the hydrogen ion index pH, and is a state in which zero is formed. For example, when the pH of the dispersion medium 92 is equal to the isoelectric point of the surface of the electrophoretic particle 93, the effective charge of the particle is zero, and the particle forms a state of no reaction to the external electric field. Further, when the pH of the dispersion medium 92 is lower than the surface isoelectric point of the particles, the surface of the particles is positively charged according to the following formula (1). When the pH of the dispersion medium 92 is higher than the surface isoelectric point of the particles, the surface of the particles is negatively charged according to the following formula (2). Low pH: M-OH + H + (excess) + ΟΗ·-Μ-ΟΗ2 + + ΟΗ· · · (1) pH high: Μ-ΟΗ + Η + + ΟΙΓ (excess) - M-OH-+ H+ · · · (2) In addition, when the difference between the pH of the dispersion medium 92 and the surface isoelectric point of the particles is increased, the charge amount of the particles is increased according to the reaction formula (1) or (2), but if the difference is formed, The above is almost saturated, and even if the pH is changed more than the above, the amount of charge does not change. Although the difference is different depending on the type, size, shape, and the like of the particles, if it is greater than or equal to i, the amount of charge will be substantially saturated regardless of the particles. -32- 200842594 The above electrophoretic particles 93 are, for example, titanium dioxide, zinc oxide, magnesium oxide, red iron oxide, aluminum oxide, black titanium oxide, chromium oxide, boehmite, silica sand, magnesium hydroxide, hydrogen. Nickel oxide, chromium oxide, copper oxide, and the like. Further, such electrophoretic particles 93 are not limited to individual particles, and may be used in a state where various surface modifications are performed. Such a surface modification method includes, for example, a method of coating a surface of a treated particle with a polymer such as an acrylic resin, an epoxy resin, a polyester resin, or a polyurethane resin, or a decane-based phthalate type or aluminum system. a method of coupling treatment with a coupling agent such as fluorine or a method of graft polymerization treatment with an acrylic monomer, a styrene monomer, an epoxy monomer, a polyisocyanate monomer, etc., etc. The treatment is carried out alone or in combination of two or more types. For the dispersion medium 92, a non-aqueous organic solvent such as a hydrocarbon, a halogenated hydrocarbon or an ether is used, which is dissolved in alcohol, yellow in oil, yellow in oil, green in oil, green in water, BALII FIRST BLUE, MACRO REX BLUE, and oil-soluble brown. A dye such as Sudan black 'firm orange or the like is dyed to exhibit a hue different from that of the electrophoretic particles 93. In the electrophoretic display device 100 configured as described above, since the circuit board 60 is provided, it is possible to increase the speed and power consumption, and to form a flexible display device. Further, the photovoltaic device using the circuit board 60 of the present invention is not limited to the embodiment, and can of course be applied to a liquid crystal display or an organic EL display. [Electronic Device] -33- 200842594 The above-described electrophoretic display device 100 is applied to various electronic devices including a display unit. Hereinafter, an example of an electronic apparatus including the above-described electrophoretic display device 100 will be described. First, an example will be described in which the electrophoretic display device 100 is applied to flexible electronic paper. Fig. 7 is a perspective view showing the configuration of the electronic paper, and the electronic paper 200 is an electrophoretic display device of the present invention as a display unit. The electronic paper 200 is provided with a main body 203 composed of a sheet having the same texture and flexibility as conventional paper. Further, Fig. 8 is a perspective view showing the configuration of the electronic note. The electronic note 3 is bundled with a plurality of sheets of the electronic paper 200 shown in Fig. 7, and is sandwiched by the envelope 301. The jacket 301 is a display material input means (not shown) that displays, for example, a display material transmitted from an external device. Thereby, the state in which the electronic paper 200 is bundled can be maintained in accordance with the display material, and the display content can be changed or updated. In addition to the above examples, other examples include LCD TVs, viewfinder or monitor direct view cameras, satellite navigation devices, callers, electronic organizers, computers, typewriters, workstations, and video phones. , POS terminals, and machines with touch panels. Of course, the photovoltaic device of the present invention can also be applied to the display portion of such an electronic device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the configuration of an interrupt control circuit according to a first embodiment of the present invention. Fig. 2 is a timing chart showing the operation of -34 - 200842594 of the interrupt control circuit according to the first embodiment of the present invention. Fig. 3 is a block diagram showing the configuration of an interrupt control circuit according to a second embodiment of the present invention. Fig. 4 is a plan view showing an embodiment of a circuit board including the interrupt control circuit of the present invention. Fig. 5 is a cross-sectional view showing an embodiment of a circuit board including the interrupt control circuit of the present invention. Fig. 6 is a cross-sectional view showing an embodiment of a photovoltaic device including the circuit board of the present invention. Fig. 7 shows a first embodiment of an electronic apparatus including the photovoltaic device of the present invention. Fig. 8 shows a second embodiment of an electronic apparatus including the photovoltaic device of the present invention. [Main component symbol description]
Cl、C2 :中斷控制電路 1、 5、9、22 :觸發電路 2、 6、 10、 13、 16、 20:延遲電路 3、 7、1 1、1 4、1 7 :倒相電路 4、 8、12、15、18、24、25、26: AND 電路 1 9、2 1 : Ο R 電路 23:中斷向量發生電路 24 :解碼器電路 60 :電路基板 -35- 200842594 100 :光電裝置（電泳顯示裝置） 200 :電子紙（電子機器） 3 00 :電子筆記（電子機器）Cl, C2: interrupt control circuit 1, 5, 9, 22: trigger circuit 2, 6, 10, 13, 16, 20: delay circuit 3, 7, 1 1 , 1 4, 1 7 : inverter circuit 4, 8 , 12, 15, 18, 24, 25, 26: AND circuit 1 9 , 2 1 : Ο R circuit 23 : interrupt vector generation circuit 24 : decoder circuit 60 : circuit substrate - 35 - 200842594 100 : photoelectric device (electrophoretic display Device) 200: Electronic paper (electronic machine) 3 00: Electronic note (electronic machine)