TW200839907A - Wire bonding method - Google Patents

Wire bonding method Download PDF

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TW200839907A
TW200839907A TW096131000A TW96131000A TW200839907A TW 200839907 A TW200839907 A TW 200839907A TW 096131000 A TW096131000 A TW 096131000A TW 96131000 A TW96131000 A TW 96131000A TW 200839907 A TW200839907 A TW 200839907A
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image
bonding
semiconductor wafer
joint
wire
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TW096131000A
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Chinese (zh)
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TWI351068B (en
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Kenji Sugawara
Yong Chen
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Shinkawa Kk
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention is provided to speed up a wire bonding operation and to further improve accuracy of wire bonding. The invention includes steps of: transferring a semiconductor chip 2A to a bonding center 50 (step 20), capturing the image of a bonding point of the semiconductor chip 2A (step 21), identifying position of a bonding point (step 22), wire bonding a corrected bonding point (step 24), capturing an image after the bonding for the semiconductor chip 2A is performed (step 25), transferring a next semiconductor chip 2A to a bonding center 50 (step 30), capturing the image of a bonding point of the semiconductor chip 2B (step 31), identifying position of a bonding point (step 32), wire bonding the corrected bonding point (step 34), and identifying, during wire bonding, the shift of the position of the image of the semiconductor chip 2A after the bonding is performed (step 26).

Description

200839907 九、發明說明： 【發明所屬之技術領域】 本發明係關於以光學方法辨識半導體裝置之接合點位 置，於接合點位置連接引線之打線方法。 【先前技術】 以圖3至圖5說明習知打線方法。如圖3所示，於導 線架1附著有半導體晶# 2之試料3係藉由圖4所示之打 線裝置10將引線4以打線方法連接於半導體晶片2之墊 部PI、P2…與導線架i之導線部L1、L2〜。 曰於上述打線方法中，一般係先以攝影裝置u檢測半導 體晶片2上之至少2個定點及導線架】上之至少2個定點 二正規位置偏移之量’以演算部根據其檢測值修正事先儲 子：接合座標。以該攝影裝置"檢測時，攝影裝置"之 定點係、又X軸馬達12及Y軸馬達13驅動而位於測 叙正上方。如前述接合座標被修正後，毛細管 移動於ΧΥ軸方向及ζ軸方向 破 4ϋ 、 ㈣Π將插通於毛細管15之引線 、、於半導體晶片2之墊部p j、ρ2 | 、、 部U、L2. 。 P2...與導線架1之導線 此時’由於攝影裝置U之中心車 中心鉍κ本 α與毛細官15之 輛15a有距離W之偏位’故 點之低#、，〜 辦〜展置11測得定 禹私亚修正接合座標後，χγ台16 及Y κ、土 積田X輛馬達12 軸馬達13被移動偏位量w，毛细其 第1接入之卜* p 位於試料3之 口之上方。接者，藉由x 迻及γ軸馬達13 5 200839907 台16在XY軸方向之移動以及z軸馬達14使毛細 二臂17之上下移動（或擺動）而使毛細管15在Z軸方向之 私引線4被打線於該修正後之接合座標。_ 4中，毛 細官臂17係擺動自如地設於接合頭18，攝影裝置η係透 :攝料置保持臂19固定於接合頭18。另外，xw係表示 立里…之x軸分量，Yw係表示偏位量W之Y軸分量。 置辨=打線方法為接合點之位置影像取得及接合點之位 ^ ^ 打線袁置10會因其發熱源使周圍溫 度=動作發熱等，使毛細…之熱膨脹與保持攝 攝二二之攝影裝置保持臂19之熱膨脹產生差 =置U之中心轴lla與毛細管15之中心轴I5a之偏 里w產生變動。因該 、生 置之位置偏.移。該接合位置偏差量會表現於接合位 檢測接合於塾冑P1、P2 檢測—般係以攝影裝置 或偏移量來進行檢測。·..之球體(稱為壓接球)之中心位置 以往，採用前述接合點 像辨識處理之打線方法係;^置辨識處理與接合後之影 導線架U前端之半導體日^ t流程圖之步驟進行。在 中心（攝影裝置u之“:】2A破搬送（步驟20)至接合 進行半導體晶片2之接人％ la)並定位後，以攝影裝置11 較以攝影裝置u攝絲得…)。接著，比 導體晶片2A之接合點位置t合點影像’進行算出半 (步驟22)。該接合點位 之接合點位置辨識處理 23)後，於修正後之接人S处理（步驟22)辨識完畢（步驟 口‘，進行打線（步驟24)。接著進行對 6 200839907 半導體晶片2A接合後之壓接球影像取得（步驟25)，接著 進行接合後影像位置偏移之辨識處理（步驟26)。該辨識= 理（步驟26)辨識完畢（㈣27)後，在有位置偏移時= 偏位量W。 少 人 接著，次一半導體晶片2B被搬送（步驟30)至接合中 心(攝影裝置U之中心軸lla)’受到與前述半導體晶片°2八 :樣之處理。亦即，進行半導體晶片心接合點影像取 传（步驟31)、接合點位置辨識處理（㈣32)、辨識完畢（步 導體晶片2B打線(步驟34)。接著進行對半 日日 接合後之壓接球影像取得（步驟35)，接人 影像位置偏移之辨識處理（步驟36)。該辨識處理（步驟γ =完公步驟37)後，在有位置偏移時修正該偏位量w。 種打線方法可列舉例如專利文獻U 2。另外，專利文 献2如圖5以2點鍊線所示，半導體晶片之搬 驟3〇、4〇)係與接合點位置辨識處理（步驟22、32)平^ 行，以謀求打線作業之高速化。 仃進 專利文獻1 :曰本特開平8_31863 3235008號）公報 唬（曰本專利第 專利文獻2 :曰本特開+ 9_ 3560731號）公報 琥（曰本專利第 3 * 、长打線作業之高速化者，可舉出例如專利文 3。專利文獻3之毛如其rt 牛1夕J如寻利文獻 置間之偏位量為半導體V、/、有攝影機（攝影裝置）之照明裝 了使毛細管與攝影I置之即距之整數倍。如上述，為 、置之偏位量成為半導體晶片之節距之 7 200839907 整數倍，攝影裝置係於接合頭安裝成可在χ方向移動自如。 因此，當例如偏位量與半導體晶片之節距相同時，即在對 第2半導體晶片進行之打線動作中進行已打線之第1半導 體晶片之影像取得及影像辨識處理。 專利文獻3:曰本特開平9_36164號公報 【發明内容】 於例如車載用半導體裝置，為了提升生產步驟之可信 度打線後之壓接球必須全數檢查。然而，若以圖5所示 之方法進行半導體晶片2 Α之打線後影像辨識處理（步驟 26)，假設1條引線花費〇 〇5秒，24〇條引線便需要12秒， 生產性不佳。 針對此問題專利文獻3由於在對次一半導體晶片之打 線中進行已完成打線之半導體晶片之打線後影像辨識處 理，故能大幅減少時間之浪費而可謀求生產性提升。然而， 打線後之影像取得會在打線完畢後將次一半導體晶片搬送 至接口中〜，亦即打線完畢後之半導體晶片係在搬送整數 即距後之位置進行。如上述，打線位置與打線後之影像取 得位置（載台）相異，而會有以下問題。 第1 ’已在打線位置進行打線之半導體晶片被搬送至 衫像取仟位置時，前述相異2個位置之定位位置（station) 不可能在耄米級為完全相同之狀態，且無法將導線架在兩 個位置定位為完全相同之狀態。因此，即使測定在與打線 位置（station)相異之位置定位狀態之半導體晶片，並以其 8 200839907 結果修正前述偏位量(回饋至毛細管側)，亦非正確偏位量， 故無法正確打線。 第2’檢測條件亦在打線位置與影像取得位置有溫度、 照明等微小差異。又，由於係在打線後進行搬送半導體晶 片後之打線後影像取得，故隨時間經過檢測結果亦會有微 小差異。因如上述檢測條件有差異，故與前述第i同樣地， 即使以其結果修正前述偏位量（回饋至毛細管侧），亦非正 確偏位量，故無法正確打線。 ' 纟發明之課題在於提供能謀求打線作業之高速化，並 能謀求更進一步提升打線精度之打線方法。 為解決上述課題之本發明之申請專利範圍第丨項為一 種打線方法’藉由具備插通有引線之毛細管、以及與該毛 細管偏位配設之攝影裝置之打線裝置，以攝影裝置取得被 搬送至接合中心之半導體晶片之接合點影像，在進行算出 该接合點位置偏移之接合點位置辨識處理後，於修正後之 (接合點打線，進行對該半導體晶片接合後之影像取得，接 =行接合後影像位置偏移之辨識處理，在有影像位置偏 私打修正該偏位量再進行打線，其特徵在於： 曰11亥接合後影像位置偏移之辨識處理，係在對該半導體 曰曰片接合後之影像取得後，將次一半導體晶片搬送至接合 二心士’以攝影裝置取得該半導體晶片之接合點影像，進行 •^出忒接合點位置偏移之接合點位置辨識處理 至修正後接合點之該打線中進行。 、打，、泉 由於在對半導體打線€，在該位置進行打線後之影像 9 200839907 又，由於在對次一 片之打線後影像辨 取得’故不會發生影像取得精度低落。 半導體晶片打線之步驟中進行半導體晶 識處理’故可謀求打線作業之高速化。 【實施方式】 以下，以圖1及圖2說明本發明之打線方法之一實施 形態。另外，與圖3至圖5相同或相當之構件及部分使用 相同符號加以說明。比較圖！之步驟與習知例之圖$之步 驟可得知，圖5之習知例係在半導體晶片2A、ml 後影像取得（步驟25、35··.)後進行接合後影像辨識處理（步 ㈣，…)。本實施形態係如圖”斤示，在半導體晶片2A、 瓜·.之打線後影像取得（步驟25、35.)後並未進行接 f像辨識處理（步驟26、36...)，而是在對半導體晶片2αΒ、 C ^打線（步驟34、44)中進行接合後影像辨識處轉驟 义以下參考圖3及圖4,以圖i及圖2說明。在 工 之月〇而之半導體晶片2A被搬送 考圖2⑷腦影裝置u之中心軸Ua二接合中心5〇(參 置11進行半_日片2^ 後，以攝影襄 英^ “ 2之接合點影像取得（步驟。接 。比較以攝影…丨攝得之影像與接合點影像，)妾 异出+導體晶片2之接合點位置偏移量 丁 處理（步驟叫。該接合點位置辨識處 °22=辨識 (步驟23)後，於修正後之接 m)辨識完畢 2(b)) 〇 ^ 進仃打線（步驟24)(參考圖 接者進行對半導體晶片2A接合後之髮接球影像： 200839907 得（步驟25)，以上與習知例（圖5)為相同步驟。 心5。=次一半導體…B被搬送(步驟3。)至接合中 述半=2(，攝影裝置心軸"小受到與前 體日日片2A同樣之處理。亦即，進行半導體晶片π 3點影像取得（步驟31)、接合點位置辨識處理（步驟 34)(炎老識^畢（步驟33)後’對半導體晶片2B打線（步驟 )〇考目2(d))。於本實施形態巾，係將在接合位BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding method for optically identifying a joint position of a semiconductor device and connecting a lead at a joint position. [Prior Art] A conventional wire bonding method will be described with reference to Figs. As shown in FIG. 3, the sample 3 to which the semiconductor wafer #2 is attached to the lead frame 1 is connected to the pad portions PI, P2, ... of the semiconductor wafer 2 by wire bonding means by the wire bonding device 10 shown in FIG. The lead portions L1, L2~ of the frame i. In the above-mentioned wire bonding method, generally, the imaging device u first detects at least two fixed points on the semiconductor wafer 2 and at least two fixed-point two-normal position offsets on the lead frame, and the calculation unit corrects the detected value according to the detected value. Pre-storage: joint coordinates. When the photographing device is "detected, the photographing device" is driven, and the X-axis motor 12 and the Y-axis motor 13 are driven to be positioned directly above the measurement. After the joint coordinates are corrected, the capillary moves in the x-axis direction and the x-axis direction, and (4) the lead wire inserted into the capillary 15 is inserted into the pad portion pj, ρ2 | , and the portion U, L2 of the semiconductor wafer 2. . P2... and the lead wire of the lead frame 1 at this time 'Because the center of the center of the photographic device U 铋 κ α and the 15a of the captain 15 are offset by the distance W, the low point #,, ~ Do ~ Exhibition After setting 11 to determine the fixed sub-correction joint coordinates, the χ γ stage 16 and Y κ, the soil motor X motor 12-axis motor 13 are moved by the offset amount w, and the first access of the capillary is * Above the mouth. The private lead of the capillary 15 in the Z-axis direction is moved by the x-shift and γ-axis motor 13 5 200839907 in the XY-axis direction and the z-axis motor 14 moves (or oscillates) above and below the capillary arm 17 4 is wired to the corrected joint coordinates. In the _4, the capillary arm 17 is swingably provided to the joint head 18, and the photographing device η is permeable: the photographing holding arm 19 is fixed to the joint head 18. Further, xw represents the x-axis component of Lili, and Yw represents the Y-axis component of the offset amount W. Diagnosis = wire drawing method is the position image of the joint and the position of the joint point ^ ^ The line is set to 10, because of the heat source, the ambient temperature = the action heat, etc., so that the thermal expansion of the capillary ... and the holding of the camera The thermal expansion of the holding arm 19 produces a difference: the center axis 11a of the U and the center axis I5a of the capillary 15 vary. Because of this, the position of the living is shifted. The amount of engagement position deviation is expressed by the joint position detection and the detection of the 塾胄P1, P2 detection by the photographic device or the offset. · The center position of the sphere (called the crimping ball) has been used in the past, and the wire bonding method using the joint image recognition processing is performed; the identification processing and the semiconductor front end of the shadow lead frame U after the bonding are performed. The steps are carried out. At the center ("photographing device u": 2A is broken (step 20) until the joining of the semiconductor wafer 2 is taken and positioned, the photographing device 11 is photographed by the photographing device u.) Next, The calculation is performed half of the joint position t of the conductor wafer 2A (step 22). After the joint position identification processing 23 of the joint position, the correction is performed after the correction (step 22). The step port ' is wired (step 24). Next, the crimp ball image acquisition after the bonding of the 6 200839907 semiconductor wafer 2A is performed (step 25), and then the image processing of the image position shift after the bonding is performed (step 26). = (Step 26) After the identification is completed ((4) 27), when there is a positional shift = the amount of offset W. The minority next, the next semiconductor wafer 2B is transported (step 30) to the joint center (the central axis of the photographing device U) Lla)' is subjected to the same processing as the above-mentioned semiconductor wafer. That is, the semiconductor wafer core joint image transfer (step 31), the joint position identification processing ((4) 32), and the identification is completed (the step conductor wafer 2B is wired) (Step 34). After the half-day bonding, the crimping ball image acquisition is performed (step 35), and the image position offset recognition process is performed (step 36). After the identification process (step γ = completion step 37), there is a positional shift. In the case of the wire bonding method, for example, Patent Document U 2 is exemplified. Patent Document 2 is a two-dot chain line as shown in FIG. 5, and the semiconductor wafer is moved and joined. The position identification process (steps 22 and 32) is performed in order to increase the speed of the wire-laying operation. 仃 Patent Document 1: 曰本特开平 8_31863 3235008号) 唬 (曰本 patent No. 2: 曰本特开+ 9_ 3560731) Bulletin Hu (Japanese Patent No. 3*, the high-speed operation of the long-line operation, for example, Patent Document 3. The patent document 3 is such that its rt is a nick. The amount of the semiconductor is V, /, and the illumination of the camera (photographing device) is set to an integral multiple of the distance between the capillary and the photographing I. As described above, the offset amount is set to be the pitch of the semiconductor wafer 7 200839907 Integer multiple, the photographic device is mounted on the joint head to be Therefore, when, for example, the offset amount is the same as the pitch of the semiconductor wafer, that is, the image acquisition and the image recognition processing of the first semiconductor wafer that has been wired are performed in the wire bonding operation of the second semiconductor wafer. Japanese Unexamined Patent Publication No. Hei 9-36164. SUMMARY OF THE INVENTION For example, in a vehicle-mounted semiconductor device, in order to improve the reliability of the production steps, the crimping balls after the wire bonding must be inspected in full. However, the method shown in FIG. After the semiconductor wafer 2 is subjected to image recognition processing (step 26), it is assumed that one lead takes 〇〇5 seconds, and 24 turns lead takes 12 seconds, which is not productive. In order to solve this problem, Patent Document 3 can perform image recognition processing after the wire bonding of the semiconductor wafer which has been completed in the wiring of the next semiconductor wafer, so that waste of time can be greatly reduced, and productivity can be improved. However, after the wire is taken, the next semiconductor wafer is transferred to the interface after the wire is completed, that is, the semiconductor wafer after the wire is completed is carried at the position after the integer is transferred. As described above, the position of the wire is different from the position of the image after the wire is taken (the stage), and the following problems occur. When the first semiconductor wafer that has been wired at the wire bonding position is transported to the shirt image picking position, the positioning positions of the two different positions are impossible to be in the same state at the glutinous level, and the wire cannot be used. The rack is positioned in exactly the same position in both positions. Therefore, even if the semiconductor wafer positioned at a position different from the wire position is measured and the offset amount (returned to the capillary side) is corrected by the result of 8 200839907, the amount of misalignment is not correct, and the wire cannot be correctly wired. . The second 'detection condition also has a slight difference in temperature, illumination, and the like between the wire bonding position and the image capturing position. Further, since the image is obtained after the wire is transferred after the semiconductor wafer is transferred after the wire is applied, there is a slight difference in the detection result over time. Since the detection conditions are different as described above, even if the offset amount (returned to the capillary side) is corrected as a result of the above, the amount of misalignment is not correct, and the wire cannot be correctly wired. The problem of the invention is to provide a wire bonding method that can increase the speed of wire bonding operations and further improve the accuracy of wire bonding. The ninth aspect of the patent application of the present invention for solving the above problems is a wire bonding method of obtaining a conveyed image by a photographing device by a wire splicing device having a capillary tube through which a lead wire is inserted and a photographic device that is disposed offset from the capillary The joint image of the semiconductor wafer to the bonding center is subjected to the joint position identification processing for calculating the positional deviation of the joint, and after the correction (the joint is wired, the image is obtained after the semiconductor wafer is joined, and The identification processing of the image position offset after the line bonding is performed, and the offset position is corrected by the image position, and then the line is fixed. The feature is: the identification processing of the image position offset after the jointing of the 曰11 hai is performed on the semiconductor 曰曰After the image after the film is joined, the next semiconductor wafer is transferred to the bonding two-hearted one. The image of the joint of the semiconductor wafer is obtained by the photographing device, and the joint position recognition processing of the joint position deviation is performed to the correction. The post-joining point is carried out in the line. After hitting the wire in the semiconductor, after the wire is punched at the position Image 9 200839907 In addition, since the image recognition is performed after the next one is hit, the image acquisition accuracy is not lowered. The semiconductor crystal processing is performed in the step of semiconductor wafer bonding. Therefore, the speed of the wire bonding operation can be increased. MODE FOR CARRYING OUT THE INVENTION Hereinafter, an embodiment of the wire bonding method of the present invention will be described with reference to Fig. 1 and Fig. 2. The same or equivalent components and portions as those of Figs. 3 to 5 are denoted by the same reference numerals. In the example of Fig. 5, it can be seen that the conventional example of Fig. 5 performs post-join image recognition processing (step (4), ...) after image acquisition (steps 25, 35, ...) of the semiconductor wafer 2A, ml. The embodiment is shown in the figure. After the image acquisition (steps 25 and 35.) of the semiconductor wafer 2A and the melon chip, the f image recognition process is not performed (steps 26, 36...). The image recognition after the bonding of the semiconductor wafer 2αΒ, C^ wire (steps 34 and 44) is described below with reference to FIG. 3 and FIG. 4, and is illustrated in FIG. 2 and FIG. 2. The semiconductor wafer is in the process of engineering. 2A was transferred to test picture 2 (4) brain shadow U's central axis Ua two joint center 5〇 (following the 11th half-day film 2^, and taking the image of the joint image of the camera 2) (step. Connect. Compare the image with the camera... Joint image, 妾 出 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2(b)) 〇 仃 仃 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( Step 5. The heart 5 = the next semiconductor ... B is transported (step 3) to the middle half of the joint = 2 (the photographing device mandrel " small is treated in the same manner as the precursor sundial 2A. That is, the semiconductor wafer π 3-point image acquisition (step 31) and the joint position identification processing (step 34) (after the aging is completed (step 33), the semiconductor wafer 2B is wired (step) 〇 2 2 ( d)). In this embodiment, the towel will be in the joint position.

Li:)進行半導體晶片2A之打線後影像取得(步驟25): :::里’亦即半導體晶片2A之打線後影像辨識處理(步 〜/、對半導體晶片2B之打線（步驟34)同時進行。兮 =(步驟26㈣完畢(步驟警在有位置偏料： 違偏位# W。接著進行對半導體晶# 2 球影像取得（步驟35)。 接。後之昼接 接著，次一半導體晶片2C被搬送（步驟40)至接合中 二考曰圖AW攝影裝置U之中心軸Ua)，受到：前 =“曰曰片2A、2B同樣之處理。亦即，進行半導體晶 之接合點影像取得（步驟41)、接合點位置辨識處理（步 ^…辨識完畢（步驟43)後，對半導體晶片％打線（步 脾）（ > 考圖2⑺）。於本實施形態令，與前述同樣地，係 :接合位置（接合中心5〇)進行半導體晶片2 :像：得(步驟取資料處理，亦即半導體晶片2Β之打 取後如像辨識處理（步驟36)與對半導體晶片π之打線（步 ^，44)同時進行。該辨識處理（步驟36)辨識完畢（步驟37) 在有位置偏移時修正該偏位量W。接著進行對半導體 200839907 晶片2C接合後之壓接球影像取得（步驟45)。 如上述，在對半導體晶片2A、2b , π···打綠（步驟24 後，在該位置進行打線後影像取得（步驟25、35)。* ) 不會發生根據專利文獻3列舉之第丨 。因此， 久^ Z問題點。又， 由於係將半導體晶片2A、2B 之古丁綠％旦/你 u···之打線後影像辨識處理 驟26、36)在對半導體晶片2B、沈打線（步驟34、叫之步 驟中進行，故可謀求打線作業之高速化。 【圖式簡單說明】 圖1係顯示本發明之打線方法之一實施形態之流程 圖2(a)〜（f)係顯示影像處理流程之說明圖。 圖3係顯示試料之1例之俯視圖。 圖4係顯示打線裝置之1例之立體圖。 圖5係習知打線方法之流程圖。Li:) performing image acquisition after the wire bonding of the semiconductor wafer 2A (step 25): ::: 'is the image recognition process after the wire bonding of the semiconductor wafer 2A (step ~ /, wire bonding the semiconductor wafer 2B (step 34)) simultaneously兮 = (Step 26 (4) is completed (step warning is in positional deviation: Deviation # W. Then proceed to the semiconductor crystal # 2 ball image acquisition (step 35). Then the next connection, the next semiconductor wafer 2C The conveyance (step 40) to the center axis Ua of the AW photographing device U of the second drawing is subjected to the same processing as the front = "the slaps 2A, 2B. That is, the joint image acquisition of the semiconductor crystal is performed ( Step 41), the joint position identification processing (step [...] is completed (step 43), and the semiconductor wafer % is threaded (step spleen) (> Fig. 2 (7)). In the same manner as described above, : bonding position (bonding center 5 〇) to perform semiconductor wafer 2: image: (step data processing, that is, after the semiconductor wafer 2 is captured, such as image recognition processing (step 36) and the semiconductor wafer π line (step ^ , 44) Simultaneously. This identification process (step 36 After the identification is completed (step 37), the offset amount W is corrected when there is a positional shift. Next, the crimp ball image acquisition after the bonding of the semiconductor 200839907 wafer 2C is performed (step 45). As described above, the pair of semiconductor wafers 2A, 2b , π··· is green (after step 24, the image is acquired after the line is struck at this position (steps 25, 35). *) The third item listed in Patent Document 3 does not occur. Therefore, the problem is long. , because the semiconductor wafer 2A, 2B, the green image, the image recognition processing steps 26, 36 after the bonding of the semiconductor wafer 2B, the stepping line (step 34, called step), BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing an embodiment of the wire bonding method of the present invention, and (a) to (f) are explanatory views showing a video processing flow. A plan view showing an example of a sample is shown in Fig. 4. Fig. 4 is a perspective view showing an example of a wire bonding device. Fig. 5 is a flow chart showing a conventional wire bonding method.

【主要元件符號說明】 1 導線架 2(2A，2B，2C) 半導體晶 3 試料 4 引線 10 打線裝置 11 攝影裝置 11a 中心軸 12 200839907 15 毛細管 15a 中心軸 20 半導體晶片2A之搬送 21 接合點位置影像取得 22 接合點位置辨識處理 23 辨識完畢 24 打線 25 接合後影像取得 26 接合後辨識處理 27 辨識完畢 30 半導體晶片2B之搬送 31 接合點位置影像取得 32 接合點位置辨識處理 33 辨識完畢 34 打線 35 接合後影像取得 36 接合後辨識處理 37 辨識完畢 50 接合中心 13[Description of main components] 1 Lead frame 2 (2A, 2B, 2C) Semiconductor crystal 3 Sample 4 Lead 10 Wire-wound device 11 Photographing device 11a Center axis 12 200839907 15 Capillary 15a Center axis 20 Transfer of semiconductor wafer 2A 21 Junction point position image Obtained 22 Joint position recognition processing 23 Identification completed 24 Wire 25 After image acquisition 26 After bonding recognition processing 27 Identification completed 30 Transfer of semiconductor wafer 2B 31 Joint position image acquisition 32 Joint position recognition processing 33 Identification 34 Wire 35 Bonding After image acquisition 36 Post-join identification process 37 Identification completed 50 Bonding center 13

Claims (1)

200839907 十、申請專利範圍： 1 一種打線方法，係藉由具備插通有引線之毛細管、 以及與該毛細管偏位配設之攝影裝置之打線裝置，以攝影 裝置取得被搬送至接合中心之半導體晶片之接合點影像， 在進行算出該接合點位置偏移之接合點位置辨識處理後， 於修正後之接合點打線，進行對該半導體晶片接合後之影 像取得，接著進行接合後影像位置偏移之辨識處理，在有 影像位置偏移時修正該偏位量再進行打線’其特徵在於： 該接合後影像位置偏移之辨識處理，係在對該半導體 晶片接合後之影像取得後，將次一半導 / 丁人干命魃日日片搬送至接合 令心，以攝影裝置取得該半導體曰# 彳殿日日片之接合點影俊 异出該接合點位置偏移之接合點 僚口點位置辨識處理後， 至修正後接合點之該打線中進行。 於打線 Η•一、圈式： 如次頁。 14200839907 X. Patent application scope: 1 A wire bonding method for obtaining a semiconductor wafer transferred to a bonding center by a photographing device by a wire bonding device having a capillary tube inserted with a lead wire and a photographing device disposed with the capillary bias The joint image is subjected to the joint position recognition processing for calculating the positional deviation of the joint, and the line is formed after the correction of the joint, and the image is obtained after the semiconductor wafer is bonded, and then the image position is shifted after the bonding. The identification process corrects the offset amount and then performs the wire bonding when there is an image position shift. The feature is that the identification process of the image position offset after the bonding is performed after the image of the semiconductor wafer is joined. Guide / Ding Rengan 魃 魃 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 搬 接合 接合 接合 接合 接合 接合 接合 接合 接合 接合 接合 接合After the treatment, it is carried out in the line of the joint after the correction. For the line Η • One, the circle: as the next page. 14
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JPH04343235A (en) * 1991-05-21 1992-11-30 Mitsubishi Electric Corp Wire bonding device
JPH06326163A (en) * 1993-05-12 1994-11-25 Hitachi Ltd Ultrasonic wire bonding device
JP3101853B2 (en) * 1994-04-27 2000-10-23 株式会社新川 Teaching method of bonding coordinates
JPH0917822A (en) * 1995-06-30 1997-01-17 Sony Corp Semiconductor manufacture device and method
JPH0936164A (en) * 1995-07-21 1997-02-07 Mitsubishi Electric Corp Semiconductor manufacturing device and manufacture of semiconductor device
JP3298795B2 (en) * 1996-07-16 2002-07-08 株式会社新川 How to set lead frame transport data
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