TW200839770A - Non-volatile storage system with initial programming voltage based on trial - Google Patents

Abstract

A trial programming process is performed for a first set of one or more non-volatile storage elements to test usage of the non-volatile storage system. Based on this trial programming a programming signal is calibrated by adjusting its initial magnitude. The calibrated programming signal is then used to program a second set of non-volatile storage elements (which may or may not include the first set).

Description

200839770 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present invention relates to techniques for non-volatile storage. The following application is hereby incorporated by reference in its entirety by reference in its entirety in its entirety in the the the the the the the the the the the the the the Programming 'With Initial Pr〇gramming V〇hge Based On Trial)" US Patent Application No. -~~~- [Agent Case No. SAND- • 0U24US0], inventors Teruhiko Kamei and Yan Li, cited by The method is incorporated herein. [Prior Art] Semiconductor memory has become popular in various electronic devices. For example, non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, and non-action. In computing devices and other devices, electrically erasable and programmable read-only memory (EEpR〇M) and flash memory are the most popular non-volatile semiconductor memory. Both EEPROM and flash $k are used to locate a floating gate above and insulated from the channel region in the semiconductor substrate. The floating interpole is positioned between the source region and the drain region. The control gate is provided for floating The upper pole is insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge held on the floating gate. That is, the level of charge on the floating gate is controlled to be turned on. The minimum amount of voltage that the crystal must apply to the control gate before it is allowed to conduct between its source and drain. When programming an EEPROM or flash memory device (such as a NAND flash memory device) 'usually The program voltage is applied to the control gate and the bit 127825.doc 200839770 is grounded. The electrons from the channel are injected into the floating gate. When the electrons accumulate in the floating gate, the floating gate becomes negatively charged and the memory cell is The threshold voltage is raised to make the memory unit in a stylized state. Available under the title "'Source Side Self Boosting Technique For Non-Volatile

U.S. Patent No. 6,859,397, issued to U.S. Patent No. 6, 859, 397, the entire disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire contents And incorporated herein.

By the way, the program voltage applied to the control gate during the stylization operation is applied as a series of pulses. In one embodiment, the magnitude of the pulse increases with each successive pulse in a predetermined step size. During the period between the stylized pulses, the verification operation is performed. For an array of multi-state flash memory cells, the memory cell can perform a verification step for each state to allow determination of whether the memory bank has reached its target level. For example, a state memory unit capable of storing poor materials in four states may need to perform verification operations for three comparison points. The amount of initial stylized pulses is typically set during the manufacturing or test phase using a process called fine tuning. The parts are programmed multiple times, each time using a different amount of the initial programmed pulse. When a particular amount of the initial programmed pulse results in a (4) materialization, the material is subjected to (4) to use the initial programmed pulse of the magnitude during user operation. The choice of the magnitude of the program's power is __compromise. A value that is too high will cause some S-resonant units to be over-simplified. The time value will result in a longer program. The user of the memory wants the memory to be fast. 127825.doc 200839770 In the prior art devices, the same stylized signal is used for new devices (also known as fresh devices) that are not yet in large use and for frequently used devices. However, as the non-volatile memory device undergoes many stylized cycles, the charge becomes trapped in the insulator between the floating gate and the channel region. This trapping of the charge shifts the threshold voltage to a higher level, which allows the A fe body unit to be programmed more quickly. If the magnitude of the stylized signal is set too high, even if it does not cause over-staging of the fresh device, the device may be over-programmed as it becomes more frequently used. Therefore, the new device will have its program voltage set low enough to avoid over-staging when the clothes are older. This reduction in the magnitude of the program voltage will reduce the speed of the fresh device stylized data. Additional factors that have made it difficult to optimize the magnitude of the program voltage include temperature lunar patterns, wafer variations, lot variations, wafer/batch/chip positions, and other factors. SUMMARY OF THE INVENTION A test programming process is performed on a first set of one or more non-volatile storage elements to test the use of a non-volatile storage system. Based on this test procedure, the stylized signal is corrected by dynamically adjusting the initial magnitude of the stylized signal. A second set of non-volatile storage 70 pieces, which may or may not include the first set, is then programmed using the corrected stylized signal. The human embodiment includes: a first set of one or more non-volatile storage elements * / 亍 to 长 ° 长 is long-formed, after partial stylization identifies one of the first set of non-volatile 1 storage elements Or a plurality of threshold voltage ranges, the one or more identified threshold voltages based on the first set of non-swept elements 127825.doc 200839770 range setting an initial magnitude of a set of stylized pulses, and by using the The set of programmed pulses of the initial magnitude program the third set of non-volatile storage elements.

- Embodiments comprising applying one or more stylized pulses to a control set of a first set of non-volatile storage elements, performing - or a plurality of sensing operations on a first set of non-volatile storage elements to determine a The depreciation of the current limit of the non-volatile storage element is based on the determined information about the non-volatile storage of the test: the value of the value of the threshold electric grinder to set the initial value of a set of stylized pulses' and borrow The second set of non-volatile storage elements is programmed by using the set of stylized pulses having the initial magnitude. An example implementation includes one or more management circuits including a plurality of non-volatile storage elements and in communication with the plurality of non-volatile storage elements to perform the processes discussed herein. For example, in an embodiment, the one or more management circuits perform for the first set of - or more of the non-volatile material elements: singularization 'sense' with respect to one or more non- Information on the magnitude of the first set of volatile storage elements or a plurality of power limiting a, and the second of the non-volatile storage elements by using a stylized signal having a value based on the sensed magnitude information The collection is stylized. In another implementation of the circuit, the non-volatile storage: the first set of components is at least partially stylized and the first set of non-volatile storage elements is classified as being attributed to a partially stylized threshold power. The method is set based on the classification—the set of programmed pulses ^ the initial value and the second set of non-volatile storage elements is programmed by using the set of stylized pulses having an initial magnitude. . An example structure includes a complex number_na_, a complex number of recording lines, a plurality 127825.doc 200839770 word lines, a communication with a word line - or a plurality of voltage generating circuits, a communication with a bit line - or a plurality of bit line controls Circuit and one or more of the

A control circuit and a control circuit for communicating with the one or more voltage generating circuits. Each NAND string includes a plurality of non-volatile storage elements. Each bit is connected to one of the NAND strings. Each word line is connected to a non-volatile storage element of each of the difficult strings. The control circuit causes the one or more voltage generating circuits to apply one or more programmed pulses to the word line selected for stylization. The control circuit also causes the one or more bit line control circuits to perform one or more sensing operations on the first set of volatile storage elements connected to the selected word line (four) to determine non-volatile storage The first set of components is within the threshold voltage of the one or more stylized pulses. The control circuit sets an initial magnitude of a set of stylized pulses based on the determined magnitude information and causes a connection to the selected word for stylization by using a = group of programmed pulses having the initial magnitude Stylization of the second set of non-volatile storage elements of the line. [Embodiment] One example of a flash memory system uses a NAND structure that includes a plurality of transistors sandwiched between two select gates in series. The series of transistors and select gates are referred to as NAND strings. The figure shows a top view of a NAND string. Figure 2 is an equivalent circuit diagram. The NAND string of FIGS. 1 and 2 includes four transistors 10 串联 in series and sandwiched between the first (or drain side) selection gate 120 and the second (or source side) selection gate 122, 1〇2, 1〇4, and 1〇6. The gate 120 is selected to connect the NAND string to the bit line via the bit line contact 126. Select gate 122 connects the NAND string to source line 128. The selection gate 12 is controlled by applying an appropriate voltage to the selection line SGD. Select gate 122 is controlled by applying an appropriate voltage to select line 127825.doc -10- 200839770 line SGS. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. For example, the transistor 100 has a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate • 104FG. The transistor 106 includes a control gate 106CG and a floating gate • 106FG. The control gate 100CG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL0. Note that while Figures 1 and 2 show four memory cells in a NAND string, the use of four transistors is only provided as an example. The NAND string can have four or fewer memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, 64 memory cells, 128 memory cells, and the like. The discussion herein is not limited to any particular number of memory cells in the N AND string. • A typical architecture for a flash memory system using a NAND structure will include several NAND strings. Each NAND string is connected to the source line by its source select gate controlled by the select line SGS and is connected to its associated bit line by its drain select gate controlled by the select line SGD . Each bit line and the respective NAND string connected to the bit line via the bit line contact point constitute a row of the array of memory cells. A plurality of NAND strings share a bit line. Typically, the bit lines extend on top of the NAND string in a direction perpendicular to the word lines and are connected to one or more sense amplifiers. Each memory unit can store data (analog or digital). When storing a 127825.doc -11 - 200839770 = digital data (referred to as the binary memory unit can be the scope of this threshold voltage through the j ^ body two areas. In __@ $ two " ^ In one example of the threshold voltage of the 1"&"0" element after erasing, the memory after the single-stylization of the threshold 2 is 'defined as logical' 1" The voltage is positive and is defined as logic. When the 〇, 备, 涂 涂 are negative and the control unit is applied to the control electrode, the memory unit will be turned on. The special item 5 is taken as positive and buried. South ^ Save the logic when the threshold voltage 'Working gates apply 0 volts and try to read

The memory unit will not be turned on, indicating that it stores a logic zero. (4) The % C memory unit can also be stored in the unit. In the storage of multi-level Hi level ^ (referred to as the multi-state memory range is divided into the number of data levels; Si will be possible to limit the voltage (two yuan data), break the wide case I, if you store four levels of information to the data value The threshold voltage wire is assigned to apricot 01" and "00". In the NAND type memory - in the case of the shell, the threshold voltage after the erase is selected as the negative &; and is defined as the positive threshold voltage for the data state "1〇,,,"〇1" and, 〇〇". If the health of the eight-level Beixun (or state) (for example, about Three-dimensional data), there will be eight threshold voltage ranges, assigned to the data value, ·_,,,,,001 ", "010", "011","](10)" η 1 Λ 1 〇〇, 101”, "no" and ln " The specific relationship between the data programmed into the memory unit and the threshold voltage level of the unit depends on the data encoding mechanism used for the unit. For example, U.S. Patent No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090 (both of which are The method cited in the text is incorporated herein, to describe various data encoding mechanisms for multi-state flash memory cells. In the embodiment, the data value is assigned to the threshold 127825 by using the 袼 code assignment. Doc •12- 200839770 Electric occupation so that if the floating threshold (4) is erroneously offset to the basin neighboring entity state, then only one bit will be affected. In some embodiments, for different word lines By changing the data total population flat code mechanism, the data encoding mechanism can be changed over time or the data bits of the random word line can be reversed to reduce the sensitivity of the data pattern and/or the wear on the memory unit.

Related examples of NAND-type flash memory and its operation are provided in the following U.S. Patent/Patent Application, which is incorporated herein by reference in its entirety in U.S. Patent No. 5, 57, 315; U.S. Patent No. 5,774,397 U.S. Patent No. M46,935; U.S. Patent No. 6,456,528; and U.S. Patent Publication No. 3/_2,348. The discussion herein can also be applied to other types of flash memory other than NAND and other types of non-volatile memory. Other types of non-volatile storage devices other than NAND flash memory can also be used. For example, a so-called TANOS structure (composed of a stacked layer of TaN_A12〇3_SiN_Si〇2 on a germanium substrate) may be used in conjunction with the present invention, which basically uses charge in the nitride layer (instead of the floating gate). Captured memory unit. Another type of memory cell useful in flash EEPr〇m systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. This unit is described in the article by Chan et al., A True Single-Transistor Oxide-Nitride-Oxide

EEPROM Device", IEEE Electron Device Letters, Vol. EDL 8, No. 3, March 1987, pp. 93-95. A three-layer dielectric formed of oxidized stone, nitrogen oxynitride, and yttrium oxide ("") is sandwiched between the conduction control idler and the surface of the semiconductor substrate. The cells are programmed by injecting electrons into the nitride from the 127825.doc -13- 200839770 unit channel, trapping electrons in the nitride and holding them in a limited area. This stored charge is then changed in a measurable manner to change the threshold voltage of the cell's channel. The cell is erased by injecting a thermoelectric hole into the nitride. Also see Nozaki et al. "A ^Mb EEPR〇M whh m〇n〇s Mem〇ry

Cell for Semiconductor Disk Application1,, IEEE J〇urnai 0f

Solid-State Circuits, Vol. 26, No. 4, April 1991, 497_ Spring 50 1 page, which describes a similar unit employing a split gate configuration in which a doped polysilicon gate is part of a memory cell channel The upper extension extends to form a separate selective transistor. The foregoing two articles are incorporated herein by reference in their entirety. The stylization techniques mentioned in Section i2 of the Nonvolatile Vaporization Memory Technology, edited by Wilham D. Brown and J0e E. Brewer, ΪΕΕΕ Press, 1998 (which is incorporated herein by reference) are also incorporated herein by reference. Described as applicable to dielectric charge trapping devices. Other types of memory devices can also be used. • ® 3 describes a memory device 21G having a read/write circuit for reading and writing a page of a body unit (e.g., NAND multi-element flash memory) in parallel. The memory device 21G may include - or a plurality of memory die 2 - wafers 212. The memory die 212 includes an array of memory cells (two-dimensional or three-dimensional) 200, a control circuit 220, and read/write circuits 230A and 230B. In an embodiment, the access to the memory array 2 by various peripheral circuits is performed symmetrically on opposite sides of the array, thereby reducing the density of access lines and circuits on each side. half. The read/write circuits 23a and 230B include a plurality of sensing blocks 300 that allow pages of the 127825.doc -14-200839770 memory cells to be read or programmed in parallel. The memory array 200 can be addressed by the word lines via column decoders 240A and 24013 and by row lines via row decoders 242 and 2423. In the exemplary embodiment, controller 244 and one or more memory dies 212 are included in the same memory device 210 (e.g., a removable memory card or package). Commands and data are transferred between the host and controller 244 via line 232 and 'via line 234 between the controller and one or more memory dies 212. Control circuit 220 cooperates with read/write circuits 230A and 230B to perform a memory operation on memory array 200. Control circuit 220 includes state machine 222, on-wafer address decoder 224, and power control module 226. State machine 222 provides wafer level control of memory operations. The on-wafer address decoder 224 provides an address interface between the address used by the host or memory controller and the hardware address used by the decoders 240A, 240B, 242A, and 242B. Power control module 226 controls the power and voltage supplied to the word lines and bit lines during memory operation. In one embodiment, the power control module 226 includes one or more charge pumps that can generate a voltage greater than the supply voltage. In one embodiment, control circuit 220, power control circuit 226, decoder circuit 224, state machine circuit 222, decoder circuit 242A, decoder circuit 242B, decoder circuit 240A, decoder circuit 240B, read / One or any combination of write circuit 23A, read/write circuit 230B, and/or controller 244 may be referred to as one or more management circuits. FIG. 4 depicts an exemplary structure of a memory cell array 200. In one embodiment, the array of memory cells is divided into a plurality of memory cell blocks. As is common for flash EEPROM systems, the block is the unit of erasure. Also 127825.doc -15- 200839770 That is, each block contains a minimum number of memory cells that are erased together. The block contains access to a set of NAND strings via bit lines (e.g., bit lines BL0 - BL69623) and word lines (WL0, WL1, WL2, WL3). Figure 4 shows four memory cells connected in series to form a NAND string. Although four cells are shown in each NAND string, more than four or fewer cells can be used (eg, 16, 32, 64, 128, or another number of memory cells can be on a NAND string) ). One terminal of the NAND string is connected to the corresponding bit line via the drain select gate (connected to the select gate drain line Sgd), and the other terminal is connected to the select gate source line SGS via the source select gate (SGS) Connect to the source line. In another embodiment, the bit lines are divided into even bit lines and odd bit lines. In an odd/even bit line architecture, memory cells along a common word line and connected to odd bit lines are simultaneously programmed, while at another time the gates are paired with /α common sub-lines and connected to even bit lines. The memory unit is programmed. Each block is usually divided into a number of pages. In one embodiment, the page is a stylized unit. One or more pages of data are typically stored in a list of memory cells. For example, one or more pages of f-material may be stored in a memory unit connected to a common word line. The page can store one or more sections. The section includes user data and additional item data (also known as system bedding additional data, which usually includes header information and an error correction code (ECC) that has been ejected according to the user's bedding of the section. Or other components) to calculate the coffee when the data is programmed into the array, J^ to check the ECC when the data is from the array. Or, to store the ECC and/or other additional items 127825.doc -16· 200839770 in its Regarding the user data in different pages or even different blocks, the user data section is usually 512 bytes, which corresponds to the size of the magnetic area in the disk drive. A large number of pages form blocks, at ( For example) 8 pages up to 32, 64, 128 or more than 128. Different sizes of blocks can also be used. Figure 5 shows the page (for example, from a memory unit connected to a common word line) An example of the configuration of the data in 0. The page depicted in Figure 5 includes 〇φ segments, each of which has user data, ECC data, and header (HDR) data. ECC^HDR data is not User stored information, but The data stored by the system and associated with the user's data. If the user data is one bit, the ECC data is N bits and the HDR data is p bits, there are M memories storing user data. Body unit (associated with M-strip line), N memory units storing ECC data (associated with N bit lines), and P memory units storing HDR data (related to p-bit lines) Figure 6 is a block diagram of an individual sensing block 300, which is divided into a core portion called a sensing module 480 and a common portion 49A. In one embodiment, There will be a separate sensing module 48 for each bit line and a common portion 490 for the set of multiple sensing groups 480. In an example, the sensing block 'will include a common portion 490 and eight sensing modules 480. Each of the sensing modules in the group will communicate with the associated common portion via data bus 472. For additional details, reference is incorporated herein by reference in its entirety. US Patent Application Publication No. 2006/0 140007. Sensing Module 48 0 includes a sensing circuit 470 that determines whether the conduction current in the connected bit line 127825.doc -17-200839770 is above or below a predetermined threshold level. In some embodiments, the sensing module includes the A circuit called a sense amplifier: The sense module 480 also includes a bit line latch 482 for setting the state of the ink on the connected bit line. For example, latched in the bit line latch The predetermined state in 482 will cause the connected bit line to be pulled to a state indicating stylization suppression (e.g., Vdd). Common portion 490 includes processor 492, a set of data latches, and a data latch. The set 494 of the device is connected to the data interface 496. Processor 492 performs the calculations. For example, one of its functions is to determine the data stored in the sensed memory unit and to store the determined data in a set of data latches. A collection of data latches 494 is used to store the data bits that are determined by the processor during the read operation. It is also used to store data bits that are imported from the data bus 420 during the stylization operation. The data bits of the recipients represent the data of the writers intended to be stylized into the memory. The 1/0 interface 496 provides an interface between the data latch 494 and the data bus 420. During operation or sensing, the operation of the system is under control of the state machine. The state machine 222 controls the supply of different control gate voltages to the addressed memory cells. As the voltage steps through various predefined control gate voltages corresponding to various memory states supported by the memory, the sensing module 480 can trip at one of the voltages and output Self-sensing mode, and 480 is provided to the processor via bus bar 472. At some point, the processor 492 determines the tripping event of the sensing module and the information about the control gate voltage applied by the self-talking machine via the input line 493. 127825.doc -18-200839770 Piece of S recall state. It then calculates the binary carry for the memory state, 4 yards and stores the poor bit bits into the data latch tip. In the other example of the core, the bit line latch 482 serves as a latch for latching the output of the sensing module 48 and also as a bit line as described above. Latches. - It is contemplated that some implementations will include multiple processors 492. In an embodiment,

The processor 492 will include an output line (not shown in Figure 5) such that each of the output lines is wired or logically connected (Wired-OR, d) together: in some embodiments, the output The line is reversed when connected to wired logic or lines. This configuration enables a quick decision during the stylization verification process (4), when the process is completed, because it receives wired logic or lines. It is possible to determine when all the bits programmed in the program have reached the desired level. When each 70 in Putian has reached the desired level, the logical zero of the bit will be sent to the wired logic or line (or the data m is reversed when all bits: output money (or reversed) In #i), the state machine knows that in the embodiment where the final tomb is to be communicated in each processor to the eight sensing modules, the state machine may (in some embodiments) need to read the wired logic or line. Eight or logic is added to the processor 492 to accumulate the result of the associated bit line so that the state machine only needs to read the wired logic or line once. The wide, σσσ heap $ 494 contains the corresponding sensor module. The stack of data latches. In one embodiment, there is = (or four, or another number) of data for each sensing module 480. Seto crying apricot, double 曰) Becca latch Device. In one embodiment, the latched states are each one bit. 127825.doc -19- 200839770 During stylization or verification, the data to be stylized is stored in data set 494 from data sink 420. During the verification process, processor 492 monitors the verified memory state relative to the desired memory state. When the two match, the processor 492 sets the bit line latch 482 to pull the bit line to a state indicative of stylization suppression. This suppresses the unit coupled to the bit line from further stylization even if it is subjected to a stylized pulse on its control gate. In other embodiments, the processor is initially loaded into bit line latch 482 and the sense circuit sets it to an inhibit value during the verify process. In some implementations (but not required), the data latch is implemented as a shift register such that parallel data stored therein is converted to serial data for use in data bus 420, and vice versa. In a preferred embodiment, all of the data latches corresponding to the read/write blocks of the m memory cells can be linked together to form a block shift register so that it can be serialized A block that transfers and inputs or outputs data. In particular, the set of read/write modules is adapted such that each of its set of data latches will sequentially move data into or out of the data bus as if it were the entire The portion of the shift register that reads/writes the block is general. Additional information on sensing operations and sense amplifiers can be found in (1) US Patent Application Publication No. 2004/0057287, issued March 25, 2004, 'Non-Volatile Memory And Method With Reduced Source Line Bias Errors"; (2) US Patent Application Publication No. 2004/0109357, issued June 10, 2004, ''Nonvolatile Memory And Method with Improved Sensing'; (3) 127825.doc -20- 200839770 US Patent Application Publication No. 20050169082; (4) Application filed on April 5, 2005, invented by Jian Chen entitled "Compensating for"

Coupling During Read Operations of Non-Volatile Memory 11 US Patent Publication No. 2006/0221692; and (5) Application at December 28, 2005, invented by siu Lung Chan and Raul_Adrian Cernea entitled "Reference Sense Amplifier For Non-Volatile

U.S. Patent Application Serial No. 11/321,953, the entire disclosure of which is incorporated herein by reference in its entirety in its entirety in its entirety in The threshold voltage should be within one or more distributions of appropriate threshold voltages for the programmed memory cells or for the distribution of threshold voltages of the erased memory cells. Figure 7 illustrates Example Threshold Voltage Distribution (or Data Status) of Memory Cell Arrays When Each Memory Cell Stores Two-Dimensional Data However, other embodiments may use more than two or fewer bits of data for each memory cell (eg, For each memory unit, three bits of data.) Figure 7 shows the first threshold voltage distribution E of the erased memory cell. Also depicts the three threshold voltage distributions A of the programmed memory cell. In the B and d-embodiments, the threshold dust in the 'E distribution is negative and the threshold voltage in the distribution of A, B and C is positive. Each of the different threshold voltage ranges in Figure 7 corresponds to the data bit. The predetermined value of the collection. Stylized to the memory unit funded a ,, T < Beca and specific relationship between the threshold voltage level of the early 70 ^ depends on the information encoded in the early Wu used?

mechanism. An example is to the threshold voltage range E, the centroid, and the "U", assigning "10" to the threshold voltage range A (state A), and to the first power grid (state B) pointing to 127825.doc - 21 - 200839770 派"00" and assign to the threshold voltage range c (state c), 〇!". However, in other embodiments, the Gray code is not used. In one embodiment, the two-dimensional data for each state is in a different page. Referring to state E of Figure 7, both pages store "1". See state A ' the upper page stores bit 1 and the lower page stores bit 〇. See state B 'both pages store "〇. See state c, the upper page stores the bit 〇 and the lower page stores bit 1. In another embodiment, the two-dimensional data for each state is the same In the page, although Figure 7 shows four states, the present invention can also be used in conjunction with other multi-state structures, including those that include four or more states. For example, a memory that stores three-bit data. The body unit can use eight data states. Figure 7 also shows three read reference voltages Vra, Vrb, and Vrc for reading data from the memory cell. By testing whether the threshold voltage of a given memory cell is at Vra The system can determine the state of the memory cell above or below Vrb and Vrc. The instance values of Vra, Vrb, and Vrc include vra=〇v, Vrb=1.25 V, and VrC=2.65 v. Another set of examples includes Vra =0 v, Vrb^.35 v and Vrc=2.6 v. Other values can be used. Figure 7 also shows two verification reference voltages Vva, Vvb and Vvc. When the memory is programmed into state eight, The system will test whether their memory unit is defective A threshold voltage greater than or equal to Vva. When the memory unit is programmed to state B, the system will test whether the memory unit has a threshold voltage greater than or equal to Vvb. When the memory unit is programmed to state C, The system will determine whether the memory unit of the memory unit is A or equal to 127825.doc -22- 200839770

Vvc. Example values for Vva, Vvb, and VVC include Vva=〇 4〇 v, Vvb=1.80 vlWdh v. Another set of examples includes Vva = 〇, 5 ν' VvbUvawcyj v. Other values can also be used.

In the example, as a so-called full-sequence stylization, the self-erasing state of the memory cell can be directly programmed into a stylized state. The person in charge - the person. For example, a population of memory cells to be programmed may first be erased such that all memory cells in the population are in erased LE and some memory cells are programmed from state E to state A. At the same time, other memory cells are programmed from state E to state B and/or from state E to state c. The full sequence is graphically depicted by the three curved arrows in Figure 7. 8A-8C disclose another process for stylizing non-volatile memory, which by writing a person to a specific page after writing a person to a neighboring reading unit of a previous page for a any-specific memory unit The memory cell reduces the coupling effect of the floating gate and the floating gate. In the example of the implementation of the process from Fig. 8C, the non-volatile memory unit stores two-dimensional data for each memory cell by using four tributary states. For example, t assumes that state E is an erased state and states A and BAC are stylized. The state is stored in the data 11. State A stores data 01. Shape: 』馆# Information 10. State c stores data 00. This is an example of non-Gray coding' because both bits change between adjacent states. Other data can be used to the status of the entity data. Each memory unit stores data on two pages. The reference page of the heart will be referred to as the upper page and the lower page, however, other standard irons may be given. 127825.doc -23- 200839770 Referring to state A of the process of Figures 8A-8C, the upper page stores the bit 〇 and the lower page stores bit 1. Referring to state B, the upper page stores bit j and the lower page stores bit 〇. Referring to state C, both pages store bit information 0 程式 The stylization process of Figures 8A through 8C is a two-step process. In the first step, the lower page is stylized. If the lower page is to hold the data i, the memory unit state remains in the state E. If the data is to be programmed to be 〇, then the threshold of the voltage of the memory cell is increased and the memory cell is programmed into state B'. As a matter of view, Figure 8A shows the stylization of the memory cell from state E to state B. State B depicted in Figure 8A is the inter-state state b; therefore, the verification point is depicted as Vvb1 below Vvb. In one embodiment, after the memory cell is programmed from state E to state, its neighboring memory cells (connected to WLn+1) in the NAND string will then be programmed with respect to its lower page. For example, after the lower page of the memory cell connected to WL0 is programmed, the lower page of the memory cell (adjacent memory cell) that is on the same NAND string but connected to wu will be programmed. After the stylization of adjacent memory cells, the effect of the floating gate and the floating gate will cause the apparent threshold f of the memory cell to be programmed earlier to increase (if the memory is earlier) The cell has a self-state E rise to state B, which is limited to „). This will have the effect of a threshold voltage distribution of the widened state B·, as depicted by the intermediate voltage distribution 700 of Figure 8b. This apparent widening will be renewed when the upper page is programmed. (4) The process of stylizing the upper page. If the memory is 127825.doc -24- 200839770, the voltage limit is 7GG and the upper page data is to be kept in i. , the memory unit will be programmed into the final state B. If the memory unit is in the intermediate threshold voltage distribution 700 and the upper page data is to be changed to data, the memory unit is in the erased state E and the upper page Wait until !, the memory unit will remain in state E. If the memory unit is in state and its upper page data is to be programmed to 0, the threshold voltage of the memory unit will rise to cause the memory unit At In state A. If the memory unit is in the middle

The threshold voltage of the element will rise so that the memory cell is in state c. The process depicted in Figures 8A through 8C reduces the coupling effect between the floating gates: that: the page stylization of the upper memory cells will have an effect on the apparent threshold voltage of a given memory cell. 2 is a table describing the order of staging the memory cells by using the stylization method of FIGS. 8A to 8 (the staging method). For the memory cells connected to the word axis, the lower page forms page 0. And the upper page forms page 2. The material is connected to the memory unit of the word line wu, the lower page forms page I and the upper page forms page 4. For the memory unit connected to the word line (4), the lower page forms page 3 and the upper page is formed. Page 6. For the memory unit connected to word line WL3, the lower page forms page 5 and the upper page forms page 7. The memory unit is programmed according to the page number from page 〇 to page 7. In other embodiments Can also be used

Other Orders of Modulation D ^ In the K^ example, if enough data is written to fill the word line, the system can be set to perform a full sequence write. If there is not enough data to be written, the stylization process can program the lower page by the received data. When 127825.doc -25- 200839770 receives the follow-up material, the system will then program the upper page. In yet another embodiment, the system can begin writing to the lower page in a stylized mode and convert to a full sequence if subsequently receiving sufficient data to fill the entire (or most) word line of memory cells. Mode. More details of this embodiment are disclosed in the application on 12/14/04, invented by Sergy Anatolievich Gorobets and Yan Li entitled "pipelined"

The disclosure of Non-Volatile Memories Using Early Datan, U.S. Patent Application Publication No. 2006/0126390, the disclosure of which is incorporated herein by reference. Although Figures 7 through 9 depict the use of four data states to store two-dimensional data for each memory unit, other embodiments may use different numbers of data states to store different (or the same) for each memory unit. Information on the number of bits. In one example, eight data states are used to store the three-bit data. Figure 10 is a flow chart depicting a stylization process for programming memory cells connected to selected word lines. Thus, the process of Figure 1 can be used to implement the full sequence of Figure 7 for the selected word line, or to implement a process of the two pass stylization technique of Figures 8A-8C (first process) Or the second process). The process of Figure 10 can also be used as a process for three-pass stylization techniques for three pages of data (e.g., for three-bit data for each memory unit) or as a program for another multiple processes. The technology-sub-process is implemented. Two different stylization techniques can be used in conjunction with the present invention. In an embodiment, by control circuit 22 or under the direction of control circuit 220 (state machine 222 provides control and power control 127825.doc • 26 - 200839770 := provides appropriate signals) and/or at controller 244 Refers to the community of 10. Because the stylized material includes a plurality of pages, the given stylization process can include performing the process of Figure ig multiple times. Note that in some (but not all) embodiments, the memory cells can be programmed from the source side to the immersion. For example, looking at Figure 4, I first programs the word line WL〇, then programs the wli, then programs the WL2, and so on.

In one embodiment, the memory unit is pre-programmed to a common threshold (compressed with a common starting point for uniform wear and/or erasure on the memory cell) prior to stylization and is performed Erase. In some cases, the memory cells are erased without pre-programming. In an embodiment, the P-well is raised to an erase voltage (eg, 2 volts) for a sufficient period of time and the source and bit lines are floated while the word line of the selected block is grounded and wiped In addition to the memory unit. Due to the capacitance_close, the unselected word lines, bit lines, select lines, and sources also rise to a significant portion of the erase voltage. Because: a strong electric field is applied to the tunnel oxide layer of the selected memory cell, and is erased when the electrons of the floating gate are normally emitted to the substrate side by the Førnolder Ham (FQwler_N) collision tunneling mechanism. The data of the selected memory unit Ik is shifted from the electronic self-floating gate to the threshold of the selected unit of the p-well region. Erasing can be performed on the entire memory array, block, or unit of another unit. After erasing the blocks of memory cells, various buddy cells can be programmed as described herein. After erasing, a soft-knocking can be performed to erase the erased threshold voltage of the erased memory cell. Some memory cells can be in an erased state deeper than 127825.doc -27 - 200839770 due to the erase process. Soft stylization can apply a smaller number of stylized pulses to move the threshold voltage of the erased memory cell to a narrower threshold package. Zhuang Yi can perform an erase and soft stylization on a block before staging each page. In a yoke example, the program is started by the controller issuing a "data load" command to the state machine. The address of the page address is provided to the decoder circuit, and the address of the addressed page is entered. The page of the stylized data is used for simplification. For example, in one embodiment, the data of the byte can be input to latch the data into the appropriate register for the selected bit line, in the latch 15 In some embodiments, the data is also latched in a second register for the selected bit line for verification operations. When the address and data are set, the controller provides the state machine with "Stylized" command. By triggering the program command, the data will be programmed to the selected memory controlled by state machine 222 by using a set of pulses applied to the appropriate word line based on the process discussed herein (including the process of FIG. 1). In the body unit. Other configurations can also be implemented. In step 732 of Figure 10, the program voltage signal Vpgm (e. g., the set of programmed pulses) is initialized to a starting magnitude. In conventional systems, the magnitude of the first private burst is between 12 v and 16 v depending on the implementation (other values can be used as well). However, the system described herein dynamically sets the magnitude of the first stylized pulse each time the process of Figure 10 is performed (or at other intervals) based on experimental stylization. The following is a discussion of how to dynamically set the magnitude of the first stylized pulse based on experimental stylization. Step 732 also includes initializing the program counter PC to 〇. The stylized count is maintained by state machine 222. 127825.doc -28- 200839770 Applying a stylized signal V p g m to the selected word line, by using an appropriate set of target levels (eg,

Vva, Vvb, Vvc) verify the data status of the selected memory unit. If

Detecting that the threshold voltage of the selected memory cell has reached the appropriate target level, it is excluded from the remainder of the process of FIG. 10 by raising the bit line voltage of the memory cell (eg, to the vd sentence) In addition to the future stylization, if all the memory cells that have been programmed have reached their target data state (step; 738), the stylization process is completed and successful 'because all selected memory cells are programmed and verified To the target state, report the status of "pass" in step 74. Note that in step 738 - in some implementations, check: no at least a predetermined number of memory cells have been verified to achieve their target sorrow The number of pre-supplements can be less than the number of pre-printed π page bodies 70, thereby allowing the stylization process to stop before all memory cells reach their proper verification levels.

In step 734, rush. At step 736, it is terminated. The memory unit that has not been successfully programmed can be corrected by reading (4) «by (4) miscorrection. If at the step of the process, it is determined that not all memory cells have reached their target state, then the stylization process continues. In step ,, the stylized counter pc is checked against the stylized limit value. The 1st (4) of the stylized limit value is 20; however, 'other values can be used, and the value of the right reddish counter PC is not less than the stylized limit value. Then, in step + HA i ... step 766, the memory that has not been successfully programmed is determined. Whether the number of body units is private, t 疋 is specific to or less than a predetermined number. If the number of memory cells that have not been successfully programmed is equal to or less than the predetermined number, then the process is marked as pass, and /Feng_^, 彳 will be private and the pass state is reported in step 768. In many cases, 127825.doc -29-200839770 can be used to correct the memory units that have not been successfully customized during the reading process by using error correction. However, if the number of unrecognized secondary memory cells is greater than the predetermined number, the stylization process is marked as failed and the failure status is reported in step 770. Right (in step 760) the stylized counter pc is less than the stylized limit value, then at step 762, the magnitude of the Vpgm pulse is in steps (eg, 〇 2 volts)

The step size is increased to 4 volts and the stylized counter PC is incremented. After step 762, the process returns to step 4 to apply the next pulse. Figure U is a flow chart depicting the process of privately ordering data by using a stylized signal (corrected by adjusting its initial magnitude based on the trial stylization process) from a high level. The process of Figure 11 can be performed under the direction of a state machine in response to a request to program the data. In the example, the process of Figure 11 includes performing the method of Figure 1 one or more times. In step _ of Figure U, the test stylization is performed.纟 中 'Programming the data so that the state machine will be 2: the page and each page includes - group test memory Zhao single: At least part of the test memory unit during the stylization ^. In the complete example of the test record, (4) unit during the trial stylization, the test memory unit of the user who stores the page is connected to the same memory unit of the same word. The fork 1 has the memory of the user data; the ::... page or part of the different pages. The test memory unit can be specified to store memory data such as HDR data (see Figure 5). Memory Sheet 127825.doc -30- 200839770

yuan. In the implementation, the test memory unit is a memory unit for storing a plurality of flags, and the one or more flags indicate whether the lower page and/or the upper page data have been processed according to FIG. And for a word line is stylized. Although the flag can be used to store data, these flags are treated as bin-coded data in the library because the data is only in the state (4) state c. In other embodiments, the flag may store the data in any of the data states (multiple bits of code). One example of a trial stylization process includes performing a trial stylization of a memory unit that stores flag data. If the test programmatically uses the memory unit that stores the flag data, the test program is performed on the suffix unit that does not store the user's beaker. In an alternative, the storage (4) is recorded as a unit execution test stylization. Other embodiments use a redundant flash memory unit for experimental stylization. Redundant memory units are often used instead of being identified as faulty A memory unit (eg, causing a data error). In other embodiments... a group memory unit may be included in the block for a special purpose as a test memory unit. In this case, the block may contain only Used to test 2 to 8 (or another series) of stylized. The number of test memory cells can vary based on implementation. In the embodiment, 2 to 8 test memory cells can be used. In the embodiment, the test stylization includes applying _ a stylized pulse to the control memory unit. In other embodiments, applying more than one pulse to the test: the memory unit. The rush (or eve pulse) will increase the threshold voltage of the test memory cell by 127825.doc -31 - 200839770. To prevent over-stylization, the stylized pulse of the test can be programmed. Small enough to ensure no over-stylization. Figure 12 shows the threshold voltage distribution 840 of the erased test memory cell prior to any test stylization. The threshold voltage distribution 842 represents a stylized pulse after the test stylization The same test memory unit. Figure 12 also shows three voltage values VtrL, VtrM and VtrH, which are used to distinguish between slow, medium and fast (or new, medium and old) stylized memory cells. In some implementations, VtrM Vva is similar to Vva of Figure 7 and VtrH is aligned with the high end edge of the threshold voltage distribution of state A. In other embodiments, VtrL, VtrM, and VtrH can be other values. Step 802 of Figure 11 includes performing a set of sensing operations. To determine the results of the trial stylization and classify the test memory cells into a set of threshold voltage ranges. For example, step 802 includes determining whether each of the test memory cells has less than VtrL (see Figure 12), greater than Or a threshold voltage equal to VtrL and less than VtrM, greater than or equal to VtrM and less than VtrH or greater than or equal to VtrH. In other embodiments, more or less than four of these may be used. Step 804 of Figure 11 includes setting the magnitude of the first pulse of the programmed pulse Vpgm based on the test stylization. The indication of the magnitude of the first pulse can be stored in the register for the state machine and in step 732 During this period, it is checked (see Fig. 10). In one embodiment, the magnitude of the first pulse Vpgm(O) is set as follows: If Vth is trial^VtrH, Bay Vpgm(0) = Vpgm - nominal - 3 (DAC); 127825.doc 32- 200839770 If VtrH>Vth__trial^:VtrM, then Vpgm(0)=V|)gm_nominal -2(DAC); If VtrM>Vth-trial^:VtrL, then Vpgm(0)= Vpgm—nominal -l(DAC); If VtrL>Vth—trial, Vpgm(0)=Vpgm—nominal; where Vpgm_nominal is the standard value of the first pulse without adjustment (depending on the design) From 12 volts to 16 volts, Vth_trial is the result of a trial stylization and the DAC is equal to the voltage of the step used in step 762 of FIG. In other embodiments, the DAC can be other values than the step size. In another embodiment, the magnitude of the first pulse Vpgm(0) is set as follows: If Vth-trial^:VtrH, then Vpgm(0)=Vpgm_nominal; if VtrH>Vth-trial^VtrM, Bell 1J Vpgm (0)=Vpgm—nominal+ l(DAC); if VtrM>Vth—trial>Vth—trialSVtrL, Bay]Vpgm(0)=

Vpgm—nominal + 2(DAC); If VtrL>Vth is a trial, Bellow J Vpgm(0)=Vpgm_nominal+ 3(DAC); many other configurations are also possible. The exact mechanism for adjusting the magnitude of the first pulse, Vpgm(0), may depend on the particular storage system being implemented. In one embodiment, the results of step 802 are averaged to produce Vth_trial. For example, if the six test memory cells are measured in step 802, the threshold voltage is in the third range (VtrM > Vth_trial 127825.doc -33 - 200839770 2VtrL) and the six test memories in step 802 The body unit is measured to have its threshold voltage in the first range (Vth_tria pan VtrH), then the average value is the second range and Vth_trial will be set to indicate the range VtrH > Vth_trial > VtrM 另一 In another embodiment, Set Vth_tdal to indicate the result from the fastest memory unit. For example, if three test memory cells are measured to be in the fourth range (Vth_trial < VtrL), the six test memory cells are measured to have their threshold voltage in the third range (VtrM > Vth_trial 2VtrL) The six test memory cells are measured to have their threshold voltage in the second range (VtrH > Vth_trial2VtrM) and a test memory cell is measured to have the threshold voltage in the first range (Vth_trial > VtrH) Then, Vth_trial is set to indicate that the first range Vth_trial2 VtrH 之后 after setting the magnitude of the first stylized pulse, in step 806 by using a set of stylized pulses (where the first pulse has the amount set in step 804) Value) The memory unit that stores the user data is stylized. The stylization of step 806 includes one or more iterations of the process of Figure 10 to program the data according to the method described with reference to Figures 7 and 8, or other stylized methods. Figure 13 depicts an example embodiment for implementing the concepts of Figure 11 including programming data by using a stylized signal (corrected by adjusting its initial magnitude based on a trial stylization process). In step 900 of Figure 13, in response to a particular request to program a particular profile, the state machine will pre-program all of the memory cells of the data block to state E. 127825.doc -34- 200839770 In step 902, the memory cells of the block will be erased. Page 0 will be programmed in step 904, and page 1 will be programmed in step 906. Page 2 will be programmed in step 908... Page X will be programmed in step 91. In one embodiment, the process of Figure 13 programs the word lines in the direction from the source to the drain/bit lines, and each word line stores a page of material. In another embodiment, each word line stores information for more than one page. In the embodiment associated with Figures 8A through 8C, the order of the stylized pages (steps 9〇4, 9〇6, 9〇8...91〇) can be rearranged according to the table of Figure 9. Other orders can also be used. Each step of programming a page 9〇4, 9〇6, 908~91〇 includes the process of executing Figure 14. As described above, in one embodiment, each word line (or each page) includes a first set of memory cells for storing user data and a second set of memory cells for testing stylization . The first set of memory 70 and the second set of memory cells are all connected to the same word line. For example, each of the first set and the second set of memory cells are on different NAND strings. In the embodiment, the last 2 to 8 bit lines (or another set of bit lines) are connected to the NAND strings of the test memory cells. In step 1002 of FIG. 14, the individual bit line voltages of the NAND strings (eg, which store user data) that are not used for the test stylization are raised to a suppression such as Vdd (eg, 3.5 volts). The level is suppressed to prevent it from being stylized. In step 1〇04, a stylized pulse is applied to the word line (and therefore to the control gate of the test memory cell) to perform the test stylization. In some embodiments, the test stylization may include using one or more passes of the I27825.doc -35 · 200839770 styled pulse 4 step genus to sense unsuppressed memory cells (as described above) to determine Information on the amount of electricity dust. For example, the read operations can be performed by jVtrL, VtrM, and VtrH, and the 单L body single το can be classified into one of the four (or three) ranges discussed above. In the step coffee, the magnitude of the initial stylized pulse can be set as described above. Just in step 1, follow the diagram! The process of squatting to program the data or the evening page. Step 1〇1〇 can also include completing the system

Stylized into the memory unit used to test the stylization. In the binary target example, the memory unit programmed in step 1010 includes a test memory single S. That is, some embodiments perform trial stylization of the memory unit for storing user data, and in that case, step 1010 includes completing the stylization of the user data into the memory unit subjected to the test stylization. Figure 15 is a flow diagram depicting a process for sensing data for a selected word line. The process of Figure 15 can be used during step 8〇2 (Figure 11) and during step 1006 (Figure 14). Generally, during a read and verify operation, the selected word line is connected to a voltage, and the level of the voltage is specified for each read and verify operation to determine whether the threshold voltage of the memory cell of interest has been reached. This level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell is turned on in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conducted current is not measured to be greater than the specified value, it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. 127825.doc -36- 200839770 There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current is measured by the rate at which the memory cell discharges or charges a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or does not allow) the NAND string including the memory cell to discharge the bit line. The charge on the bit line is measured after a period of time to see if it has been discharged. Additional information on read operations and sense amplifiers can be found in (1) U.S. Patent Application Publication No. 2004/0057287, issued March 25, 2004, entitled "Non-Volatile Memory And Method With Reduced (2) U.S. Patent Application Publication No. 2004/0109357, issued June 10, 2004, entitled "Nonvolatile Memory And Method with Improved Sensing,; (3) US Patent Application Publication No. 20050169082 (4) Applying on April 5, 2005, 'Inventor is Jian Chen's US Patent Publication No. 2006/0221692 entitled "Compensating for Coupling During Read Operations of Non-Volatile Memory"; (5) Application No. 11/321,953 to Siu Lung Chan and Raul-Adrian Cernea, entitled "Reference Sense Amplifier For Non-Volatile Memory", U.S. Patent Application Serial No. 11/321,953. All of the five or more listed patent documents are incorporated herein by reference in their entirety. In step 1100 of Figure 15, a first comparison voltage (e.g., VtL) is applied to the selected word line WLn. In step 1102, a bit line associated with the page is sensed to determine if the addressed memory cell is turned "on (based on applying a first comparison voltage to its control gate). The conductive bit line indicates the memory list 127825.doc •37· 200839770 yuan is turned on; therefore, the threshold voltage of their memory cells is below the first comparison voltage. In step 1104, the sensed results of the bit lines are stored in appropriate latches for their bit lines. Instead of sensing the bit line voltage, the capacitor can be sensed in the sense amplifier as mentioned above. In step 1106, a second comparison voltage (e.g., VtM) is applied to the selected word line WLn. In step 〇8, the bit line associated with the page is sensed. It is determined whether the addressed memory cell is turned on (based on applying the first comparison voltage to its control gate). The conductive bit lines indicate that the memory cells are turned on; therefore, the threshold voltages of their memory cells are below the second comparison voltage. In step 1110, the sensed results of the bit lines are stored in appropriate latches for their bit lines. Instead of sensing the bit line voltage, the capacitor can be sensed in the sense amplifier as mentioned above. In step 1112, a third comparison voltage (e.g., VtH) is applied to the selected word line WLn. In step 1114, a bit line associated with the page is sensed to determine if the addressed memory cell is turned "on (based on applying a first comparison voltage to its control gate). The conductive bit lines indicate that the memory cells are turned on; therefore, the threshold voltages of their memory cells are below the second comparison voltage. In step 1116, the sensed results of the bit lines are stored in appropriate latches for their 'bit lines. Instead of sensing the bit line voltage, the capacitor can be sensed in the sense amplifier as mentioned above. In step 1118, the memory cells connected to the selected word line are sorted based on the results of the three sensing operations. For example, whether the memory cell is in the first range of the threshold voltage below VtL, in the second range of the threshold voltage greater than or equal to VtL and less than VtM, greater than or equal to 127825.doc -38-200839770 and The memory cell is tested in a third range of the threshold SVtH or in a fourth range greater than or equal to VtH. In another embodiment t, the first range and the second range may be combined into A single range. Four or more or four or less ranges may be used, and other ranges may be used. In a λ example, 'classification is performed by the processor 492 at the end of the process. In another embodiment, 'processor milk The range is determined during operation such that the data analysis is updated as each perceptive knowledge is executed. Processor 492 will store the determined range indication in the appropriate latch for each bit line. In other embodiments A state machine or other component may be used to determine the range. Figure 16 depicts another embodiment for implementing the concept of using the formula # (by adjusting the initial amount of the basin based on the trial stylization process) value Correct the data and program the data. In the example of the figure, the memory connected to the WLG (the word line adjacent to the source line) will be programmed to be programmed. In the embodiment (4) is also the first word line to be stylized. In the instance, the test will be performed on all the ticks connected to wl〇. • In another example, the pair will be connected to WL0. The subset of memory cells performs experimental stylization, such as the ticketing discussed above, the storage of memory cells, the storage of other system data, or the storage of users 7 degrees (multi-state or two-bit) a subset of the data. Based on, the: test execution of the L〇 execution will set the first stylized pulse for the remainder of the block of memory cells during the current stylization process (in response to the current stylized request) The future stylization process will reset the magnitude of the first stylized pulse based on the new test stylization. In the step of Figure 16, in response to the stylization of specific data, 127825.doc -39- 200839770 Specific request, state machine will Program servant Yao M f & all memory cell to the state of knowledge Great eight Tu-shell block of E. In step 1002, candesartan ^ p & T erase block of the memory unit.

In step 1204, the test is stylized by applying a singularity to the WL0.

The control gate of the memory unit involved provides a stylized pulse (because the word line is connected to the control gate of the memory unit). If not all memory cells connected to WL0 participate in the trial stylization, the bit lines of the memory cells that are not involved in the test stylization will be raised to (4), and the bits of the memory cells participating in the test stylization The line will be in volts. In step 12〇6, the memory unit (as described above) involved in the stylization of the test is sensed to determine information about the magnitude of its threshold voltage. For example, you can

VtrL, VtrM, and VtrH perform read operations, and the memory single π can be correspondingly classified into one of the four (or three) ranges discussed above with reference to FIG. In the step, the magnitude of the initial stylized pulse can be set as described above. This magnitude of the initial stylized pulse can then be used to program the memory cells connected to other word lines of the current block. In step 1210, the process of page 〇 on WL0 (or all WL〇) is completed. It may have been programmed (in some cases, done) to stylize the page by trial stylization; therefore, the stylization is done in step 121. Page 1 will be programmed in step 1212, and page 2 will be programmed in step 1214... the page will be stylized again in step 1216. In one embodiment, steps U12, U14, ... U16 each include the process of performing Figure 1 and each includes using a first pulse (or set of pulses) having the magnitude set in step 1208. For example, if sixty-four pages are programmed, there will be fourteen first pulses (each of the magnitudes 127825.doc -40-200839770 equal to the magnitude set in step 1208). Page one). In one embodiment, the process of FIG. 16 programs the word lines in the direction from the source to the drain/bit lines, and each word line stores the data of one page. In another embodiment, each The word line stores more than one page. In the embodiment associated with Figures 8A-8C, the order of the stylized pages (steps 1212, 1214, .1216) can be rearranged according to the table of Figure $. Other orders can also be used. In addition, other embodiments may use other pages or other word lines for experimental stylization. The foregoing detailed description of the invention has been set forth Many modifications and variations are possible in light of the above teachings. The embodiments described are chosen to best illustrate the principles of the invention and its application in the application of the invention. The present invention is utilized. It is intended that the scope of the invention be defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of a NAND string. Figure 2 is an equivalent circuit diagram of the N AND string. Figure 3 is a block diagram of a non-volatile memory system. 4 is a block diagram depicting one embodiment of a memory array. Figure 5 depicts an exemplary organization of data along a word line. 6 is a block diagram depicting one embodiment of a sensing block. Figure 7 depicts an example set of threshold voltage distributions and describes the process used to program non-volatile & 127825.doc -41· 200839770 Figures 8A-8C show various 庐 稷 限 U-limit voltage distributions and describe the process for stylizing non-volatile Z 丨 丨 体. Fig. 9 is a table showing an example of the sequence of the staging of the non-volatile I. Figure 10 depicts a flow chart, an embodiment of a process for programming non-volatile memory. Figure 11 depicts a flow diagram of an embodiment of a process in which a basin is used to program a non-volatile memory, and an initial program voltage is set based on a test in a 1 φ u tool. Figure 12 depicts the threshold voltage distribution. Figure 13 is a flow chart depicting the use of fine reflow for non-volatile memory.

In one embodiment of the stylization process, 苴φ I U soldiers f set the initial program voltage based on the test. Figure 14 depicts an embodiment of the process of a flow chart. Figure 15 depicts a flow diagram depicting one embodiment of a process for programming a data page to describe a process for sensing non-volatile memory. Figure 16 depicts the flow-flow®' description of the process for programming non-volatile memory. The initial program voltage is set based on the test. [Main component symbol description] 100 Transistor 100CG control gate 100FG Floating gate 127825.doc -42- 200839770 102 Transistor I02CG Control gate 102FG Floating gate 104 Transistor 104CG Control gate 104FG Floating gate 106 Transistor 106CG Control gate 106FG Floating gate 120 First (or no pole Side) Select Gate 122 Second (or Source Side) Select Gate 126 Bit Line Contact Point 128 Source Line 200 Memory Cell Array 210 Memory Device 212 Memory Chip or Wafer 220 Control Circuit 222 State Machine / State machine circuit 224 on-chip address decoder/decoder circuit 226 power control module/power control circuit 230A read/write circuit 230B read/write circuit 232 line 234 line 127825.doc -43 - 200839770

240A column decoder/decoder circuit 240B column decoder/decoder circuit 242A row decoder/decoder circuit 242B row decoder/decoder circuit 244 controller 300 sensing block 420 data bus 470 sensing circuit 472 poor Material bus 480 sensing module 482 bit line latch 490 common part 492 processor 493 input line 494 data latch / data latch stack 496 I / O interface 700 intermediate threshold voltage distribution 840 threshold voltage Distribution 842 threshold voltage distribution A threshold voltage distribution / threshold voltage range / stylized state B threshold voltage distribution / threshold voltage range / stylized state BLO - BL69623 bit line B, state C threshold voltage distribution / Pro Limit voltage range / stylized status 127825.doc -44- 200839770

E SGD SGS Vra Vrb Vrc Vva Vvb Vvb丨Vvc VtrH VtrL VtrM WLO WL1 WL2 WL3 First threshold voltage distribution / threshold voltage range / erase state selection line select line read reference voltage read reference voltage read reference voltage verification Reference voltage verification reference voltage verification point verification reference voltage voltage value voltage value voltage value word line word line word line word line 127825.doc -45-

Claims (1)

200839770 X. The scope of the patent application includes the method of stylizing non-volatile storage, the package part = a non-volatile storage element - the first set performs at least one::: after the stylization, identifies the non-volatile One or more threshold voltage ranges of the raft of the storage element; one of the non-volatile storage elements is identified by the power limit (four) and is set to -: two = - or multiple rushed - initial magnitude And the 4-type pulse-to-pulse hunting is programmed by using a second set of the set of stylized storage elements having the initial magnitude. The method of claim 1, wherein the performing at least partially stylized comprises applying a stylized pulse to the control gate of the first set of non-volatile storage elements. Identifying includes performing a range by using a plurality of threshold voltage comparison values and selecting a range based on the sensing; _ each of the first pulse magnitudes of the set of stylized pulses associated with different first pulse magnitudes The person is associated with one of the persons, and the setting step selects one of the different pulse magnitudes based on the sensing operations. 3. The method of claim 1, wherein the first one of the one or more non-volatile storage elements comprises a plurality of non-127825.doc 200839770 volatile storage elements; the one or more threshold voltages are identified The range includes the recognition range; (4) Limit voltage The initial value is set based on one of the plurality of threshold voltage ranges. 3 is not the fastest 4. The method of claim 1, wherein: the first set of volatile storage elements of one or more non-volatile storage elements; comprising a plurality of non-specific voltage ranges; The plurality of threshold voltage ranges includes identifying the plurality of initial values based on the plurality of identified threshold voltage averages. The method of claim 1, wherein: the first set of volatile storage elements of the plurality of non-volatile storage elements; the plurality of non-identifications or the plurality of threshold electrical ranges Range; one of the threshold voltage ranges is calculated based on the plurality of identified threshold electronic functions. Target 6 - The method of claim 1, wherein - or - a plurality of non-volatile storage materials, and ... a collection of non-volatile storage elements - or a plurality of non-volatile storage elements. The method of claim 6, wherein: or the non-volatile storage element of the non-volatile storage element 隹/a set and one or more 8· The method of claim 1, wherein the ··* port is connected to the common word line. The fourth component of the non-volatile storage element is also the method of claim 1, wherein: the second set of non-volatile storage elements is also for the non-volatile storage element. Step 1 〇. As requested by the method, where: 〇 〇 订 订. The set of programmed pulse values; and the parented pulse in * has a different amount 11 - 2:: The magnitude is used for the first pulse in the set of programmed pulses. A non-volatile storage system comprising: a plurality of groups of connected non-volatile storage elements; and: or a plurality of management circuits that communicate with a plurality of connected non-volatile storage elements The plurality or plurality of management circuits measure resistance information of the plurality of groups of non-volatile storage elements connected to the one or more management circuits by self-connecting non-volatile storage elements using the resistance information Wait for the group to read the data. 12. The non-volatile storage system of claim 1, wherein: the one or more management circuits classify each group as being related to a high resistance state or a low resistance state; and the one or more management circuits The data is read from the group reading 127825.doc 200839770 using a read parameter, the one or more management circuits being classified as being related to a high resistance state or a low resistance state based on a respective group The group selects the read parameter individually. 13. The non-volatile storage system of claim π, wherein: the one or more management circuits individually select a bit line voltage for each group based on the resistance information by the one or more management circuits And reading data from these groups. 14. The non-volatile storage system of claim 11, wherein: the one or more management circuits use a word line voltage individually selected for each group based on the resistance information by the one or more management circuits Read data from these groups. i: > • the requesting item - or a plurality of management circuits from the group by using the one or more management circuits for each of the groups individually selected for sensing based on the resistance information The group reads the data. 16. The non-volatile storage system of claim 15, wherein: each group of non-volatile storage elements comprises a target non-volatile storage element in each group; =^ non-volatile storage Each of the _ groups includes adjacent non-volatile storage elements adjacent to the target - adjacent non-volatile storage elements. or a plurality of management circuits are from the target non-volatile storage elements; The adjacent non-volatile storage elements provide supplements. 17. The non-volatile storage system of claim U, wherein 127825.doc 200839770 the one or more management circuits determine the message; and the status of the adjacent storage elements is 18 The supplement is based on the status information and the non-volatile storage system of the electric appliance, wherein the one or more management circuits include a control motor circuit, a decoder, a read/write circuit, and a controller. Either or a combination. p and information. Where: road, power circuit, state processor, sense amplifier 19. A non-volatile storage system as claimed in claim 7, wherein the group of non-volatile storage elements connected is a nand string. 20. The non-volatile storage system of claim 11, wherein: the violation-or plurality of management circuits apply a _th voltage to the non-volatile storage--sub-set of the group The second subset of the groups of volatile storage elements apply a second voltage and sense the current in the groups to measure the resistance information. 21. The non-volatile storage system of claim U, wherein: the group of connected non-volatile storage elements stores data for a plurality of bits in each non-volatile storage element. 22. The non-volatile storage system of claim 11, wherein: the parameter is a control gate voltage. 127825.doc