TW200838002A - Damascene phase change RAM and manufacturing method - Google Patents

Abstract

A method for manufacturing a memory device uses a damascene process to define memory elements. The device comprises a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A damascene patch crosses the insulating member aligned with the first and second electrodes, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided.

Description

</ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [Parties to the Joint Research Contract] New York International Business Machines Corporation, Taiwan Wanghong International Co., Ltd. and Infineon Technologies A.G. are the parties to the joint research contract. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a south density memory device based on phase change memory materials, and a method of fabricating such devices, the phase change memory material comprising a chalcogenide material and other materials. [Prior Art] Memory materials based on phase change are widely used in reading and writing optical discs. These materials include at least two solid phases, including, for example, a solid phase that is largely amorphous, and a solid phase that is substantially crystalline. Laser pulses are used to read and write optical discs to switch between the two phases and to read the optical properties of such materials after phase changes. Such phase change memory materials, such as chalcogenides and the like, can be altered by applying a current whose amplitude is applied to the integrated circuit. In general, the amorphous state is characterized by a higher electrical resistance than the crystalline state, and this resistance value can be easily measured and used as an indication. This feature has led to interest in the use of programmable resistive materials to form non-volatile memory circuits. This 200838002 circuit can be used for random access. From the non-S day sorrow to the crystalline state _ like a low yield. &quot; The crystalline state transitions to the amorphous state (hereinafter referred to as g, . k &quot;, the mouth of the weeping cow® \ L軏 is reset) is generally a high-electromusic step 'it includes - (four) high The current density pulse melts the crystalline structure 'after which the phase change material rapidly cools, suppressing the phase change process' so that at least part of the phase change structure is maintained at amorphization. Under the sorrow of the phase, the phase change of the phase change material from the crystalline state to the amorphous state, the lower the better. To reduce the magnitude of the reset current required for resetting, this can be achieved by reducing the size of the phase change material component in the memory and the contact area of the r electrode with the phase change material, so that the material component can be changed for this phase A lower absolute current value is applied to achieve a higher current excess. A method developed in this field is to create tiny holes in an integrated circuit structure and fill these tiny holes with a trace of programmable resistance material. The patents dedicated to such microscopic holes include: U.S. Patent No. 5,687,^2, published November 11, 1997, Multibit Single Cell Memory Element Having Tapered Contact, inventor Ovshinky; August 4, 1998 U.S. Patent No. 5,789,277, Method of Method of Memory Chalogenide [sic] Memory Device,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Of Fabricating the Same", the inventor is Doan et al. The study also found that the etching compound used to pattern the phase change material may damage the surface layer of the material by unevenly removing the composition of the phase change material from the surface. The core area of the phase change material can be protected from such damage. When manufacturing these devices on very small scales and the rigorous process variables required to produce large size memory devices, you will encounter the question 6 200838002 J S 2 S: a kind of memory cell (me_ry, the structure includes ϋΐϊϊί current' and In order to manufacture such structures, it is possible to provide a strict process variable specification for the ~ic set. A better process of the peripheral circuit is fabricated and fabricated on the same-integrated circuit. Phase change random access memory pcram memory device i, bean package circuit. The technology described herein includes -i: Ray C has one of the page side of the first electrode, has a top side member. Located at the first The insulating top core between the electrode and the second electrode? The ij pole 3, close to the first electrode, spans the side of the slow furnace, and has a visibility. A mosaic film guide defines an electrode gate two in the first The first electrode and the second electrode have a path between the dipoles across the insulating member - and phase or voltage can be applied between the first and second electrodes: the volume of the memory material can be very small, by the insulating structure ===path length of the path), the film used to form the bridge ί, the width of the bridge perpendicular to the path length (ζ direction), the thickness of the film, the thickness of the crucible, and the memory used to form the bridge The material 'bestness' is formed by the film thickness in each embodiment. The method is not limited to the lithography process for fabricating the memory cell. The guide bridge also has the best feature size F, which is used to pattern each material layer in the stencil yoke example. The lithography process has the advantage that the phase change memory cell can be easily fabricated, which has a simple structure and achieves very small reset current and low power consumption. w 7 200838002 is listed in the technology of the embodiment of the present invention. In this array, a plurality of electrical layers have an upper surface 'which is in some embodiments of the present invention's two-pole insulating member' and on the upper surface of her layer includes C cow = between each of this array - In the memory cell, a current path from the electrode layer; the m-pole, through the thin film viaduct on the upper surface of the electrode layer, is established. One of the electrician's layers is the circuit under the electrode layer on the field circuit, which can be used by the well-known #circuit technology and memory array. In the embodiment, as in the case of the memory cell - the conductor - the conductor forms a conduction between the terminal and the second of the transistor. According to the - representative embodiment, the electrode path device. The plurality of isolation devices have a first-terminal turn==press line, a second-second terminal, and a first electrode of a conductor extension strip: the first electrode belongs to the memory cell in the array. In addition, a plurality of word lines are provided in the path below the electrode layer. A plurality of word line lines are coupled to a link between the memory cell along the array = column and one of the plurality of bias lines. In an array embodiment of the present invention, a plurality of bias lines are arranged next to the pairs of rows in the array, and in a plurality of isolation devices = isolation devices (coupled to corresponding column pairs of memory cells) Connect) a common bias line in the &amp; crimp line. In the case of an array embodiment of the present invention, the circuit includes a plurality of bit lines on the electrode layer. In one embodiment having &amp; element line 8 200838002 above the electrode layer of the present invention, the electrode members in the electrode layer act as a first electrode of a memory cell and are shared such that a single electrode member acts in the array The first electrode of both of the rows of memory cells. Meanwhile, in an embodiment of the invention, the bit lines of the plurality of bit lines are arranged along corresponding rows of the array, and the two adjacent memory cells in the corresponding row share a contact structure to contact The first electrode. The present invention describes a method of fabricating a memory device using damascene techniques to form phase change elements. The method includes forming an electrode layer on a substrate including circuitry fabricated using a front-end process. The electrode layer in this method has an upper surface. For each phase change memory cell to be formed, the electrode layer includes a first electrode and a second electrode, and an insulating member between the first and second electrodes. The first and second electrodes and the insulating member extend to the upper surface of the electrode layer, and the insulating member has a width between the upper surfaces of the first and second electrodes, as described above, connected to the phase change memory cell structure. The method also includes, for each memory cell to be formed, forming a memory using a damascene technique (including etching a trench in a material on a layer of electrodes and filling the trench with a memory material to form a damascene viaduct) The material is bridged on the upper surface of the electrode layer across the insulating member. The bridge includes a film of memory material having a first side and a second side and contacting the first and second electrodes with a first side. The bridge is defined between the first and second electrodes across the insulating member and defines an inter-electrode path whose path length is defined by the width of the insulating member. In an embodiment of the method, an access structure is formed on the electrode layer by forming a patterned conductor layer over the viaduct and then forming a contact between the first electrode and the patterned conductor layer. In the embodiment of the present invention, a method for forming a damascene viaduct includes: forming a dielectric layer on the electrode layer; engraving a trench array in the dielectric layer; 9 200838002 / 二尤a stack of materials in the trenches in the array of trenches, an array of inlaid material blocks over the upper surface of the electrode layer, the array of inlay blocks including corresponding to the pair of electrodes Each of the electrodes in the array, the memory material block, is in contact with the corresponding first and second electrodes, the insulating member of the corresponding electrode, and the blocks of the mosaic memory material include the corresponding k兮二ΐΐ: the first side and the first The second side, and the first side contacts a second electrode, the second electrode, the memory material block defines the diameter, the electrode between the two electrodes and the electrode between the electrodes; There is: path length 'the length of the path is determined by the pole pair = column ^ Over the memory material block, and electrical - V bad connection between the lattice patterned conductive layer forming method may be of: forming a non-conductive micro-bridge square of J-bridge structure embedded within the memory cell is conductive bridge. Available with a very structured resistor material. The clothing's use of a technique other than the phase change that is close to the main phase change guide' does not cause the compound to be damaged; The composition of the present invention will be described by the method of charging and polishing, the surface layer of the crucible, and the core region of the viaduct being exposed to the etching or the seal by using the inlaid abrasive compound cT, _. The invention is described in the following: (2) The invention can be fully understood through the following features, objects and advantages of the embodiment of the present invention. [Embodiment] A thin film fuse phase change memory cell, an array of the memory cell, 200838002, and a method for manufacturing the memory cell are described in detail with reference to Fig. 1J7. FIG. 1 illustrates the basic structure of the memory cell 10, including a memory material vial 11 above the electrode layer, the electrode layer including a first electrode 12, a second electrode 13, and a first electrode 12 and a first electrode The insulating member 14 between the two electrodes 13. As previously described, the first and second electrodes 12, 13 have upper surfaces 12a, 13a, respectively. Similarly, the insulating member 14 has an upper surface 14a. The upper surface 12a, 13a, 14a of each of the structures in the electrode layer defines a substantially flat upper surface of the electrode layer, as in the illustrated embodiment. The memory material guide 14 is located above the flat upper surface of the electrode layer such that the contact between the first electrode 12 and the via 11 and between the second electrode 13 and the via 11 is located at the via 11 Bottom side. Figure 2 illustrates a current path 15 formed by the memory cell structure between the first electrode 12, the via 11 and the second electrode 13. The access circuit can be implemented to contact the first electrode 12 and the second electrode 13 in different configurations, thereby controlling the operation of the memory cell, so that the memory material bridge 11 can be programmatically reversibly disposed in at least two solid phases One. For example, using a chalcogenide-based phase change memory material, the memory cell can be set to a relatively high resistivity state, wherein the via 11 is at current: at least a portion of the path 15 is amorphous State, and can be set to a relatively low resistivity state, wherein the majority of the via 11 in the current path 15 remains crystalline. Figure 3 depicts the active channel 16 of the vial 11, wherein the active channel 16 is the region in which the memory material is induced to switch between at least two solid phases. It will be appreciated that the active channel 16 can be very small in the illustrated configuration, reducing the magnitude of the current required to induce phase changes. The fourth figure shows the important size of the memory cell 10. The path length L (X direction) of the active channel between the electrodes is defined by the thickness of the insulating member 14 (referred to as a channel dielectric in the drawing) between the first electrode 12 and the second electrode 13 200838002. In the embodiment of the memory cell, this length L can be changed by controlling the width of the insulating member 14. In a representative embodiment, the width of the insulating member 14 can be determined by thin film deposition techniques used to form a thin film sidewall dielectric on the side of an electrode stack. Therefore, in the embodiment of the memory cell, the width of the insulating member 14 and the accompanying path length L are less than 100 nm. Other embodiments may have a path length L of about 40 nm or less. In other embodiments, the path length L can be less than 20 nm. It will be appreciated that the path length L can be even less than 20 nm, depending on the needs of the particular application, using thin film deposition techniques such as atomic layer deposition. Similarly, in embodiments of the memory cell, the via thickness T (y direction) can be very small. The bridge thickness T can be established on the upper surfaces of the first electrode 12, the insulating member 14, and the second electrode 13 by a thin film deposition technique. Thus, embodiments of the memory cell have a via T thickness of 50 nm or less. Other embodiments of memory cells have a via thickness of 20 nm or less. In other embodiments, the via thickness T is 10 nm or less. It can be understood that the thickness T of the bridge can be even less than 10 nm, which is achieved by using a thin film deposition technique such as atomic layer deposition according to the requirements of a specific application, as long as the thickness is sufficient for the bridge to perform the function of its memory element. That is, it has at least two; the solid phase is reversibly induced by a current or a voltage applied between the first electrode 12 and the second electrode 13. As shown in Fig. 4, the guide bridge width W (z direction) can also be very small. In the preferred embodiment, the via width W is implemented using a damascene process such that it has a width of less than 100 nm. In some embodiments, the via width W is about 40 nm or less. Embodiments of the memory material include phase change based memory materials, including chalcogenide based materials and other materials as the vias 11. The chalcogenide includes any of the following four elements: oxygen (Ο), sulfur (S), sir (Se), and tellurium (Te), forming part of the group VI of the periodic table. 12 200838002 Sulfur includes the combination of a chalcogen with a more positive element or free radical. The chalcogen compound alloy includes a combination of a chalcogen compound, a cowpea, a transition metal, and the like. A chalcogenide alloy typically includes more than one element from the sixth column of the meta-period table, such as the error (Ge) and tin jSn). Generally, the chalcogenide alloy includes one or more of the following elements: Sb, gallium (Ga), indium (In), and silver (Ag). Many phase change-based memory materials have been described in the technical documents, including the following alloys: gallium/germanium, indium/record, indium/bismuth, antimony/bismuth, antimony/bismuth, antimony/bismuth, antimony/indium/ Record / 碲, gallium / Shixi / 钖, 钖 / recorded / broken, indium / 锑 / 锗, silver / indium / recorded 碲 / 碲, 锗 / tin / recorded / 碲, wrong / 锑 / 砸 / 、, and 碲/锗/锑/sulfur. In the 锗/record/碲 alloy, family, a wide range of alloy compositions can be tried. This ingredient can be expressed in the following special political form: TeaGebSbioo^a,. One researcher described the most useful alloys in that the average enthalpy concentration contained in the deposited material is well below 70%, typically below 60%, and the bismuth content in the general type alloy ranges from the lowest. 23% up to 58%, and the best line is between 48% and 58%. The concentration of cerium is above about 5% and its average range in the material ranges from a minimum of 8% to a maximum of 30%, typically less than 50%. Most preferably, the concentration range of 锗 is between 8% and 40%. The main component remaining in this composition is 锑. The above percentages are atomic percentages, which are all 100% of all constituent elements. (Ovshinky '112 patent, columns 10-11) Special alloys evaluated by another investigator include Ge2Sb2Te5, GeSb2Te4, and

GeSb4Te7. (Noboru Yamada, &quot;Potential of Ge-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording,,, π/五ν·37(10), pp·28-37 (1997)) More generally, transition metals Such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt), and mixtures or alloys thereof, may be combined with 锗 / 锑 / 碲 to form a phase Varying alloys include programmable resistance properties. A special example of a memory material that can be used is described in column 11_13 of the Ovshinsky '112 patent, an example of which is incorporated herein by reference. 13 200838002 Phase change alloys can be switched between the first structural state in which the material is in a generally amorphous state and the second structural state in a generally crystalline solid state in the active channel region of the cell. These materials are at least bistable. The term "amorphous" is used to refer to a relatively unordered structure that is more unordered than one of the single crystals, with detectable features such as a resistance value souther than the crystalline state. The term "crystal sad" is used to refer to a relatively ordered structure that is more ordered than amorphous and therefore includes detectable features such as lower resistance than amorphous. Typically, the phase change material can be electrically switched to all detectable, distinct states between the fully crystalline state and the fully amorphous state. Other materials that are affected by changes in amorphous and crystalline states include atomic order, free electron density, and activation energy. The material can be switched to a different solid state, or can be switched to a mixture of two or more solid states, providing a gray-scale portion from amorphous to crystalline. The electrical properties of this material may also change. The phase change alloy can be switched from one phase to another by applying an electrical pulse. Previous observations indicate that a shorter, larger amplitude pulse tends to change the phase of the phase change material to a substantially amorphous state. A longer, lower amplitude pulse tends to change the phase of the phase change material to a substantially crystalline state. The energy in the shorter, larger amplitude pulse is large enough to break (the bond of the bad crystalline structure, while being short enough to prevent the atoms from re-arranging into a crystalline state. In the absence of improper experimentation, the special Appropriate pulse volume curve for a particular phase change alloy. In the subsequent part of this paper, this phase change material is referred to as GST, and we also need to understand that other types of phase change materials can be used. A material suitable for use in PCRAM is Ge2Sb2Te5. Other programmable memory materials that can be used in other embodiments of the invention include GST doped with N2, GexSby, or other materials that are converted to different resistances by different crystalline states. ; PrxCayMn03, PrSrMnO, ZrOx, TiOx, NiOx, WOx, doped SrTi03 or other materials that use electrical pulses to change the resistance state of electricity 14 200838002; or other substances that use an electrical pulse to change the resistance state; TCNQ (7, 7,8,8-tetracyanoquinodimethane), PCBM (methanofullerene 6,6-phenyl C61 -butyric acid methyl ester), TCNQ-PCBM, Cu-TCNQ, Ag-T CNQ, C60-TCNQ, TCNQ doped with other materials, or any other polymeric material including bistable or multi-stable resistance states controlled by an electrical pulse. Examples of other programmable resistive memory materials include GeSbTe, GeSb, NiO,

Nb-SrTi03, Ag-GeTe, PrxCayMn03, Zno, Nb20, Cr-SrTi03. Next, four types of resistive memory materials are briefly described. The first type is a chalcogenide material such as GexSbyTez, where x:y:z = 2:2:5, or other components X: 0 to 5; y: 0 to 5; z: 0 to 10. GeSbTe doped with nitrogen, helium, titanium or other elements can also be used. An exemplary method for forming a chalcogenide material is by PVD sputtering or Magnetron Sputtering, the reaction gas being argon, nitrogen, and/or helium at a pressure of 1 mTorr to 1 Torr. 〇mTorr. This deposition step is generally carried out at room temperature. A collimator with an aspect ratio of ^ can be used to improve its filling performance. In order to improve its filling performance, a DC bias of tens to hundreds of volts can also be used. On the other hand, it is also feasible to combine DC bias and collimator. A deposition fire treatment may be selectively performed in a vacuum or in a nitrogen atmosphere to improve the crystalline state of the chalcogenide material. The annealing treatment is typically between 1 〇 (TC to 4 〇 (^c, and the annealing time is less than Deng Bazhong.) The thickness of the sulphur chalcogenide material is as follows: the thickness of the chalcogenide It is greater than 8 nm, and the material exhibits at least a bistable resistance state. The second type is suitable for use in the giant magnetoresistance (CMR) material of the embodiment of the present invention, such as Kiss One, and its two materials = For the super^5, the composition is Υ〇·5·0·5, L, and he becomes 4 X. (M; y: W. The super giant magnetoresistance including nuclear oxide 15 200838002 Material can also be used. An exemplary method for forming a giant magnetoresistive material is a PVD , bond, a magnetron sputtering method in which the reaction gas is argon, nitrogen, oxygen, and/or helium at a pressure of 1 mTorr to 100 mTorr. The temperature can be between room temperature and 600 ° C, depending on the post-treatment conditions. A collimator with an aspect ratio of ^ 2 can be used to improve its filling performance. 'It is also possible to use DC bias voltages of tens to hundreds of volts. On the other hand, it is also feasible to combine DC bias and collimator. Can apply dozens of Gauss (Gauss to 1 Tesla buckle 31 &amp; 10,000 Gauss) =

A magnetic field to improve its magnetic crystalline state. The ruthenium can be selectively annealed in a vacuum or in a nitrogen atmosphere or in an oxygen/nitrogen, chelating environment to improve the crystalline state of the giant magnetorheological material. The annealing temperature is typically between 4 〇 (TC to 6 〇〇p and annealing time is less than 2 hours. 'The thickness of the giant magnetoresistive material is related to the design of the memory cell structure. A giant magnetoresistive material from 10 nm to 200 nm can be used as a =° core material. A YBCO (YBaCu〇3, a high-temperature superconductor material) is usually used to improve the crystalline state of a giant magnetoresistive material. This hoarding is carried out before depositing the super giant magnetoresistive material. The YBCO is chosen by you, sinking Mrrnmm. The third system is a two-element compound, such as Ni 〇.

TixOy, AlxOy, WxOy, ZnxOy, Zrx〇y, Cux〇y, etc., wherein X ', 0.5: 0.5, or other components are x: 0~1; y: 0~1. The exemplary method for forming the material is by PVD sputtering or magnetron sputtering. The material gas is argon, nitrogen, oxygen, and/or helium, and the pressure is 1 100 mTorr, and the target metal oxide is used. For example, Nix〇y, Tix〇, Α^Γ

WxOy, ZnxOy, ZrxOy, CuxOy, etc. This deposition step is generally carried out at a temperature. A collimator having an aspect ratio of 1 to 5 can be used to improve its filling and revitalization. In order to improve its filling performance, it is also possible to use a tens of tens to hundreds of volts of the straight line of the 200838002 flow bias. It is also possible to combine DC bias and collimator if necessary. A post-deposition annealing treatment may be selectively performed in a vacuum or in a nitrogen atmosphere or an oxygen/nitrogen mixed atmosphere to improve the distribution of oxygen atoms in the metal oxide. The temperature of this annealing treatment is typically between 400 ° C and 600 ° C and the annealing time is less than 2 hours. An alternative formation method utilizes PVD sputtering or magnetron sputtering, and the reaction gases are argon/oxygen, argon/nitrogen/oxygen, pure oxygen, helium/oxygen, helium/nitrogen/oxygen, etc. The pressure is from 1 mTorr to 100 f mTorr, and the metal oxide of the standard is such as Ni, Ti, Al, W, Zn.

Zr, Cu, etc. This deposition step is generally carried out at room temperature. A collimator with an aspect ratio of 1 to 5 can be used to improve its filling performance. In order to improve its filling performance, a DC bias of tens to hundreds of volts can also be used. It is also possible to combine DC bias and collimator if necessary. A post-deposition annealing treatment may be selectively performed in a vacuum or in a nitrogen atmosphere or an oxygen/nitrogen mixed atmosphere to improve the distribution of oxygen atoms in the metal oxide. The temperature of this annealing treatment is typically between 400 ° C and 600 ° C and the annealing time is less than 2 hours. Another method of formation is by oxidation using a high temperature oxidation system such as a high temperature furnace tube or a rapid thermal process (RTP). This temperature is between 200 ° C and 700 ° C and is carried out as a mixed gas of pure oxygen or nitrogen/oxygen at a pressure of several mTorr to one atmosphere. The progress can take from a few minutes to a few hours. Another oxidation process is plasma oxidation. A radio frequency or DC voltage source plasma is mixed with a pure oxygen or argon/oxygen gas mixture, or an argon/nitrogen/oxygen gas mixture, and the metal surface is oxidized at a pressure of 1 mTorr to 100 mTorr, such as Ni, Ti, A, W, Zn, Zr, Cu, and the like. This oxidation time is from a few seconds to a few minutes. The oxidation temperature is from room temperature to about 300 ° C depending on the degree of plasma oxidation. The fourth type of memory material is a polymer material, such as TCNQ doped with copper, carbon 17 200838002, silver, or the like, or a mixed polymer of PCBM and TCNQ. One method of formation utilizes thermal evaporation, electron beam evaporation, or atomic beam stray crystal system (MBE) for evaporation. A solid TCNQ and dopant pellets are co-evaporated in a single chamber. The solid state TCNQ and dopant pellets are placed in a crane or a squat or a ceramic seat. A large current or electron beam is then applied to smudge the reactants so that the materials are mixed and deposited on the wafer. No reactive chemicals or gases are used here. This deposition is carried out at a pressure of 10_4 Torr to 10_1 GTorr. The wafer temperature is between room temperature and 200 °C. A post-deposition annealing treatment may be selectively performed in a vacuum or in a nitrogen atmosphere to improve the composition distribution of the polymer material. The temperature of this annealing treatment is typically between room temperature and 300 ° C, and the annealing time is less than i hours. Another technique for forming a layer of polymer-based memory material is to use a spin coater with a doped TCNQ solution at a speed of less than 1000 rpm. After spin coating, the wafer is allowed to stand (typically at a temperature of: or below 200 ° C) for a sufficient time to solidify. This rest time can range from a few minutes to a few days, depending on the temperature and conditions. Figure 5 depicts the structure of the PCRAM memory cell. This is formed on the yttrium semiconductor substrate 2G. For example, the shallow trench isolation dielectric ^) and other isolation structures 'separate the access transistor of each of the two columns of memory cells to access the crystal, in the substrate 2G to η-type ^ 3 common source terminal, And doped with n-type region 25,27, ° ° domain ^, winter 鳊. The word lines 23, 24 may be composed of polysilicon: J is a bungee j. A dielectric fill layer (not shown) is formed at = line m scoop red: the electrically filled layer (not otherwise) is patterned&apos; thus forming a conductive one. It can be a tungsten port suitable for use in plug and wire structures. The common source line 28 contacts the doped region 26 and acts as a common source line along the column of column = 200838002. The damming structures 29, 30 are in contact with the f5-doped domains 25, 26, respectively. A dielectric fill layer (not shown), a common source line 28, and a plug base structure 29, 30 have a substantially flat upper surface suitable for forming an electrode layer 31. The electrode layer 31 includes electrode members 32, 33, 34 which are isolated from each other by an insulating member, for example, formed by a side wall process as described below, and a bottom member. In this embodiment of the structure, the base member may have a degree of η greater than the insulating members 35a, 35b and may be spaced apart to reduce the capacitive coupling effect between the ^3 common source and the line 28. For example, HI Hi 3! can have a thickness of 80 幻 40 nm, and the insulation is technically narrower. In the illustrated embodiment, the insulating member is inclined & the thin film dielectric material on the sidewalls of the electrode members 32, 34. The thickness of the surface of the tantalum layer is determined by the film thickness of the sidewall. , 37 (for example, by (2) forming a 355", the thin film viaduct 36 is formed across the insulating member 35a i such that: the memory cell 'and the thin film via 37 traverses the 遂 因而 and thus becomes a second memory cell Filling under the member 3 5: (not shown) is located on the film guides 36, 37. ' ΐί ϊΐ: Γ: ΪΓ electric filling layer is used for the post-setting process ΐ: ί Electric filling material. In the preferred embodiment, the dielectric UJ is a very good thermal insulator and tantalum insulator, and a conductive plug 38' is formed of a material such as a bridge 36. Or a layer of other conductive material, layer 4, includes a bit line in the array, and bit 4 = contacts the body 38 to the plug 38 to establish access to the cell of the thin film vial.圮 第 6'' shows a plan view of the junction 19 200838002 located above the substrate 2G as shown in FIG. Thus, the word lines 23, 24 are arranged in columns of the substantial memory cell array: the drain terminals in the +V body substrate and the electrode structure are connected to the T. Note that the material film guides 36, 37 are Located on the electrode members 32, 34, the bottom, and the insulating members 35a, 35b separate the electrode members 3, 4 of 38 into contact with the electrode members 33, ', 4 between the bridges 36, 37. The plug 3 body layer 40 A metal bit line 41 (the middle case J side. The metal bit line 42 (non-transparent) is simultaneously shown = 2) to emphasize the array layout of this structure. 曰τ in the brother 6 picture, in operation, Achieved by the signal of the memory cell of the bridge 36 to the word line 23, the word line 23 is 丄 = applied by the doped region 25, the plug 29, and the electrode member; the wire bridge 36. The electrode member 33 is via Pinned to the bit line in the body layer 40. Similarly, the pair = located in the figure _, 'by the application of the control signal to the memory of the word line 7 = 'multiple materials can be applied to the 5th and 6th The dried bismuth can be metallized by copper. Other types of bismuth: non-human ^ Shao, ^ titanium, and containing materials, etc., can be your field ^ 士 ^ ^ Ϊ Ϊ For example, if doped polysilicon or the like, it can also be used. In your 丨-, pole = ff is a vaporized titanium or nitrided surface. The metal/aluminum button' may include more than one selected from U and wave AI, tungsten,锢, aluminum, bismuth, copper, platinum, silver, stretch, and structure TM can be oxidized without;; gas; meaning more than the above group of elements: hair, titanium 5 U using other cell furnace And the array structure of 116 in Figure 7 can be configured, cell, and. In Figure 7, the common source line = 20 200838002 word line 23, and the word line 41 and The 42 series is approximately = 4 lines arranged substantially parallel to the Y axis. A 解码 axis decoder of the bit 盥 2 = axis, arranged. Therefore, in block 45, 23, 24. A sub-±wire driver in the block village is coupled to the word line and coupled to the bit line 41盥42. The 轴^ axis decoder and the set of sense amplifier systems 50, 51, 52, 53 of the terminal end. ^; The original 28 _ is connected to the access transistor to the word line 23. Accessing the gate of the Ray-Ang access transistor 50, 52 is coupled 24 . The access transistor 5 is connected to the word line channel bridge 36, and the electrode structure π is coupled to the ground by the electrode member, and the access transistor 51 is coupled to the antenna. To the electrode member 33. Similarly, the cell bridge 37 is electrically connected to the cell via the electrode member 34, and is shown in the bit line 4, which is convenient and convenient, and the electrode member is in an independent position in other embodiments. It can be understood that at the guide bridges 36, 37. The body member of the access device can be applied to the independent memory cell 42. It can be seen from the figure that 1 曰曰^2, 53 is connected to the bit line in a similar manner. One of the columns, such as the -2 v line, is shared by the two columns of memory cells, and is arranged in the y-axis direction of the display. Similarly, the two memory cells of the electrode member 33 \ two - gamma ray are shared, and one row is arranged in the X-axis direction as shown in the figure. According to an embodiment of the invention, a simplified circuit is shown. The integrated circuit 74 includes a memory array 60 that is implemented on a semiconductor substrate using the thin film fuse phase change memory cells of the present invention. A column of decoders 61 is coupled to a plurality of word line lines 62 and arranged along columns in memory array 60. A row of decoders 63 is coupled to a plurality of bit lines 64 that are arranged along the lines in memory array 60 and used to read and program the data obtained from the multi-gate memory cells in memory array 60. The address is supplied from the bus bar 65 to the row decoder 63 and the column decoder 61. The sense amplifier and data-in line in block 66 are coupled to row decoder 63 via data bus 67. The data 21 200838002 is supplied to the data input structure of the block 66 via the data input line 71 from the input/output port on the integrated circuit substrate 75 or from other internal or external data sources of the integrated circuit 75. In the embodiment, the integrated circuit includes other circuits, such as a general purpose processor or a special purpose application circuit, or is supported by a thin film fuse phase change memory cell array to provide a system on a chip. ) The integrated module of the function. The data is passed from the sense amplifier in block 66 to the input/output port of the integrated circuit 75 via the data output line 72, or to other data objects internal or external to the integrated circuit 75. In the present embodiment, one of the controllers of the biasing arrangement state machine 69 is used to control the application of the bias voltage to supply the voltage 68, such as reading, programming, erasing, erasing confirmation, and stylizing confirmation voltage. This controller can be used with conventional purpose-specific logic circuits. In an alternate embodiment, the controller includes a general purpose processor that can be applied to the same integrated circuit that executes a computer program to control the operation of the component. In yet another embodiment, the controller uses a combination of specific purpose logic circuitry and a general purpose processor. In the embodiment of the front-end (4) structure, the standard is formed as shown in Fig. 7, corresponding to the word lines, the source lines, and the access transistors in the array of Fig. 7. The doped primordial line 106 2 located in the semiconductor substrate in Fig. 9 corresponds to the doped region in the figure: the first side of the side: the ff body region 2 = the surface of the junction extending to the junction ^ in the case 4 r does not extend from the λ region 103 to the upper surface of the structure 99, or the line 106 is one of the doped regions, and the substrate J can be included in the doped region. The doped region (10) corresponds to the first access voltage η: includes a germanium including a wire 107 (which may be exemplified by a 汲 a body of a drain terminal), and a conductive cover 108 22 200838002 (exemplified by a telluride) The formed one of the word lines acts as the gate of the first access transistor. Dielectric layer 109 is located over conductor 107 and conductive cover 108. The conductive plug 110 contacts the doped region 104 and provides a conductive path to the surface of the structure 99 to contact a memory cell electrode in the following manner. The drain terminal of the second access transistor is provided by doping region 105. A word line including a wire 111 and a conductive cover (not shown) functions as a gate of the second access transistor. The conductive plug 112 contacts the doped region 105 and provides a conductive path to the upper surface of the structure 99 to contact a memory cell electrode in the following manner. The two transistor structures coupled to the plugs 110, 112, and the adjacent two transistor structures are isolated by the isolation trenches 〇1,1〇2. On the left side of the isolation trench 101, a word line including one of the wires 117 and a conductive plug 114 contacting the doped region 115 are shown. The right side of the isolation trench 102 is a conductive plug 113 including a word line of wires 118 and a contact to doped region 116. Structure 99 in Figure 9 provides a substrate for forming memory cell elements, including first and second electrodes and memory material vias, as described in more detail below. Figure 10 illustrates the next step in the process in which a thin dielectric layer 120 is formed on the upper surface of structure 99, which includes nitride or other materials. Next, a conductive electrode material layer 121 (for example, titanium nitride) is formed on the dielectric layer 120. The 11A and 11B drawings illustrate the next step of the process, in which the conductive electrode layer 121 and the dielectric layer 120 are Patterned to define electrode stacks 130, 131, 132 on the surface of structure 99. Figure 11A is a top view of the structure of Figure 11B. In one embodiment, electrode stacks 130, 131, 132 utilize masks The lithography method defines a photoresist patterning layer, followed by a conventional sizing and confirming step, followed by etching the conductive electrode layer 121 and the dielectric layer 120 to form electrode stacks 130, 131, 132, and exposed Structure 99 between stacks 130, 131, 132. Figure 12 illustrates the next step in the process by first forming a thin dielectric with 131 200838002 stacks 131, 132, 133 and sidewalls 133, 134. a layer, followed by anisotropic etching of the thin dielectric layer to remove regions between the stacks 130, 131, 132, and over the stacks 130, 131, 132, leaving over the sidewalls 133, 134 Thin film dielectric layer to shape over sidewalls 133, 134 Sidewall insulators 140, 141, 142, 143. In the embodiment of the process, the materials used to form the sidewall insulators 140, 141, 142, 143 include tantalum nitride or other dielectric materials such as dioxide, nitrogen, and nitrogen. Oxide oxide, alumina, etc. Figure 13 illustrates the next step of the process in which a second electrode material layer 150 is formed on the stacks 13, 131, 132 and the sidewall insulators 140, 141, 142, 143. The electrode material layer 15 includes titanium nitride or other suitable conductive materials, such as a nitride button, an aluminum alloy, a copper alloy, a doped polysilicon, etc. Figure 14 depicts the next step of the process, wherein Two-electrode material: 1 wall insulator 14〇, 141, 142, 143, and stack 13〇, 131132 Thunder and planarization' to define a CMP on the substrate provided by structure 99: etch and planarize Embodiments of the process, including chemical mechanical polishing (4) cultivating brush cleaning and (4) or gas cleaning procedures, are well known. The electrode layer includes insulating members 163, 164, 1 which are electrode layers in the first example, ^ iiW6G, between 162. In the illustration As shown in the implementation, the electrode "." flat upper surface. As shown in Fig. 14 on the electrode layer and the insulating members 163, 164 are exposed, the insulating members 163, 164 are made of different materials. 106 Isolation. Other exemplary structures allow 163, 164 16°^ to prevent 屺L, 枓 枓 to photoresist, and photoresist 24 200838002 stripping process. The first inlay technique begins with Figure 15A-15T. 15A-15B are diagrams showing the structure of Fig. 14 including a front stage process structure (labeled 101-107 and 1HM12), and including a first electrode member 161, a left second electrode member 160, and a right side. The electrode layer of the second electrode member is parallel to the direction perpendicular to the page, as described in detail above. According to a first embodiment of the damascene technique, a dielectric layer 500 (e.g., hafnium oxide) is formed over the electrode layer, and a cap layer 5?1 (e.g., tantalum nitride) is opened &gt; Above. The photoresist 502 is coated and patterned to define the location 503 of the trench and subsequently etched into the layers 500, 501.

A portion of the surface of the cover layer 501 is exposed at this location and is located above the insulating structures 163, 164. T In the next step depicted by the 16th-16th diagram, the layer 5〇〇盥5〇1 is etched and the photoresist 5〇2 is stripped, in the layer 5〇〇, 5〇1 Leave, 504, 505 extending to the surface of the electrode layer. / 接接, as shown in Figure 17, hh, ΙΟΰ _ 踎 你 你 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性 选择性Above 〇7. For layer lions (from the relationship of dioxane 506, I = = material layer 509. Since the hidden material layer 507 above the hidden material layer is not formed on the sidewall of the dielectric layer, the groove 5G4, 5G5. Then / two cover 7 coffin strips and fill the process to flatten the power layer 512 such as CMP on the memory material strip 508, as shown in Figure 19 to form a medium 25 200838002 20A-20B The figure illustrates the next step in which a photoresist layer is applied over the dielectric layer 512 and patterned to form a mask 52, and defines a first electrode 514, a second electrode 515, 510, and a memory material guide. The layout of the bridges 5U, 513. The dielectric layer 512, the strip of memory material 5〇8, and the second electrode members 160, 162 are etched down to the isolation structure 101, 102 according to the patterned photoresist mask 52〇 And forming a trench 51. The subsequent process is continued to fill the trench 510, forming a contact of the first electrode 514, forming a patterned conductive layer over the structure, and at the first electrode 514 and the patterned guide Contacts are formed between the lightning layers. (Figure 21 shows the beginning of an alternative mosaic technique for forming a memory material viaduct. The process begins after the formation of the front-end process structure (101-107, 110-112 in the figure), and the electrode layer includes a first electrode member 161, a left/first electrode member 16A, and a right side. a second electrode member 162, which is a strip-like structure perpendicular to the page, as detailed above. In this alternative technique, a layer of sacrificial material 450 (including polysilicon or other material deposited on the electrode layer) - as in section 22A -22B/show, a layer of photoresist is applied and patterned to define a mask 451 that is positioned to form an electrode structure from electrode members 16, 161, 162, and mask 451 defines A pattern of sacrificial blocks is formed from the sacrificial material layer 45. The mask 451 is then trimmed (eg, by isotropic etching) to form a narrow mask structure 452, as shown in Figures 23A-23B. Narrow mask structure 452 It is then used as a surname mask to define a narrow sacrificial block 453 of sacrificial material over the electrode layer, and a sidewall structure 454 is formed over the sacrificial block 453 as shown in Figure 24A-24B. 454 and sacrificial block 453 are most used as electrode layers The electrode structure has a surname mask, and the electrode layer includes the electrode member 162 and the insulating members 163, 164. The lumps 453 and the downward generation 25A-25B illustrate the use of an etch mask (by the sidewall structure) 4M is formed by the result of the counter electrode layer 26 200838002 trenches to the isolation structures 101, 102 and the electrode structure is isolated. After re-etching, the sacrificial block 453 is selectively removed, thereby leaving the sidewall structure 454 The groove. A memory material layer 460 is then formed which covers the sidewall structure 454 and fills the trenches 455 and the trenches defined by the sidewall structures 454, as shown in FIG. Next, a dielectric fill is applied by, for example, hafnium oxide or the like, covering the memory material layer 46 and filling the trench 455. This structure is then etched and planarized by means such as CMP to remove dielectric fill and portions of layer 460 on sidewall structure 454, while layer 460 is separated into individual components, including vias 461 and Memory material portion 462 in trench_f. As shown in Fig. 27, another dielectric fill 464 is applied and planarized to form a structure which can then be subjected to a via, contact plug, and metallization process, as described above. Most of the phase change memory cells known to the applicant, the tiny holes are filled with phase change material, and then 3 = the stylized current is low without the need for micro-chemical control. In addition, in the memory cell of the present invention, the memory cell of the present invention may be caused to avoid phase damage in the process of forming the upper electrode. The memory cell of the present invention includes two bottom electrodes, a spacer, and a mosaic. Phase change material guide [: Yes" is formed in the front-end process CMOS logic on the electrode layer (shape easy to support built-in memory and function ^ for a single-chip (SOC) device. Japanese film, ', mouth structure, for example The advantages of the Yao* case include that the phase change occurs in the center of the guide (4), above the dielectric spacer; the sin of the bridge is used for the vehicle. At the same time, the current used for resetting and stylizing 27200838002 In a small volume, the south current is allowed to be post-degree, and the resulting local heating requires only a low reset current level and a low reset power consumption. The structure in the embodiment of the invention allows the memory cell The two dimensions are defined by the film thickness to achieve better process control at the nanometer scale, and only one dimension of the memory cell can be defined by the damascene process. Although the invention has been described with reference to the preferred embodiments, Will be ours It is to be understood that the creation of the present invention is not limited by the detailed description thereof: 2 modes and f styles have been suggested in the previous description, and other ΠίίΞ styles will be considered by those skilled in the art. Ming: and the method, all of the members having substantially (four) ^ steps of the month, and the mouth a reach the essence of the present invention, the P1 4 sibbene is out of the spirit of the invention. The word of the mouth is not intended to fall within the scope of the present invention in the alternatives and modifications defined by the invention. The scope of the patents and the equivalents of the patents are all in the series. And the patent application and printing [simplified description of the drawing] The first picture is the green display - the second figure of the town is shown in the embodiment of the phase change / 匕 memory element. The current path in the film. Fig. 3 of the phase change memory element shows the active area of the 1st. &quot;Fig. 4 of the film guide phase change memory element in the film guide phase change memory element in the figure. Dimensions.................................................................... The top view includes the bit line. Figure 7 is a plan view of the structure. The memory array is not included with the phase change memory. 28 200838002 Figure 8 is a block diagram of an integrated circuit device, including a film phase change. The memory array and other circuits. Fig. 9 is a cross-section of a substrate including a pen path accessed by a front-end process, and is manufactured in a process in which the phase change memory device shown in Fig. 5 is virtual. The basic section of the horse base section _ Fig. 1 shows the initial steps of forming the first pole layer by the junction of the 50th. The 11A and 11B diagrams show the structure of the 1G diagram and the profile of the 1G diagram. The electrode material insulation is formed on the structure of the first step of the electric material 4± forming the side wall of the step drawing shirt. Fig. 14 is a cross-sectional view showing the step of grinding the neutron in Fig. 13. The material of the electrical material and the edge of the insulating material of the sidewall are produced by using the damascene process - the memory material 4 is shown by the use of the inlay and the memory is formed by the inlay - the third figure of the memory is shown in the third using the inlaid bridge step. The fabrication of a memory material guide 18 is illustrated in a fourth step in the use of a damascene bridge. The fabrication of a memory material guide is illustrated in the fifth step of the use of a mosaic bridge. $ Manufacturing a memory material guide 20A-20B is a sixth step in the use of a pepper guide. ~I process to create a memory material Figure 21 shows the use of a replacement lens ~ process to create a memory material 29 200838002 The first step of the material guide bridge. Figure 22A-2B illustrates a second step in the fabrication of a memory material viaduct using an alternate damascene process. Figures 23A-23B illustrate a third step in the fabrication of a memory material viaduct using an alternate damascene process. Figures 24A-24B illustrate a fourth step in the fabrication of a memory material viaduct using an alternate damascene process. 25A-25B illustrate a fifth step in the fabrication of a memory material viaduct using an alternative damascene process. Fig. 26 shows the sixth step of manufacturing a memory material &quot;material guide bridge using an alternative damascene process. Figure 27 is a diagram showing the seventh step in fabricating a memory material viaduct using an alternative damascene process. [Main component symbol description] 10 Memory cell 11 Memory material bridge 12 First electrode 12a First electrode upper surface 13 Second electrode 13a Second electrode upper surface 14 Insulating member 14a Insulating member upper surface 15 Current path 16 Active channel 20 Semiconductor Substrate 23, 24 word line 25, 27 DMD terminal 26 Common source terminal 28 Common source line 29, 30 Plug structure 31 Electrode layer 30 200838002 l 32, 33, 34 Electrode member 35a, 35b Insulating member 36, 37 Memory Material Guide 38 Conductive Plug 39 Base Member 40 Patterned Conductor Layer 41, 42 Metal Bit Line 50-53 Access Crystal 60 Memory Array 61 Column Decoder 62 Word Line 63 Line Decoder 64 Bit Line 65, 67 Bus 68 biasing supply voltage 69 biasing state machine 71 data input line 72 data output line 75 integrated circuit substrate 99 memory structure 101, 102 isolation trench 103-105 doped region 106 source line 107, 111 wire 108 conductive cover 110 -114 Conductive plug 115,116 Doped region 117 Conductor 120 Dielectric layer 31 200838002 121 Conductive Pole material layer 130-132 electrode stack 133, 134 sidewall 140-143 sidewall insulator 160-162 electrode member 163, 164 insulating member 450 sacrificial material layer 451 mask 452 narrow mask 453 sacrificial block 454 sidewall structure 455 trench 460 memory material layer 461 462 Memory material portion 500 in the trench dielectric layer 501 cap layer 504, 505 trench 506 bump portion 507 sidewall 508 memory material strip 509 memory material layer 510 trench 511, 513 memory material via 512 dielectric layer 514 first electrode 515, 516 Second electrode 520 mask 32

Claims (1)

200838002 X. Patent Application Range: 1. A method for manufacturing a memory device, comprising: forming an electrode layer having an upper surface, the electrode layer comprising a first electrode member and a second electrode member and located at the An insulating member between the first electrode member and the second electrode member, wherein the first and second electrode members and the insulating member extend to an upper surface of the electrode layer, the insulating member being located between the first and second electrode members Having a width at the upper surface; forming a trench in a film of material on the electrode layer, wherein the trench extends over the insulating member between the first and second electrode members; &quot; depositing a layer of memory Material in the trench to form a mosaic memory material block on the upper surface of the electrode layer and across the insulating member, the mosaic memory material block comprising a memory material film having a first side and a second side And contacting the first and second electrode members with the first side, the mosaic memory material block defining a first and second electrodes between the first and second electrodes and spanning the insulating member The inter-electrode path 'the inter-electrode path has a path length' which is defined by the width of the insulating member, wherein the memory material has at least two solid phases. The method of claim 1, wherein the step of forming a groove x groove comprises: forming a film of a sacrificial material on the upper surface of the electrode layer and crossing the insulating member, coating one a first residual mask over the sacrificial material film, the first etch mask defining a pattern of sacrificial blocks, the sacrificial block being formed from the sacrificial material film; trimming the first surname mask to form a trimmed a masked mask defining a narrower sacrificial block pattern; etching the sacrificial material film according to the trimmed etch mask to form the sacrificial block over the electrode layer; 33 200838002 Forming a sidewall structure over the sacrificial material block to form a second etch mask defining a first electrode and a second electrode, respectively formed from the first electrode member and the second electrode member; according to the second etch Masking and selectively etching the electrode layer and aligning with the sacrificial block to form the first and second electrodes; selectively removing the sacrificial block leaving a trench defined by the sidewall structure groove. 3. The method of claim 1, wherein the step of forming a trench comprises: forming a dielectric layer over the electrode layer; and etching the trench in the dielectric layer. 4. A method for fabricating a memory device, comprising: forming an electrode layer having an upper surface, the electrode layer comprising a first electrode member and a second electrode member, and the first and second electrode members One of the insulating members, such that the first and second electrode members and the insulating member extend to the upper surface of the electrode layer, the insulating member having a width between the first and second electrode members Forming a sacrificial material film on the upper surface of the electrode layer and across the insulating member, coating a first surname on the sacrificial material film, the first etch mask defining a sacrificial block a pattern, the sacrificial block will be formed from the sacrificial material film; the first etch mask is trimmed to form a trimmed etch mask defining a narrower pattern of the sacrificial block; Masking and etching the sacrificial material film to form the sacrificial block on the electrode layer; forming a sidewall structure over the sacrificial block to form a second etch mask 34 200838002 Defining a pattern of a first electrode and a second electrode, respectively, from the first electrode member and the second electrode member; selectively engraving the electrode layer ' according to the second surname mask and The sacrificial block is aligned to form the first and second electrodes; selectively removing the sacrificial block leaving a trench defined by the sidewall structure; depositing a layer of memory material in the trench to form a Inserting a memory material block on the upper surface of the electrode layer and across the insulating member, the mosaic memory material block comprising a memory material film having a first side and a second side, and contacting the first side to The first and second electrode members define a path between the first and second electrodes and span the inter-electrode path of the insulating member. The inter-electrode path has a path length. The path length is Defined by the width of the insulating member, wherein the memory material has at least two solid phases. 5. The method of claim 4, wherein the insulating member has a width of less than 100 nm, and the inlaid block has a thickness of less than 100 nm in a direction perpendicular to an upper surface of the electrode layer. (6) The method of claim 4, wherein the mosaic is less than 20 nm in thickness perpendicular to the surface of the electrode layer. 7. The method of claim 4, The step of forming an electrode layer includes: forming a dielectric layer on a substrate; forming a first conductive layer on the dielectric layer; etching a pattern in the first conductive layer to define a stack, The stack includes a portion of the dielectric layer and the first conductive layer, the pattern including a region between the stacks to expose the substrate, the stack having sidewalls; 35 200838002 forming a sidewall dielectric layer thereon Overlying the stack, and etching the sidewall dielectric layer to form sidewall dielectrics on the sidewalls of the stacks; forming a second conductive layer on the sidewall dielectrics, the stacks, and between the stacks Etching and planarizing the second conductive layer to define the electrode layer such that the dielectric sidewall sub-system is exposed over the upper surface and acts as the insulating member, the first of the stacks Conductive layer The sub-system is exposed to the upper surface and acts as the first electrode, and the second conductive layer portion located in the region between the stacks is exposed above the upper surface and acts as the second electrode. 8. The method of claim 7, wherein the etching and planarizing step comprises chemical mechanical polishing. 9. The method of claim 4, comprising forming the electrode layer on one of the substrates In a surface, the substrate includes a circuit for accessing a memory cell, including a contact on the surface of the substrate, and the second electrode of the electrode layer is coupled to the contact. The method of claim 4, comprising forming a pattern (the conductive layer is over the damascene block, and forming a contact between the first electrode and the patterned conductive layer. The method of claim 4, wherein the memory material comprises an alloy comprising a combination of ruthenium, ruthenium, and ruthenium. 12. The method of claim 4, wherein the memory material Including an alloy The alloy comprises a combination of two or more of the following groups: ruthenium, osmium, hoof, indium, titanium, gallium, silk, tin, copper, satiety, ship, silver, sulfur, and gold. 36 200838002 1 A method for manufacturing a memory device, comprising: forming a circuit in a substrate, the substrate having an upper surface, the circuit including an array of contacts on the upper surface of the substrate; forming an electrode layer The electrode layer has an upper surface, the electrode layer includes an array of electrode pairs, and the pair of electrodes includes corresponding first and second electrodes, and corresponding insulating members are located corresponding to the first and second Between the electrodes, wherein the second electrode contacts a corresponding contact in the array of contacts, and wherein the first and second electrodes and the insulating member extend to the upper surface of the electrode layer, and the insulating member is Having a width at the upper surface between the first and second electrodes; forming a dielectric layer on the electrode layer; etching an array of trenches in the dielectric layer; depositing a layer of memory material in the array of trenches Forming a mosaic memory material block array on the upper surface of the electrode layer, the array of mosaic memory material blocks including mosaic memory corresponding to each of the electrode pairs in the array of electrodes a block of material contacting the corresponding first and second electrodes and extending across the corresponding insulating member, the blocks of inlaid memory material comprising a memory material film having a first side and a second side, and One side contacts the corresponding first and second electrodes, and the embedded memory material blocks define an inter-electrode path between the first and second electrodes and across the insulating member, the inter-electrode path has a path a length, the path length being defined by the insulating member, wherein the memory material has at least two solid phases; and forming a patterned conductive layer over the mosaic memory material block and the first of the pair of electrode pairs An array of contacts is formed between the electrodes and the patterned conductive layer. 14. The method of claim 13, wherein the at least one insulating member of the electrode array 37 200838002 has a width of less than 50 nm, and the inlaid material block is perpendicular to the upper surface of the electrode layer. The thickness of the direction is less than 50 nm. The method of claim 13, wherein the step of forming an electrode layer comprises: forming a dielectric layer on a substrate; forming a first conductive layer thereon Overlying the dielectric layer; etching a pattern in the first conductive layer to include a stacked array comprising the dielectric layer and a portion of the first conductive layer, the pattern comprising interposed between the stacks to expose the substrate a region having sidewalls; forming a sidewall dielectric layer over the stacks; and etching the sidewall dielectric layer to form sidewall dielectrics on the sidewalls of the stack of the stacked array; forming a second Conducting a layer between the regions between the stacks, the sidewall dielectrics, and the stacks; etching and planarizing the second conductive layer to define the electrode layer such that the dielectric sidewalls Exposed on the upper surface and acting as the insulating member, the first conductive layer portion of the stack is exposed to the upper surface and acts as the first electrode, and is located in the region between the stacks The second conductive layer portion is exposed on the upper surface and functions as the second electrode. 16. The method of claim 15, wherein the etching and planarizing steps comprise chemical mechanical polishing. 17. The method of claim 13, wherein the circuit comprises a plurality of word lines, and an insulating device controlled by signals on the plurality of word lines, and the patterned conductive layer comprises a plurality of lines Bit line. 38. The method of claim 13, wherein the pair of electrodes in the pair of electrodes, including the series of electrically conductive members, including a first electrically conductive member, acts as the first of the pair of electrodes For one of the second electrodes, a second conductive member acts as a first electrode in the pair of electrodes, and a third conductive member acts as a second electrode of the second pair of the pair of electrodes. 19. The method of claim 13, wherein the memory material comprises an alloy comprising a combination of tantalum, niobium, and niobium. The method of claim 13, wherein the memory material comprises an alloy comprising a combination of two or more of the following groups: wrong, recorded, hoof, indium, titanium , gallium, grade, tin, copper, New Zealand, ship, silver, sulfur, and gold. 39