200835156 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電壓位準移位電路，特別是有 關於一種適用於高頻且低電壓之輸入信號的電壓位準移 位電路。 【先前技術】 電壓位準移位電路係將訊號在兩個不同的電壓供應 • 範圍中進行轉換，例如，電壓位準電路可以將由操作在 低電壓下之電路所產生的訊號，轉換到操作在高電壓下 之電路所需的電壓位準範圍。當需要同時使用兩個不同 • 之操作電壓位準範圍的電路時，電壓位準移位電路就會 被用來將其中一個電路產生的訊號電壓，轉換成在另一 個電路所需之操作電壓位準範圍内。 第1圖係顯示習知的電壓位準移位器10之電路圖， 習知的電壓位準移位器10可由兩個NMOS電晶體 • 103A、103B，兩個 PMOS 電晶體 104A、104B，以及三 個反相器101、102A與102B所組成，其中輸入信號SIN_ 的電壓位準低於電壓源vDD。當輸入信號SIN為可使 NMOS電晶體103A導通的高電壓時，節點X的電壓會 因NMOS電晶體103A的導通而拉低至Vss，節點X的低 電壓Vss更進一步使PMOS電晶體104B導通，將節點Y 的電壓拉高至VDD，經過兩個反相器102A與102B緩衝 後’使得輸出信號S〇ut之電壓位準拉尚至Vdd。而當輸 0773-A32708T WF;P2006061 ;alice 5 200835156 入信號SIN為無法導通NMOS電晶體103 A之低電壓時， 輸入信號SIN經過反相器101反相後，形成可使NMOS 電晶體103B導通的高電壓。NMOS電晶體103B的導通 使節點Y的電壓拉低至Vss，在經過兩個反相器102A與 102B緩衝後’使得輸出信號S〇ut.之電壓位準拉低為低電 壓 Vss。 然而當輸入信號SIN為高頻且低電壓位準範圍的信 號時，由於輸入信號的電壓位準很低，因此當NMOS電 * 晶體103A的導通時，導通的電流會很小，於是需要較多 時間將節點X的電壓拉低至vss，導致電路的反應速度 ^過慢，例如當輸入信號SIN為5MHz的主時脈信號（Master Clock，MCK)時，由於節點X的電壓變化反應時間會大於 200ns，因此節點X的電壓來不及反應主時脈信號的變 化，而使得輸出信號S0UT之電壓位準來不及改變，導致 電壓位準移位器失去作用。 因此，需要一種改良的設計使得電壓位準移位適用 於高頻且低電壓位準的輸入信號。 【發明内容】 根據本發明之一實施例，——種電壓位準移位電路， 包括一第一第一電晶體，第一第一電晶體之第一極耦接 至第一電壓源，一第一第二電晶體，第一第二電晶體之 第一極耦接至第二電壓源，並且第一第二電晶體之閘極 耦接第一第一電晶體之閘極於一第一節點，一第一第三 0773-A32708TWF;P2006061;alice 6 200835156 電晶體，耦接於第一第一電晶體與第一第二電晶體之 間，——第一開關，耦接於第一第三電晶體之閘極與第二 電壓源之間，一第二開關，耦接於第一第二電晶體與第 一第三電晶體之一第一連接點以及第一節點之間，一電 容器，耦接於一信號輸入電路與第一節點之間，一第二 第一電晶體，第二第一電晶體之第一極耦接至第一電壓 源，一第二第二電晶體，第二第二電晶體之第一極耦接 至第二電壓源，並且第二第二電晶體之閘極耦接至第二 第一電晶體之閘極於一第二節點，一第二第三電晶體， 耦接於第二第一電晶體與第二第二電晶體之間，一第三 開關，耦接於第二第三電晶體之閘極與第二電壓源之 間，一第四開關，耦接於第二第二電晶體與第二第三電 晶體之一第二連接點以及第二節點之間，一第五開關， 耦接於第二第三電晶體之閘極與第一連接點之間，一第 六開關，耦接於第一第三電晶體之閘極與第二連接點之 間，一反相器，耦接於第一節點與第二節點之間，一輸 出端，用以輸出一輸出信號，以及一第七開關，耦接於 第二連接點與輸出端之間。 根據本發明之另一實施例，一種電壓位準移位電 路，包括一第一 PMOS電晶體，第一 PMOS電晶體之源 極耦接至第一電壓源，——第一 NMOS電晶體，第一 NMOS 電晶體之源極耦接至第二電壓源，並且第一 NMOS電晶 體之閘極耦接第一 PMOS電晶體之閘極於一第一節點， 一第二PMOS電晶體，耦接於第一 PMOS電晶體與第一 0773-A32708TWF;P2006061;alice 7 200835156 NMOS電晶體之間，一第一開關，耦接於第二PMOS電 晶體之閘極與第二電壓源之間，一第二開關，耦接於第 一 NM0S電晶體與第二PM0S電晶體之一第一連接點以 及第一節點之間，一電容器，耦接於一信號輸入電路與 第一節點之間，——第三PM0S電晶體，第三PM0S電晶 體之源極耦接至第一電壓源，一第二NM0S電晶體，第 二NM0S電晶體之源極耦接至第二電壓源，並且第二 NM0S電晶體之閘極麵接至第三PM0S電晶體之閘極於 一第二節點，一第四PM0S電晶體，耦接於第三PMOS 電晶體與第二NM0S電晶體之間，一第三開關，耦接於 第四PMOS電晶體之閘極與第二電壓源之間，一第四開 關，耦接於第二NM0S電晶體與第四PMOS電晶體之一 第二連接點以及第二節點之間，一第五開關，耦接於第 四PMOS電晶體之閘極與第一連接點之間，一第六開關， 耦接於第二PMOS電晶體之閘極與第二連接點之間，一 反相器，耦接於第一節點與第二節點之間，——輸出端， 用以輸出一輸出信號’以及一第七開關’搞接於第二連 接點與輸出端之間。 【實施方式】 為使本發明之製造、操作方法、目標和優點能更明 顯易懂，下文特舉幾個較佳實施例，並配合所附圖式， 作詳細說明如下： 實施例： 0773-A32708TWF;P2006061;alice 8 200835156 第2圖係顯示根據本發明之一實施例所述之電壓位 準移位電路20，電壓位準移位電路20包括兩個NMOS 電晶體203A、203B，四個PMOS電晶體204A、204B、 205A、205B以及三個反相器101、102A、102B，其中 PMOS電晶體204A與204B之源極分別耦接至電壓源 VDD，PMOS電晶體204A之閘極耦接至節點A，PMOS 電晶體204B之閘極耦接至節點B，並且反相器101耦接 於節點A與節點B之間。NMOS電晶體203A與203B之 源極分別耦接至電壓源Vss，NMOS電晶體203 A之閘極 耦接至節點A，並且NMOS電晶體203B之閘極耦接至節 點B。PMOS電晶體205A耦接於PMOS電晶體204A與 NMOS電晶體203A之間，PMOS電晶體205B耦接於 PMOS電晶體204B與NMOS電晶體203B之間。電壓位 準移位電路20更包括複數開關，其中開關211耦接於 PMOS電晶體205A之一閘極與電壓源Vss之間，開關212 耦接於節點C與節點A之間，開關213 |馬接於PMOS電 晶體205B之一閘極與電壓源Vss之間，開關214耦接於 卽點D與郎點B之間’開關215輕接於pmqs電晶體205B 之閘極與節點C之間，開關216耦接於pmos電晶體205A 之閘極與節點D之間，開關217耦接於節點d與反相器 102A之間。第2圖中所示的電壓位準移位電路2〇更包 括電容器206以及一輸入電路21，輪入電路21具有開關 218耦接輸入信號SIN至節點E，以及開關219耦接電壓 源VREF至節點E，其中輸入信號sIN可為一交流信號源， 0773-A32708TWF;P2006061;alice 9 200835156BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage level shifting circuit, and more particularly to a voltage level shifting circuit suitable for a high frequency and low voltage input signal. [Prior Art] A voltage level shifting circuit converts a signal in two different voltage supply ranges. For example, a voltage level circuit can convert a signal generated by a circuit operated at a low voltage to operate. The range of voltage levels required for circuits at high voltages. When it is necessary to use two different operating voltage level ranges simultaneously, the voltage level shifting circuit is used to convert the signal voltage generated by one of the circuits into the operating voltage level required for the other circuit. Within the scope. 1 is a circuit diagram showing a conventional voltage level shifter 10, which can be composed of two NMOS transistors 103A, 103B, two PMOS transistors 104A, 104B, and three. The inverters 101, 102A and 102B are composed of a voltage level of the input signal SIN_ lower than the voltage source vDD. When the input signal SIN is a high voltage that can turn on the NMOS transistor 103A, the voltage of the node X is pulled down to Vss due to the conduction of the NMOS transistor 103A, and the low voltage Vss of the node X further turns on the PMOS transistor 104B. Pulling the voltage of node Y high to VDD, after buffering by two inverters 102A and 102B, 'the voltage level of the output signal S〇ut is pulled to Vdd. When the input signal SIN is inverted by the inverter 101, the input signal SIN is inverted by the inverter 101, and when the input signal SIN is inverted by the inverter 101, the input NMOS transistor 103B is turned on. high voltage. The conduction of the NMOS transistor 103B causes the voltage of the node Y to be pulled down to Vss, and after being buffered by the two inverters 102A and 102B, the voltage level of the output signal S〇ut. is pulled down to the low voltage Vss. However, when the input signal SIN is a signal of a high frequency and a low voltage level range, since the voltage level of the input signal is very low, when the NMOS electric crystal 103A is turned on, the conduction current is small, so that more is required. Time pulls the voltage of node X down to vss, causing the response speed of the circuit to be too slow. For example, when the input signal SIN is the main clock signal (Master Clock, MCK) of 5 MHz, the reaction time will be greater than the voltage change of the node X. 200 ns, so the voltage of the node X is too late to reflect the change of the main clock signal, so that the voltage level of the output signal SOUT can not be changed, resulting in the voltage level shifter losing its effect. Therefore, there is a need for an improved design that allows voltage level shifting to be applied to high frequency and low voltage level input signals. According to an embodiment of the present invention, a voltage level shifting circuit includes a first first transistor, and a first electrode of the first first transistor is coupled to the first voltage source, a first second transistor, the first electrode of the first transistor is coupled to the second voltage source, and the gate of the first second transistor is coupled to the gate of the first first transistor Node, a first third 0773-A32708TWF; P2006061; alice 6 200835156 transistor, coupled between the first first transistor and the first second transistor, the first switch, coupled to the first a second switch is coupled between the first second transistor and the first connection point of the first third transistor and the first node, and a capacitor is connected between the gate of the third transistor and the second voltage source. And coupled to a signal input circuit and the first node, a second first transistor, the first electrode of the second first transistor is coupled to the first voltage source, and the second second transistor is The first pole of the second transistor is coupled to the second voltage source, and the gate of the second transistor is coupled to a gate of the second first transistor is coupled to the second node, a second transistor is coupled between the second first transistor and the second transistor, and a third switch is coupled to the second transistor a fourth switch between the gate of the second third transistor and the second voltage source, coupled between the second connection point of the second second transistor and the second third transistor, and the second node a fifth switch coupled between the gate of the second third transistor and the first connection point, and a sixth switch coupled between the gate of the first third transistor and the second connection point An inverter is coupled between the first node and the second node, an output terminal for outputting an output signal, and a seventh switch coupled between the second connection point and the output terminal. According to another embodiment of the present invention, a voltage level shifting circuit includes a first PMOS transistor, a source of the first PMOS transistor is coupled to a first voltage source, a first NMOS transistor, The source of the NMOS transistor is coupled to the second voltage source, and the gate of the first NMOS transistor is coupled to the gate of the first PMOS transistor to a first node, and the second PMOS transistor is coupled to Between the first PMOS transistor and the first 0773-A32708TWF; P2006061; alice 7 200835156 NMOS transistor, a first switch is coupled between the gate of the second PMOS transistor and the second voltage source, a second The switch is coupled between the first connection point of the first NMOS transistor and the second PMOS transistor and the first node, and a capacitor is coupled between the signal input circuit and the first node, and the third a PM0S transistor, a source of the third PMOS transistor is coupled to the first voltage source, a second NMOS transistor, a source of the second NMOS transistor is coupled to the second voltage source, and the second NMOS transistor is The gate surface is connected to the gate of the third PM0S transistor at a second node, one The fourth PMOS transistor is coupled between the third PMOS transistor and the second NMOS transistor, and a third switch is coupled between the gate of the fourth PMOS transistor and the second voltage source, and a fourth The switch is coupled between the second connection point of the second NMOS transistor and the fourth PMOS transistor and the second node, and a fifth switch coupled to the gate of the fourth PMOS transistor and the first connection point a sixth switch is coupled between the gate of the second PMOS transistor and the second connection point, and an inverter coupled between the first node and the second node, the output end, The output signal 'and a seventh switch' are connected between the second connection point and the output end. [Embodiment] In order to make the manufacturing, the operation method, the object and the advantages of the present invention more obvious, the following detailed description of the preferred embodiments and the accompanying drawings are described in detail below. Example: 0773- A32708TWF; P2006061; alice 8 200835156 FIG. 2 shows a voltage level shifting circuit 20 according to an embodiment of the invention, the voltage level shifting circuit 20 comprising two NMOS transistors 203A, 203B, four PMOS The transistors 204A, 204B, 205A, and 205B and the three inverters 101, 102A, and 102B, wherein the sources of the PMOS transistors 204A and 204B are respectively coupled to the voltage source VDD, and the gate of the PMOS transistor 204A is coupled to the node. A, the gate of the PMOS transistor 204B is coupled to the node B, and the inverter 101 is coupled between the node A and the node B. The sources of the NMOS transistors 203A and 203B are respectively coupled to the voltage source Vss, the gate of the NMOS transistor 203 A is coupled to the node A, and the gate of the NMOS transistor 203B is coupled to the node B. The PMOS transistor 205A is coupled between the PMOS transistor 204A and the NMOS transistor 203A. The PMOS transistor 205B is coupled between the PMOS transistor 204B and the NMOS transistor 203B. The voltage level shifting circuit 20 further includes a plurality of switches, wherein the switch 211 is coupled between a gate of the PMOS transistor 205A and the voltage source Vss, and the switch 212 is coupled between the node C and the node A, and the switch 213 | Connected between one of the gates of the PMOS transistor 205B and the voltage source Vss, the switch 214 is coupled between the defect D and the point B. The switch 215 is connected between the gate of the pmqs transistor 205B and the node C. The switch 216 is coupled between the gate of the pmos transistor 205A and the node D, and the switch 217 is coupled between the node d and the inverter 102A. The voltage level shifting circuit 2 shown in FIG. 2 further includes a capacitor 206 and an input circuit 21, the wheeling circuit 21 has a switch 218 coupled to the input signal SIN to the node E, and the switch 219 is coupled to the voltage source VREF to Node E, wherein the input signal sIN can be an AC signal source, 0773-A32708TWF; P2006061; alice 9 200835156
電壓源VRE]F可為0.5倍VDD，而電容器206耦接於節點A 與節點E之間。 第2圖中所示的電壓位準移位電路20，其中開關 211、212、213、214以及219係根據控制信號Si執行切 換之動作，而開關215、216、217、218係根據控制信號 82執行切換之動作，其中控制信號Si與控制信號S2互為 反相，以控制電壓位準移位電路20操作於兩個不同的階 段。The voltage source VRE]F can be 0.5 times VDD, and the capacitor 206 is coupled between the node A and the node E. The voltage level shifting circuit 20 shown in FIG. 2, wherein the switches 211, 212, 213, 214, and 219 perform switching operations according to the control signal Si, and the switches 215, 216, 217, and 218 are based on the control signal 82. The switching action is performed in which the control signal Si and the control signal S2 are mutually inverted to control the voltage level shifting circuit 20 to operate in two different stages.
第3圖係顯示第2圖中所示之電壓位準移位電路20 的第一階段，電壓位準移位電路20的第一階段係利用控 制信號S〗將開關211、212、213、214以及219導通，而 此時開關215、216、217、218無法導通而形成開路。如 第3圖中所示，由於開關211導通，電壓源Vss使PMOS 電晶體205A導通進而將PMOS電晶體204A之汲極耦接 至NMOS電晶體203A之汲極，形成一反相器電路，其 中節點A為反相器之輸入端，節點C為反相器之輸出端。 由於開關212也導通，將反相器之輸入端與輸出端短路， 因此此輸入端與輸出端短路的反相器電路於節點A形成 一直流偏壓V INY 9 Vinv 之電壓值可介於Vdd與Vss之間’ 隨著PMOS電晶體204A與NMOS電晶體203A的尺寸比 例變化而改變。同時由於開關219導通，將電壓源VREF 輛接至節點E，因此節點A與節點E分別具有電壓值Vinv 與Vref進而於電容器206的兩端形成一跨壓（Vinv-Vref)。 第4圖係顯示第2圖中所示之電壓位準移位電路20 0773-A32708TWF;P2006061;alice 10 200835156 的第二階段，電壓位準移位電政0Λ 制信號S2將開關215、216二:=階__ 關211、212、213、214以及2 :導通，而此時開 ._ 19無法¥通而形成開路。 由於電壓位準移位電路20在第_ ^ ^ 甘乐_階段於 哭 端形成一跨壓（Vinv-Vref)，而輪 、 ' 較低的交流信號。當輸入信號 ^ 現bIN的電壓位準V為 NMOS電晶體203A導通+賢為丁使 對冋电壓時，由於雷交哭 206的兩端具有跨壓（VlNv、v 士 、 口口 REF)因此卽點A的電壓位進 可被提高至vIN+(vINV-vREF)，節 命 、 卢點C的電壓位準也合田 NMOS電晶體203A的導通而 ^也曰因 _ _ n 低至Vss。另一方面輪入 信號SIN經過反相器101反 技# 後，於郎點B形成可你 PMOS電晶體204B導通的低带 v p 使 J他甩壓，又節點C的低雷3 is a first stage of the voltage level shifting circuit 20 shown in FIG. 2, and the first stage of the voltage level shifting circuit 20 uses the control signal S to turn the switches 211, 212, 213, 214. And 219 is turned on, and at this time, the switches 215, 216, 217, 218 cannot be turned on to form an open circuit. As shown in FIG. 3, since the switch 211 is turned on, the voltage source Vss turns on the PMOS transistor 205A to couple the drain of the PMOS transistor 204A to the drain of the NMOS transistor 203A to form an inverter circuit. Node A is the input of the inverter and node C is the output of the inverter. Since the switch 212 is also turned on, the input terminal of the inverter is short-circuited with the output terminal, so the inverter circuit whose input terminal is short-circuited with the output terminal forms a DC bias voltage V INY 9 Vinv at the node A, which can be between Vdd Between and Vss' changes as the size ratio of the PMOS transistor 204A to the NMOS transistor 203A changes. At the same time, since the switch 219 is turned on, the voltage source VREF is connected to the node E, so the node A and the node E have voltage values Vinv and Vref, respectively, and form a voltage across the capacitor 206 (Vinv-Vref). 4 is a second stage of the voltage level shifting circuit 20 0773-A32708TWF; P2006061; alice 10 200835156 shown in FIG. 2, the voltage level shifting the power 0 signal S2 will be the switches 215, 216 := __ _ 211, 212, 213, 214, and 2: On, and at this time open. _ 19 can not be punctured to form an open circuit. Since the voltage level shifting circuit 20 forms a voltage across the crying end (Vinv-Vref) at the _ ^ ^ 甘乐_ stage, the wheel, 'lower AC signal. When the voltage level V of the input signal ^bIN is NMOS transistor 203A is turned on + 为 使 使 冋 冋 冋 由于 由于 由于 由于 由于 由于 由于 由于 由于 的 的 206 206 206 206 206 206 206 206 206 206 206 206 206 206 206 206 206 206 206 206 206 206 206 206 206 206 206 The voltage bit of point A can be increased to vIN+(vINV-vREF), and the voltage level of the node and the point C is also turned on by the NMOS transistor 203A, and the ___ is as low as Vss. On the other hand, after the round-in signal SIN passes through the inverter 101 anti-technique #, the low-band v p which can turn on the PMOS transistor 204B at the point B is formed, so that J is pressed, and the low-thunder of the node C
Vss更進一步使PMOS電晶體/ 一 他讀 广一 曰體2〇5B導通，將節點D的雷 壓拉南至VDD’在經過兩個反相器撤A與H)2B緩衝後， 使得輸出信號S，之電屋位準拉高至％。而當輸 號SIN為無法使NMOS電晶體2〇3 a導通的低電壓時，: 入俏號SIN經過反相态101反相後，形成可使^ 晶體203B導通的咼電壓。NM〇s電晶體2〇3B的導通^ 節點D的電壓拉低至vss，在經過兩個反相器1〇2八 102B緩衝後，使得輸出信號s〇ut之電壓位準拉低至人 曹 口口 v S s0 由於電容器206兩端的跨壓（Vinv_Vref)可將節點 的電壓位準提南，當輪入信號Sin為高頻且低電壓饭準= 圍的信號時，NMOS電晶體2〇3A的閘極電壓可透過電$Vss further turns on the PMOS transistor / one read wide 2 〇 2B 5B, and pulls the lightning pressure of node D to VDD' after being buffered by two inverters A and H) 2B, so that the output signal S, the electric house is raised to %. When the input signal SIN is a low voltage that cannot turn on the NMOS transistor 2〇3a, the in-phase SIN is inverted by the inverted state 101 to form a chirp voltage that turns on the transistor 203B. NM〇s transistor 2〇3B conduction ^ node D voltage is pulled down to vss, after buffering through two inverters 1〇2-8102B, the voltage level of the output signal s〇ut is pulled down to the human The mouth v S s0 can increase the voltage level of the node due to the voltage across the capacitor 206 (Vinv_Vref). When the wheel signal Sin is a high frequency and a low voltage meal = the surrounding signal, the NMOS transistor 2〇3A The gate voltage is permeable to electricity $
器206兩端跨壓而被提高至Vin+(Vinv_Vref)，較 I η町閘 0773-A32708TWF;P2006061 ;alice 11 200835156 極電壓可產生足夠的驅動電流，因此根據本發明之實施 例所示之電壓位準移位電路20可反應高頻且低電壓位準 範圍之輸入信號SIN的改變，將節點C的電壓迅速拉低至 Vss，並將PMOS電晶體205B導通，使得輸出信號SOUT 之電壓位準可拉高至VDD。 第5圖係顯示根據本發明之一實施例所述之電壓位 準移位器之各節點之電壓位準與信號源之波形圖，其中 輸入信號SIN為電壓位準介於0〜2V，頻率為5MHz的主 鲁 時脈信號，RST為一控制信號，用以重置電容器206，以 避免電容器206的滲漏（leakage)現象影響電壓位準移位 電路20的運作，VREF為一 0.8V的直流信號◦待電路重 置完成，節點A的電壓位準開始隨著輸入信號SIN的變 化而改變，由於節點A具有電壓Vin+(Vinv-Vref)，節點 A的電壓可被提高至1.2V〜3.2V，足以反應主時脈信號的 快速變化’因此輸出信號S〇ut可輸出相對應之電壓位準 移位結果。 — 本發明雖以較佳實施例揭露如上，然其並非用以限 定本發明的範圍，任何熟習此項技藝者，在不脫離本發 明之精神和範圍内，當可做些許的更動與潤飾，因此本 發明之保護範圍當視後附之申請專利範圍所界定者為 準0 【圖式簡單說明】 第1圖係顯示一電壓位準移位器電路圖。 0773-A32708TWF;P2006061 ;alice 12 200835156 第2圖係顯示根據本發明之一實施例所述之電壓位 準移位器電路圖。 第3圖係顯示根據本發明之一實施例所述之電壓位 準移位器電路圖之第一階段。 第4圖係顯示根據本發明之一實施例所述之電壓位 準移位器電路圖之第二階段。 第5圖係顯示根據本發明之一實施例所述之電壓位 準移位器之各節點之電壓位準與信號源之波形圖。 【主要元件符號說明】 10、20〜電壓位準移位器； 21〜輸入電路； 101、102A、102B〜反相器； 103A、103B、203A、203B〜NMOS 電晶體； 104A、104B、204A、204B、205A、205B〜PMOS 電 晶體； • 211 、 212 、 213 、 214 、 215 、 216 、 217 、 218 、 219〜 開關； A、B、C、D、E、X、Y〜節點； RST、Si、S2〜控制信號； S IN〜輸入信號， S〇UT〜輸出信號； V〇d、Vss、Vref〜電壓源·’The device 206 is raised across the pressure to Vin+(Vinv_Vref), which is more than I η 闸 0773-A32708TWF; P2006061; alice 11 200835156 The extreme voltage can generate sufficient driving current, so the voltage level according to the embodiment of the present invention The quasi-shift circuit 20 can reflect the change of the input signal SIN of the high frequency and low voltage level range, rapidly lower the voltage of the node C to Vss, and turn on the PMOS transistor 205B, so that the voltage level of the output signal SOUT can be Pull up to VDD. 5 is a waveform diagram showing voltage levels and signal sources of respective nodes of a voltage level shifter according to an embodiment of the present invention, wherein the input signal SIN is a voltage level between 0 and 2 V, and the frequency is For the 5MHz main Lu clock signal, RST is a control signal for resetting the capacitor 206 to prevent the leakage phenomenon of the capacitor 206 from affecting the operation of the voltage level shifting circuit 20, and the VREF is a 0.8V. The DC signal needs to be reset by the circuit, and the voltage level of the node A starts to change with the change of the input signal SIN. Since the node A has the voltage Vin+(Vinv-Vref), the voltage of the node A can be raised to 1.2V~3.2. V, sufficient to reflect the rapid change of the main clock signal' so the output signal S〇ut can output the corresponding voltage level shift result. The present invention is disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any modifications and refinements may be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is defined as defined in the appended claims. [Simplified Schematic] FIG. 1 shows a circuit diagram of a voltage level shifter. 0773-A32708TWF; P2006061; alice 12 200835156 FIG. 2 is a circuit diagram showing a voltage level shifter according to an embodiment of the present invention. Figure 3 is a diagram showing the first stage of a circuit diagram of a voltage level shifter in accordance with an embodiment of the present invention. Figure 4 is a diagram showing the second stage of the circuit diagram of the voltage level shifter in accordance with an embodiment of the present invention. Figure 5 is a waveform diagram showing voltage levels and signal sources of respective nodes of a voltage level shifter according to an embodiment of the present invention. [Major component symbol description] 10, 20~ voltage level shifter; 21~ input circuit; 101, 102A, 102B~ inverter; 103A, 103B, 203A, 203B~ NMOS transistor; 104A, 104B, 204A, 204B, 205A, 205B to PMOS transistors; • 211, 212, 213, 214, 215, 216, 217, 218, 219~ switches; A, B, C, D, E, X, Y~ nodes; RST, Si , S2 ~ control signal; S IN ~ input signal, S 〇 UT ~ output signal; V 〇 d, Vss, Vref ~ voltage source · '
ViN、ViNV〜電壓。 0773-A32708TWF;P2006061 ;alice 13ViN, ViNV ~ voltage. 0773-A32708TWF; P2006061; alice 13