TW200834332A - System including bus matrix - Google Patents

System including bus matrix

Info

Publication number
TW200834332A
TW200834332A TW097105024A TW97105024A TW200834332A TW 200834332 A TW200834332 A TW 200834332A TW 097105024 A TW097105024 A TW 097105024A TW 97105024 A TW97105024 A TW 97105024A TW 200834332 A TW200834332 A TW 200834332A
Authority
TW
Taiwan
Prior art keywords
bus matrix
system including
bus
including bus
matrix
Prior art date
Application number
TW097105024A
Other languages
English (en)
Inventor
Jae-Shin Lee
Jin-Kwon Park
Cheon-Su Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200834332A publication Critical patent/TW200834332A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW097105024A 2007-02-13 2008-02-13 System including bus matrix TW200834332A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070014971A KR100854973B1 (ko) 2007-02-13 2007-02-13 버스 매트릭스를 포함하는 시스템

Publications (1)

Publication Number Publication Date
TW200834332A true TW200834332A (en) 2008-08-16

Family

ID=39733940

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097105024A TW200834332A (en) 2007-02-13 2008-02-13 System including bus matrix

Country Status (4)

Country Link
US (1) US20080215781A1 (zh)
JP (1) JP2008198209A (zh)
KR (1) KR100854973B1 (zh)
TW (1) TW200834332A (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101853237B (zh) * 2010-05-31 2012-07-04 华为技术有限公司 片上系统及axi总线下的传输方法
US9043634B2 (en) 2011-04-29 2015-05-26 Qualcomm Incorporated Methods, systems, apparatuses, and computer-readable media for waking a SLIMbus without toggle signal
US9065674B2 (en) * 2011-04-29 2015-06-23 Qualcomm Incorporated Multiple slimbus controllers for slimbus components
US8583844B2 (en) 2011-05-31 2013-11-12 Lsi Corporation System and method for optimizing slave transaction ID width based on sparse connection in multilayer multilevel interconnect system-on-chip architecture
JP5865067B2 (ja) * 2011-12-26 2016-02-17 キヤノン株式会社 データ転送装置及びデータ転送方法
CN105677605B (zh) * 2014-11-20 2019-04-30 深圳市中兴微电子技术有限公司 一种高效的可配置片上互联系统及其实现方法、装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6836839B2 (en) * 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7096439B2 (en) * 2003-05-21 2006-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for performing intellectual property merge
CN1771482A (zh) * 2003-05-27 2006-05-10 皇家飞利浦电子股份有限公司 访问保护的总线系统
JP4193746B2 (ja) * 2004-04-13 2008-12-10 沖電気工業株式会社 マトリックス状バス接続システム
US7602777B2 (en) * 2004-12-17 2009-10-13 Michael Ho Cascaded connection matrices in a distributed cross-connection system
JP2006195746A (ja) * 2005-01-13 2006-07-27 Oki Electric Ind Co Ltd マルチレイヤバスシステム
US7246188B2 (en) * 2005-02-10 2007-07-17 Qualcomm Incorporated Flow control method to improve bus utilization in a system-on-a-chip integrated circuit
KR100762264B1 (ko) * 2005-06-14 2007-10-01 충남대학교산학협력단 지연 시간을 감소시키는 버스 매트릭스 구조
US7661006B2 (en) * 2007-01-09 2010-02-09 International Business Machines Corporation Method and apparatus for self-healing symmetric multi-processor system interconnects
US7743186B2 (en) * 2007-04-27 2010-06-22 Atmel Corporation Serialization of data for communication with different-protocol slave in multi-chip bus implementation
US7689758B2 (en) * 2007-07-12 2010-03-30 Atmel Corporation Dual bus matrix architecture for micro-controllers
JP2009294744A (ja) * 2008-06-03 2009-12-17 Nec Electronics Corp バスインターフェース設計装置、バスインターフェース設計方法、及びプログラム

Also Published As

Publication number Publication date
KR20080075705A (ko) 2008-08-19
KR100854973B1 (ko) 2008-08-28
US20080215781A1 (en) 2008-09-04
JP2008198209A (ja) 2008-08-28

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