200830813 九、發明說明： 【發明所屬之技術領域】 本發明係’-種通訊裝置，尤指―種以序煎料傳送的通訊 裝置與其相關方法。 【先前技術】 在習知技術的網路通訊系統當中，實體鍊接層（physicallink hyer，以下簡稱PHY層）與媒體存取控制層（medium此霞c她& layer ’以下簡稱MAC層）之_ f料傳輸是以平行傳輸的方式， 且透過特定的通訊協定（protocol)進行，舉例來說，「媒體獨立介 面」（mediaindependentiitoface’Mn)以及「簡化媒體獨立介面」 (reducedMH，_)就是其使用之傳輸介面的兩個例子。若ρΗγ 層與MAC是以不同的⑼分舰行實施，則代表勤者晶片需要 使用到大量的電路接腳（pin)’若ΡΗγ層與祖〇層是在同一網 •路控制晶片内，則該晶片内有關於1>11¥層與祖(：層兩者之大量 走線(layout)會較為複雜，進而可能影響到該晶片之尺寸以及其效 能。 ’、 然而隨著網路技術的快速進步，現今網路所使用的速度也越來 . 越高，在具有數十億位元（multi-gigabit)頻寬的網路系統中，不 • 使用疋「十億位元媒體獨立介面」（gigabit Mil，GMII)或是「簡 化十彳思位元媒體獨立介面」（reducedGMII，Rgmii)，作為phy 7 200830813 層與層之_平行傳輸介面，可能會使叫 腳’在祕成本財量以及'她發展性財量之下，太多的電路 接腳並非疋系統設計者所樂見的情形。 【發明内容】 ’在於提供—種細相t料傳送的 因此本發明的目的之一 通訊裝置與其相關方法。 依據本發明之一實施例，JLiSyiit 置包含有-第-處理2用ft供了一種通訊裝置。該通訊裝 產生一第一平行資料；一平行轉應一第一網路層之資料以 列資料;4二處Z路所輸出之該第-平行資料產生-序 轉相單元:Γ 平行轉相單元，时對該平行 接於該傳輸介^，=5=傳輪；—序列轉平行單元，粞 • 一第二平行資料；以及一第傳輸之該序列資料轉換為 料以輸出對應一第二網路層之資料；第二平行資 係與該第一、該第二處理電路之操作頻率面之傳輸頻率 依據本發明之一實施例，1 置包含有-第-處理電路，料城置。該通訊裝 產生-第-平行俩·一f处里對應一弟一網路層之資料以 路’用來依據該第二處理電第1於該第-處理電 丨询饵之該4 一平行資料產生一序 200830813 用來對該平行 =單:：介*，·接於該平行轉序列單元， 接，該傳輪相’縣频雜介面所傳 一第二平行資料；以及一第 “…一疋雌之序列m進行傳輪；—序列轉平行單元，搞 料以輸出對應一第二網路声^ 二處理電路之操作頻率係^目同，。4，、、中該弟—處理電路與該第 輸之該序列資料轉換為 •處理電路，用來處理該第二平行資 明之—實施例，其提供了—種通訊方法。該通訊方 將St理對應一第一網路層之資料以產生-第-平行資料; U一平仃純序列化，以產生—糊資料；藉由—傳輸介面 以傳輸該序列資料；接收該序列資料，並將該序列資料平行化以 產生-第二平行資料；以及處理該第二平行資料以輸出對應一第 二網路層之資料；其巾’傳輸該相#料之傳輸辭與處理該第 一網路層資料、該第二平行資料之操作頻率不相同。 以 鲁 絲本發狀-實細，其提供了 _麵财法。該通訊方 法包含有處理對應一第一網路層之資料以產生一第一平行資料； 將該第一平行資料序列化，以產生一序列資料；藉由一傳輸介面 以傳輸該序列資料；接收該序列資料，並將該序列資料平行化以 產生一第二平行資料；以及處理該第二平行資料以輸出對應一第 二網路層之資料；其中該第一網路層與該第二網路層係對應至相 同層級之網路層。 9 200830813 【實施方式】 請參考第1圖，第1圖所示係為本發明通訊裝置1〇〇之一實 施例的示意圖。通訊裝置1〇〇包含有一第一網路端12〇與一第二 網路端140，本實施例中，第一網路端12〇包含有一第一處理電路 (亦即第一媒體存取控制(Media Access Control，MAC)電路101a)、 一第一處理電路(亦即第二媒體存取控制電路102a)、一平行轉序 列單元(亦即串化器（serializer) l〇3a)、一序列轉平行單元(亦即解 _ 串化器（De-serializer) 104a)、一編碼電路i〇5a、一解碼電路l〇6a、 一合併單元l〇7a以及一解合併單元i〇8a ;另一方面，第二網路端 140包含有一第一媒體存取控制電路1〇lb、一第二媒體存取控制 電路102b、一串化器l〇3b、一解串化器l〇4b、一編碼電路l〇5b、 一解碼電路l〇6b、一合併單元l〇7b以及一解合併單元l〇8b。 於第一網路端120中，第一媒體存取控制電路101a用來處理 對應一第一網路層（在此實施例中，第一網路層係為MAC層）之 _ 資料DATAla以產生一第一平行資料Spla以及用來依據一第一解碼 後平行資料Sdlj理對應該第一網路層之資料DATAla ;第二媒體 存取控制電路102a用來依據一第二解碼後平行資料心七處理對應 該該第一網路層之資料D ATA2 a以及用來處理對應該第一網路層 之資料DATA2aU產生一第二平行資料Spa;串化器i〇3a用來依據 第一媒體存取控制電路l〇la與第二媒體存取控制電路102a所輸 出之第一平行資料Spla及第二平行資料Spa轉換為一序列資料 D〇uu ;接著，序列資料Doutl係透過一介面，該介面可以為一光纖 200830813 網路、乙太網路或是晶片中之金屬導I等，將資料傳送至第二 網路端14G;解串化n驗用來將串化器職所輪出之—序列次 料Dout2轉換為一第二平行資料s咖；編碼電路嶋用來編一 平行資料Spla及第二平行資料^以分別產生一第一編媽後平行 資料Sela及-第二編碼後平行資料‘，依據一實施例，編碼電路 腕係可為-擾頻編碼（Scramble)電路，對所接收到之平行資料 進2擾頻編碼’接著，串化H職係依據第—編碼後平行資料、$ 及第二編碼後平行資料U生為序職料;解碼電路1〇^ 用來依據第二平行貧料&分別產生第一解碼後平行資料^及 第二解碼後平行資料I，依據—實施例，解碼電路職係^為 -擾頻解j (De_seramble)料，對雌收狀平行賴進行擾‘ 、為碼接著，合併單元職用來合併編碼電路贿所輸出之第 ,、、扁碼後平仃貪料ha及第二編碼後平行資料&以產生一合併後 平行資料Sma，其巾料謂a雜合併後平行資料&轉序 1料L;解合料元驗聽鱗红平时料Sp3a以產生 第-分解後平行資料Ssla與一第二分解後平行資料、，其中解 碼=06a係分別解瑪第一、第二分解後平行資料^以分 另，生弟一解石馬後平行資料U與第二解石馬後平行資料Sd2a。 ，外，於第二網路端14〇 +，第一媒體存取控制電路咖 :來處:對應一第二網路層(在此實施例中，第二網路層係為 MAC層）之資料請^以產生一第一 據-第-解賴I—. 貝料Splb以及用來依 平行貨料Sdlb處理對應該第二網路層之資料 11 200830813 DATAlb;第二媒體存取控制電路102b用來依據一第二解碼後平杆 資料Sd2b處理對應該該第二網路層之資料data%以及用來處理對 應該第二網路層之資料DATAm以產生一第二和亍資料Sp2b ;串化 器103b用來依據第一媒體存取控制電路1〇lb與第二媒體存取控 制電路腿所輸出之第一平行資料Splb及第二平行資料Sp2b產生 序列資料;解串化器i〇4b用來將串化器1〇3a所輸出之一序 列貧料DOTtl轉換為一第三平行資料s娜；編碼電路1〇%用來編碼 φ第一平行資料S帥及第二平行資料SpZb以分別產生一第一編碼後 平行資料Selb及一第二編碼後平行資料Sezb，其中串化器1〇北係 依據第-編碼後平行資料Selb及第二編碼後平行資料s必產生為 序列資料;解碼電路1〇6b用來依據第三平行資料s卿分別產 生第-解碼後平行資料Sdlb及第二解碼後平行資料合併單元 107b用來合併編碼電路1〇5b所輸出之第一編碼後平行資料“ 及第二編碼後平行資料Se2b以產生—合併後平行資料、，其中串 化器103b係將合併後平行龍‘轉換為序列聽d⑽2;解合併 •單元108b用來分解第三平行資料^以產生一第一分解後平行資 料Sslb與-第二分解後平行資料^，其中解碼電路祕係分別 解碼第-、第二分解後平行㈣—以分難生第一解碼後 平行資料sdlb與第二解碼後平行資料Sd此。 • #第一網路端12G之舰存取控制電路1_和1()2a要對第 二網路端14(3之媒體存取控制電路lGlb和獅傳送第一 8咖以 及第二平行資料Sp2a時，在本實施例中，第一平行資料Sp ^及第 12 200830813 二平行資料sp2a的輪出形式均為難並行的輸 而且^^丁赠Spla會與—雜CLKi(125Mh綱步，如第2 所不’第2圖係第！圖所示之通訊裝置1〇〇中平行資料$ =後二資料sela、Se2a以及合併後平行資料、_^^ 田平订貝料spla、、輸入至編碼電路105a後，編碼電路腕 會編碼出編碼後平行資料Sel、Se2a，其輸出形式亦為10個並行的 輸出資料’每-個輸出資料的位元率係125百萬位元/秒，且平行 貢料Spla、se2a會與-時脈CLK2(125MHz)同步(如第2圖所示)。在 本發明中’編碼電路105a係用來對平行資料s咖、提供盆傳 輸所必需的資訊，例如’進行加密的動作、進行資料擾動/、 (SCrambling)來編碼出可容忍_料亂度以防止直流平衝(DC 脑㈣的現象、提供控制資淑改善資料在另一端被正確接收的 能力等等。接著，編碼後平行資料&、^會同時輸入合併單元 _以合似生-合錢精資料、，而合併縣辟料‘的 輸出形式係以1G個並行的資料被輸出，因此合併後平行資料8 包含了媒體存取控制電路1Gla和職所輸㈣#訊。可以得知服 合併後平行資料s·之每-個輸出f料的位元率係25()百萬位元/ 秒’即每一筆資料的週期為4ns’而且合併後平行資料、會與一 時脈CLK3(250MHZ)同步(如第2圖所示）。接著，合併後平行資料 S咖會輸人串化||脑以便將合併後平行:#料8⑽串化成一高頻的 序列資料Doutl。因此’輸出的序列資料I的位元率係25憶位 元/秒，即每一筆資料的週期為〇 4ns。 13 200830813 • 明參閱第二圖，第三圖為串化器l〇3a之一實施例，該串化 l〇3a包含電流單元3〇2、電晶體單元撕及負載單元3〇6，其 :負，單对由電阻R所實施。如圖所示，當串化器職藉由電 日日體單元304接收由合併單元斯續輸出的平行資料I後，平 行資料Sma將決定電晶體b〇〜的導通與否，使得電流單元中之 電流會透過被導通之電晶體流經至電阻R上，並產生—相對應於 ⑩平行貝料5咖之輸出電壓Vout，此輸出電壓v〇ut即代表序列資料 ’接著，再透過一傳輸介面將此序列龍〇。如之減傳送至 第二網路端140。請注意，在本發明之實施例通訊裝置励中之第 -網路端140亦包含有一同步控制器(未顯示)祕於該解串化器 l〇4b用來產生一日守脈控訊號至該解串化器⑴扑以同步該解串 化裔104b所接收到的序列資料D〇uti之訊號。 本發明之第一網路端12〇及第二網路端14〇並不侷限於上述 鲁MAC層的應用，亦可以是ΡΗγ層或者是祖〇層與ρκγ層的任 意組合，換句話說，第一媒體存取控制電路1〇la、1〇lb和第二媒 體存取控㈣路H)2a、獅便絲舰裝置勘的_而以實體 鍊接電路來加以取代，舉例來說，於本發明另一實施例巾，第一 媒體存取控制電路101a、102b和第二媒體存取控制電路i〇2a、i〇2b 均以實體鍊接電路來取代以處理兩ΡΗγ層之間的資料傳送；於本 發明另一實施例中，第一媒體存取控制電路1〇1&與第二媒體存取 控制電路102a均以實體鍊接電路來取代，麟，通訊震置_便 200830813 處理PHY層與mac層之間的資料傳送。不僅如此，本發明之第 一網路端120及第二網路端14〇係可操作於不同頻率之下，例如， 第-網路端120係操作於1〇〇 Mhz，而第二網路端14〇係操作於 1000MHz，再透過串化器將資料利用序列的方式於一傳輸介面上 進行傳送。 另一方面，當第一網路端120及第二網路端14〇係設置於不 _ 门的ro片上時，序列>料〇。饥1、Dout2可以透過光纖網路來進行長 距離傳輸，例如，將第1圖所示之實施例中的序列資料D。如、 透過光纖網路在串化器l〇3a以及解串化器104b、串化器1〇31)以 及解串化器104a之間傳送。不僅如此，當本發明之第一網路端12〇 及第二網路端14〇是應用於PHY層時，其網路層之資料DATAia、 DATA2a'DATAlb、DATA2b係可透過光纖網路或雙絞線(Twisted-pair cable)來傳送，因此，本發明之另一實施例為將第丨圖所示之實施 例的第一網路端120及第二網路端140應用於PHY層，且網路層 • 之資料DATAia、DATA2a、DATAib、DATA2b以雙絞線來傳送；本 發明之另一實施例為將第1圖所示之實施例的第一網路端12〇及 第二網路端140應用於以PHY層，網路層之資料DATAla、 DATA%、DATAlb、DATA2b以雙絞線來傳送，但序列資料DQUtl、 Drat2t則透過光纖網路來傳輸；本發明之另一實施例為將第〗圖所 示之實施例的第一網路端120及第二網路端140應用於PHY層， 且網路層之資料DATAla、DATA2a、DATAlb、DATA2b以光纖網路 來傳送，但序列資料D。^、則透過光纖網路來傳輸；本發明 15 200830813 '之另一實施例為將帛1圖所示之實施例的第一網路端m及第二 *網路端140應用於PHY層，且網路層之資料DATAia、DATA2a、 mTAlb、DATA2b以先_路來傳送。另外，#第—網路端^及 第二網路端14G係設置於相_晶壯時，相資飢此、％ ，可以透過晶片中金屬線來進行傳輸。請注意，熟習此項技藝者 經由上述教導所推導出的任何可行變化均屬本發明之範缚。 π參考第4圖’第4圖所示係本發鴨訊方法之-實施例的 流程圖。騎訊方法以第1圖所示之通訊裝置100來加以實施， 其運作簡單歸納如下： 步驟402 :傳送第-平行資料V以及第二平行資料sp2a; 步驟4G4 :編碼第—平行資料‘以及第二平行資料s仙以產 生第一編碼後平行資料Sela和第二編碼後平行資料 se2a; .步驟4〇6 :合併f _編錢平行資料、和帛二編碼後平行資 料Se2a以產生合併後平行資料; 步驟4〇8:串化合併後平行資料sma以產生序列資料D〇utl進行 傳送； ’驟彻·接收並解串化資料D_以產生第三平行資料s卿； 乂驟412、解合併第二平行資料8卿以產生第一分解後平行資 料sslb與一第二分解後平行資料&2b ;以及 步驟414 ·解碼第一分解後平行資料Sslb與-第二分解後平行 200830813 • 資料Ss2b以產生第一解碼後平行資料sdlb及第二解 - 碼後平行資料sd2b。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 ^ ，1圖為本發明通訊裝置之一實施例的示意圖。 第2圖為第1圖所示之第_平行資料、第二平行資料、第一編瑪 後平行資料、第二編碼後平行資料、合併後平行資料以及序 列資料的傳送時序圖。 第3圖為串化器之一實施例的示意圖。 第4圖為本發明通訊方法之一實施例的流程圖。 【主要元件符號說明】 100 ~-- 通訊裝置 101a > 101b 第一媒體存取控制電路 102a > 102b ^ 第二媒體存取控制電路 103a、103b 串化器 104a、104b 解串化器 105a、105b 編碼電路 106a、106b 解碼電路 107a、107b 合併單元 17 200830813 108a、108b 解合併單元 302 電流單元 304 電晶體單元 306 負載單元200830813 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a communication device, and more particularly to a communication device for transmitting a decocted material and a related method thereof. [Prior Art] Among the network communication systems of the prior art, the physical link layer (physical link hyer, hereinafter referred to as PHY layer) and the medium access control layer (medium this c- & layer 'hereinafter referred to as the MAC layer) _ f material transmission is a parallel transmission, and through a specific protocol, for example, "media independentii" (mediaindependentiitoface'Mn) and "simplified media independent interface" (reducedMH, _) is its Two examples of the transport interface used. If the ρΗγ layer and the MAC are implemented in different (9) sub-ships, it means that a large number of circuit pins are needed for the worker's chip. If the ΡΗ γ layer and the ancestor layer are in the same network control chip, then There are a lot of layouts between the 1>11 layer and the ancestor (the layer) in the chip, which may affect the size of the chip and its performance. ', However, with the rapid development of network technology Progress, the speed of today's networks is also increasing. The higher the network system with multi-gigabit bandwidth, the more than one billion-bit media independent interface ( Gigabit Mil, GMII) or "Simplified Tencent Space Media Independent Interface" (reducedGMII, Rgmii), as the physical parallel interface of phy 7 200830813 layer and layer, may make the foot 'in secret cost and ' Under her developmental financial resources, too many circuit pins are not the case that the system designer would like to see. [Summary of the Invention] [In view of providing a fine-phase material transfer, the communication device of the present invention is Related methods. According to this issue In one embodiment, the JLiSyiit includes a -the-process 2 for providing a communication device with a ft. The communication device generates a first parallel data; a parallel translation of a data of the first network layer to list data; The first-parallel data output-sequence phase-transfer unit outputted by the Z-way: 平行 parallel phase-shifting unit, when the parallel connection is connected to the transmission medium, =5=transmission wheel; - sequence to parallel unit, 粞• a second parallel data; and a sequence of the transmitted data converted into a material to output data corresponding to a second network layer; a transmission frequency of the second parallel stream and the operating frequency plane of the first and second processing circuits According to an embodiment of the present invention, a device includes a -th processing circuit, and the data is generated. The communication device generates a data corresponding to a network layer of the first-parallel and a f-channels. According to the second processing power, the fourth parallel data generation order 200830813 is used to connect the parallel/sequence unit to the parallel rotation sequence unit, The second phase of the pass-through phase of the county's frequency interface; and a first "... The sequence of the females is carried out by the sequence m; the sequence is transferred to the parallel unit, and the output is output to correspond to a second network sound. The operating frequency of the circuit is the same as that of the processing circuit. 4, , , the middle of the brother - the processing circuit and The sequence data of the first input is converted into a processing circuit for processing the second parallel asset-implementation, which provides a communication method. The communication party associates the data of the first network layer with Generating-parallel data; U-level is purely serialized to generate-paste data; the transmission data is transmitted by the transmission interface; the sequence data is received, and the sequence data is parallelized to generate - second parallel data And processing the second parallel data to output data corresponding to a second network layer; the towel transmitting the phase of the transmission message and processing the first network layer data, the second parallel data operating frequency is not the same. In the form of Lussian hair-solid, it provides the _ face money method. The communication method includes processing data corresponding to a first network layer to generate a first parallel data; serializing the first parallel data to generate a sequence of data; transmitting the sequence data through a transmission interface; receiving The sequence data is parallelized to generate a second parallel data; and the second parallel data is processed to output data corresponding to a second network layer; wherein the first network layer and the second network The road layer corresponds to the network layer of the same level. 9 200830813 [Embodiment] Please refer to Fig. 1, which is a schematic view showing an embodiment of a communication device 1 of the present invention. The communication device 1 includes a first network terminal 12 and a second network terminal 140. In this embodiment, the first network terminal 12 includes a first processing circuit (ie, the first media access control). (Media Access Control, MAC) circuit 101a), a first processing circuit (ie, second medium access control circuit 102a), a parallel sequence unit (ie, serializer), a sequence a parallel parallel unit (ie, a de-serializer 104a), an encoding circuit i〇5a, a decoding circuit 16a, a merging unit 〇7a, and a de-merging unit i 〇 8a; In one aspect, the second network end 140 includes a first media access control circuit 1 lb, a second media access control circuit 102b, a serializer l 〇 3b, a deserializer l 〇 4b, and an encoding. The circuit l〇5b, a decoding circuit 16b, a merging unit 〇7b, and a de-merging unit 〇8b. In the first network end 120, the first media access control circuit 101a is configured to process a data DATAla corresponding to a first network layer (in this embodiment, the first network layer is a MAC layer) to generate a first parallel data Spla and a data DATAla corresponding to the first network layer according to a first decoded parallel data Sdlj; the second media access control circuit 102a is configured to use a second decoded parallel data heart seven Processing a data D ATA2 a corresponding to the first network layer and a second parallel data spa for processing the data DATA2aU corresponding to the first network layer; the serializer i 〇 3a is used for accessing according to the first medium The first parallel data Spla and the second parallel data Spa outputted by the control circuit 101a and the second media access control circuit 102a are converted into a sequence of data D〇uu; then, the sequence data Doutl is transmitted through an interface, and the interface can Data is transmitted to the second network end 14G for a fiber optic 200830813 network, Ethernet or metal conduction in the chip; the deserialization test is used to rotate the serializer's office-sequence The secondary material Dout2 is converted into a second parallel data s coffee; The encoding circuit is configured to compile a parallel data Spla and a second parallel data to generate a first parallel data Sela and a second encoded parallel data respectively. According to an embodiment, the encoding circuit wristband can be - Scrambling circuit (Scramble) circuit, the scrambling code is input to the parallel data received. Then, the serialized H grade is based on the first-coded parallel data, and the second encoded parallel data U is used as the sequence material. The decoding circuit 1 〇 ^ is used to generate the first decoded parallel data and the second decoded parallel data I according to the second parallel poor material & respectively, according to the embodiment, the decoding circuit grade ^ is - scrambling solution (De_seramble), the female parallelism is disturbed', the code is followed, the merged unit is used to merge the output of the coded circuit bribe, the flat code is flat and the second coded parallel data & to produce a combined parallel data Sma, the towel material is said to be a mixed and parallel data & 1 sequence L; the decomposed element check the scaly red flat material Sp3a to produce the first-decomposed parallel data Ssla and Parallel data after a second decomposition, where decoding = 06a Do Ma first solution, the second parallel data decomposition ^ In the other points, a brother calcite raw data Ma Houping U row and the second row data Ma Houping calcite Sd2a. And at the second network end 14〇+, the first media access control circuit: the corresponding: corresponding to a second network layer (in this embodiment, the second network layer is the MAC layer) The data is requested to generate a first data-first-relief I-. The bedding material Splb and the data for processing the second network layer according to the parallel material Sdlb 11 200830813 DATAlb; the second medium access control circuit 102b The data data% corresponding to the second network layer and the data DATAm corresponding to the second network layer are processed according to a second decoded flat data Sd2b to generate a second sum data Sp2b; The decoder 103b is configured to generate sequence data according to the first parallel data Splb and the second parallel data Sp2b output by the first media access control circuit 1〇1b and the second media access control circuit leg; the deserializer i〇4b It is used to convert a sequence of lean material DOTtl outputted by the serializer 1〇3a into a third parallel data sna; the encoding circuit 1〇% is used to encode φ first parallel data S handsome and second parallel data SpZb respectively Generating a first encoded parallel data Selb and a second encoded parallel data Sezb, wherein the string The northbound system according to the first-coded parallel data Selb and the second encoded parallel data s must be generated as sequence data; the decoding circuit 1〇6b is used to generate the first-decoded parallel data Sdlb according to the third parallel data sqing And the second decoded parallel data combining unit 107b is configured to merge the first encoded parallel data "and the second encoded parallel data Se2b output by the encoding circuit 1"5b to generate - merged parallel data, wherein the serializer 103b Converting the merged parallel dragon into a sequence listening to d(10)2; the unmerging unit 108b is used to decompose the third parallel data^ to generate a first decomposition parallel data Sslb and a second decomposition parallel data^, wherein the decoding circuit secret The system decodes the first and second decompositions in parallel (four) - to divide the first decoded parallel data sdlb and the second decoded parallel data Sd. • #第一网络端12G ship access control circuit 1_ And 1 () 2a to the second network end 14 (3 of the media access control circuit lGlb and lion transfer the first 8 coffee and the second parallel data Sp2a, in this embodiment, the first parallel data Sp ^ and 12th 200830813 Second parallel capital The sp2a round-off form is difficult to parallel and the ^ 丁 赠 S S S CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK The data $ = the second data sela, Se2a and the parallel data after the merger, _^^ Tianping staple material spla, and input to the encoding circuit 105a, the encoding circuit wrist will encode the encoded parallel data Sel, Se2a, and its output form is also For 10 parallel output data, the bit rate of each output data is 125 megabits per second, and the parallel slogs Spla and se2a are synchronized with the clock CLK2 (125MHz) (as shown in Figure 2). ). In the present invention, the 'encoding circuit 105a is used to provide information necessary for the transmission of the parallel data, such as 'encryption action, data perturbation/, (SCrambling) to encode tolerable _ mess. Prevent DC flushing (DC brain (4) phenomenon, provide control, improve the ability of the data to be correctly received at the other end, etc. Then, the encoded parallel data &, ^ will simultaneously input the merged unit _ to match the bio-combination The output form of Qianjing data and the combined county materials is output with 1G parallel data, so the combined parallel data 8 contains the media access control circuit 1Gla and the office (4). The bit rate of each of the output materials after the merged data s· is 25 () megabits per second', that is, the period of each data is 4 ns' and the parallel data after the combination is CLK3 with a clock (250 MHz). Synchronization (as shown in Figure 2.) Then, after the merge, the parallel data S will lose the serialization||brain so that the merged parallel: #料8(10) is serialized into a high-frequency sequence data Doutl. Therefore 'output The bit rate of the sequence data I is 25 memory bits/second. , that is, the period of each data is 〇4ns. 13 200830813 • Referring to the second figure, the third figure is an embodiment of the serializer l〇3a, which includes a current unit 3〇2, a transistor The unit tearing and load unit 3〇6, which: negative, single pair is implemented by the resistor R. As shown in the figure, when the serializer receives the parallel data I output by the merging unit by the electric solar unit 304 After that, the parallel data Sma will determine whether the transistor b〇~ is turned on or not, so that the current in the current cell will flow through the turned-on transistor to the resistor R, and correspondingly - corresponding to 10 parallel shells The output voltage Vout, which represents the sequence data, is then transmitted through a transmission interface to the second network 140. Note that the communication in the embodiment of the present invention The first-network end 140 of the device excitation also includes a synchronization controller (not shown) for the deserializer l〇4b to generate a day-to-day pulse control signal to the deserializer (1) to synchronize the The signal of the sequence data D〇uti received by the deserialized 104b. A network terminal 12〇 and a second network terminal 14〇 are not limited to the application of the above-mentioned Lu MAC layer, and may be a ΡΗγ layer or any combination of the ancestor layer and the ρκγ layer. In other words, the first media storage Taking the control circuit 1〇1a, 1〇1b and the second medium access control (4) way H) 2a, the lion's ship device is replaced by a physical link circuit, for example, another embodiment of the present invention In the embodiment, the first media access control circuits 101a, 102b and the second media access control circuits i 〇 2a, i 〇 2b are replaced by physical link circuits to process data transfer between the two ΡΗ γ layers; In another embodiment of the present invention, the first media access control circuit 1〇1& and the second media access control circuit 102a are replaced by a physical link circuit, and the communication is set to _200830813 to process the PHY layer and the MAC layer. Data transfer between. Moreover, the first network end 120 and the second network end 14 of the present invention are operable to operate under different frequencies. For example, the first network end 120 operates at 1 〇〇 Mhz, and the second network The terminal 14 is operated at 1000 MHz, and then the data is transmitted through a serializer on a transmission interface through a serializer. On the other hand, when the first network end 120 and the second network end 14 are disposed on the ro slice of the _ gate, the sequence > Hunger 1, Dout2 can be transmitted over long distances through a fiber optic network, for example, the sequence data D in the embodiment shown in Fig. 1. For example, it is transmitted between the serializer l〇3a and the deserializer 104b, the serializer 1〇31), and the deserializer 104a through the optical network. Moreover, when the first network end 12〇 and the second network end 14〇 of the present invention are applied to the PHY layer, the data layer DATAia, DATA2a'DATAlb, DATA2b of the network layer can be transmitted through the optical network or the double Twisted-pair cable is used for transmission. Therefore, another embodiment of the present invention applies the first network end 120 and the second network end 140 of the embodiment shown in FIG. Network layer • The data DATAia, DATA2a, DATAib, DATA2b are transmitted in a twisted pair; another embodiment of the present invention is the first network terminal 12 and the second network of the embodiment shown in FIG. The terminal 140 is applied to the PHY layer, and the data of the network layer DATAla, DATA%, DATAlb, DATA2b is transmitted in a twisted pair, but the sequence data DQUtl and Drat2t are transmitted through the optical network; another embodiment of the present invention is The first network end 120 and the second network end 140 of the embodiment shown in the figure are applied to the PHY layer, and the data DATAla, DATA2a, DATAlb, DATA2b of the network layer are transmitted by the optical network, but the sequence is Information D. ^, then transmitted through the optical network; another embodiment of the present invention 15 200830813' is to apply the first network end m and the second * network end 140 of the embodiment shown in FIG. 1 to the PHY layer. And the data of the network layer DATAia, DATA2a, mTAlb, DATA2b are transmitted first. In addition, the #第-network terminal ^ and the second network terminal 14G are arranged in the phase _ crystal strong, the phase hunger, %, can be transmitted through the metal wire in the wafer. It is to be understood that any feasible variations that may be derived by those skilled in the art from the above teachings are the scope of the invention. π refers to Fig. 4', which is a flow chart of an embodiment of the present invention. The riding method is implemented by the communication device 100 shown in FIG. 1 , and its operation is simply summarized as follows: Step 402: transmitting the first parallel data V and the second parallel data sp2a; Step 4G4: encoding the first parallel data and the first The two parallel data s cents are used to generate the first encoded parallel data Sela and the second encoded parallel data se2a; . Step 4〇6: merge f _ edit parallel data, and 帛 second encode parallel data Se2a to produce merged parallel Data; Step 4〇8: Serialized merged parallel data sma to generate sequence data D〇utl for transmission; 'Suddenly receive and de-serialize data D_ to generate third parallel data s Qing; Step 412, Solution Combining the second parallel data 8 qing to generate the first decomposition parallel data sslb and a second decomposition parallel data &2b; and step 414 · decoding the first decomposition parallel data Sslb and the second decomposition parallel 200830813 • data Ss2b to generate the first decoded parallel data sdlb and the second solution-code parallel data sd2b. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS ^ , 1 is a schematic diagram of an embodiment of a communication device of the present invention. Fig. 2 is a timing chart showing the _parallel data, the second parallel data, the first post-parallel data, the second encoded parallel data, the merged parallel data, and the sequence data shown in Fig. 1. Figure 3 is a schematic illustration of one embodiment of a serializer. Figure 4 is a flow chart of an embodiment of a communication method of the present invention. [Main component symbol description] 100 ~-- communication device 101a > 101b first media access control circuit 102a > 102b ^ second media access control circuit 103a, 103b serializer 104a, 104b deserializer 105a, 105b encoding circuit 106a, 106b decoding circuit 107a, 107b merging unit 17 200830813 108a, 108b de-merging unit 302 current unit 304 transistor unit 306 load unit
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