200830415 九、發明說明 關連申請案之相互參照 本案係針對2006年10月19日申請之日本特願 2006-285559號申請案及2007年9月13日申請之日本特 願2 0 0 7-23 8 1 48號申請案提出優先權主張。又參照該日本 特願2006-28 5 559號申請案及2007年9月13日申請之日 本特願2007-23 8 1 48號申請案的全部內容，編入此說明書 而構成本案。 【發明所屬之技術領域】 本發明係關於一種包含介由光罩薄膜之開口部而對被 處理基體施予選擇性的處理工程之半導體裝置的製造方法 、及藉由該製造方法所製造之半導體裝置。 【先前技術】 第5圖係爲顯示習知之典型的MOS型電晶體的剖面 。雖然在閘極電極1 04的側壁上形成被稱爲所謂的側壁間 隔膜105的膜，但是近年來，則要求能夠容易除去該膜的 技術。以下，針對該技術背景加以說明。 在MOS電晶體之源極101及汲極102之間，爲了抑 制短通道效應，而形成較源極及汲極更淺，且摻雜濃度爲 低之被稱爲延伸部1 03的領域。源極1 0 1及汲極1 02與延 伸部103係使摻雜濃度及pn接合深度不同。 在習知的半導體裝置之製造方法中，於閘極電極104 -5- 200830415 再形成深的源極1 0 1 極102，在進行離子 高溫（1 0 0 0 °c程度） 於源極1 0 1、及汲極 高溫下進行熱處理， 而有擴大到較設計値 )1、及汲極102的領 隔膜 105 ( side wall 形成之方法。藉由在 極101、及汲極102 會曝露在高溫下，而 殘渣且對於構成延伸 式，除去在源極1 〇 1 專光罩之側壁間隔膜 丨來作爲側壁間隔膜 成損傷，當要利用濕 易殘留殘渣的問題點 中也有同樣的問題。 形成後，首先形成延伸部1〇3’其次 及汲極1 0 2。爲了形成源極1 〇 1及汲 注入後，爲了活性性此等離子而進行 的熱處理。 然而在這樣的習知製造方法中， 102的領域形成時，延伸部103也在 使得延伸部1 〇3領域的不純物擴散， 更深之不合宜的情況。 針對此點，提出了在形成源極1 ( 域後，除去被用來作爲光罩之側壁間 spacer)，其後再進行延伸部103的 延伸部103的領域形成前更先進行源 的領域形成，使延伸部103的領域不 能夠如同設計値地控制其接合深度。 但是，在該情況下，必須以沒有 部103領域的底層不會造成損傷之方 、及汲極102的領域形成時用來作j 105，但是在利用乾飩刻除去一般用 105之氮化矽膜時，恐怕會對底層造 鈾刻加以除去時，會有根據條件而容 〇200830415 IX. Inventions Cross-references for related applications The case is for the Japanese Patent Application No. 2006-285559 filed on October 19, 2006 and the Japanese Patent Application No. 2 0 0 7-23 8 on September 13, 2007. The No. 48 application filed a claim of priority. Reference is made to the Japanese Patent Application No. 2006-28 5 559 and the application date of September 13, 2007. The entire contents of the application No. 2007-23 8 1 48 are incorporated into this specification to constitute the present case. [Technical Field] The present invention relates to a method of manufacturing a semiconductor device including a process for imparting selectivity to a substrate to be processed through an opening of a photomask film, and a semiconductor manufactured by the method Device. [Prior Art] Fig. 5 is a cross section showing a conventional MOS type transistor. Although a film called a so-called inter-wall diaphragm 105 is formed on the side wall of the gate electrode 104, in recent years, a technique capable of easily removing the film has been demanded. Hereinafter, this technical background will be described. Between the source 101 and the drain 102 of the MOS transistor, in order to suppress the short channel effect, a region in which the source and the drain are shallower and the doping concentration is low is referred to as the extension portion 103. The source 1 0 1 and the drain 102 and the extension 103 have different doping concentrations and pn junction depths. In a conventional method of fabricating a semiconductor device, a deep source 10 1 1 pole 102 is formed on the gate electrode 104 -5 - 200830415, and an ion high temperature (about 100 ° C) is applied to the source 10 1. Heat treatment at the extreme temperature of the bungee, and the method of forming the side wall 105 (the method of forming the side wall by expanding the design to the base 1 and the drain 102). The pole 101 and the drain 102 are exposed to high temperatures. However, in the case of the residue, the side wall spacer film of the source 1 〇1 mask is removed to be damaged as a sidewall spacer film, and the same problem is also caused when the wet residue remains to be used. First, the extension 1 〇 3 ′ and the drain 1 0 2 are formed first. In order to form the source 1 〇 1 and the ruthenium injection, heat treatment is performed for the active plasma. However, in such a conventional manufacturing method, 102 When the field is formed, the extension portion 103 also causes the impurity in the field of the extension portion 1 〇 3 to diffuse, which is deeper and less suitable. For this point, it is proposed that after the source 1 (domain is removed, the removal is used as a mask). Spacer between the side walls), The field formation of the source is performed before the formation of the region of the extension portion 103 of the extension portion 103, so that the field of the extension portion 103 cannot control the joint depth as in the design. However, in this case, there must be no portion. The bottom layer of the 103 field does not cause damage, and the field of the bungee 102 is used for the formation of j 105. However, when the dry film is used to remove the generalized tantalum nitride film of 105, it is feared that the bottom layer of uranium will be engraved. When removed, there will be conditions based on conditions
不限於上述例子，在其次的製程I 習知以來，若是元件細微化的話，則期待性能的提升 。例如在MOS型電晶體的情況下，若是依照刻度尺寸而 200830415 細微化的話，電晶體之汲極電流則會增大。增大汲極電流 係意指訊號傳達速度變快，而與MPU或記憶體裝置的高 速化相關連。 然而，當細微化至數十奈米時，即使縮小圖案尺寸， 但是電晶體的性能並無法提升到所期待的程度。爲此，最 近以來，則是注意在增大載子移動度之應變矽技術。 汲極電流係以下述的數學式簡單表示。 [數1]It is not limited to the above example, and since the next process I is known, if the components are fine, the performance is expected to be improved. For example, in the case of a MOS type transistor, if the thickness is 200830415 according to the scale size, the gate current of the transistor increases. Increasing the buckling current means that the signal is transmitted faster and is associated with the speed of the MPU or memory device. However, when the size is reduced to several tens of nanometers, even if the pattern size is reduced, the performance of the transistor cannot be improved to the desired degree. For this reason, recently, attention has been paid to the strain 矽 technique for increasing the mobility of the carrier. The drain current is simply expressed by the following mathematical formula. [Number 1]
Id = W/L^*Cox*[(Vg-Vt)*Vd-l/2*Vd2] (1) 在此，Id爲汲極電流，W及L爲通道寬幅及通道長 度，Vg爲施加於閘極之電壓（閘極電壓），Vt爲臨界値 電壓（電晶體成爲開狀態的電壓），μ爲電子或電洞等載 子的移動度，Cox爲閘極絕緣膜的容量。 以應變通道部的矽而提升移動度之技術係爲在上述之 (1 )式中使μ增大，其結果爲達到汲極電流Id增大的目 的之技術。 就應變矽的方法而言，有2種方法，在此，使用圖面 說明關於本發明之層疊應力大的氮化矽膜後，將應力施加 於通道部的方法。 在第5圖中，於最上部形成應力大之氮化矽膜1 06。 更加詳細說明的話，在η型電晶體上層疊張力大的氮化矽 膜後，將張力施加於通道部，在Ρ型電晶體上層疊壓縮應 力大的氮化矽膜後，將壓縮應力施加於通道部。其結果爲 200830415 ，在η型電晶體中提升了電子的移動度，在p型電晶體中 提升了電洞的移動度。 但是，從第5圖可以明確得知，被用來爲了形成源極 101及汲極102之側壁間隔膜1〇5係殘留在閘極電極1〇4 的兩側，而成爲介由該膜將應力施加於通道部的構造。爲 此’使得氮化矽膜的應力無法充分地傳達到通道部。在爲 了充分地施加應力，以除去側壁間隔膜1 05並對閘極直接 φ 層疊氮化矽膜爲佳。 但是，就側壁間隔膜1 05而言，係使用氮化矽膜（利 用熱CVD或是電漿（：¥0加以層疊的膜），爲了除去此膜 ，一般都是使用熱磷酸。即使是使用已加熱的磷酸，但氮 化矽膜的蝕刻速度爲慢，而無法避免鈾刻時間變長。在經 過長時間蝕刻的期間，金屬矽化膜1 07也會被蝕刻而變薄 ，造成擴散層或閘極電極1 04之電阻提升的課題。 [專利文獻1]日本特開2005- 1 75 1 32號 【發明內容】 (發明所欲解決之課題） 本發明係以提供能夠在對元件構造部不會造成損傷下 除去側壁間隔膜等，並且製造出高積體化之高性能半導體 裝置之半導體裝置的製造方法爲目的。 (解決課題之手段） 根據本發明之半導體裝置的製造方法，係具備： -8- 200830415 在被處理基體上形成由GeCOH或是GeCH 第1薄膜的工程； 除去該第1薄膜的一部份後而形成殘留部的 介由前述第1薄膜之被除去空間，對前述被 施予既定處理之處理工程。 根據本發明之半導體裝置的製造方法，其中 前述處理工程係具有介由前述第1薄膜之被 Φ ，對前述被處理體注入既定的元素離子之工程。 根據本發明之半導體裝置的製造方法，其中 備： 除去前述殘留部之工程； 介由該殘留部之被除去空間，對前述被處理 定的元素離子之工程。 根據本發明之半導體裝置的製造方法，其中 /开 · 備. Φ 在位於前述第1薄膜之被除去空間的下方之 體上，層疊第2薄膜的工程， 前述處理工程係具有利用前述第1薄膜之被 ，使前述被處理基體與前述第2薄膜產生化學反 成第3薄膜之工程。 根據本發明之半導體裝置的製造方法，其中 殘留前述第3薄膜而除去前述殘留部與第2 根據本發明之半導體裝置的製造方法，其中 除去前述殘留部之工程係使用濕蝕刻法加以 所構成之 工程；及 處理基體 9 除去空間 進一步具 體注入既 進一步具 被處理基 除去空間 應後而形 薄膜。 進行。 200830415 根據本發明之半導體裝置的製造方、法，， 前述濕餓刻法係使用包含1^〇4及Η2〇2之触刻液加 以進行。 根據本發明之半導體裝置的製造方法，其中， 則述處理工程係包含使用前述第1薄膜之被除去空間 而除去前述被處理基體之一部份的工程。 根據本發明之半導體裝置的製造方法，其中， φ 前述被處理基體係包含層間絕緣膜， 除去ΒΙ[述被處理基體之一'部份的工程係爲除去被包含 在前述被處理基體中的層間絕緣膜之一部份的工程。 根據本發明之半導體裝置，係藉由具備以下工程之製 造方法加以製造： 在被處理基體上形成由GeCOH或是GeCH所構成之 第1薄膜的工程； 除去該第1薄膜的一部份後而形成殘留部的工程；及 介由[述第1溥膜之被除去的空間，對前述被處理基 體施予既定處理之處理工程。 (發明之效果） 藉由利用濕蝕刻而能夠容易除去以 GeCOH或是 GeCH所形成的光罩膜（第1薄膜），可以在爲對元件構 造部不會造成損傷下除去光罩膜，並且可以製造高積體化 之高性能半導體裝置。 -10 - 200830415 【實施方式】 以下，參照添附的圖示針對本發明之實施例具體說明 [實施例1] 以下，使用第l(a)-(d)圖及第2(a)-(c)圖 ，說明本發明之實施例1。在本實施例中係使用GeCOH 膜作爲離子注入處理的光罩。 首先，如第1 ( a )圖所示，在例如由矽所構成的半 導體基扳1上，藉由例如熱氧化法，形成由氧化矽所構成 的閘極絕緣膜2。又在形成閘極絕緣膜2前，藉由例如 STI (淺溝隔絕，Shallow Trench Isolation)技術，將元 件分離領域3形成在半導體基板1上。 其次，如第1 ( b )圖所示，在閘極絕緣膜2上形成 閘極電極4。 在nMOS電晶體的情況下，形成由含有As或是P之 多晶矽膜或是多晶矽鍺膜所構成之閘極電極4作爲η型不 純物。在pMO S電晶體的情況下，形成由含有Β之多晶矽 膜或是多晶矽鍺膜所構成之閘極電極4作爲ρ型不純物（ 以下，僅圖示η型或是ρ型之一種MOS電晶體）。 又形成不含不純物之多晶矽膜，並藉由利用光阻光罩 的蝕刻，加工爲閘極電極4後，在該閘極電極4及半導體 基板1上離子注入η型不純物或是ρ型不純物亦可。 其次，如第1 ( c )圖所示，在閘極電極4的側壁上 -11 - 200830415 形成側壁間隔膜5。例如以覆蓋閘極電極4的方式在半導 體基板1上，成膜GeCOH膜後，再藉由回蝕該膜，而在 閘極電極4的側壁上形成由GeCOH膜所構成之側壁間隔 膜（殘留部）5。 該GeCOH膜係以四甲基（TMG)鍺作爲主原料氣體 ，並利用PECVD法加以形成。就具體的成膜條件之例子 而言，可以利用TMG流量200sccm、C02流量200sccm、 處理室內壓力267Pa、基板溫度300°C、將13MHz的高頻 (RF )電力施加於上部電極並以RF電力200W的條件加 以成膜。就GeCOH膜的原料氣體而言，除了上述之TMG 外，也可以使用GeH4與CH系氣體（例如CH4等）的混 合氣體。又就GeCOH膜的成膜裝置而言，也可以使用利 用高密度電漿的CVD裝置取代PECVD，使用PVD裝置加 以成膜亦可。 其次，如第1 ( d )圖所示，藉由以閘極電極4及側 壁間隔膜5作爲光罩進行離子注入，形成源極•汲極領域 6。在nMOS電晶體的情況下，離子注入n型不純物後， 形成η型的源極•汲極領域6。在pMOS電晶體的情況下 ，離子注入P型不純物後，形成p型的源極•汲極領域6 。接著，爲了活化性源極•汲極領域6，藉由急遽RTA ( 快速熱退火，Rapid Thermal Annealer)以 1 000°C程度的 高溫進行熱處理。 其次，如第2 ( a )圖所示，藉由濕蝕刻除去側壁間 隔膜5。GeCOH膜係可以藉由含有H2S〇4及H202的蝕刻 -12- 200830415 液而容易除去。就其他的蝕刻液而言，也可以使用含有 NH3OH及H202之溶液、DHF (稀釋氫氟酸）溶液、加熱 的磷酸等。又根據GeCOH膜的組成（各元素比例），也 可以利用H2〇2加以除去。 其次，如第2 ( b )圖所示，以覆蓋閘極電極4的方 式形成SiN膜，並藉由回蝕該膜而在閘極電極4的側壁上 形成偏置間隔膜7。 其次，如第2 ( c )圖所示，以閘極電極4及偏置間 隔膜7作爲光罩，藉由離子注入n型不純物或p型不純物 ，形成延伸領域8。在η型電晶體的情況下，離子注入η 型不純物後，形成η型的延伸領域8。在ρ型電晶體的情 況下，離子注入Ρ型不純物後，形成Ρ型的延伸領域8。 接著，爲了活性化延伸領域8，藉由閃光燈退火，利用較 前述之源極•汲極領域6之活性化情況下更爲低溫的溫度 進行熱處理。 如此一來，即使在形成源極•汲極領域6後，除去側 壁絕緣膜（側壁間隔膜5 )，其後再形成延伸領域8的情 況下，藉由利用GeCOH膜形成側壁絕緣膜，可以容易地 除去該GeCOH膜，並且不會留下殘渣，又對元件構成部 不會造成損傷。 在形成延伸領域8後，以覆蓋閘極電極4及偏置間隔 膜7的方式形成Si02膜，並藉由回蝕該膜而再次形成側 壁絕緣膜等後，進行通常的MOSFET形成工程，其詳細 說明則加以省略。 -13- 200830415 [實施例2] 以下，使用第3 ( a ) - ( f)圖說明本發明之實施例2 〇 在本實施例中，首先藉由熱氧化在p型（10 0) Si基 板21上形成閘極絕緣膜22 (厚度約爲2nm )，接著藉由 使用甲矽烷氣體（SiH4 )之熱CVD法，形成無添加不純 物之多晶Si膜（膜厚150nm)。利用光微影法，覆蓋η 型MOS電晶體形成領域，再以加速電壓 2kV、摻雜量 5xl015cnT2的條件下，在沒被覆蓋之p型MOS電晶體形 成領域的多晶Si上離子注入硼（B )。利用氧電漿灰化剝 離光阻後，再次利用光微影法，藉由光阻覆蓋p型MOS 電晶體形成領域，再於η型MOS電晶體形成領域的多晶 Si上離子注入Ρ (磷）。加速電壓爲15 kV、摻雜量與Β 相同。其後，利用氧電漿灰化剝離光阻，再使用 h2o2 · H2S04混合溶液進行殘渣除去。 其次，進行光微影工程後，形成對應閘極電極的圖案 ，再以光阻爲光罩進行多晶S i膜的餘刻，形成閘極電極 24。在多晶Si飩刻後，在800°C的氧環境中僅氧化2nm， 而利用氧化矽膜2 7 ( S i 〇2 )覆蓋閘極電極2 4的周圍。 其次，再度利用光微影工程，以光阻作爲光罩形成延 伸部2 8 °在形成ρ型延伸部2 8的情況下，以加速電壓 0.5kV、摻雜量7xl014cm·2的條件離子注入BF3(B:硼） ，在形成η型延伸部2 8的情況下，以加速電壓1 5 kv、摻 -14- 200830415 雜量7xl014cm_2的條件離子注入As。 第3 ( a )圖係爲顯示該情況者，形成了閘極電極2 4 及延伸部28 (以下，僅圖示p型之一種MOS電晶體）。 其次，以厚度50nm形成GeCOH膜，並使用氟碳化 合物氣體進行反飩，在閘極電極的側壁上留下GeCOH膜 後而形成側壁間隔膜（殘留部）30。GeCOH膜的層疊條 件係與實施例1相同。 接著，藉由使用SiH4與NH3氣體之電漿CVD法，形 成厚度10nm的SiN膜31。同樣地，藉由使用氟碳化合物 氣體之乾飩刻進行回蝕，而形成2層構造之側壁間隔膜（ 第3 ( b )圖）。 其次，塗布光阻，經由光微影工程而覆蓋η型MOS 電晶體形成領域，並在Ρ型MOS電晶體形成領域進行離 子注入而形成深的Ρ +領域32，藉由氧電漿灰化剝離光阻 。反覆進行同樣的工程而在η型MOS電晶體形成領域上 形成深的η +領域，並再次藉由氧電漿灰化剝離光阻。 因爲在氧電漿灰化後，通常都會留下殘渣，且包含於 光阻中之金屬會殘留在基板上，爲了除去該等，一般都會 進行使用H2S04 · Η202混合溶液之處理。由於GeCOH膜 係可以藉由H2S04 · H202混合溶液加以鈾刻，因此側壁間 隔膜3 0係採取利用SiN膜3 1所覆蓋的層疊構造。 接著，使用熱磷酸溶液進行SiN膜31的蝕刻。因爲 厚度達到l〇nm的薄，而可以容易地除去（第3(c)圖） -15- 200830415 其次，在側壁間隔膜（殘留部）30、及位於GeC OH 膜之被除去空間的下方之延伸部2 8上，層疊Ni膜3 4。 換言之，將基板放入濺射裝置，使用Ar氣體而濺射鈾刻 Si〇2 (閘極絕緣膜22 )後，以膜厚20nm濺射成膜Ni膜 3 4 (第 3 ( d )圖）。 其後，以45 0°C進行30秒的熱處理後，使露出表面之 延伸部28中的Si與Ni反應而形成Ni Si (鎳矽化物）33 φ (第3 ( e )圖）。又在本實施例中，由於使閘極電極24 的上面露出，並使該上面與Ni膜34互相接觸，因此在閘 極電極24的上面也形成NiSi (鎳砂化物）33a。 在形成 NiSi33、及 NiSi33a 後，利用 H2S04.H2〇2 混 合溶液剝離未反應之Ni膜34。此時，GeCOH膜（側壁間 隔膜30)也同時被除去。藉由這樣的製程，如第3(f) 圖所示，對於NiSi33、及NiSi33a不會造成損傷，且可以 達到沒有側壁間隔膜30的狀態。 [實施例3] 其次，針對使用GeCOH膜作爲光罩蝕刻層間絕緣膜 之第3實施例，利用第4 ( a ) - ( d )圖加以說明。 如第4(a)圖所示，以覆蓋被形成在矽半導體基板 41上之層間絕緣膜42的方式，形成作爲光罩之GeCOH 膜43。再者，藉由光微影工程，使形成了既定開口部的 光阻44形成在該光罩43上。又在本實施例中，藉由矽半 導體基板4 1、及設置在該矽半導體基板4 1上之層間絕緣 -16- 200830415 膜42而構成被處理基體。 在使用 Cl2氣體或是CF系氣體之電漿蝕刻中， GeCOH膜係對於光阻膜44而言具有充份的蝕刻選擇性， 如第4 ( b )圖所示，藉由使用此等氣體之電漿蝕刻，使 光阻膜44的開口圖案轉印到GeCOH膜，而能夠形成有一 部份開〇之GeCOH膜（殘留部）43。 其次’如第4 ( c )圖所示，除去光阻後，以已轉印 開口圖案之GeCOH膜43作爲光罩，蝕刻在該GeCOH膜 43下的層間絕緣膜42，而形成用以配線之凹溝或導通孔 的開口 45。被用於層間絕緣膜42的Si 02或SiN係在使 用CF系氣體的電漿鈾刻中，對於GeCOH膜43而言具有 充分的蝕刻選擇性，因此GeCOH膜43係達到作爲光罩的 機能。 其次，如第4 ( d)圖所示，藉由使用包含H2S04與 H2〇2的溶液之濕飩刻除去GeCOH膜。在該濕蝕刻中，與 使用CF系氣體的電漿蝕刻不同，由於GeCOH膜43被蝕 刻的速度係較層間絕緣膜42被蝕刻的速度更快，因此可 以在對層間絕緣膜不會造成損傷下除去GeCOH膜43。 以上，雖然針對本發明的實施例加以說明，但是本發 明係不限於上述之實施例。例如，在對矽結晶施予變形而 增加通道中之載子移動度的應變矽技術中，藉由在源極· 汲極上進行矽鍺的磊晶成長’在閘極上利用施予壓縮應力 之氮化矽膜加以覆蓋，而製作施加壓縮應力於P型MOS 電晶體的構造時，也考量了對閘極上之阻礙矽鍺成長所用 -17- 200830415 之使用GeCOH膜來作爲罩蓋材料。在該情況下，可以在 對閘極不會造成損傷下利用濕蝕刻容易除去。 又上述的實施例中的任何一者都是使用GeCOH膜的 情況加以說明，但是也同樣可以使用GeCH膜。 【圖式簡單說明】 第1圖係爲說明本發明之第1實施例之工程的圖面。 第2圖係爲說明本發明之第1實施例之工程的圖面。 第3圖係爲說明本發明之第2實施例之工程的圖面。 第4圖係爲說明本發明之第3實施例之工程的圖面。 第5圖係爲說明習知工程之半導體裝置的剖面圖。 【主要元件符號說明】 1 z半導體基板 2 z閘極絕緣膜 3 :元件分離領域 4 :閘極電極 5 =側壁間隔膜（殘留部） 6 :源極•汲極領域 7 :偏置間隔膜 8 :延伸領域 21 : Si基板 22 :閘極絕緣膜 23 :元件分離領域 -18- 200830415 2 4 :閘極電極 27 :氧化矽膜 2 8 :延伸部 3 0 :側壁間隔膜（殘留部） 31 : SiN 膜 32 : p +領域 34 : Ni 膜Id = W/L^*Cox*[(Vg-Vt)*Vd-l/2*Vd2] (1) Here, Id is the drain current, W and L are the channel width and channel length, and Vg is applied. At the gate voltage (gate voltage), Vt is the critical 値 voltage (voltage at which the transistor is turned on), μ is the mobility of carriers such as electrons or holes, and Cox is the capacity of the gate insulating film. The technique for increasing the mobility by the enthalpy of the strain channel portion is to increase the μ in the above formula (1), and as a result, it is a technique for increasing the gate current Id. There are two methods for the strain enthalpy. Here, a method of applying stress to the channel portion after the tantalum nitride film having a large lamination stress according to the present invention will be described with reference to the drawings. In Fig. 5, a tantalum nitride film 106 having a large stress is formed on the uppermost portion. More specifically, when a tantalum nitride film having a large tensile force is laminated on an n-type transistor, tension is applied to the channel portion, and a tantalum nitride film having a large compressive stress is laminated on the germanium-type transistor, and then a compressive stress is applied to the tantalum-type transistor. Channel section. The result is 200830415, which improves the mobility of electrons in the n-type transistor and improves the mobility of the hole in the p-type transistor. However, as is clear from Fig. 5, the sidewall spacer film 1〇5 used to form the source electrode 101 and the drain electrode 102 remains on both sides of the gate electrode 1〇4, and becomes a film through the film. Stress is applied to the configuration of the channel portion. For this reason, the stress of the tantalum nitride film cannot be sufficiently transmitted to the channel portion. In order to sufficiently apply stress, it is preferable to remove the sidewall spacer film 105 and laminate the tantalum nitride film directly to the gate. However, in the case of the sidewall spacer film 105, a tantalum nitride film (a film laminated by thermal CVD or plasma (: 0) is used, and in order to remove the film, hot phosphoric acid is generally used. Even if it is used The heated phosphoric acid, but the tantalum nitride film is slow to etch, and the uranium engraving time cannot be prevented from becoming longer. During the long etching period, the metallized film 107 is also etched and thinned, resulting in a diffusion layer or [Problems to be solved by the invention] [Patent Document 1] Japanese Laid-Open Patent Publication No. 2005- 1 75 1 32 (Problems to be Solved by the Invention) The present invention provides that the component structure portion can be provided. A method for manufacturing a semiconductor device in which a high-performance semiconductor device having a high integrated body is removed, and a method of manufacturing a semiconductor device having a high-integration high-performance semiconductor device is provided, and the method for manufacturing a semiconductor device according to the present invention includes: -8- 200830415 A process of forming a GeCOH or a GeCH first film on a substrate to be processed; removing a portion of the first film to form a residual portion through the space in which the first film is removed, According to the method of manufacturing a semiconductor device of the present invention, the processing system has a process of implanting a predetermined elemental ion into the object to be processed via the Φ of the first film. A method of manufacturing a semiconductor device according to the present invention, comprising: a process of removing the residual portion; and a process of removing the element ions to be processed through the removed space of the residual portion. According to the method of manufacturing a semiconductor device of the present invention, In the case of the second film, the process of laminating the second film is performed on the body below the removed space of the first film, and the process is performed by using the first film, and the substrate to be processed is The second film is produced by chemically reacting the third film. According to the method of manufacturing a semiconductor device of the present invention, the third film is left to remove the remaining portion and the second method for manufacturing the semiconductor device according to the present invention, wherein the The engineering of the residual portion is a process constructed by wet etching; and the processing substrate 9 Further, the de-space is further injected into the film, and the film is removed, and the film is formed. 200830415 According to the manufacturing method and method of the semiconductor device of the present invention, the wet etching method includes 1^〇4 and Η2〇. According to the method of manufacturing a semiconductor device of the present invention, the process engineering includes a process of removing a part of the substrate to be processed by using the removed space of the first film. In the method of manufacturing a semiconductor device according to the invention, the φ of the substrate system to be treated includes an interlayer insulating film, and the engineering system for removing the 之一 [the one of the substrates to be processed] is to remove the interlayer insulating film contained in the substrate to be processed. One part of the project. The semiconductor device according to the present invention is manufactured by a manufacturing method comprising: forming a first thin film made of GeCOH or GeCH on a substrate to be processed; and removing a part of the first thin film The process of forming the residual portion; and the process of applying the predetermined treatment to the substrate to be processed via the space in which the first film is removed. (Effect of the Invention) The photomask film (first film) formed of GeCOH or GeCH can be easily removed by wet etching, and the photomask film can be removed without causing damage to the device structure portion. Manufacturing high-performance semiconductor devices with high integration. -10 - 200830415 [Embodiment] Hereinafter, an embodiment of the present invention will be specifically described with reference to the attached drawings. [Embodiment 1] Hereinafter, the first (a)-(d) and the second (a)-(c) are used. Fig. 1 is a view showing Embodiment 1 of the present invention. In the present embodiment, a GeCOH film was used as a photomask for ion implantation treatment. First, as shown in Fig. 1(a), a gate insulating film 2 made of ruthenium oxide is formed by, for example, thermal oxidation on a semiconductor substrate 1 made of, for example, ruthenium. Further, before the formation of the gate insulating film 2, the element isolation region 3 is formed on the semiconductor substrate 1 by, for example, STI (Shallow Trench Isolation) technique. Next, as shown in Fig. 1(b), the gate electrode 4 is formed on the gate insulating film 2. In the case of an nMOS transistor, a gate electrode 4 composed of a polycrystalline germanium film containing As or P or a polycrystalline germanium film is formed as an n-type impurity. In the case of a pMO S transistor, a gate electrode 4 composed of a polysilicon film containing germanium or a polysilicon film is formed as a p-type impurity (hereinafter, only an MOS transistor of an n-type or a p-type is illustrated) . Further, a polycrystalline germanium film containing no impurities is formed, and after being processed into the gate electrode 4 by etching with a photoresist mask, n-type impurities or p-type impurities are ion-implanted on the gate electrode 4 and the semiconductor substrate 1. can. Next, as shown in Fig. 1(c), a sidewall spacer film 5 is formed on the sidewall of the gate electrode 4 -11 - 200830415. For example, a GeCOH film is formed on the semiconductor substrate 1 so as to cover the gate electrode 4, and then the film is etched back to form a sidewall spacer film composed of a GeCOH film on the sidewall of the gate electrode 4 (residual Department) 5. The GeCOH film was formed by a PECVD method using tetramethyl (TMG) ruthenium as a main raw material gas. For an example of specific film formation conditions, a TMG flow rate of 200 sccm, a C02 flow rate of 200 sccm, a process chamber pressure of 267 Pa, a substrate temperature of 300 ° C, and a high frequency (RF) power of 13 MHz can be applied to the upper electrode and RF power is 200 W. The conditions are applied to form a film. As the material gas of the GeCOH film, in addition to the above TMG, a mixed gas of GeH4 and a CH-based gas (e.g., CH4 or the like) may be used. Further, in the film forming apparatus of the GeCOH film, a CVD apparatus using a high-density plasma may be used instead of PECVD, and a film formation by a PVD apparatus may be employed. Next, as shown in Fig. 1(d), the source/drainage field 6 is formed by ion implantation using the gate electrode 4 and the side wall spacer film 5 as a mask. In the case of an nMOS transistor, after n-type impurity is ion-implanted, an n-type source/drain region 6 is formed. In the case of a pMOS transistor, a p-type source and a drain region are formed after ion implantation of a P-type impurity. Next, for the activating source/bungee field 6, heat treatment is performed at a high temperature of about 1 000 °C by an emergency RTA (Rapid Thermal Annealer). Next, as shown in Fig. 2(a), the inter-wall separator 5 is removed by wet etching. The GeCOH film system can be easily removed by etching -12-200830415 containing H2S〇4 and H202. As the other etching liquid, a solution containing NH3OH and H202, a DHF (diluted hydrofluoric acid) solution, or a heated phosphoric acid may be used. Further, depending on the composition of the GeCOH film (the ratio of each element), it may be removed by H2〇2. Next, as shown in Fig. 2(b), the SiN film is formed to cover the gate electrode 4, and the offset spacer film 7 is formed on the sidewall of the gate electrode 4 by etching back the film. Next, as shown in Fig. 2(c), the gate electrode 4 and the inter-bias diaphragm 7 are used as a mask to form an extension field 8 by ion-implanting an n-type impurity or a p-type impurity. In the case of an n-type transistor, an n-type extension field 8 is formed after ion implantation of an n-type impurity. In the case of a p-type transistor, an ion-type extension field 8 is formed after ion implantation of a ruthenium-type impurity. Next, in order to activate the stretching region 8, heat treatment is performed by flash lamp annealing at a temperature lower than that in the case of activation of the source/drain region 6 described above. In this way, even after the source/drain region 6 is formed, the sidewall insulating film (sidewall spacer film 5) is removed, and thereafter, the extension region 8 is formed, and the sidewall insulating film can be formed by using the GeCOH film. The GeCOH film is removed, and no residue remains, and damage to the element constituent portion is not caused. After the extension region 8 is formed, the SiO 2 film is formed so as to cover the gate electrode 4 and the offset spacer film 7, and the sidewall insulating film or the like is formed again by etching back the film, and then a normal MOSFET formation process is performed. The description is omitted. -13- 200830415 [Embodiment 2] Hereinafter, Embodiment 2 of the present invention will be described using Figs. 3(a) - (f). In this embodiment, first, by thermal oxidation on a p-type (10 0) Si substrate A gate insulating film 22 (having a thickness of about 2 nm) was formed on 21, and then a polycrystalline Si film (film thickness: 150 nm) to which no impurity was added was formed by a thermal CVD method using a methanol gas (SiH4). The photolithography method is used to cover the formation field of the n-type MOS transistor, and then boron is ion-implanted on the polycrystalline Si in the unformed p-type MOS transistor formation field under the condition of an acceleration voltage of 2 kV and a doping amount of 5×l015cnT2. B). After the photoresist is removed by oxygen plasma ashing, the photolithography method is used again to cover the p-type MOS transistor formation region by photoresist, and then ion implantation (phosphorus) on the polycrystalline Si in the field of n-type MOS transistor formation. ). The accelerating voltage is 15 kV and the doping amount is the same as Β. Thereafter, the photoresist was removed by oxygen plasma ashing, and the residue was removed using a mixed solution of h2o2 · H2S04. Next, after the photolithography project is performed, a pattern corresponding to the gate electrode is formed, and the photoresist is used as a mask to carry out the remnant of the poly Si film, thereby forming the gate electrode 24. After the polycrystalline Si was etched, only 2 nm was oxidized in an oxygen atmosphere at 800 ° C, and the periphery of the gate electrode 24 was covered with a yttrium oxide film 27 (S i 〇 2 ). Secondly, the photolithography project is again used, and the photoresist is used as the mask to form the extension portion. 8 8 ° In the case of forming the p-type extension portion 28, the ion implantation BF3 is performed under the condition of an accelerating voltage of 0.5 kV and a doping amount of 7×l014 cm·2. (B: boron), in the case where the n-type extension portion 28 is formed, As is ion-implanted at a condition of an acceleration voltage of 15 kV and a doping of -14,304,304, and a quantity of 7xl014 cm_2. In the third (a) diagram, the gate electrode 24 and the extension portion 28 are formed (hereinafter, only a p-type MOS transistor is shown). Next, a GeCOH film was formed to a thickness of 50 nm, and ruthenium was formed using a fluorocarbon compound gas, and a GeCOH film was left on the sidewall of the gate electrode to form a sidewall spacer film (residual portion) 30. The laminated condition of the GeCOH film was the same as in Example 1. Next, a SiN film 31 having a thickness of 10 nm was formed by a plasma CVD method using SiH4 and NH3 gas. Similarly, the etchback is performed by dry etching using a fluorocarbon gas to form a sidewall spacer film having a two-layer structure (Fig. 3(b)). Next, the photoresist is coated, and the n-type MOS transistor formation field is covered by photolithography, and ion implantation is performed in the field of Ρ-type MOS transistor formation to form a deep Ρ + field 32, which is stripped by oxygen plasma ashing. Light resistance. The same work was repeated to form a deep η + field in the field of n-type MOS transistor formation, and the photoresist was again stripped by oxygen plasma ashing. Since the residue is usually left after the ash plasma is ashed, the metal contained in the photoresist remains on the substrate, and in order to remove the above, the H2S04·Η202 mixed solution is generally used. Since the GeCOH film can be uranium-etched by the H2S04·H202 mixed solution, the inter-wall separator 30 is a laminated structure covered with the SiN film 31. Next, etching of the SiN film 31 is performed using a hot phosphoric acid solution. Since the thickness is as thin as 10 nm, it can be easily removed (Fig. 3(c)) -15-200830415 Next, the sidewall spacer film (residual portion) 30, and the space below the removed space of the GeC OH film On the extension portion 28, a Ni film 34 is laminated. In other words, the substrate is placed in a sputtering apparatus, and the uranium engraved Si〇2 (gate insulating film 22) is sputtered using Ar gas, and then the Ni film 3 4 is sputtered at a film thickness of 20 nm (Fig. 3 (d)) . Thereafter, after heat treatment at 45 ° C for 30 seconds, Si in the extended portion 28 on the exposed surface reacts with Ni to form Ni Si (nickel telluride) 33 φ (Fig. 3(e)). Further, in the present embodiment, since the upper surface of the gate electrode 24 is exposed and the upper surface and the Ni film 34 are in contact with each other, NiSi (nickel sand compound) 33a is also formed on the upper surface of the gate electrode 24. After NiSi33 and NiSi33a were formed, the unreacted Ni film 34 was peeled off by the H2SO4.H2〇2 mixed solution. At this time, the GeCOH film (the inter-sidewall separator 30) was also removed at the same time. By such a process, as shown in Fig. 3(f), damage to NiSi33 and NiSi33a is not caused, and the state in which the sidewall spacer film 30 is absent can be achieved. [Embodiment 3] Next, a third embodiment in which a GeCOH film is used as a photomask etching interlayer insulating film will be described using a fourth (a) - (d) diagram. As shown in Fig. 4(a), a GeCOH film 43 as a photomask is formed so as to cover the interlayer insulating film 42 formed on the germanium semiconductor substrate 41. Further, a photoresist 44 having a predetermined opening portion is formed on the photomask 43 by photolithography. Further, in the present embodiment, the substrate to be processed is constituted by the germanium semiconductor substrate 41 and the interlayer insulating -16 - 200830415 film 42 provided on the germanium semiconductor substrate 41. In plasma etching using Cl2 gas or CF-based gas, the GeCOH film has sufficient etching selectivity for the photoresist film 44, as shown in Fig. 4(b), by using such gases. The plasma etching causes the opening pattern of the photoresist film 44 to be transferred to the GeCOH film, and a partially opened GeCOH film (residual portion) 43 can be formed. Next, as shown in Fig. 4(c), after the photoresist is removed, the interlayer insulating film 42 under the GeCOH film 43 is etched by using the GeCOH film 43 having the transferred opening pattern as a mask to form a wiring for wiring. The opening 45 of the groove or via. The Si 02 or SiN used for the interlayer insulating film 42 has a sufficient etching selectivity for the GeCOH film 43 in the plasma uranium engraving using the CF-based gas, so that the GeCOH film 43 functions as a photomask. Next, as shown in Fig. 4(d), the GeCOH film was removed by wet etching using a solution containing H2S04 and H2?2. In the wet etching, unlike the plasma etching using the CF-based gas, since the GeCOH film 43 is etched at a faster rate than the interlayer insulating film 42 is etched, it is possible to prevent damage to the interlayer insulating film. The GeCOH film 43 is removed. Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, in a strain enthalpy technique in which deformation of a ruthenium crystal is applied to increase the mobility of a carrier in a channel, by performing epitaxial growth of germanium on the source and drain electrodes, nitrogen is applied to the gate on the gate. When a ruthenium film is covered and a compressive stress is applied to the structure of the P-type MOS transistor, a GeCOH film using -17-200830415 for the growth of the barrier on the gate is also considered as a cover material. In this case, it is possible to easily remove it by wet etching without causing damage to the gate. Further, any of the above embodiments is described using a GeCOH film, but a GeCH film can also be used. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing the construction of the first embodiment of the present invention. Fig. 2 is a view for explaining the construction of the first embodiment of the present invention. Fig. 3 is a view showing the construction of the second embodiment of the present invention. Fig. 4 is a view showing the construction of the third embodiment of the present invention. Figure 5 is a cross-sectional view showing a semiconductor device of a conventional engineering. [Main component symbol description] 1 z semiconductor substrate 2 z gate insulating film 3: component isolation field 4: gate electrode 5 = sidewall spacer film (residual portion) 6 : source • drain region 7: offset spacer film 8 : Extension field 21 : Si substrate 22 : Gate insulating film 23 : Component separation field -18 - 200830415 2 4 : Gate electrode 27 : Cerium oxide film 2 8 : Extension portion 3 0 : Side wall spacer film (residual portion) 31 : SiN film 32: p + field 34 : Ni film
33、33a : NiSi (鎳矽化物） 4 1 :矽半導體基板 42 :層間絕緣膜 43: GeCOH 膜 44 :光阻 45 :開□ 101 :源極 102 :汲極 103 :延伸部 104 :閘極電極 105 :側壁間隔膜 106 :氮化矽膜 1 0 7 :金屬矽化膜 -19-33, 33a: NiSi (nickel telluride) 4 1 : germanium semiconductor substrate 42: interlayer insulating film 43: GeCOH film 44: photoresist 45: opening 101: source 102: drain 103: extension portion 104: gate electrode 105: sidewall spacer film 106: tantalum nitride film 1 0 7 : metal germanium film-19-