200830392 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種藉由分 半導體晶片之何體晶片^—體晶®而獲得複數個 導艘元件形成於半導體晶圓：;:=中已將複數個半 【先前技術】 ％路形成面上。 近來關於將半導體晶圓分 技術㈣，已對當㈣半導γ/別半㈣晶片的新穎 投注特別注意力。前述之電之損傷小的電黎切製 換士夕* 切製包含以下的切製技術。 成㈣膜形成於半導體晶圓之與其電路形 成面對置之面（即，背面）上 兒峪形 用於使半導體元件彼此分#乂:：’：此抗刪膜中沿 溝槽)；且其後在將其中經形成：等二成溝槽(即’邊界 遮：的同時，將半導體晶圓電 半導體 離方式切割及分割成個別的半導體晶片。= 二用在此電裝切製中，採用微影技術製造遮罩。缺而： 影技術製造遮罩時，需要較高成本。因此:已有： &出無遮罩類型的電漿切製（參照專利公告υ。換言之， [專利公告 1] JP-A-2003-1 97569 ^ 4吏=遮罩藉由操作機械切割裝^於半導圓 表面中形成溝槽，隨後再自溝槽進行電漿 「直別八；Φ 1 Ί ττ^ I ^ Λ Λ ^ ^ 【發明内容】 然而，前述專利公告i中所述 gl7 A K方去具有下述問題。亦 I7 ’ 一 ：!又而言，由於利用電漿切萝 刀衣的餘刻速率需要大約2 312ΧΡ/發明說明書(補件)/97-02/96150218 6 200830392 链未/分鐘，因而若於進行溝 域的厚度過厚，則在切製步驟中之切割邊緣區 •間，以致製造效率劣化。另 θ，〜要地需要冗長的時 亦即，若於進行溝槽機器加工後之切^方^有另一問題。 -薄，則半導體晶圓會容易破裂，以致區域的厚度過 漿钱刻處理等) 體晶圓輸送至真空室中以進行電 因此’本發明之一目的為 籲切製所需之% 的為美供一種可藉由縮短進行電f 刀衣所而之時間而改良半導 < 4丁包水 進行電漿切製之前浐逆本道^日 衣化效率，同時當在 裂等等的半導體晶片之製造方法。h體曰曰0不會破 晶Hir月、一種用以獲得複數個半導體晶片之半導體 =…衣&方法在於沿切製線分割已於半導體晶圓之恭 路形成面上形成複數個半導、、日曰 私 導體元件彼此分割開，牛之半導體晶圓，以使半 置之半導體曰鬥夕北x法匕括·研磨與電路形成面對 •,日日®之月面的背面研磨 經研磨背面上形成抗蝕劑薄膜牛¥體阳®之 m μ n +„ -r ,* μ潯馭的抗蝕劑溥膜形成步驟；利 绩^ ^ =置移除於抗餃劑薄膜之厚度方向中沿切f 之厂曰声^! 邊緣區域以及於半導體晶圓 t 向中位於抗钱劑薄膜側上之半導體晶圓之-部 緣區域兩者的溝槽機器力^步驟；在將抗餘劑 遮罩使用作為遮罩的同時對半導體晶圓進行電聚姓刻製 %’以將半導體晶圓於其厚度方向中沿切製線之所有殘餘 切割邊緣區域移除的電聚切製步驟；及於進行電裝切製步 3i2XP/發明說明書(補件)/97-02/96150218 ? 200830392 驟後自半導體晶圓移 驟。 ’、 J 4膜的抗蝕劑薄膜移除步 於申請專利範園第2項尹 .方法的特徵在於在申請專：之：：體晶片之製造 .體晶片之製造方法中，於進行溝二:中：引述之半導 體晶圓於其厚度方向t沿切制加工步驟後，半導 係50至200微米。 衣、"之殘餘切割區域的厚度 在本發明中，於在半導妒曰 緣區域之部分移除，且半導體晶；二的切割邊 會產生任何其在輸送半導體晶圓時絕不 餘切割邊緣二=進刻製程而將所有殘 移除所有切割邊缘u 、⑽由進行電漿蝕刻製程 所需時間相比：電::::割及分㈣^ 因此，根據本發：二刀：：所需的時間可大咖 晶圓時半導體歹在進行電聚切製之前輸送半導體 時間，以致可大大地改良半導體晶片的製造二所-的 體t夕圓卜上由之t電浆餘刻製程係於將抗勉劑薄膜形成於半導 於^體2進行，因而於電裝大氣内分解之自由基集中 經機械切割々_分的附近，以致㈣ 外，在利用心切:::切；實現高速電漿姓刻製程。此 形成抗蚀劑薄J及移除切割邊緣區域的同時 、抗蝕劑圖案，以致不再需要高成本的微 312XP/發明說明書(補件)/97·〇2/9615〇2ΐ8 ^ 200830392 影術。 半=在片:，割階段中將半導體晶圓切割及分割為 漿蚀刻處理進二二此作係藉由切割損傷小的電 =“0於其之與其形成抗_薄膜之面對置之面， 黾路形成面）上且右息立沾 明的主道鵰 易坪的低介電物質層時’前述之本發 月的+ ¥心日日片之製造方法變得尤其有利。 【實施方式] ΐ先’參照圖i及圖2說明利韻本發明 中之⑽割裝置10及電裝處理裝置3〇的構造。、式 現荼照圖式說明本發明之具體例模式。在® 1中，刀片 y衣置1G係經配置成包括晶圓固持單$ η、輸送板 片13、刀片固持單元14、刀片輸送機構“、刀片 驅動機構17、晶圓輸送機構18、控制單元Μ、識別單元 20紅作/輸入單元2卜工作資料儲存單元、及並類 :元件。晶圓固持單W將半導體晶圓i固持於應接受 处理的水平位置。輸送板12係以可自由輸送的方式設置 於晶圓固持單元11上方。刀片固持單元14係較於輸送 板12+上/且以可環繞水平旋轉軸（假定將沿旋轉軸延伸的 =向疋義為X軸）自由旋轉的方式固持住刀片13。除了將 二相械15固疋於輸送板12上之外，刀片輸送機構16輸 送該輸送板12。刀片驅動機構17可旋轉地驅動刀片13。 f圓輸送機構18輸送（包括旋轉）晶圓固持單元11。控制 單疋19控制此等機構16、17、18之操作。識別單元 312XP/發明說明書(補件)/97-02/96150218 9 200830392 =照相機15所拍攝得之影像執行半導體 —/ 。工作貧料儲存單元22係連接至控制單元19。 • 包括將半導體晶圓1固定/固持於 之固以固持70件諸如真空卡盤時，半導體曰 圓1係以使此本導，曰m， 卞守耻_ 样㈣ 之面朝向利用刀片U進行溝 二固持η:上方向的方式被此固定，固持元件固定 ·(= 主。刀片輸送機構16沿X軸方向及ζ轴方向(上/ II" 12 片口持早兀14及照相機15兩者於控制單 控制下在半導體晶们的 之 17於护制里-, 万二間中輪迗。刀片驅動機構 13、二 制下環繞旋轉軸可旋轉地驅動刀片 13。日日圓輸送機構18於控制 ^即’在水平面内…交之方向= 且亦使晶圓固持單^ 11環繞位在平行於Z轴之上/ 轉。照相機15利用紅外光拍攝 半導體晶圓丨。識別單元2。基於照相機心 執行半導體晶圓1的位置識別，接著再將自位置識 19。又付之關於半導體晶圓1的位置訊息傳送至控制單元 的19基於自識別單元20傳送來之半導體晶圓1 的^置机息而知曉半導體晶圓i與刀片13 係。操作/輸入單元21回應操作人員 二= 種輸入信號提供至控制單元19。在已將關於 312XP/發明說明書(補件)/97·〇2/96150218 200830392 切製線2的資料鍺存於工作 形狀之切製線2構成當將、f存早70 22中’且格柵 半導體晶片時所利用 缓曰曰® 1切割且分割為個別 i㈣其資料已儲存於工;=，控制單元以使刀片 2相對於半導m相元2 2中之切製線 送機構16及晶圓輪送機構18兩者的^作控制關於刀片輪 圖2中’電漿處理裳置3〇 上方電極33、高頻供電 至=方， 路徑36、氧氣供給單元37、^ "/早几35、氣體供給 -開體供給單元⑽、第 及第…w丨： 制閥4〇、第二開，關閥41、 及弟―率技制閥42所構成。下方電極&及上 L3兩者係設置於真空室31内。高頻供電單元34對；方 ^=3盾2，加Γ頻電壓。冷卻單元3 5使冷卻劑於下方電極 内#^«供給路徑36係自上方電極犯之内部於 真空室31之外部延伸’且於真空室31之外部分歧。氧氣 供給單元37係連接至分歧氣體供給路徑⑽的―側分= 徑（以下將稱為「第一分支路徑咖」）。氣系列氣體供仏 單元38係連接至分歧氣體供給路徑36的另-側分支特 (?將稱為「第二分支路請」）。第-開綱3; 及第一流率控制閥40兩者係插置於第一分支路徑36& 中。第一開/關閥41及第二流率控制閥42兩者係插置於 第二分支路徑36b中。 真空室31之内部空間係經設置為用於對半導體晶圓工 進行電漿製程操作之緊密封閉的空間。下方電極犯係以 312XP/發明說明書(補件)/97-〇2/96150218 \\ 200830392 導體晶圓〗之固持面向上設置的 31内’而上方雷炼冬 飞17又置於直处它 下方使此上方電極33之下：二至 ::極32之上方面對置的方式設置…室二方面與 在將由真空卡盤及靜電吸取機構所構：：：以内。 構（未不於圖令）及由電絕緣材料製成之产曰曰加圓固持機 者設置於下方電極32 衣’ 1架32a兩 # JL牲、隹—干败 面上時，半導體晶圓1在 /寺進仃笔漿處理操作之面朝上且其周邊部二、係以 32a圍繞，且經由晶 鬥故。卩分破框架 _方面上的方式受支;機構固定於下方電極Μ之上 當將氧氣（或者可制主要氣 填充至氧氣供給單元37中時， 合氣體） 打開(第二開/關閥41關閉)時 氣體供給路㈣供給至上方電極33。經 控制閥以之開度而調整氧氣自氧氣供給單元二：二 極充此外’當將氟系列氣體(例如，六㈣ 第H 供給單元3 δ中時’氣系列氣體係在 弟-開〈關閥41打開(第一開，關閥3 9關閉)時經由第二 分支路徑36b及氣體供給路徑36供給至上方電極33。經 由控制第二流率控制閥42之開度而調整氟系列氣體自氟 系列氣體供給單元38供給至上方電極33的流率。 當將具有扁平板狀之多孔板33a設置於上方電極33之 了方面上時，經由氣體供給路徑36供給的氧氣及氟系列 氣體經由此多孔板33a均勻喷灑於下方電極32之上方面 上。 312XP/發明說明書(補件)/97-〇2/96150218 12 200830392 接下來’爹照圖3之流程圖、及圖4、圖5、及圖6中 所π之步驟說明圖說明製造半導體晶片之方法 電物質層3設置於半導體晶圓1之電路形成面lp田上^ •已於使用低介電物質層3作為絕緣層之情況下於電路带 ,成面lp上形成複數個半導體元件4(圖4(a))。 一 如先前所說明，為經由沿切製線2分割已於電路形成面 1P上形錢數辦導體元件4之铸體晶圓丨以導 體兀件4,彼此分割開而獲得複數個半導體晶#工，（圖 6(d)) ’首先’如圖4(b)所指示，將具有黏著特性的片狀 保護膠帶（例如，UV膠帶）5黏著於半導體晶圓k電路形 成面lp上（圖3所示之保護膠帶黏著步驟S1)。 於完成保護膠帶黏著步驟S1後，如圖4(c)所示，利用 背面研磨裝置50研磨半導體晶圓i的背面lq((圖3所示 之月面研磨步驟S2)。背面^係與電路形成面“對置。 为面研磨裝置50係由旋轉台51及設置於旋轉台51上 _方的旋轉研磨機52所構成。半導體晶圓】係以使半導體 晶圓1之背面方向朝上的方式裝置於旋轉台51之上方 面上。當將半導體晶圓1裝置於旋轉台51上時，旋轉研 磨機52自上方向下壓抵半導體晶圓1之背面lq(圖4(c)200830392 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor wafer obtained by dividing a semiconductor wafer into a semiconductor wafer by a semiconductor wafer: A plurality of [previous techniques] % roads are formed on the surface. Recently, regarding semiconductor wafer sub-technology (4), special attention has been paid to novel bets on (four) semi-conducting gamma/semi-four (four) wafers. The above-mentioned electric damage is small, and the following cutting technique is included. Forming (iv) a film formed on a surface of the semiconductor wafer facing the circuit (ie, the back surface) for dividing the semiconductor elements into each other #乂::': the anti-deletion film is along the trench; Thereafter, the semiconductor wafer is electrically cut and divided into individual semiconductor wafers while being formed into two equal grooves (ie, 'boundary masks'). The use of lithography technology to create masks. Lack of: Shadow technology requires a higher cost when manufacturing masks. Therefore: already: & unmasked type of plasma cutting (refer to the patent notice υ. In other words, [patent Announcement 1] JP-A-2003-1 97569 ^ 4吏=Mask is formed by machining a mechanical cutting device to form a groove in the semi-circular surface, and then plasma is applied from the groove. “Leave eight; Φ 1 Ί Ττ^ I ^ Λ Λ ^ ^ [Summary of the Invention] However, the gl7 AK side described in the aforementioned Patent Publication i has the following problems. Also I7 'I: In addition, due to the use of the plasma dicer knife The engraving rate needs to be approximately 2 312 ΧΡ / invention specification (supplement) /97-02/96150218 6 200830392 chain not / min Therefore, if the thickness of the trench region is too thick, the cutting edge region is cut during the cutting step, so that the manufacturing efficiency is deteriorated. Another θ, ~ the need for a lengthy time, that is, if the groove machining is performed There is another problem with the latter. - Thin, the semiconductor wafer will be easily broken, so that the thickness of the region is processed by the plasma, etc.) The bulk wafer is transported into the vacuum chamber to perform electricity. The purpose is to improve the semi-conductor by shortening the time required for the electric f-knife to reduce the amount of time required for cutting. 4 Dingbao water is used for plasma cutting before reversing the road. Efficiency, while manufacturing methods for semiconductor wafers such as cracks, etc. h body 曰曰0 does not break crystal Hir month, a semiconductor used to obtain a plurality of semiconductor wafers...the method is to divide along the cut line Forming a plurality of semi-conductors on the forming surface of the semiconductor wafer, and separating the private conductor elements from each other, and the semiconductor wafer of the Niu, so that the semi-conducting semiconductor 曰 x x x · 研磨 研磨 研磨 研磨Forming the face of the face of the sun Grinding the resist film forming step of the m μ n + „ -r , * μ浔驭 of the resist film formed on the back surface of the polished film; the result is ^ ^ = removed from the anti-dumping film The groove machine force of the edge region and the edge region of the semiconductor wafer on the anti-drug film side in the semiconductor wafer t direction; Using the anti-surplus agent mask as a mask while electro-polymerizing the semiconductor wafer to remove the semiconductor wafer in its thickness direction along all the residual cutting edge regions of the cut line The steps are made; and the electrical cutting step 3i2XP / invention manual (supplement) /97-02/96150218 ? 200830392 is moved from the semiconductor wafer. ', J 4 film resist film removal step in the patent application Fan Park No. 2 Yin. The method is characterized in the application of:: the manufacture of the body wafer. The method of manufacturing the body wafer, in the trench 2 : Medium: The semiconductor wafer cited is in the thickness direction t along the cutting process, and the semiconductor is 50 to 200 microns. The thickness of the remaining cut area of the garment, " is removed in the semi-conducting edge region, and the semiconductor crystal; the cutting edge of the second will produce any cutting when it is transporting the semiconductor wafer. Edge 2 = Inscribed process and all defects are removed from all cutting edges u, (10) compared to the time required to perform the plasma etching process: electricity:::: cutting and dividing (four) ^ Therefore, according to this hair: two knife:: The time required for semiconductor wafers to transport semiconductors before electroforming can be greatly improved, so that the fabrication of semiconductor wafers can be greatly improved. The anti-caries film is formed on the semi-conducting body 2, so that the free radicals decomposed in the electric atmosphere are concentrated by mechanical cutting 々 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ High-speed plasma surnamed process. This forms the resist thin J and removes the cut edge region while the resist pattern, so that the high cost micro 312XP/invention specification (supplement)/97·〇2/9615〇2ΐ8 ^ 200830392 . Half = in the film:, the semiconductor wafer is cut and divided into a plasma etching process in the cutting stage. This is done by cutting the small damage of the electricity = "0" and forming an anti-film facing surface. When the low-dielectric material layer of the main road of the ruins of the main road is carved on the side of the road, the manufacturing method of the above-mentioned 发 发 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日 日The structure of the (10) cutting device 10 and the electrical equipment processing device 3 in the present invention will be described with reference to FIG. 1 and FIG. 2, and a specific example mode of the present invention will be described with reference to the drawings. The blade y 1G system is configured to include a wafer holding unit η, a conveying plate 13, a blade holding unit 14, a blade conveying mechanism, a blade driving mechanism 17, a wafer conveying mechanism 18, a control unit, and an identification unit. 20 red work / input unit 2 work data storage unit, and congener: components. The wafer holding unit W holds the semiconductor wafer i in a horizontal position to be processed. The conveying plate 12 is disposed above the wafer holding unit 11 in a freely transportable manner. The blade holding unit 14 holds the blade 13 in a manner that is freely rotatable relative to the conveying plate 12+ and in a manner that is rotatable about a horizontal axis of rotation (assuming that the axis extending along the axis of rotation is X-axis). The blade transport mechanism 16 transports the transport plate 12 in addition to the two-phase mechanism 15 being fixed to the transport plate 12. The blade drive mechanism 17 rotatably drives the blade 13. The f-circle transport mechanism 18 transports (including rotates) the wafer holding unit 11. The control unit 19 controls the operation of these mechanisms 16, 17, 18. Identification unit 312XP/Invention manual (supplement)/97-02/96150218 9 200830392 = Image taken by camera 15 executes semiconductor —/ . The working lean storage unit 22 is connected to the control unit 19. • Including fixing/holding the semiconductor wafer 1 to hold 70 pieces such as a vacuum chuck, the semiconductor circle 1 is such that the surface of the guide, 曰m, 卞 卞 _ _ (4) faces toward the blade U Groove 2 holds η: the upper direction is fixed by this, and the holding member is fixed (= main. The blade transport mechanism 16 is along the X-axis direction and the x-axis direction (upper/II" 12-piece hold 14 and the camera 15 Under the control of the single control, the semiconductor linings are in the middle of the semiconductor lining. The blade driving mechanism 13 and the two rotating shafts rotatably drive the blade 13. The Japanese yen conveying mechanism 18 controls That is, 'in the horizontal plane...the direction of intersection=and also causes the wafer holding unit to be placed on/off the Z axis. The camera 15 captures the semiconductor wafer cassette by infrared light. The identification unit 2. is executed based on the camera core The position identification of the semiconductor wafer 1 is followed by the position recognition 19. The positional information about the semiconductor wafer 1 is transmitted to the control unit 19 based on the semiconductor wafer 1 transferred from the identification unit 20. Know the semiconductor wafer i and the knife The operation/input unit 21 responds to the operator 2 = input signal to the control unit 19. The data on the 312XP/invention manual (supplement)/97·〇2/96150218 200830392 cut line 2 has been stored. The cutting line 2 of the working shape constitutes when the f is stored in the early 70 22' and the grid semiconductor wafer is cut by the buffer 1 and divided into individual i (four) whose data has been stored in the work; =, the control unit Controlling the blade 2 relative to both the cutting line feed mechanism 16 and the wafer transfer mechanism 18 in the semi-conductive m-phase element 2 2 with respect to the blade wheel in FIG. 2 'plasma processing 3 〇 upper electrode 33 , high frequency power supply to = square, path 36, oxygen supply unit 37, ^ " / early 35, gas supply - open body supply unit (10), first and ... w丨: valve 4 〇, second open, off The valve 41 and the second-rate valve 42 are formed. Both the lower electrode & and the upper L3 are disposed in the vacuum chamber 31. The high-frequency power supply unit 34 is paired; the square ^=3 shield 2 is twisted with a frequency. The cooling unit 35 causes the coolant to be in the lower electrode. The supply path 36 is extended from the inside of the vacuum chamber 31 from the upper electrode. The gas supply unit 37 is connected to the side of the branch gas supply path (10), which is referred to as a "first branch path" (hereinafter referred to as "first branch path coffee"). The gas series gas supply unit 38 is connected. The other side branch (which will be referred to as "second branch path") connected to the branch gas supply path 36. The first stage 3; and the first flow rate control valve 40 are interposed in the first branch. In the path 36 & both the first on/off valve 41 and the second flow rate control valve 42 are interposed in the second branch path 36b. The internal space of the vacuum chamber 31 is provided as a tightly closed space for the plasma processing operation of the semiconductor wafer. The lower electrode is tied to the upper part of the 312XP/invention manual (supplement)/97-〇2/96150218 \\ 200830392 conductor wafer, and the upper refining winter flight 17 is placed next to it. The upper surface of the upper electrode 33 is disposed opposite to the upper side of the second electrode: the upper side of the electrode 32. The second aspect of the chamber is to be constructed by a vacuum chuck and an electrostatic suction mechanism. The structure (not in the order) and the calori-filling holder made of electrically insulating material are disposed on the lower electrode 32, the '32', the semiconductor wafer 1 The face of the / 仃 仃 仃 仃 仃 仃 且 且 且 且 且 仃 仃 仃 仃 仃 仃 仃 仃 仃 仃 仃 仃 仃 仃 仃 。 。 。 The second aspect of the opening/closing valve 41 is closed when the oxygen is fixed (or the main gas is filled into the oxygen supply unit 37). The gas supply path (4) is supplied to the upper electrode 33. The oxygen is supplied from the oxygen supply unit by the control valve at the opening degree: the two-pole charge is further 'when the fluorine series gas (for example, six (four)th H is supplied to the unit 3 δ), the gas series system is in the middle-opening When the valve 41 is opened (the first opening and the closing valve 39 is closed), it is supplied to the upper electrode 33 via the second branch path 36b and the gas supply path 36. The fluorine series gas is adjusted by controlling the opening degree of the second flow rate control valve 42. The flow rate of the fluorine-based gas supply unit 38 to the upper electrode 33. When the porous plate 33a having a flat plate shape is provided on the upper electrode 33, the oxygen gas and the fluorine-based gas supplied through the gas supply path 36 pass through The perforated plate 33a is uniformly sprayed on the upper surface of the lower electrode 32. 312XP/Invention Manual (Replenishment)/97-〇2/96150218 12 200830392 Next, the flow chart of FIG. 3 and FIG. 4 and FIG. And the method of manufacturing the semiconductor wafer in FIG. 6 illustrates the method of manufacturing the semiconductor wafer. The electrical material layer 3 is disposed on the circuit formation surface lp of the semiconductor wafer 1 and has been used in the case where the low dielectric material layer 3 is used as the insulating layer. Circuit strip, on the face lp A plurality of semiconductor elements 4 (Fig. 4(a)). As explained earlier, the conductor wafers of the conductor elements 4 which have been formed on the circuit forming surface 1P by the dividing line 2 are conductors The pieces 4 are divided from each other to obtain a plurality of semiconductor crystals, (FIG. 6(d)) 'Firstly' as shown in FIG. 4(b), a sheet-like protective tape (for example, UV tape) having adhesive properties is used. 5 is adhered to the semiconductor wafer k circuit forming surface lp (protective tape adhesion step S1 shown in Fig. 3). After the protective tape adhesion step S1 is completed, as shown in Fig. 4(c), the semiconductor is polished by the back grinding device 50. The back surface lq of the wafer i ((the lunar surface polishing step S2 shown in Fig. 3). The back surface is formed to face the circuit forming surface. The surface polishing apparatus 50 is provided by the rotating table 51 and the rotating table 51. The rotary grinder 52 is configured to be mounted on the turntable 51 such that the back surface of the semiconductor wafer 1 faces upward. When the semiconductor wafer 1 is mounted on the rotary stage 51, The rotary grinder 52 is pressed down from the top to the back surface lq of the semiconductor wafer 1 (Fig. 4(c)
•中所不之前頭「A」）。此外，當旋轉台51及旋轉研磨機 52分別環繞上方軸及下方軸旋轉（圖4(c)中所示之箭頭B 及C)時’旋轉研磨機52於水平面内擺動（圖4(c)中所示 之前頭D)。結果，半導體晶圓1之背面lq被研磨，以致 半導體晶圓1之厚度比大約6〇〇至15〇微米還薄。應暸解 312XP/發明說明書(補件)/97-02/96150218 13 200830392 =於在月面lq經研磨後將此—具有大约工微米深度之受 =(即’尚未由單晶製得之層）形成於半導體晶圓1之此 二17而要對自背面研磨裝置5°拆下之半導體晶圓 、月1q進打拋光處理或電漿蝕刻處理，以移除 層。 4只 於完成背面研磨步驟§2後，如圖5(a)所示， :則_形成於半導體晶圓1之背面(圖；中所 =抗形成步驟S3)。此抗兹劑薄膜6在稍後 將進灯的黾漿切製步驟S6中作為遮罩。 署：完f充飯劑薄膜形成步驟幻後，將半導體晶圓！褒 雕广片切割裝置10的晶圓固持單元11上。此時，半導 版曰曰圓1係以使經形成抗飿劑薄膜6之背面上 i立在/口切製線2之沿此抗餘劑薄膜6之厚产方 向劑薄膜6的所有切割邊緣區· 6a : ==半導體晶圓i之厚度方向之半導體晶圓= 區域la的部分lb，以將其移除(圖”斤 心加工步驟S4)。上述切割邊緣區域&之部分 劑！膜6之側上、结果’半導體晶圓1達到半導 错由沿切製線2之切割邊緣區域18内之殘餘切 :之緣區域1c而沿半導體晶圓1之面内方向連接，同時 刀糾邊緣區域㈣留於低介電物質層3之側上的狀能。 312XP/發明說明書(補件)/97-02/96150218 作Ϊ:情況’如先前所述’當將切製線2之資料儲存於工 乍貝料储存單it 22中時，控制單元19基於儲存於此工作 200830392 資料儲存單元22中之切製線2之資 拍攝所取得之半導體晶圓丨之位、，及經由照相機15之 晶圓固持單元U兩者(即，輪送刀:,送該輸送板12及 兩者)。由於晶圓固持單元11係在旋韓刀，半導體晶圓1 晶圓1接觸的情況下沿¥軸方向輪、关耔刀片〗3與半導體 行設置之-切製線2進行溝槽機工因：可沿與Y軸平 器加工係經由彼此組合兩種輸送模式而果’此溝槽機 沿以格栅形狀排列之所有切製線2的溝样：=致可進行 之，在一種輸送模式中，沿χ轴方向加=換言 ζ軸旋轉90度角。 、'中使晶圓固持單元η繞 二==加工步驟s”，沿切製線 脰日日圓1之尽度方向之丰導辦曰 守 1 h r产「 體日日0 1之殘餘切自J邊绫F奸 靖度「t」(參照圖5(c))成為大約50至2=域 ，明瞭50微未至2QG微米之厚度值係等於可確 度之值’藉此在於前述溝槽機器加工步驟5成=進 =晶圓帶入步驟S”(即，在將半導體晶圓4 = 至31中之步㈣中)不會產生問題。如厚度變得小；前 述厚度範圍（50至200微米），則會有輪送中之半導體晶 圓、1破裂的風險。如厚度變得大於前述厚度範圍，則會i曰 於：槽機器加工步驟S4後執行電漿蝕刻製程(電漿切製 步驟=)所需之時間延長的不便可能性。亦應注意在此溝 槽機器加工步驟S4中，沿切製線2的抗餘劑薄膜6被移 除。因此，恰於殘留的抗餘劑薄膜6上形成電漿餘刻製程 312XP/發明說明書(補件)/97-〇2/96150218 15 200830392 (稱後即將進行）中所需的抗蝕劑圖案。 於溝槽機态加工步驟S4完成後，將半導體晶圓1自刀 片切割裝置10之晶圓固持單元丨丨卸下’且將卸下的半導 •體晶圓1帶入至電漿處理裝置3()之真空室31中，隨後將 -半導體晶圓1固定於下方電極32之上方面上（圖3所示之 晶圓帶入步驟S 5)。此時，半導體晶圓i係以使經形成抗 蝕劑薄膜6之背面iq方向朝上的方式設置。 於晶圓帶入步驟S5完成後，在將抗蝕劑薄膜6使用作 攀為遮罩的同時，經由相對於半導體晶圓}傳送I系列氣體 而進行电水钮刻製程操作（圖3所示之電漿切製步驟％) 〇 在前述之電㈣製步驟S6中，首先在關閉第一開/關 閥⑽的狀況下打開第二開^/關閥4卜以將氣系列氣體自 氟系列氣體供給單元38供給至上方電極33。因此，氟系 列氣體自上方電極33經由多孔板33a喷灑於半導體晶圓 1之上方面上。當於此狀況下驅動高頻供電單元34，以對 φ下方電極32施加高頻電壓時，於下方電極32與上方電極 33之間產生氟系列氣體之電漿Pf(圖6(a))。 所產生之氟系列氣體之電漿pf自抗蝕劑薄膜6經於溝 槽機器加工步驟S4中移除之部分開始蝕刻半導體晶圓 • 1 °結果’半導體晶圓1沿切製線2之厚度方向的所有殘 餘切割邊緣區域移除，同時此等殘餘切割邊緣區域係對應 於半導體晶圓1之厚度方向的切割邊緣區域lc及低介電 物質層3沿其厚度方向的切割邊緣區域％兩者。接著以 批次方式沿切製線2將半導體晶圓1切割為具有抗餘劑薄 312XP/發明說明書(補件)/97·〇2/9615〇218 16 200830392 膜6的個別半導體晶片丨，（見圖6(b))。亦應明瞭在經由 傳送氟系列氣體之電漿Pf而進行半導體晶圓丨之蝕刻製 程的同時，驅動冷卻單元35以使冷卻劑於下方電極犯= 循環而避免此半導體晶圓1之溫度因電漿pf之熱而提高。• The head "A" is not in the middle. Further, when the rotary table 51 and the rotary grinder 52 are rotated around the upper and lower shafts respectively (arrows B and C shown in FIG. 4(c)), the rotary grinder 52 is swung in the horizontal plane (FIG. 4(c) Before the head D) is shown. As a result, the back surface lq of the semiconductor wafer 1 is ground so that the thickness of the semiconductor wafer 1 is thinner than about 6 Å to 15 Å. It should be understood that 312XP / invention manual (supplement) /97-02/96150218 13 200830392 = after grinding on the lunar surface lq - this has a micron depth of about = (ie 'layer not yet made of single crystal") The semiconductor wafer 1 is formed on the semiconductor wafer 1 and the semiconductor wafer removed from the backside polishing apparatus is subjected to a polishing treatment or a plasma etching treatment to remove the layer. 4 After completing the back grinding step § 2, as shown in Fig. 5(a), : is formed on the back surface of the semiconductor wafer 1 (Fig. 1; anti-forming step S3). This resist film 6 is used as a mask in the slurry cutting step S6 of the lamp to be introduced later. Department: After the f-filler film formation step magic, the semiconductor wafer will be!雕 Engraving the wafer holding unit 11 of the multi-chip cutting device 10. At this time, the semi-guide plate is rounded so that all the cuts of the thick-oriented film 6 along the anti-removal film 6 on the back surface of the anti-caries film 6 are formed. Edge region · 6a : = = semiconductor wafer in the thickness direction of the semiconductor wafer i = portion lb of the region la to remove it (Fig. "Spinning step S4). Part of the cutting edge region & On the side of the film 6, the result 'the semiconductor wafer 1 reaches the semi-deformation is connected in the in-plane direction of the semiconductor wafer 1 by the residual cut: edge region 1c in the cut edge region 18 along the cut line 2, while the knife Correcting the edge region (4) The shape energy remaining on the side of the low dielectric material layer 3. 312XP/Invention Manual (Supplement)/97-02/96150218 Ϊ: The situation 'as previously described' when the cutting line 2 When the data is stored in the workbill storage unit it 22, the control unit 19 captures the position of the semiconductor wafer obtained based on the cut line 2 stored in the work storage unit 22 of the work 200830392, and via the camera. 15 wafer holding unit U (ie, the transfer knife:, the transport plate 12 and both). Because of wafer holding In the case where the semiconductor wafer 1 is in contact with the semiconductor wafer 1 and the wafer 1 is in contact with the wafer, the groove is arranged along the axis of the shaft, the blade 3 and the line 2 of the semiconductor line. The leveling machine is processed by combining the two conveying modes with each other. The groove machine is along the groove of all the cutting lines 2 arranged in the shape of the grid: = can be performed, in one conveying mode, along the boring axis Direction plus = in other words, the ζ axis is rotated by 90 degrees. , 'The wafer holding unit η is wound around two == processing step s', along the cutting line, the day of the Japanese yen 1 is in the direction of the 1st hr "The residual of 0 1 on the body day is cut from the J edge and the degree "t" (see Fig. 5(c)) becomes about 50 to 2 = domain. It is clear that the thickness value of 50 micrometers to 2QG micrometers is equal to the accuracy. The value 'in this is because the aforementioned groove machining step 5 == wafer is brought into step S" (ie, in the step (4) of the semiconductor wafer 4 = to 31), such as thickness change Smaller; the aforementioned thickness range (50 to 200 microns) will have the risk of rupturing the semiconductor wafer in the turn. If the thickness becomes larger than the aforementioned thickness range The possibility of extending the time required for the plasma etching process (plasma cutting step =) after the slot machining step S4 is extended. It should also be noted that in the groove machining step S4, the cutting is performed. The anti-surplus film 6 of the line 2 is removed. Therefore, a plasma remnant process 312XP/invention specification (supplement)/97-〇2/96150218 15 200830392 is formed on the residual anti-surplus film 6 The resist pattern required in the next step. After the trench processing step S4 is completed, the semiconductor wafer 1 is unloaded from the wafer holding unit of the blade cutting device 10 and the half to be removed is removed. The wafer 1 is brought into the vacuum chamber 31 of the plasma processing apparatus 3 (), and then the semiconductor wafer 1 is fixed on the lower electrode 32 (the wafer shown in FIG. 3 is brought to step S). 5). At this time, the semiconductor wafer i is disposed such that the back surface iq of the resist film 6 is formed to face upward. After the wafer is brought into step S5, the resist film 6 is used as a mask, and the electro-hydraulic button process is performed by transferring the I-series gas with respect to the semiconductor wafer. Plasma cutting step %) 〇 In the aforementioned electric (4) manufacturing step S6, firstly, the second opening/closing valve 4 is opened under the condition that the first opening/closing valve (10) is closed to select the gas series gas from the fluorine series. The gas supply unit 38 is supplied to the upper electrode 33. Therefore, the fluorine-based gas is sprayed from the upper electrode 33 onto the semiconductor wafer 1 via the porous plate 33a. When the high-frequency power supply unit 34 is driven in this state, a high-frequency voltage is applied to the lower electrode 32 of φ, and a plasma Pf of a fluorine-based gas is generated between the lower electrode 32 and the upper electrode 33 (Fig. 6(a)). The plasma pf of the generated fluorine series gas is etched from the resist film 6 through the portion removed in the groove machining step S4. 1 ° result 'The thickness of the semiconductor wafer 1 along the cut line 2 All residual cutting edge regions of the direction are removed, and such residual cutting edge regions are both the cutting edge region lc corresponding to the thickness direction of the semiconductor wafer 1 and the cutting edge region % of the low dielectric material layer 3 along the thickness direction thereof. . The semiconductor wafer 1 is then cut along the cut line 2 in batches into individual semiconductor wafers 具有 with anti-reagent thin 312XP/invention specification (supplement)/97·〇2/9615〇218 16 200830392 film 6 ( See Figure 6(b)). It should also be understood that while the etching process of the semiconductor wafer is performed by transferring the plasma Pf of the fluorine-based gas, the cooling unit 35 is driven to cause the coolant to circulate at the lower electrode to avoid the temperature of the semiconductor wafer 1 due to electricity. The heat of the pulp pf is increased.
於電漿切製步驟S6完成後，接著於真空室31 ”内產生I 氣之電tPo,以將於圖3所示之抗蝕劑薄膜移除步驟= 中殘留於半導體晶圓1(即，各別之經切割及分割開之半 導體晶片Γ經由保護膠¢5而彼此相連的晶圓狀態）之 上方面（背面lq)上之抗蝕劑薄膜6的灰分移除。 為進行此灰分移除操作，首先在第二開/_ 41 的狀態下打開第-開/關閥39，以將氧氣自氧氣供仏單 元37供給至上方電極33。因此，氧氣自上方電極二, 由多孔板33a喷灑於半導體晶圓i之上方面上。當於此= 二下驅動高頻供電單元34’以對下方電極32施加高頻带 壓時，於下方電極32與上方電極33之間產生氧氣之電； P义'6(c))。此氧氣之電漿_目當於有機物體之抗蝕 广專，6灰化’以致自（各半導體晶片i，之）半導體晶圓 1 =月面lq移除抗蝕劑薄膜6(參照圖6(d))。亦應注音 在丽述的抗钮劑薄膜移除步驟S7中，在經由傳: 電漿Po而進行抗蝕劑薄膜6之灰化移除操作的同 以使冷卻劑於下方電極32内循環而避免此 丰V體Β曰囫1之溫度因電漿ρ〇之熱而提高。 ’將半導體晶圓 經由UV膠帶5 於抗蝕劑薄膜6之灰分完全移除後 1(即，經切割及分割開之半導體晶片1， 312ΧΡ/發明說明書(補件)/97·〇裏15〇218 17 200830392 彼此相連的半導體晶圓狀態）自真空室3ι 中所指示之晶圓帶出步驟S8)。 ㈣出來(圖3 因此’完成半導體晶片Γ的製造操作， 晶圓1自真空室31輸送出來後，若將黏著於半導^體 1之電路形成面lp上的保護膠帶5拉伸，則緩切二圓 =之半導體晶片r τ達到使此等半導體晶片i,彼: 为離的狀態。接著若保護膠帶5係為uv膠 〜 夕:射線照射於此保護膠帶5上時，此 , 如务‘併、十.—日日片 可谷易地自保護膠帶5剝落。 ’在根據本具體例模式的半導體晶片之势迭 背面Γ :將:’侧膜6形成於半導體晶圓1之經研磨 制/之4 ，藉由相當於機械切割裝置的刀片13將、、八 之部分的切割邊緣區域(一、 ： 二=除’且使半導體晶圓1沿其厚度方向 晶圓料會nr’其在輸送半導體 程而將所古从U 其後經由執行電漿钱刻製 〜：t 割邊緣區域(1。、如)移除。因此，與 二c Γ二漿崎程將所有的切割邊緣區域(6 a、 時間相比二除而4切副及分割開半導體晶圓1時所需的 根製中所需的時間可大大罐。因此， 電聚切製之前輸送半導：？;曰製造方法，在當在進行 同時，可縮短電聚切製：:=半導體晶圓1未破裂的 導體晶片r的製造效率。而㈣間，以致可大大地改良半 2ΧΡ/__β_件)/97-G2/96150218 18 200830392 導=圓由二製將抗_薄膜6形成於半 …進订’因而於電漿大氣内分解之白ώ茸 體晶圓1之經機械切割，移除部分的附近，： 二刻速：(例如，至25微米〜)可獲得二二 因^ ’可只現尚速電漿韻刻製程。此外，在利用 切吾·!及移除切割邊緣區域的同時形成抗 膜 ，劑圖案，以致不再需要高成本的 =6= 未將抗_薄膜6形成於半導 在:二= 籲刀片^沿切製線2切割及移除半導體晶们之即使當f用 id)的-部分，其後再進行 /面（月面 、·泉切衣+ ¥體晶圓i(前述之專利公告D 況，於電漿大氣内分解之自由基不 :=在私 夕铖77 H 1Q丄~ 土个1里刀政於+導體晶圓1 ，，二刀片13切副及移除的部分附近，並 體晶圓1之整個表面（整個背面lq)。 :刀=於h ⑽刻速率成為2微米/分鐘，即變;相當t晶圓1 此外，在於最終切割階段中將半導體晶圓B 為+導體晶片i’的情況中，此切割操 ：：二 小的:裝_處理進行。結果，如本具體例模』 ，田切狀分割半導體晶圓i且此半導體晶圓1於盆之 U成抗蝕劑薄膜6之面對置之 二 層3時，前述之本 牛V體阳片之製造方法變得尤其有利。 (工業應用性） 在半導體W之製造方法中，在t在進行電襞切製之前 312XP/發明說明書(補件)/9742/96150218 19 200830392 半導體晶圓未破裂的同時，可縮短電聚 ^所而的_，以致可大大地改良半導體晶片的製造效 •=物系以2005年12月26曰提出申請之曰本專利 二㈣6-3侧號為基礎並主張其之優先權利，將 Μ扁專利之全體内容併入本文為參考資料。 【圖式簡單說明】 ^ 1係'於本發明之—具體·式中使用之刀片 _置的透視圖。 圖2係於本發明之具體例模式中使用之 的剖面圖。 包κ处I衣罝 圖、3係描述根據本發明之具體例模式製造半導體晶片 之方法之步驟順序的流程圖。 圖4(a)至（d)係說明根據本發明之具體例模式之半導體 晶片之製造方法的步驟說明圖。 曰曰 圖5(a)至（c)係說明根據本發明之具體例模式之半導體 片之製造方法的步驟說明圖。 圖6(a)至（d)係說明根據本發明之具體例模式之半導體 片之製造方法的步驟說明圖。 主要元件符號說明】 曰曰 1 半導體晶圓 1， 半導體晶片 la 切割邊緣區域 lb 切軎彳邊緣區域之部分 312XP/發明說明書(補件)/97-02/96150218 20 200830392 1 c 殘餘切割邊緣區域 Ip 半導體晶圓1之電, lq 半導體晶圓1之背 2 格栅形狀之切製線 3 低介電物質層 3a 低介電物質層之切 4 半導體元件 5 片狀保護膠帶 6 感光性抗钱劑薄膜 6a 切割邊緣區域 10 刀片切割裝置 11 晶圓固持單元 12 輸送板 13 刀片 14 刀片固持單元 15 照相機 16 刀片輸送機構 17 刀片驅動機構 18 晶圓輸送機構 19 控制單元 20 識別單元 21 操作/輸入單元 22 工作資料儲存單元 30 電漿處理裝置 312XP/發明說明書(補件)/97-02/96150218 21 200830392 31 真空室 32 下方電極 32a 環形框架 33 上方電極 33a 多孔板 34 高頻供電單元 35 冷卻單元 36 氣體供給路徑 36a 第一分支路徑 36b 第二分支路徑 37 氧氣供給單元 38 氟系列氣體供給單元 39 第一開/關閥 40 第一流率控制閥 41 第二開/關闊 42 第二流率控制閥 50 背面研磨裝置 51 旋轉台 52 旋轉研磨機 A 箭頭 B 箭頭 C 箭頭 D 箭頭 Pf 氟系列氣體之電漿 312XP/發明說明書(補件)/97-02/96150218 22 200830392After the plasma cutting step S6 is completed, the electric power tPo of the I gas is generated in the vacuum chamber 31" to remain in the semiconductor wafer 1 in the resist film removing step = shown in FIG. 3 (ie, The ash of the resist film 6 on the upper side (back surface lq) of the separately cut and divided semiconductor wafers connected to each other via the protective paste 5) is removed. In operation, first, the first on/off valve 39 is opened in the state of the second opening /_41 to supply oxygen from the oxygen supply unit 37 to the upper electrode 33. Therefore, oxygen is ejected from the upper electrode 2 by the perforated plate 33a. Sprinkling on the semiconductor wafer i. When the high frequency power supply unit 34' is driven to apply a high frequency band voltage to the lower electrode 32, oxygen is generated between the lower electrode 32 and the upper electrode 33. P meaning '6(c)). This oxygen plasma _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In addition to the resist film 6 (refer to Fig. 6 (d)), it should also be phonetic in the anti-button film removal step S7 of the reference, in the pass : The plasma ash Po is subjected to the ashing removal operation of the resist film 6 so that the coolant circulates in the lower electrode 32 to prevent the temperature of the swelled V body Β曰囫1 from being increased by the heat of the plasma 〇 'The semiconductor wafer is completely removed by the ash of the resist film 6 via the UV tape 5 (ie, the cut and divided semiconductor wafer 1, 312 ΧΡ / invention specification (supplement) / 97·〇里15 〇 218 17 200830392 The state of the semiconductor wafer connected to each other) is carried out from the wafer indicated in the vacuum chamber 3 to step S8). (4) Come out (Fig. 3 thus 'finishing the manufacturing operation of the semiconductor wafer cassette, the wafer 1 from the vacuum chamber 31 After the conveyance is performed, if the protective tape 5 adhered to the circuit forming surface lp of the semiconductor body 1 is stretched, the semiconductor wafer r τ of the slow-cutting two-circle = is reached so that the semiconductor wafers i are separated from each other. Then, if the protective tape 5 is made of uv glue ~ eve: when the radiation is irradiated on the protective tape 5, this, if the service 'and, ten. - Japanese film can be peeled off from the protective tape 5. The potential back surface of the semiconductor wafer of this specific example mode: will: 'the side film 6 is formed in the semiconductor The wafer 1 is ground/4, by the blade 13 corresponding to the mechanical cutting device, and the cutting edge region of the portion of the eight (1, 2 = divided 'and the semiconductor wafer 1 is crystallized along its thickness direction) The round material will be nr' which is in the process of transporting the semiconductor and will be removed from the U by the execution of the plasma money to cut the ::t edge region (1., such as). Therefore, with the two c Γ 二浆崎程The time required for all the cutting edge regions (6 a, time divided by 2, and 4 cuts and divided into semiconductor wafers 1) can be greatly increased. Therefore, half of the transport is performed before electroforming. The manufacturing method of the germanium wafer can be shortened while the material is being processed:: = manufacturing efficiency of the semiconductor wafer 1 without breaking the conductor wafer r. And (4), so that the semi-two ΧΡ/__β_ pieces can be greatly improved) /97-G2/96150218 18 200830392 Guide = round by the two system of anti-film 6 formed in the half ... booked 'and thus decomposed in the plasma atmosphere The white velvet body wafer 1 is mechanically cut and removed from the vicinity of the part: 2 speed: (for example, to 25 microns ~) to obtain the second two factors ^ 'can only be the speed of the plasma rhyme process. In addition, the anti-film and agent patterns are formed at the same time as the cutting edge region is removed, so that the high cost is no longer required = 6 = the anti-film 6 is not formed in the semi-conducting at: two = yaw blade ^ Cutting and removing the semiconductor crystals along the cutting line 2 even when f is the part of id), and then performing / surface (moon surface, · spring cutting + ¥ body wafer i (the aforementioned patent announcement D status) , the free radicals decomposed in the plasma atmosphere are not: = in the private 铖 77 H 1Q 丄 ~ soil 1 knives in the + conductor wafer 1, the second blade 13 cut and removed parts, and body The entire surface of the wafer 1 (the entire back surface lq). : Knife = at h (10), the rate becomes 2 μm / min, that is, change; equivalent t wafer 1 In addition, the semiconductor wafer B is a + conductor wafer in the final cutting stage. In the case of i', the cutting operation: two small: loading_processing proceeds. As a result, as in the specific example, the semiconductor wafer i is segmented and the semiconductor wafer 1 is in the basin. When the film 6 faces the two layers 3, the aforementioned manufacturing method of the cow V body positive sheet becomes particularly advantageous. (Industrial Applicability) In the semiconductor W In the manufacturing method, before the electric cutting is performed, 312XP/Invention Manual (Supplement)/9742/96150218 19 200830392 The semiconductor wafer is not broken, and the electropolymerization can be shortened, so that it can be greatly improved. The manufacturing efficiency of the semiconductor wafers == The system is based on the second paragraph of the patent (2) 6-3 of the application filed on December 26, 2005 and claims its priority rights. The entire contents of the patent are incorporated herein by reference. BRIEF DESCRIPTION OF THE DRAWINGS [1] A perspective view of a blade used in the present invention - a specific embodiment of the present invention. Fig. 2 is a cross-sectional view used in a specific example mode of the present invention. FIG. 4(a) to (d) illustrate a method of manufacturing a semiconductor wafer according to a specific example mode of the present invention. FIG. 4(a) to (d) are diagrams showing a procedure for manufacturing a semiconductor wafer according to a specific example mode of the present invention. 5(a) to (c) are diagrams illustrating the steps of a method of manufacturing a semiconductor wafer according to a specific example mode of the present invention. Figs. 6(a) to (d) are diagrams illustrating the present invention. The specific example mode of the semiconductor chip system Description of the steps of the method. Description of the main components: 曰曰1 Semiconductor wafer 1, semiconductor wafer la Cutting edge region lb Cutting edge region 312XP/Invention manual (supplement)/97-02/96150218 20 200830392 1 c Residual cut edge area Ip Semiconductor wafer 1 power, lq Semiconductor wafer 1 back 2 Grid shaped cut line 3 Low dielectric material layer 3a Low dielectric material layer cut 4 Semiconductor component 5 Sheet protective tape 6 Photoreceptor film 6a Cutting edge area 10 Blade cutting device 11 Wafer holding unit 12 Conveying plate 13 Blade 14 Blade holding unit 15 Camera 16 Blade conveying mechanism 17 Blade driving mechanism 18 Wafer conveying mechanism 19 Control unit 20 Identification unit 21 operation/input unit 22 working data storage unit 30 plasma processing device 312XP/invention specification (supplement)/97-02/96150218 21 200830392 31 vacuum chamber 32 lower electrode 32a annular frame 33 upper electrode 33a perforated plate 34 high frequency power supply Unit 35 cooling unit 36 gas supply path 36a first branch path 36b second Branch path 37 oxygen supply unit 38 fluorine series gas supply unit 39 first on/off valve 40 first flow rate control valve 41 second opening/closing width 42 second flow rate control valve 50 back grinding device 51 rotary table 52 rotary grinding machine A arrow B arrow C arrow D arrow Pf fluorine series gas plasma 312XP / invention manual (supplement) /97-02/96150218 22 200830392
Po 氧氣之電漿 t 殘餘切割邊緣區域lc之厚度 23 312XP/發明說明書(補件)/97-02/96150218Po Oxygen plasma t Thickness of residual cut edge area lc 23 312XP/Invention manual (supplement)/97-02/96150218