TW200828022A - System and method for implementing a single-wire serial protocol - Google Patents

Abstract

A method and apparatus for a single-wire serial communication includes defining a predetermined short pulse as data and a predetermined long pulse as a data separator. A method of arbitrating between multiple controllers in a serial communication includes interchanging the role of a controller and a receiver; defining said controller as idle if its communication line has no transition for a predetermined interval of inactivity; and addressing listening controllers using a presiding controller so as to poll and select a next controller to preside through an addressed instruction packet. A single wire serial communication system comprising a controller that operates as a transmitter when said controller includes a strong drive only.

Description

200828022 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to the field of systems, and more particularly to electronic serial communication systems. [Prior Art] Circuits of modern electronic reading gradually require higher-level functions, and (often, circuits with communication ports are often used to set critical parameters. Although high-level functions are required, many traditional applications often use only one or Two tubes (pm) are used for control. For example, the _ pin interface is usually used as a single line in the hinge area of a very space-critical, compact telephone. The new-generation components of these traditional applications must also Still using one or two squadrons as the interface. In the single-line string warping, the mode must be transmitted: secret polarity and data μ. In order to achieve this, some known single-line serial communication protocol c uses pulses. In these protocols, a pulse pattern separated by a pause is received, and the receiver counts the pulse after the pause. The count value ρ is the value of the pulse packet. The repeated pattern sends a plurality of values to the receiver to use ^ Handling D commands. However, the counting pulse itself is an inefficient technique. - Some other protocols include pulse width modulation to distinguish between high and low duty cycles. Low. In a circuit that requires duty cycle resolution, it is necessary to measure the difference between high and low in the measurement of the period and pulse width. These methods require the entire period of duty cycle estimation, and these The square ^ is inherently less efficient. A typical prior art single-wire interface protocol requires a relatively large number of complex 6 200828022 private paths. The following describes a preferred single-line serial protocol that can be effectively implemented. The system, the device and the method are described and illustrated. In addition to the aspects of the invention described in the section of the disclosure, other aspects of the invention may be made by referring to the figures and reading the following detailed description. It is clear that a method and apparatus for single-line serial communication includes: defining a predetermined short pulse as data and a predetermined long pulse as a data separator. In the method, it also includes · when transmitting continuous data of the same polarity When pulsed, only one of the data separators is provided between the consecutive data pulses; and when the transmission polarity is In the case of a continuous data pulse, no data separation symbol is provided between consecutive data pulses of alternating polarity. In the method, the predetermined short pulse includes a minimum width and a maximum width for defining a pulse width U acceptable width. And the lengthwise pulse includes a minimum width, and optionally includes a maximum width if a rest interval is used. In the method, the serial communication includes a combination of a strong and weak controller drive and only a strong controller drive. In the method, the serial communication further includes a receiver that directly drives the communication line when the controller uses a strong drive and a weak drive' or uses the strong drive and current or The communication line is indirectly driven by the controller of the voltage sensor; wherein the "pass" of the line by the receiver includes the shredding and response. 7 200828022 In this method, the A long pulse terminator further comprising two consecutive long pulses as an optional = terminator. In the method, the serial communication further includes: after the controller transmits the double long pulse of the double, pulse terminator, confirming the packet communication by directly or indirectly flipping the polarity of the second long pulse Termination of the second long pulse; and when the two receivers are not successfully acknowledged within the waiting interval, the controller is forced to change the polarity of the second long pulse. In the method, further comprising: transmitting the data to the plurality of devices and the selected one of the controllers by using the main controller; using the main controller developed in the double long pulse terminator (four)-pulse, so that The receiver can change the polarity to the second long pulse; and the master controller can use the same controller to clear the same protocol until the receiver receives the double long pulse terminator. In the method of reprinting ίί, it also includes the direct indirect side assistance from the selected receiver. The indirect drive of the office is sufficient to read the information and read the information until it is obtained. The rush termination is terminated, or is interrupted by the selected receiver to the occurrence of the double long pulse terminator, or the qing qing pulse terminator is used in conjunction with the strong and weak drive in the " method The meter 8 200828022 describes short pulses and premature changes in the long pulses. In the method, the main controller uses the selected ::::Γ to thereby make the end of the agreement _ _ _ _ _ _ _ _

In the =, ::_, between the multiple controllers, the idle = t: there is a transition, then the controller is defined as the addressed instruction packet for control. h response from the takeover control (four) takeover command, in 雔 ==:, pulse Exact TM in the financial law 'the control · including the fine button, its t is longer than the financial cessation _ the general control _ drive to keep New polarity. After the interval, try to lightly record by using a weak drive = change I - control, and the competition V:!;:!^ r having the longest time interval is purely long; and changing the line polarity === side in the failure to pass the compensated crane犹姆__Next Rest In this method, the main controller maintains the line polarity 'ignoring arbitration 9 200828022 以及 test and the readout current from the I brother controller disappears, or by transmitting long pulses (4) Try to stop the release control. The present invention also provides a single-line serial communication system including a controller. When the control n includes only a strong drive, the control (4) acts as a transmitter. (

In the system, the controller acts as the transmitter and receiver when the controller includes the strong drive and current or voltage sense corrections. In the system, when the controller includes the strong drive and a weak drive, the controller functions as the transmitter and the receiver, and the receiver includes a weaker than the strong drive red cake The intermediate drive of the weak crane, the two-degree address of the corps, or the unreceivable reception = the receiver is the unaddressable receiver, the reception = sleepy f,; (d) The connection (4) is the receiver of the button, and the receiver is a dormant receiver or an acknowledge receiver. The step further comprises a non-return receiver or a readback receiver Cui for the serial communication system. Including: a timer, a clock domain for data with a jr pulse, and a non-clock signal with a 4-separated symbol; ::= to r to the object, based on the low pulse = two = ^ =: „ and the low pulse width identifier to determine the received pulse 200828022 is the data separator symbol. = system =, the timer advance step includes: the first - bistable multi-vibration " ' Used to store the high-frequency pulse discs that appear, crying with u, smashing six scorpions, and knowing the sounds of 夕, 夕: the low-long pulse of ==; and combinatorial logic Road for two terminator = long pulse from the first - spectrum oscillation σσ flip-Di Cloth the second flip-flop.

ί [Embodiment] ° ° 2 Ming provides - a method and equipment for the inspection of single-line string assignments. The specific actual wealth of this 曰 了 本 本 本 本 本 本 本 本 本 本 本 本 四 本 本 本 本 四 四 四 四 四 四 四 四 四 四 四In the following description I, for a better description, the specific details of the report are set forth to provide a comprehensive understanding of the pair. However, it will be apparent to those skilled in the art that, in the absence of these specific details, the present invention may still be described in the specification as "an embodiment," or "embodiment," Specific specific features associated with the embodiments of the embodiments of the invention. The phrase "in one embodiment" or "in some embodiments," does not denote the same embodiment, and is not independently or exclusively present in other embodiments. The protocol can be used for any device that transmits data between the controller and the receiver, and the receiver can be any device that receives the data. This protocol can also be used for controllers and devices that can receive data. Receiver of the data transmission. The information mentioned here is used to represent any information, = including but not limited to instructions, commands, codes, addresses or any other information represented by the binary code 200828022. Basic Principles This Agreement provides: Short A pulse of a predetermined width is considered to be a data pulse. A pulse longer than the predetermined width is ignored. Therefore, a data pulse whose pulse width is within a pre-turn degree is represented as a significant bit value, and a pulse width greater than a pre-turn width is expressed as The bit value is ignored. The high and low polarities of the short pulses accepted as data are respectively determined to be high or low. If the long pulse is long enough, it is considered not to be The pulse does not take into account its height. Some implementations also support the use of two long pulses at the end as terminators. Since there is no need to have two long pulses in the data communication protocol, two consecutive ignore bit values can be used. The sequence is used as a communication terminator. Figure 1 shows the basic data model of the protocol. Figure 1 shows the transmission model with maximum pulse width communication. The transition at the beginning 100 can be used to set the logical polarity of the first data pulse. As described above, the reception can be set to ignore a transition having its previous width greater than the audibility. In the example of Figure 1, the first short pulse is a high pulse. The short high pulse is at the receiver. Record the south by clock in the shift register. In order to avoid recording the low value by clock after the ,, the subsequent low pulse is retracted as a long pulse. The exemplary sequence is 1〇3, 1〇4, and 1〇5 by clock. And low 106. Pulses 103-106 are both short enough to be within a predetermined acceptable width. The maximum pulse width 13 对于 for data reception can be specified. Continuous high or continuous low can be pressed between two short pulses The clock records a long pulse. In the example of Figure j, a long low value pulse of 1〇2 is used between the high pulses 1〇1 and 103. Similarly, a long high value pulse is used between the low pulses 106 and 1〇8. 7. Thus, 12 200828022 A pulse whose width is within a predetermined acceptance width is considered to represent a data value, such as a logic high or a logic low of a bit. Due to the physical limitations of the circuit or the noise cancellation requirement, the protocol is implemented. Electrical embodiments of the controller and receiver require a minimum pulse width. In some embodiments, a single lead interface protocol can be implemented with a minimum pulse width of, for example, 〇丨 microseconds. That is, its high or low pulse values remain less than The microsecond depletion pulse will not be considered a data pulse. Other minimum pulse widths can be defined based on physical or logical factors. This protocol defines a short pulse whose pulse width is greater than the minimum pulse width and less than any acceptable selection. value. In some embodiments, a pulse that is shorter than 5 seconds and greater than 〇 1 microsecond is defined as a short pulse. A pulse greater than 5 microseconds is defined as a long pulse. In some real scarves, it is also possible to protect the guard band between the pulse and the long pulse, and other minimum or maximum time periods. FIG. 4 shows a method of classifying data using the above agreement. Step 4〇 defines the standard pulse width (PWs) of the significant digits. In step 4〇2, the received data bit pulse width (PWi) is compared with the standard pulse width (pWs). If the received data bit pulse width (PWi) is greater than the standard pulse width (PWs), then in step, step 4〇3, the data is classified into a long pulse or data separation, and is not determined to be valid. Data bit. In step 404, if the received data bit pulse width is greater than the standard pulse width (hidden), the data is classified as a short pulse or an effective poor bit. If the data is detected as two consecutive long pulses in the step, the clocking data is clocked. If ^ 13 200828022 knows that the poor material separator is not detected in 405 (4), the upper limit / Ding Zhi is executed in step 402, and the recovery - Bay level, pulse width (PWi) and the comparison are compared. 4彳4 pulse health (PWs) is terminated. f t ^ The above-mentioned co-shooting uses a long pulse in the continuous high or low secret. Finally, two consecutive long pulses of the age-reduced polarity are used to end the shape and indicate that the data is compared. The graph shows that the pulse 120 is followed by a long high pulse 121. Since the previous valid bit ^ is high', it is terminated to start with a long low pulse. The transition order of this example can be used to indicate termination. Although not shown in the figure, if the previous valid bit is low, h, ', the stop sequence can be a long high pulse, and the subsequent long low pulse starts. Termination is optional and is not used in some embodiments. For example, when not, when locking data from the shift register, as in the case of a pair of controllers and receivers, it is not necessary to terminate. In these embodiments, since the receiving receiver that does not use the termination payment contains only a long pulse, it can be ignored. 2A and 2B show an example in which termination such as that formed by the pulse sum in Fig. j is not employed. Figure M shows the same data sequence <1101001>' as in Figure 但 but without the data value ln. Fig. 2B shows the same data sequence <11010011> as Fig. 1. The data acceptance width 201 is shown in both embodiments. In some examples, the long pulse used by the controller can be close to or longer than all pulses provided by the receiver. If the receiver is silent, the long pulse can be arbitrarily long. 14 200828022 Protocol application for different types of controllers and receivers The protocol described here can be applied to the case of one controller or to multiple controllers with the same-root lead. This protocol can also be used in conjunction with one or more dormant receivers, data acknowledgment receivers or data readback (readback) receivers. In addition, a variety of methods can be used to implement the agreement between the previously listed devices.

Various embodiments of a controller-receiver combination of serial interfaces are possible. For example, the device may be a dedicated receiver or controller that is interactive or uses any combination of the following: output drive, data lock, double long pulse terminator identification or confirmation. The sleep receiver does not require a drive function. Receivers without an address do not require the lock data or double long pulse terminator to identify and receive all incoming data. A dormant receiver with an address can use the address encoded in the protocol to select which communication packet is received. The lock can occur in the double long pulse termination sequence. The responding receiver may have such an 'intermediate drive' to perform data acknowledgment or use a short pulse meter to traverse the intermediate drive change during readback. If the + work is done, the current or voltage can be detected. A separate controller that uses ^ support data confirmation or data readback can be implemented by using only strong output. It will (4) address multiple connections " ignore the return without making other lines with other controllers; '= The controller for material confirmation and data readback can be connected to multiple controllers and receivers. The following examples illustrate the present invention exemplarily, but are not limited thereto. A K%, for example, can be rotated by using different degrees in the controller and receiver. 15 200828022 Force::Bai now communicates in both directions. The drive output in the order of decreasing force can be driven by the vertical force, the intermediate drive of the receiver, the weak drive of the controller and the driveless or the high impedance of the μ to the controller_receiver. In this application, the receiver can insert its line polarity change at the appropriate point when the system is driven. Standard off-the-shelf controllers are available through 〇

L I 夕,. This method is implemented by using pins of different values instead of using variable drive outputs to form multiple strings. Use a strong drive on the applicator 'at the receiver and the controller has a current sensor or with °. In the ^ tiger shot all transitions, but will detect the internal ==: the appropriate point of the fixed point and the weak drive of the second two to the second = ground ^ receive crying and ancient 4 stay hold. The control current sense sensor detects from = the phase of the agreement to determine whether to change the polarity. Line __, also detects another control in its idle phase: j in the buffer _ to _ can be used as = can be used to indicate the priority of the inactivity time period, longer than the delay in the scheduled rest The pulse is double-widthed to prevent new control 200828022 association or data transfer. The main controller can maintain idle control by sending : . However, in this example, :=: The two request controllers wait for a predetermined rest period; for example: one: they use weak _ long pulse coffee line, ρ ~ spoon to participate in reverse hold - expected. The main control age, then Lei,, six,, choose whether to release, line control. The _W, 丨1•亚亚 c disappears. If, force...,... ignore the current until it waits for 'to' data transmission. _, and another & rest period to try again. If yes: Arbitration. By using a driver based on the priority of each controller, two drives ' and tries to flip the line polarity. If the segment ιϋι, the controller gives up the attempt and waits for the next rest time. ^ The polarity of the line is reversed in the weak drive. Assuming strong control is dominant and is performed, in another embodiment, an arbitration method uses the white and Becky instruction packets from the main controller to get confirmation from the waiting controller. Periodically, the intervening master controller can use a binary search or another search method to poll the material controller with the appropriate priority. Once the candidate controller is found: the main control H will send a data command to the wait control II to control the line. Switching occurs while waiting for the acknowledgment rollover of the double long pulse terminator sent by the controller. The priority delay timer and current sensor are not required, and the standard non-custom controller can be used for 2008 200828022. A number of changes have been made to these methods to facilitate two-way communication by using a single-lead serial. As a non-limiting example, protocol mechanisms may include, controller data transmission, receiver acknowledgment, receiver data readback, controller arbitration, and controller switching. Some embodiments of the protocol may include an optional confirmation function. In the -Beibei example, a related example can be described by using the double long pulse terminator in a predetermined manner to see Cui, Fig. 3A and Fig. 3B. In these examples, the data model <〇11〇> is presented. After the one-bit or multi-bit data is recorded in the receiving device towel, the control _ double-long pulse, and ς stop payment is followed by the first long pulse after the control is issued, and the following is longer than the acceptable width of the preview. After any length of pulse capture, the controller sets its output to either high impedance or weak drive. At point 3G7, if the receiving device is confirming the controller, it can flip the logic polarity of the controller signal. Therefore, if an acknowledgment is performed, the high signal 3〇5 will be switched to the low acknowledgment signal 3〇6 at point 3〇7. The controller can check the flip state using a driver in a high impedance state. If no acknowledgment is performed, the signal remains unchanged as indicated by the dashed line 3〇8, and the control is such that the protocol can be terminated with the second long pulse 3〇8, accepting no communication acknowledgment. No confirmation appears as a long start pulse in the termination sequence. In some embodiments, the receiver attempts to confirm at a predetermined time interval after the appropriate data entry. Only use a strongly driven controller to reverse the acknowledgment signal of a weakly driven receiver. The receiver can be configured to detect if the signal can be flipped in either case. This can be used to transmit signals when data is locked. 18 200828022 Input 0 Response When this protocol does not require a dormant receiver to drive the data line, the device is configured to trace the difference between the τ and _, and the weak drive is strongly read back. Protocol = impedance. The intermediate driving force of the receiver is weaker than the controller but the control is stronger than the control.

C ί. -- Some embodiments support the confirmation and data readback functions. Figures 5 and 6 show no exemplary protocol for data readback. Confirm function start data readback sequence 歹J return item, control is, strong drive is applied on the line to transmit instructions for the receiving device. Figure 5 shows two examples. In the first example, the last data bit of the driver, state is ♦. In the second example, the last data bit of the drive lag 550 is <1;>. During the first half of the double long pulse termination signal 510, the controller terminates the polarity of the previous pulse in the second half cycle, but maintains the pulse using the weak driver M1. The response receiver then forces polarity flipping 512 with its own intermediate driver. This flip confirms the controller. The controller then responds by timing a full length pulse, which is used in a narrow manner, and drive = 4 to force the polarity 513 to be reversed. This passes the signal to the receiver to transmit the first-lean, bit 7〇'. If the bit polarity is in line with the current line state, the most significant bit is transmitted first. The polarity of the short pulse indicates the polarity of the transmitted data bit. If the polarity of the touch and the money line are the same, the receiver will force the polarity when the controller returns to the weak drive or the controller weakly changes the polarity. The polarity change will be clocked to generate a short pulse for transmitting the signal transmitting the valid data bit. 19 200828022 The receiver compares the following data bits in the following transitions. If the bit and (4) line polarity do not match, the receiver will keep the line secret for as long as possible 3 while ignoring (4) the wire polarity change. When the j pole & and the line polarity, the U can generate a short pulse after a weak drive of the controller, 夂 or a predetermined time less than the acceptable width of the pulse. From 1 long pulse to & slightly pulse, touch the mixed current bit until the short pulse white, the correct polarity appears. Therefore, the protocol can achieve data transmission with no more than one long pulse between two short pulses. The controller can also continue to use a weak drive flip until a long pulse occurs. At the end of the long pulse, the controller causes the (four) axis to force the polarity flip and the lean back phase to continue. The receiver check _ line changes and according to the current level of the secret state of the mosquito to make the secret pulse is the ship. If the receiving port only detects that the control is to use only a strong drive, the receiver will use the timer to insert the driver to force the transition. The receiver timer can be set to a ride greater than & to allow the controller to time = in the case of a hybrid controller drive. This situation allows the controller to check the receiver's short pulses 疋π. In some cases, the controller only controls the timing under the assumption of the receiver and controller's standard timing model. The sequence continues to be transmitted until the controller detects a certain number of short pulses and detects a double long pulse termination sequence t ”over_moving_end. This sequence can be used for the singularity of any number of bits. In some embodiments The data of the readback sequence or the length of the data can be different, which is used to distinguish the readback data from the controller commands of other receivers. A variety of different check and readback modes can be used, as shown in Fig. 5, 20 200828022 If the data bit is <G>, the strong high check mode 56G, the weak high check mode 570, the short high readback mode 580, and the long high readback mode 590 can be used. If the data 4 is <1>, Bellow A strong low check mode 561, a weak low check mode 571, a low low readback mode 581, and a long low readback mode 591 can be used. Figure 5 shows an example of a partial readback mode in the strong and weak drive states 599.

To implement this protocol, the controller can drive weak and strong levels and detect the corresponding drive level from the receiver. As shown in Figure 6, the controller can be implemented by using two wheel-in-out pins 6〇1 and 6〇2 or the like. Pin 601 is directly connected to line 6〇4, and the other pin 6〇2 is connected to line _3 through weak drive resistor 6〇3. As a non-limiting example, the direct drive pin 601 can have a resistance of one thousand ohms and the weak drive resistance 6 〇 3 can have a resistance of about 25 kilo ohms. The receiver can have an intermediate drive corpse of 5 kilo ohms to control the drive line when returning to a weak drive. The controllers described in this morning to implement this protocol may include current sensors and crane control with input and output pin combinations. In some embodiments, control = only I is forced to drive TJ1, except that the controller abandons the line control to another. The receiver can try to change the line with a weak drive, but it cannot be done under the controller drive. The receiver is available - the internal timer is flipped at the appropriate time. In some embodiments, receiving := may be longer than the short pulse timing used by the controller. This allows the standard control profile to be driven with strong and weak signals so that the receiver drives the line. If the age = rush to ΐ ' then in some embodiments, the receiver will try the polarity: Μ 付 控制 控制 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 If the data of 11 is being acknowledged, the receiver will attempt to change the polarity of the 21st 200828022 long pulse to the second long pulse. The controller realizes the view of the wire from the receipt of the crane. If an oscilloscope subscribes to the spectator, the control benefit can extend the first long pulse in the phase to more clearly show that there is no weak drive, so no acknowledgment signal is detected on the line. Referring now to Figure 8, an example of a readback scheme _ is illustrated in accordance with an embodiment of the present invention. In this example, the data model <1〇1_1〇> is sent, and the poor model <011001> is read back. The readback scheme _ shows that only the strong drive with the current sensor of the controller is used, and only the weak drive of the receiver is used: first, the controller starts with the passive line 811 and sends the data 812: in the poor At the end of the material transfer 810, the controller implements a first transition 821 of the double pulse terminator _. At this point, the receiver is properly addressed and ready to confirm the sentence, the information sent. The reception is cried by starting its weakly driven milk at the beginning of the long pulse or starting the weak drive 823 at the beginning of the first long pulse. Detecting the result of the weak drive, the controller causes the polarity change to change: the second long pulse. If a weak pulse from the acknowledgment receiver does not exist, the level 825 remains until there is a time not stated here. Once the acknowledgment is successful, the controller completes the second long pulse by flipping polarity 831. Therefore, the acknowledged receiver is signaled' to first correspond to the most significant data bit during the readback request. The receiver uses its weak driver 832 to hold the line ^ or not use the driver at all. The controller detects that there is no opposite current, passes a long pulse and changes the polarity change 833 to low. The receiver detects a low condition that matches the polarity of the bit it must transmit. The receiver sets its weak drive 834 so that the long pulses are reversed. The control is cried back by performing a polarity change 835 22 200828022 to generate a short data pulse. The same operation is repeated for the high pulses 836, 837 and the ignored low pulses 838, 839. After the data is read back, the receiver or controller will cause the double long pulse terminator to be displayed. In some embodiments, the receiving portion may have an interface that combines the input_output power and the current sensor. Using a current sensor, this part can be weaker and _stable in the same day (d), in order to correct the polarity. Can use 0, two different drive modes. In the first case, the weak confirmation drive uses the flip of the two long pulses of the drive. In the data mode, if the data readback bit and the line polarity do not match, the weak drive will try to keep the long pulse, or if the data readback bit and the line polarity match, the weak drive will try after the short pulse interval. Flip the pulse. The short pulse delay of the receiving section can be longer than the short pulse timing used in the control gain. In some embodiments, the controller often uses a strong drive when controlling the line. A current sensor can be used to determine if there is a response. In the second case, the strong_weak drive causes the controller to time the edge transition to the weak drive transition. In the case of only strong drives, the controller waits for a longer time to detect the current from the partial polarity flip attempt. In some of the examples, the logic levels of 'single-lead turns' are matched so that a power mismatch will not cause one part to drive another part of the power supply. In some embodiments, the logic swing range can be reduced to 2V, such that V8Vil and 12Vih_Uvih are approximate limits when powering up to 5V is used. This limit can be configured to address the weak drive induced variations in the strong drive voltage levels by setting the appropriate limit guard band. In some embodiments, a debounce circuit (not 23 200828022) can be used to prevent interference with data. 100 nanoseconds or longer Filtering is used to suppress unwanted voltage and current disturbances. Circuitry, in some embodiments, a relatively simple circuit can be used to measure the pulse width and determine the reception of the pulses. One embodiment of such a serial port circuit is shown in FIG. As shown in Figure 9, the serial timer 91 monitors the short pulses. If a short pulse is found, a narrow clock pulse is generated on line 915 and sent to the shift input of shift register 950. The inverter 9〇5 inverts the data pole on the data line 9〇1 and outputs the data inverted on the conductor 9〇3 to the shift register sand latch 95G. In some embodiments, the inverted (four) signal is used as the input to the private register 950, since the logic level of the fU is required to be received before the electrical pulse ends. For example, a narrow high pulse ends at a transition to a low %. Therefore, the low signal is active when the CLK signal 915 pulse is high. So 'inverting 1 9〇5 can be used to store data polarity. In other embodiments, the inverter 905 can be omitted if the data polarity is not required or it is stored, known, or can be determined. When the RDY signal 916 is triggered, the shift register 95 〇 (4) Standard Data 2 The rising edge of the RDY signal 916 is clocked in the latch. In some cases, the high-low pulse of the 91G towel is symmetrical. In those $examples, the H 906 is optional. It can be seen that the driver 9 () 6 will flip the rain direction of the U Tiger L1 920 and L2 925, but will not affect the operation of the circuit. When the shift register and latch 95 are described as an integrated function list 24 200828022, the ship can be driven to output the bus _. In the example, the destination can be set to transmit more or fewer bits. _ = 仙 :: Signal 902 can be used to restart the string: just :: Spears register and latch 960. Γ

The serial timer 91 is not shown in Figure U). One embodiment. Two pulse trains are used in this example circuit, with high pulse detection and low pulse chambers. The pulse width recognizer includes one or (four) representations that enable delay. The pulse width recognizer just 5 includes an asymmetric timer deletion and an asymmetric timer view. As a non-limiting example, the asymmetry timer 1003 is set to approach Gns, the τ drop time s, and the asymmetry timer 1002 is set to a rise time of 5 us, and the fall time is shifted. The output of the misaligned timing H 1GG2 can also be connected to the inverter face. The pulse width discriminator face includes an asymmetric timer 1_, a bribe, and an inverter 1006. The delay time of the asymmetric timer 1_ and the blue may be selected to be the same as or different from the asymmetric timers 1003, 1〇〇2. - If the input pulse on data line 1017, whether high or low, is longer than the pre-I degree, then pulse width recognizer 1〇〇5 and will output a high signal on lines (7)^$ and 1016, respectively. Any high pulse from the inverse gate 〇〇4 or the inverse gate 1005 will prevent the 或 pulse necessary for the counter or gate 1〇2〇 to clock the register. Some embodiments also include D flip-flops 1025 and 1030 to store long pulses. If there are two long pulses in a row, as discussed earlier, the signals L1 1040 and l2 1045 will be high, and the rdY output brain of the phase 2049 will be high as the agreed number. > Port In some embodiments, if it is not necessary to lock the batting in the shift register 95, all or - portions of the flip-flops 1025 and 1030, the inverse gate 1048 and the inverter 1 〇 49 may be omitted. The omission of these components saves space in a separate receiver application. r A timing diagram of high pulse width discrimination is shown in FIG. The low pulse width Γ _ is similar to this. As mentioned earlier, asymmetric timers with their own different = falling edge times generate clocks and ready pulses. Figure u shows two high pulses, the first 1150 narrow and the second 116 wide. In transition 1101, a narrow chirped pulse begins. This pulse causes the output of the asymmetrical timer 1〇〇3 to go high at the transition 1111. In contrast, the turn of the gate is turned low by 11G3 at the transition 1112. Due to the narrow width of the pulse (10), the asymmetric timer 1002 does not have time to go high, so the output of the inverter face remains high. When the c f pulse 1150 ends at the transition 1 suffix, the asymmetric timer deletes the output by 1 ns after the transition 1105. This causes the output of the inverse gate to remain low before the transition 1106 goes high 丨ι〇3丨(8) still. Because the corresponding low pulse width recognizer will turn low at the output of the opposite gate 9 at the beginning of the low = punch, which is the same as the output of the opposite gate at the beginning of the high pulse, the two low levels will A 1 ns south pulse 1113 is generated at the clock output. The low gate 1004 is clocked at the flip flop 1025 when the narrow pulse 1150 terminates at the transition Π04, so that the output u 1 〇 4 〇 is low _ narrow pulse 1114 . The width of the low pulse 1114 does not affect the next rising transition output 26 200828022 1130 1131 and 1132 because the minimum width of the pulse is greater than the timer ο. ? or 1002 has a long falling edge. In the case of a wide pulse 116 为 bounded by transitions 1130 and 1140, the processing of the asymmetry timer 1003 is the same as in the case of a narrow pulse. However, the asymmetrical juice of the 1002 has sufficient time to reach its 5us timing. Timer 1002 goes high at transition 1107, causing the ugly output of the inverter to go low at transition 1108, while the output of NAND1 becomes high at transition_. Since the off time of the timer 1002 is 25 ns, the 瞒 time of the timer 1 〇〇 3 is 10 〇 ns, and the falling edge of the pulse i 16 〇 at the transition j 14 不 is not transmitted to the clock output. The timer has effectively prevented the transition and the pulse caused by 1141. The high level of the inverted output causes the wide pulse 1160 to fall at the transition 114〇 to record the high level clock at the bistable multi-resonance ill 1025. The output L1 then transitions to a high 111 〇 to indicate a long pulse. Symmetrically, if the same phase is sent to the bistable multi-resonant S 1030 and the 丨 L2 1045, a double long pulse termination signal will be generated at the rdy illusion (4) to terminate the agreement. Another embodiment is shown in FIG. The inverter 905 in the figure $ is not used in this embodiment. Moreover, the serial timer 1201 does not include the output L1 or L2, and is accordingly represented as 920 and 925 in FIG. As shown in Figure 13, in some embodiments, the shift register and latch can be implemented without a reset input. Shame, t signal line service can be directly input to the serial timer 1310. In some cases, the data is not latched. An example of such an embodiment is shown in FIG. As shown in Figure 14, the shift register H is just 27 200828022 crying Γ4Γ / fresh field. In this embodiment, the serial timed state 1410 can be configured to not require a J-day guard width to be rotated. According to the pulse embodiment, the recording is accepted. In the data line of the docking county register shown in Figure 14, there is 1425' but there is no decision circuit. Mouth map = in the example of the serial timing crying crying used in the embodiment shown in Fig. 14, the timer 1501_1504 is an asymmetric delay meter two objects 150 Μ 5 () 4 (and any other mentioned timer) time Can be individually programmed or set, with the pulse width discrimination according to the agreement requirements. In some implementations, the calculation = 15G0 can only be seen through the inverter (10) on f_5()5. The physical heart ίο can also not make the light health town Wei and the logical structure. Ί Conclusion The present invention discloses a new protocol for the serial communication system. Among them, 'short pulse represents data, and long pulse represents data separator. The polarity of the short pulses represents their value. In some embodiments, a controller and controllers may be used interchangeably with receivers connected to their - root communication lines (routes). The receiver may include one or more dormant receivers, a data acknowledgement receiver, and/or a poor material readback interface (4). Control II and (4) can be driven according to their line control state (4) wheel drive, weak output purchase, towel output drive or no output drive (high output impedance). In an embodiment using a single controller, if the receiver is dormant, the 200828022 second strong drive. If you use multiple data to read back, you can still control the combination of the _ wheel drive surface. Usually = the receiver does not use the driver. Yi ^ ^ can not be interchanged with the use of the middle wheel ^ her and _ when they can Γ

In some embodiments, during the strong drive process, the control assists 3 = thus allowing indirect reception from the receiver _ and the readback 'is not used to overcome the load and the surrounding environment:: Zhuang / ^, secret /Short pulsed daily casting specifications can be selected to overcome problems such as on-board, noise, and line transmission characteristics. In some embodiments, a dormant receiver does not lock the data and does not use a terminator. In addition, the sleep receiver does not drive the line. Multiple addressable receivers can respond to double long burst terminator locks when properly addressed. On the other hand, in response to the receiver, in the case of readback and confirmation, it can be = weaker 咼 drive and weaker low drive, or even no drive. The protocol described in Tinley can be effectively executed using only a finite circuit structure. Controllers and receivers that can communicate using this protocol can be implemented using the upper circuit. The implementation of the exemplified Weikelai is implemented in conjunction with: In the following, the various embodiments set forth herein may be implemented without all of the features or aspects described herein. A person skilled in the art will recognize that many modifications and variations can be made without departing from the spirit and scope of the invention. Embodiments of the present invention can be used with many different types of 29 200828022 2 transmission systems. In addition, several transitions of a real _ can be combined with other examples. Some features may not be elaborated here by a single embodiment. The details of some embodiments of the present invention are set forth in the specification and in FIG. 5 to provide a comprehensive understanding of these embodiments. However, it will be understood by those skilled in the art that the present invention may be practiced without these details or additional details of the invention. No. 2 shows or describes the public (four) structure and Wei, and the description does not necessarily obscure the description of the embodiments of the present invention. As mentioned above, one element that is "connected" to each other can be directly (ie, there are no other elements between the connected elements = (ie, there is one or more other enclosures between the connected elements == explicit) Needs [: in the = book and the patent application is not the only or detailed meaning; the meaning of the two ^ ^ ^ contains "M, including but not limited to", "3 meaning." In addition, in this article The words "in,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ί The list of two or more projects refers to the following explanations of the vocabulary reading the words: all items in the list in the list and all the items in the list - the combination of the project limits m == The description is not exhaustive or makes the invention a form. The specific embodiment of the invention, 30 200828022 Examples are exemplified above, but one of ordinary skill in the art will recognize that various variations can be made in the invention. (iv) Modifications, for example, although presented in the order given Multiple processing and blocks, but the rank generation embodiment may execute the program with these steps in a different order, employ these parties, and some processes or boxes may be deleted, moved, added, split, Combinations and/or modifications to provide alternative or recombined processes and blocks. The towel-per-process and block can be implemented in a variety of ways: in addition, although this aspect or block is sometimes shown as The ordering is performed, but the processing or miscellaneous can also be stored and the job is performed at different times. The teachings of the present invention provided in one j can be applied to other systems, and it is not necessary to be the above system. The elements and operations may be combined or altered to provide other embodiments. In accordance with the description of the Detailed Description section above,

The terms used in the detailed description are intended to be interpreted in the broadest sense, and the detailed description is to be used in any way that is to be construed in conjunction with the specific embodiments of the present invention. In general, some terms may be emphasized, however, the terms used in the scope of the limited patent application are disclosed in the specific implementation section and are subsequently applied for the special thorns + a π — 31 200828022 Noon To limit the invention to the specific embodiments disclosed in the specification, these terms are clearly defined in the section of the 5%. Therefore, the scope of the present invention is not limited to the scope of the patent, and the above-disclosed embodiments of the present invention, and all equivalents of the application or the application of the present invention. 32 200828022 [Simplified illustration of the drawings] Examples of the invention are shown by the drawings. These drawings are to be considered as illustrative and not restrictive. Figure 1 shows an exemplary protocol sequence. 2A and 2B show an exemplary protocol sequence without a terminator.

3A and 3B illustrate an exemplary protocol sequence with data validation. Figure 4 shows the method of data classification. Figure 5 shows an exemplary protocol sequence for readback. Figure 6 shows the structure of an exemplary controller. Figure 7 shows an exemplary readback protocol sequence driven by a hybrid strong and weak controller. Figure 8 illustrates an exemplary readback protocol sequence driven by a strong controller. Figure 9 shows an exemplary circuit of a single line sequence. Figure 10 illustrates an exemplary serial timer that distinguishes between pulse widths. Figure 11 shows an exemplary input and output sequence. Figure 2 shows an exemplary serial port circuit. Figure 3 shows an exemplary sequence 埠 circuit. Figure 14 illustrates an exemplary serial port circuit. Figure 15 illustrates an exemplary serial timer that differentiates pulse widths. [Main component symbol description] PWi receiving data bit pulse width PWs standard pulse width 1〇〇 beginning 101, 103, 105 short high pulse 104, 106, 108 short low pulse 102 long low value pulse 107 long high value pulse 33 200828022

108 low pulse 111 valid bit 120 long low pulse 130 maximum pulse width 121 long high pulse 201 data acceptance width 301-304 - bit or multi-bit data 305 high signal 306 low acknowledgment signal 307 any length pulse 308 second long pulse 501 drive state 510 double long pulse termination signal 550 drive state 511 weak drive 512 polarity flip 5113 forced flip polarity 514 strong drive 560 strong check mode 561 strong low check mode 570 weak high check mode 571 weak low check mode 580 short high readback Mode 581 short low readback mode 590 long high readback mode 591 long low readback mode 599 strong and weak drive state 601-602 input-output pin 603 weak drive resistance 604 line 800 readback scheme 810 data transmission 811 passive line 812 data 820 double pulse terminator 821 transition 830 readback 822 weak drive 823 weak drive 824 polarity change 825 level 831 flip polarity 832 weak drive 833 polarity change 834 weak drive 835 polarity change 836, 837 high pulse 34 200828022

838, 839 low pulse 901 data line 902RESET signal 903 wire 905, 906 inverter 910 serial timer 915CLK signal 916RDY signal 920 signal L1 925 signal L2 950 shift register 960 bus 1001, 1049 inverter 1002, 1003 not Symmetrical timers 1004, 1048 and gate 1005 high pulse width recognizer 1010 low pulse width recognizer 1015, 1016 respectively on line 1017 data line 1020 reverse or gate 1025, 1030 multivibrator 1040 signal L1 1045 signal L2 1050RDY output 1150 narrow High pulse 1160 wide high pulse type f 1100 , 1101 , 1104-1109 transition 11 Π , 1112 , 1140 , 1141 transition 1102 high 1103 low 1113 to pulse 1 1114 low _ narrow pulse 1130 , 1131-32 rising transition output 1160 wide pulse 1201, 1310, 1410, 15〇〇 serial timer 1302 reset signal line 1305 shift register and latch 1405 shift register 1420 data line 1425, 1510 inverter 1501-1504 timer (asymmetric delay timing 1505 data line 35

Claims (1)

Patent Application Range: The method of the letter, including: Defining the predetermined length of the data separator symbol. A predetermined short pulse and as a pulse for providing data flow through the data. The method of claim 1, further comprising: providing only one of the data separation symbols between the consecutive data pulses when transmitting consecutive #material pulses of the same polarity; and when transmitting polarity (four) _#ship_, in the continuous alternating of the polarity of Wei Chongzhi provides: miscellaneous separator symbol. The method of claim 1, wherein the method defines a short pulse, including a minimum width and a maximum width defining a pulse acceptable width; and the pre-pulse pulse includes a minimum width, and if the rest interval is The ground selection includes the maximum width. For example, if the application for the special machine is described in the first aspect, the serial communication includes the selection between the _ H drive _ combined with the Longjian controller drive. The method of claim 1, wherein the serial communication comprises a receiver that directly drives a communication line when the controller uses a strong drive and a weak drive, or The communication circuit is indirectly driven by the driver of the strong drive and current or voltage sensor, wherein the drive to the communication line by the receiver includes confirmation and response. The method of claim 1, further comprising: transmitting double 200828022, a pulse terminator, wherein the double long pulse terminator comprises two consecutive long pulses as an optional protocol terminator. The method of claim 6, wherein the serial communication further comprises: transmitting, by the controller, the first long pulse of the double long pulse terminator, by directly or indirectly transferring the second The polarity of the long pulse is used to confirm the termination of the packet communication; and the field is forced to change the polarity of the second long pulse after the reception is not successfully acknowledged within the waiting interval. 8. The method of claim 7, further comprising: transmitting data to a plurality of receivers and selected ones of the controllers using the primary controller; transmitting the double long pulses using the primary controller The first pulse in the terminator causes 4 received $ to change the polarity to the second long pulse; and the master controller sends an initial polarity change such that the selected receiver can begin transmitting back read data with the same protocol Until the selected receiver sends a double long pulse terminator. 9. The method of claim 8, further comprising: transmitting back to read by direct drive from the selected receiver or by an indirect drive from the selected receiver assisted by the primary control community. according to. 10. The method of claim 9, further comprising: continuously reading back the data until the double-long pulse terminator is interrupted by the primary controller after obtaining sufficient but not necessarily all of the resources 37 200828022 Or the protocol; or by the selected reception being transferred to the returning rabbit by the occurrence of the double long pulse terminator, causing the double long pulse terminator to interrupt or terminate the protocol. 11·:::青:: The method described in item 10 of the scope’ It uses a U-timer' to avoid premature changes in the short pulses and the long pulses. 12· ===, the method of item 11 wherein the main control ^吏I, from (4) order is returned to the processing of the selected receiver, thereby forming a short pulse during the readback period. 13. The patent is difficult (4) to describe the method in which the main control is at the end of the long pulse to allow the protocol to continue. - A method of arbitrating between multiple controllers in a serial communication: ° swapping the roles of the controller and receiver; if the communication line does not transition within a predetermined rest interval, the controller is idle And A uses the host controller to address the listening controller to poll and select the next controller to be bound by the addressed instruction packet. 15.=Apply the method described in item 14 of the patent scope, which responds to the takeover command from the release controller, and in the double long pulse termination process, when the polarity is changed for the second pulse, the controller is arbitrary The method of claim 4, the method of claim 4, wherein the controller includes an allocation address, and the arbitration time is short with a clear and rest interval: 2 After the release, the change of the polarity of the line causes the competition of the control line, and the competing controllers maintain a new polarity with a strong drive. Second = after the respective set time interval, by using the weak drive 4', the change of the polarity of the spring road to compete for the line control, and (4) = the competition controller of the interval wins the competition for the line control, the middle for the higher priority The sequence sets the application interval longer; and when the line polarity is not changed by the weak drive, the competing controller drives the line by waiting for the output to wait for the next-rest interval. 17 ·= Please refer to the control method described in item 14 of the patent, in which the main control The device rejects the line polarity, ignores the arbitration attempt, and waits for the read current from the competing controller to disappear, or rejects the release control by transmitting a continuous sequence of long pulses to prevent the arbitration attempt. 18. A single-line string riding system comprising a control, the controller acting as a transmitter when the controller includes only a strong drive. The single-line serial communication system according to claim 18, wherein the controller comprises the strong drive and the current or voltage sensor, and the controller is used as the transmitter and a receiver. . The single-line serial communication system of claim 18, wherein when the controller includes the strong drive and a weak drive, the 39 200828022 is controlled to be used as the transmitter and the The receiver, wherein the receiving is an intermediate drive that is weaker than the hard drive and stronger than the weak drive. 1. The single-line serial communication system of claim 1, wherein the receiver is an addressable or non-addressable receiver, and when the receiver is the non-addressable receiver, the receiving Is a dormant receiver; and when the receiver is the addressable receiver, the receiver is dormant to receive 11 or confirm Wei; the towel of the light receiver further includes a non-readback receiver or Read back the receiver. 22. A single-line serial communication system comprising: a clock for generating data as a predetermined short pulse and a non-clock signal for generating a data separation symbol as a predetermined long pulse; and shifting a register coupled to the timer for storing data based on the generated clock signal. 3. The single-line serial communication system according to claim 22, wherein the timer further comprises: a high pulse width identifier; a low pulse width identifier; and a group, a circuit connected to the high pulse A wide identifier and the low pulse width identifier are used to determine whether the receive_pulse is said: tilt or; 24. The single-line serial communication system of claim 22, wherein the timer of 40 200828022 further comprises: a first bistable multivibrator for storing high-intensity pulses that occur; a bi-stable multivibrator for storing the occurrence of low long pulses; and a combinational logic circuit for determining whether the double long pulse terminator is from the first bistable multivibrator or the Two bistable multivibrators. 41